2 * common defines for all CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #error cpu.h included from common code
32 #ifndef TARGET_LONG_BITS
33 #error TARGET_LONG_BITS must be defined before including this header
36 #ifndef TARGET_PHYS_ADDR_BITS
37 #if TARGET_LONG_BITS >= HOST_LONG_BITS
38 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
40 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
44 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
46 /* target_ulong is the type of a virtual address */
47 #if TARGET_LONG_SIZE == 4
48 typedef int32_t target_long
;
49 typedef uint32_t target_ulong
;
50 #define TARGET_FMT_lx "%08x"
51 #define TARGET_FMT_ld "%d"
52 #define TARGET_FMT_lu "%u"
53 #elif TARGET_LONG_SIZE == 8
54 typedef int64_t target_long
;
55 typedef uint64_t target_ulong
;
56 #define TARGET_FMT_lx "%016" PRIx64
57 #define TARGET_FMT_ld "%" PRId64
58 #define TARGET_FMT_lu "%" PRIu64
60 #error TARGET_LONG_SIZE undefined
63 /* target_phys_addr_t is the type of a physical address (its size can
64 be different from 'target_ulong'). We have sizeof(target_phys_addr)
65 = max(sizeof(unsigned long),
66 sizeof(size_of_target_physical_address)) because we must pass a
67 host pointer to memory operations in some cases */
69 #if TARGET_PHYS_ADDR_BITS == 32
70 typedef uint32_t target_phys_addr_t
;
71 #define TARGET_FMT_plx "%08x"
72 #elif TARGET_PHYS_ADDR_BITS == 64
73 typedef uint64_t target_phys_addr_t
;
74 #define TARGET_FMT_plx "%016" PRIx64
76 #error TARGET_PHYS_ADDR_BITS undefined
79 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
81 #define EXCP_INTERRUPT 0x10000 /* async interruption */
82 #define EXCP_HLT 0x10001 /* hlt instruction reached */
83 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
84 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
86 #define TB_JMP_CACHE_BITS 12
87 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
89 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
90 addresses on the same page. The top bits are the same. This allows
91 TLB invalidation to quickly clear a subset of the hash table. */
92 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
93 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
94 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
95 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
97 #define CPU_TLB_BITS 8
98 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
100 #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
101 #define CPU_TLB_ENTRY_BITS 4
103 #define CPU_TLB_ENTRY_BITS 5
106 typedef struct CPUTLBEntry
{
107 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
108 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
110 bit 3 : indicates that the entry is invalid
113 target_ulong addr_read
;
114 target_ulong addr_write
;
115 target_ulong addr_code
;
116 /* Addend to virtual address to get physical address. IO accesses
117 use the correcponding iotlb value. */
118 #if TARGET_PHYS_ADDR_BITS == 64
119 /* on i386 Linux make sure it is aligned */
120 target_phys_addr_t addend
__attribute__((aligned(8)));
122 target_phys_addr_t addend
;
124 /* padding to get a power of two size */
125 uint8_t dummy
[(1 << CPU_TLB_ENTRY_BITS
) -
126 (sizeof(target_ulong
) * 3 +
127 ((-sizeof(target_ulong
) * 3) & (sizeof(target_phys_addr_t
) - 1)) +
128 sizeof(target_phys_addr_t
))];
131 #ifdef WORDS_BIGENDIAN
132 typedef struct icount_decr_u16
{
137 typedef struct icount_decr_u16
{
146 typedef struct CPUBreakpoint
{
148 int flags
; /* BP_* */
149 struct CPUBreakpoint
*prev
, *next
;
152 typedef struct CPUWatchpoint
{
154 target_ulong len_mask
;
155 int flags
; /* BP_* */
156 struct CPUWatchpoint
*prev
, *next
;
159 #define CPU_TEMP_BUF_NLONGS 128
161 struct TranslationBlock *current_tb; /* currently executing TB */ \
162 /* soft mmu support */ \
163 /* in order to avoid passing too many arguments to the MMIO \
164 helpers, we store some rarely used information in the CPU \
166 unsigned long mem_io_pc; /* host pc at which the memory was \
168 target_ulong mem_io_vaddr; /* target virtual addr at which the \
169 memory was accessed */ \
170 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
171 uint32_t interrupt_request; \
172 /* The meaning of the MMU modes is defined in the target code. */ \
173 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
174 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
175 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
176 /* buffer for temporaries in the code generator */ \
177 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
179 int64_t icount_extra; /* Instructions until next timer event. */ \
180 /* Number of cycles left, with interrupt flag in high bit. \
181 This allows a single read-compare-cbranch-write sequence to test \
182 for both decrementer underflow and exceptions. */ \
185 icount_decr_u16 u16; \
187 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
189 /* from this point: preserved by CPU reset */ \
190 /* ice debug support */ \
191 CPUBreakpoint *breakpoints; \
192 int singlestep_enabled; \
194 CPUWatchpoint *watchpoints; \
195 CPUWatchpoint *watchpoint_hit; \
197 struct GDBRegisterState *gdb_regs; \
199 /* Core interrupt code */ \
201 int exception_index; \
203 int user_mode_only; \
205 void *next_cpu; /* next CPU sharing TB cache */ \
206 int cpu_index; /* CPU index (informative) */ \
207 int running; /* Nonzero if cpu is currently running(usermode). */ \
211 const char *cpu_model_str; \
212 struct KVMState *kvm_state; \
213 struct kvm_run *kvm_run; \