hw/dma.c

   1 /*
   2  * QEMU DMA emulation
   3  *
   4  * Copyright (c) 2003-2004 Vassili Karpov (malc)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "isa.h"
  26
  27 /* #define DEBUG_DMA */
  28
  29 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
  30 #ifdef DEBUG_DMA
  31 #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
  32 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
  33 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
  34 #else
  35 #define lwarn(...)
  36 #define linfo(...)
  37 #define ldebug(...)
  38 #endif
  39
  40 #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
  41
  42 struct dma_regs {
  43     int now[2];
  44     uint16_t base[2];
  45     uint8_t mode;
  46     uint8_t page;
  47     uint8_t pageh;
  48     uint8_t dack;
  49     uint8_t eop;
  50     DMA_transfer_handler transfer_handler;
  51     void *opaque;
  52 };
  53
  54 #define ADDR 0
  55 #define COUNT 1
  56
  57 static struct dma_cont {
  58     uint8_t status;
  59     uint8_t command;
  60     uint8_t mask;
  61     uint8_t flip_flop;
  62     int dshift;
  63     struct dma_regs regs[4];
  64 } dma_controllers[2];
  65
  66 enum {
  67     CMD_MEMORY_TO_MEMORY = 0x01,
  68     CMD_FIXED_ADDRESS    = 0x02,
  69     CMD_BLOCK_CONTROLLER = 0x04,
  70     CMD_COMPRESSED_TIME  = 0x08,
  71     CMD_CYCLIC_PRIORITY  = 0x10,
  72     CMD_EXTENDED_WRITE   = 0x20,
  73     CMD_LOW_DREQ         = 0x40,
  74     CMD_LOW_DACK         = 0x80,
  75     CMD_NOT_SUPPORTED    = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
  76     | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
  77     | CMD_LOW_DREQ | CMD_LOW_DACK
  78
  79 };
  80
  81 static void DMA_run (void);
  82
  83 static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
  84
  85 static void write_page (void *opaque, uint32_t nport, uint32_t data)
  86 {
  87     struct dma_cont *d = opaque;
  88     int ichan;
  89
  90     ichan = channels[nport & 7];
  91     if (-1 == ichan) {
  92         dolog ("invalid channel %#x %#x\n", nport, data);
  93         return;
  94     }
  95     d->regs[ichan].page = data;
  96 }
  97
  98 static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
  99 {
 100     struct dma_cont *d = opaque;
 101     int ichan;
 102
 103     ichan = channels[nport & 7];
 104     if (-1 == ichan) {
 105         dolog ("invalid channel %#x %#x\n", nport, data);
 106         return;
 107     }
 108     d->regs[ichan].pageh = data;
 109 }
 110
 111 static uint32_t read_page (void *opaque, uint32_t nport)
 112 {
 113     struct dma_cont *d = opaque;
 114     int ichan;
 115
 116     ichan = channels[nport & 7];
 117     if (-1 == ichan) {
 118         dolog ("invalid channel read %#x\n", nport);
 119         return 0;
 120     }
 121     return d->regs[ichan].page;
 122 }
 123
 124 static uint32_t read_pageh (void *opaque, uint32_t nport)
 125 {
 126     struct dma_cont *d = opaque;
 127     int ichan;
 128
 129     ichan = channels[nport & 7];
 130     if (-1 == ichan) {
 131         dolog ("invalid channel read %#x\n", nport);
 132         return 0;
 133     }
 134     return d->regs[ichan].pageh;
 135 }
 136
 137 static inline void init_chan (struct dma_cont *d, int ichan)
 138 {
 139     struct dma_regs *r;
 140
 141     r = d->regs + ichan;
 142     r->now[ADDR] = r->base[ADDR] << d->dshift;
 143     r->now[COUNT] = 0;
 144 }
 145
 146 static inline int getff (struct dma_cont *d)
 147 {
 148     int ff;
 149
 150     ff = d->flip_flop;
 151     d->flip_flop = !ff;
 152     return ff;
 153 }
 154
 155 static uint32_t read_chan (void *opaque, uint32_t nport)
 156 {
 157     struct dma_cont *d = opaque;
 158     int ichan, nreg, iport, ff, val, dir;
 159     struct dma_regs *r;
 160
 161     iport = (nport >> d->dshift) & 0x0f;
 162     ichan = iport >> 1;
 163     nreg = iport & 1;
 164     r = d->regs + ichan;
 165
 166     dir = ((r->mode >> 5) & 1) ? -1 : 1;
 167     ff = getff (d);
 168     if (nreg)
 169         val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
 170     else
 171         val = r->now[ADDR] + r->now[COUNT] * dir;
 172
 173     ldebug ("read_chan %#x -> %d\n", iport, val);
 174     return (val >> (d->dshift + (ff << 3))) & 0xff;
 175 }
 176
 177 static void write_chan (void *opaque, uint32_t nport, uint32_t data)
 178 {
 179     struct dma_cont *d = opaque;
 180     int iport, ichan, nreg;
 181     struct dma_regs *r;
 182
 183     iport = (nport >> d->dshift) & 0x0f;
 184     ichan = iport >> 1;
 185     nreg = iport & 1;
 186     r = d->regs + ichan;
 187     if (getff (d)) {
 188         r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
 189         init_chan (d, ichan);
 190     } else {
 191         r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
 192     }
 193 }
 194
 195 static void write_cont (void *opaque, uint32_t nport, uint32_t data)
 196 {
 197     struct dma_cont *d = opaque;
 198     int iport, ichan = 0;
 199
 200     iport = (nport >> d->dshift) & 0x0f;
 201     switch (iport) {
 202     case 0x08:                  /* command */
 203         if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
 204             dolog ("command %#x not supported\n", data);
 205             return;
 206         }
 207         d->command = data;
 208         break;
 209
 210     case 0x09:
 211         ichan = data & 3;
 212         if (data & 4) {
 213             d->status |= 1 << (ichan + 4);
 214         }
 215         else {
 216             d->status &= ~(1 << (ichan + 4));
 217         }
 218         d->status &= ~(1 << ichan);
 219         DMA_run();
 220         break;
 221
 222     case 0x0a:                  /* single mask */
 223         if (data & 4)
 224             d->mask |= 1 << (data & 3);
 225         else
 226             d->mask &= ~(1 << (data & 3));
 227         DMA_run();
 228         break;
 229
 230     case 0x0b:                  /* mode */
 231         {
 232             ichan = data & 3;
 233 #ifdef DEBUG_DMA
 234             {
 235                 int op, ai, dir, opmode;
 236                 op = (data >> 2) & 3;
 237                 ai = (data >> 4) & 1;
 238                 dir = (data >> 5) & 1;
 239                 opmode = (data >> 6) & 3;
 240
 241                 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
 242                        ichan, op, ai, dir, opmode);
 243             }
 244 #endif
 245             d->regs[ichan].mode = data;
 246             break;
 247         }
 248
 249     case 0x0c:                  /* clear flip flop */
 250         d->flip_flop = 0;
 251         break;
 252
 253     case 0x0d:                  /* reset */
 254         d->flip_flop = 0;
 255         d->mask = ~0;
 256         d->status = 0;
 257         d->command = 0;
 258         break;
 259
 260     case 0x0e:                  /* clear mask for all channels */
 261         d->mask = 0;
 262         DMA_run();
 263         break;
 264
 265     case 0x0f:                  /* write mask for all channels */
 266         d->mask = data;
 267         DMA_run();
 268         break;
 269
 270     default:
 271         dolog ("unknown iport %#x\n", iport);
 272         break;
 273     }
 274
 275 #ifdef DEBUG_DMA
 276     if (0xc != iport) {
 277         linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
 278                nport, ichan, data);
 279     }
 280 #endif
 281 }
 282
 283 static uint32_t read_cont (void *opaque, uint32_t nport)
 284 {
 285     struct dma_cont *d = opaque;
 286     int iport, val;
 287
 288     iport = (nport >> d->dshift) & 0x0f;
 289     switch (iport) {
 290     case 0x08:                  /* status */
 291         val = d->status;
 292         d->status &= 0xf0;
 293         break;
 294     case 0x0f:                  /* mask */
 295         val = d->mask;
 296         break;
 297     default:
 298         val = 0;
 299         break;
 300     }
 301
 302     ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
 303     return val;
 304 }
 305
 306 int DMA_get_channel_mode (int nchan)
 307 {
 308     return dma_controllers[nchan > 3].regs[nchan & 3].mode;
 309 }
 310
 311 void DMA_hold_DREQ (int nchan)
 312 {
 313     int ncont, ichan;
 314
 315     ncont = nchan > 3;
 316     ichan = nchan & 3;
 317     linfo ("held cont=%d chan=%d\n", ncont, ichan);
 318     dma_controllers[ncont].status |= 1 << (ichan + 4);
 319     DMA_run();
 320 }
 321
 322 void DMA_release_DREQ (int nchan)
 323 {
 324     int ncont, ichan;
 325
 326     ncont = nchan > 3;
 327     ichan = nchan & 3;
 328     linfo ("released cont=%d chan=%d\n", ncont, ichan);
 329     dma_controllers[ncont].status &= ~(1 << (ichan + 4));
 330     DMA_run();
 331 }
 332
 333 static void channel_run (int ncont, int ichan)
 334 {
 335     int n;
 336     struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
 337 #ifdef DEBUG_DMA
 338     int dir, opmode;
 339
 340     dir = (r->mode >> 5) & 1;
 341     opmode = (r->mode >> 6) & 3;
 342
 343     if (dir) {
 344         dolog ("DMA in address decrement mode\n");
 345     }
 346     if (opmode != 1) {
 347         dolog ("DMA not in single mode select %#x\n", opmode);
 348     }
 349 #endif
 350
 351     r = dma_controllers[ncont].regs + ichan;
 352     n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
 353                              r->now[COUNT], (r->base[COUNT] + 1) << ncont);
 354     r->now[COUNT] = n;
 355     ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
 356 }
 357
 358 static QEMUBH *dma_bh;
 359
 360 static void DMA_run (void)
 361 {
 362     struct dma_cont *d;
 363     int icont, ichan;
 364     int rearm = 0;
 365
 366     d = dma_controllers;
 367
 368     for (icont = 0; icont < 2; icont++, d++) {
 369         for (ichan = 0; ichan < 4; ichan++) {
 370             int mask;
 371
 372             mask = 1 << ichan;
 373
 374             if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
 375                 channel_run (icont, ichan);
 376                 rearm = 1;
 377             }
 378         }
 379     }
 380
 381     if (rearm)
 382         qemu_bh_schedule_idle(dma_bh);
 383 }
 384
 385 static void DMA_run_bh(void *unused)
 386 {
 387     DMA_run();
 388 }
 389
 390 void DMA_register_channel (int nchan,
 391                            DMA_transfer_handler transfer_handler,
 392                            void *opaque)
 393 {
 394     struct dma_regs *r;
 395     int ichan, ncont;
 396
 397     ncont = nchan > 3;
 398     ichan = nchan & 3;
 399
 400     r = dma_controllers[ncont].regs + ichan;
 401     r->transfer_handler = transfer_handler;
 402     r->opaque = opaque;
 403 }
 404
 405 int DMA_read_memory (int nchan, void *buf, int pos, int len)
 406 {
 407     struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
 408     target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 409
 410     if (r->mode & 0x20) {
 411         int i;
 412         uint8_t *p = buf;
 413
 414         cpu_physical_memory_read (addr - pos - len, buf, len);
 415         /* What about 16bit transfers? */
 416         for (i = 0; i < len >> 1; i++) {
 417             uint8_t b = p[len - i - 1];
 418             p[i] = b;
 419         }
 420     }
 421     else
 422         cpu_physical_memory_read (addr + pos, buf, len);
 423
 424     return len;
 425 }
 426
 427 int DMA_write_memory (int nchan, void *buf, int pos, int len)
 428 {
 429     struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
 430     target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 431
 432     if (r->mode & 0x20) {
 433         int i;
 434         uint8_t *p = buf;
 435
 436         cpu_physical_memory_write (addr - pos - len, buf, len);
 437         /* What about 16bit transfers? */
 438         for (i = 0; i < len; i++) {
 439             uint8_t b = p[len - i - 1];
 440             p[i] = b;
 441         }
 442     }
 443     else
 444         cpu_physical_memory_write (addr + pos, buf, len);
 445
 446     return len;
 447 }
 448
 449 /* request the emulator to transfer a new DMA memory block ASAP */
 450 void DMA_schedule(int nchan)
 451 {
 452     CPUState *env = cpu_single_env;
 453     if (env)
 454         cpu_interrupt(env, CPU_INTERRUPT_EXIT);
 455 }
 456
 457 static void dma_reset(void *opaque)
 458 {
 459     struct dma_cont *d = opaque;
 460     write_cont (d, (0x0d << d->dshift), 0);
 461 }
 462
 463 static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
 464 {
 465     dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
 466            nchan, dma_pos, dma_len);
 467     return dma_pos;
 468 }
 469
 470 /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
 471 static void dma_init2(struct dma_cont *d, int base, int dshift,
 472                       int page_base, int pageh_base)
 473 {
 474     static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
 475     int i;
 476
 477     d->dshift = dshift;
 478     for (i = 0; i < 8; i++) {
 479         register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
 480         register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
 481     }
 482     for (i = 0; i < LENOFA (page_port_list); i++) {
 483         register_ioport_write (page_base + page_port_list[i], 1, 1,
 484                                write_page, d);
 485         register_ioport_read (page_base + page_port_list[i], 1, 1,
 486                               read_page, d);
 487         if (pageh_base >= 0) {
 488             register_ioport_write (pageh_base + page_port_list[i], 1, 1,
 489                                    write_pageh, d);
 490             register_ioport_read (pageh_base + page_port_list[i], 1, 1,
 491                                   read_pageh, d);
 492         }
 493     }
 494     for (i = 0; i < 8; i++) {
 495         register_ioport_write (base + ((i + 8) << dshift), 1, 1,
 496                                write_cont, d);
 497         register_ioport_read (base + ((i + 8) << dshift), 1, 1,
 498                               read_cont, d);
 499     }
 500     qemu_register_reset(dma_reset, d);
 501     dma_reset(d);
 502     for (i = 0; i < LENOFA (d->regs); ++i) {
 503         d->regs[i].transfer_handler = dma_phony_handler;
 504     }
 505 }
 506
 507 static void dma_save (QEMUFile *f, void *opaque)
 508 {
 509     struct dma_cont *d = opaque;
 510     int i;
 511
 512     /* qemu_put_8s (f, &d->status); */
 513     qemu_put_8s (f, &d->command);
 514     qemu_put_8s (f, &d->mask);
 515     qemu_put_8s (f, &d->flip_flop);
 516     qemu_put_be32 (f, d->dshift);
 517
 518     for (i = 0; i < 4; ++i) {
 519         struct dma_regs *r = &d->regs[i];
 520         qemu_put_be32 (f, r->now[0]);
 521         qemu_put_be32 (f, r->now[1]);
 522         qemu_put_be16s (f, &r->base[0]);
 523         qemu_put_be16s (f, &r->base[1]);
 524         qemu_put_8s (f, &r->mode);
 525         qemu_put_8s (f, &r->page);
 526         qemu_put_8s (f, &r->pageh);
 527         qemu_put_8s (f, &r->dack);
 528         qemu_put_8s (f, &r->eop);
 529     }
 530 }
 531
 532 static int dma_load (QEMUFile *f, void *opaque, int version_id)
 533 {
 534     struct dma_cont *d = opaque;
 535     int i;
 536
 537     if (version_id != 1)
 538         return -EINVAL;
 539
 540     /* qemu_get_8s (f, &d->status); */
 541     qemu_get_8s (f, &d->command);
 542     qemu_get_8s (f, &d->mask);
 543     qemu_get_8s (f, &d->flip_flop);
 544     d->dshift=qemu_get_be32 (f);
 545
 546     for (i = 0; i < 4; ++i) {
 547         struct dma_regs *r = &d->regs[i];
 548         r->now[0]=qemu_get_be32 (f);
 549         r->now[1]=qemu_get_be32 (f);
 550         qemu_get_be16s (f, &r->base[0]);
 551         qemu_get_be16s (f, &r->base[1]);
 552         qemu_get_8s (f, &r->mode);
 553         qemu_get_8s (f, &r->page);
 554         qemu_get_8s (f, &r->pageh);
 555         qemu_get_8s (f, &r->dack);
 556         qemu_get_8s (f, &r->eop);
 557     }
 558
 559     DMA_run();
 560
 561     return 0;
 562 }
 563
 564 void DMA_init (int high_page_enable)
 565 {
 566     dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
 567               high_page_enable ? 0x480 : -1);
 568     dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
 569               high_page_enable ? 0x488 : -1);
 570     register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]);
 571     register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]);
 572
 573     dma_bh = qemu_bh_new(DMA_run_bh, NULL);
 574 }