?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-ppc: Remove a few TCG temp variable leaks
[qemu/qemu-JZ.git] / linux-user / main.c
bloba5aefce3dc244d1b3aa8c646d49f7e4a633ac37e
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <stdarg.h>
23 #include <string.h>
24 #include <errno.h>
25 #include <unistd.h>
26
27 #include "qemu.h"
28 #include "qemu-common.h"
29 /* For tb_lock */
30 #include "exec-all.h"
31
32 #define DEBUG_LOGFILE "/tmp/qemu.log"
33
34 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
35 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
36
37 #if defined(__i386__) && !defined(CONFIG_STATIC)
38 /* Force usage of an ELF interpreter even if it is an ELF shared
39 object ! */
40 const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2";
41 #endif
42
43 /* for recent libc, we add these dummy symbols which are not declared
44 when generating a linked object (bug in ld ?) */
45 #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC)
46 asm(".globl __preinit_array_start\n"
47 ".globl __preinit_array_end\n"
48 ".globl __init_array_start\n"
49 ".globl __init_array_end\n"
50 ".globl __fini_array_start\n"
51 ".globl __fini_array_end\n"
52 ".section \".rodata\"\n"
53 "__preinit_array_start:\n"
54 "__preinit_array_end:\n"
55 "__init_array_start:\n"
56 "__init_array_end:\n"
57 "__fini_array_start:\n"
58 "__fini_array_end:\n"
59 ".long 0\n"
60 ".previous\n");
61 #endif
62
63 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
64 we allocate a bigger stack. Need a better solution, for example
65 by remapping the process stack directly at the right place */
66 unsigned long x86_stack_size = 512 * 1024;
67
68 void gemu_log(const char *fmt, ...)
69 {
70 va_list ap;
71
72 va_start(ap, fmt);
73 vfprintf(stderr, fmt, ap);
74 va_end(ap);
75 }
76
77 void cpu_outb(CPUState *env, int addr, int val)
78 {
79 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
80 }
81
82 void cpu_outw(CPUState *env, int addr, int val)
83 {
84 fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val);
85 }
86
87 void cpu_outl(CPUState *env, int addr, int val)
88 {
89 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
90 }
91
92 int cpu_inb(CPUState *env, int addr)
93 {
94 fprintf(stderr, "inb: port=0x%04x\n", addr);
95 return 0;
96 }
97
98 int cpu_inw(CPUState *env, int addr)
99 {
100 fprintf(stderr, "inw: port=0x%04x\n", addr);
101 return 0;
102 }
103
104 int cpu_inl(CPUState *env, int addr)
105 {
106 fprintf(stderr, "inl: port=0x%04x\n", addr);
107 return 0;
108 }
109
110 #if defined(TARGET_I386)
111 int cpu_get_pic_interrupt(CPUState *env)
112 {
113 return -1;
114 }
115 #endif
116
117 /* timers for rdtsc */
118
119 #if 0
120
121 static uint64_t emu_time;
122
123 int64_t cpu_get_real_ticks(void)
124 {
125 return emu_time++;
126 }
127
128 #endif
129
130 #if defined(USE_NPTL)
131 /***********************************************************/
132 /* Helper routines for implementing atomic operations. */
133
134 /* To implement exclusive operations we force all cpus to syncronise.
135 We don't require a full sync, only that no cpus are executing guest code.
136 The alternative is to map target atomic ops onto host equivalents,
137 which requires quite a lot of per host/target work. */
138 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
139 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
140 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
141 static int pending_cpus;
142
143 /* Make sure everything is in a consistent state for calling fork(). */
144 void fork_start(void)
145 {
146 mmap_fork_start();
147 pthread_mutex_lock(&tb_lock);
148 pthread_mutex_lock(&exclusive_lock);
149 }
150
151 void fork_end(int child)
152 {
153 if (child) {
154 /* Child processes created by fork() only have a single thread.
155 Discard information about the parent threads. */
156 first_cpu = thread_env;
157 thread_env->next_cpu = NULL;
158 pending_cpus = 0;
159 pthread_mutex_init(&exclusive_lock, NULL);
160 pthread_cond_init(&exclusive_cond, NULL);
161 pthread_cond_init(&exclusive_resume, NULL);
162 pthread_mutex_init(&tb_lock, NULL);
163 } else {
164 pthread_mutex_unlock(&exclusive_lock);
165 pthread_mutex_unlock(&tb_lock);
166 }
167 mmap_fork_end(child);
168 }
169
170 /* Wait for pending exclusive operations to complete. The exclusive lock
171 must be held. */
172 static inline void exclusive_idle(void)
173 {
174 while (pending_cpus) {
175 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
176 }
177 }
178
179 /* Start an exclusive operation.
180 Must only be called from outside cpu_arm_exec. */
181 static inline void start_exclusive(void)
182 {
183 CPUState *other;
184 pthread_mutex_lock(&exclusive_lock);
185 exclusive_idle();
186
187 pending_cpus = 1;
188 /* Make all other cpus stop executing. */
189 for (other = first_cpu; other; other = other->next_cpu) {
190 if (other->running) {
191 pending_cpus++;
192 cpu_interrupt(other, CPU_INTERRUPT_EXIT);
193 }
194 }
195 if (pending_cpus > 1) {
196 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
197 }
198 }
199
200 /* Finish an exclusive operation. */
201 static inline void end_exclusive(void)
202 {
203 pending_cpus = 0;
204 pthread_cond_broadcast(&exclusive_resume);
205 pthread_mutex_unlock(&exclusive_lock);
206 }
207
208 /* Wait for exclusive ops to finish, and begin cpu execution. */
209 static inline void cpu_exec_start(CPUState *env)
210 {
211 pthread_mutex_lock(&exclusive_lock);
212 exclusive_idle();
213 env->running = 1;
214 pthread_mutex_unlock(&exclusive_lock);
215 }
216
217 /* Mark cpu as not executing, and release pending exclusive ops. */
218 static inline void cpu_exec_end(CPUState *env)
219 {
220 pthread_mutex_lock(&exclusive_lock);
221 env->running = 0;
222 if (pending_cpus > 1) {
223 pending_cpus--;
224 if (pending_cpus == 1) {
225 pthread_cond_signal(&exclusive_cond);
226 }
227 }
228 exclusive_idle();
229 pthread_mutex_unlock(&exclusive_lock);
230 }
231 #else /* if !USE_NPTL */
232 /* These are no-ops because we are not threadsafe. */
233 static inline void cpu_exec_start(CPUState *env)
234 {
235 }
236
237 static inline void cpu_exec_end(CPUState *env)
238 {
239 }
240
241 static inline void start_exclusive(void)
242 {
243 }
244
245 static inline void end_exclusive(void)
246 {
247 }
248
249 void fork_start(void)
250 {
251 }
252
253 void fork_end(int child)
254 {
255 }
256 #endif
257
258
259 #ifdef TARGET_I386
260 /***********************************************************/
261 /* CPUX86 core interface */
262
263 void cpu_smm_update(CPUState *env)
264 {
265 }
266
267 uint64_t cpu_get_tsc(CPUX86State *env)
268 {
269 return cpu_get_real_ticks();
270 }
271
272 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
273 int flags)
274 {
275 unsigned int e1, e2;
276 uint32_t *p;
277 e1 = (addr << 16) | (limit & 0xffff);
278 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
279 e2 |= flags;
280 p = ptr;
281 p[0] = tswap32(e1);
282 p[1] = tswap32(e2);
283 }
284
285 #ifdef TARGET_X86_64
286 static uint64_t idt_table[512];
287
288 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
289 uint64_t addr, unsigned int sel)
290 {
291 uint32_t *p, e1, e2;
292 e1 = (addr & 0xffff) | (sel << 16);
293 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
294 p = ptr;
295 p[0] = tswap32(e1);
296 p[1] = tswap32(e2);
297 p[2] = tswap32(addr >> 32);
298 p[3] = 0;
299 }
300 /* only dpl matters as we do only user space emulation */
301 static void set_idt(int n, unsigned int dpl)
302 {
303 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
304 }
305 #else
306 static uint64_t idt_table[256];
307
308 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
309 uint32_t addr, unsigned int sel)
310 {
311 uint32_t *p, e1, e2;
312 e1 = (addr & 0xffff) | (sel << 16);
313 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
314 p = ptr;
315 p[0] = tswap32(e1);
316 p[1] = tswap32(e2);
317 }
318
319 /* only dpl matters as we do only user space emulation */
320 static void set_idt(int n, unsigned int dpl)
321 {
322 set_gate(idt_table + n, 0, dpl, 0, 0);
323 }
324 #endif
325
326 void cpu_loop(CPUX86State *env)
327 {
328 int trapnr;
329 abi_ulong pc;
330 target_siginfo_t info;
331
332 for(;;) {
333 trapnr = cpu_x86_exec(env);
334 switch(trapnr) {
335 case 0x80:
336 /* linux syscall from int $0x80 */
337 env->regs[R_EAX] = do_syscall(env,
338 env->regs[R_EAX],
339 env->regs[R_EBX],
340 env->regs[R_ECX],
341 env->regs[R_EDX],
342 env->regs[R_ESI],
343 env->regs[R_EDI],
344 env->regs[R_EBP]);
345 break;
346 #ifndef TARGET_ABI32
347 case EXCP_SYSCALL:
348 /* linux syscall from syscall intruction */
349 env->regs[R_EAX] = do_syscall(env,
350 env->regs[R_EAX],
351 env->regs[R_EDI],
352 env->regs[R_ESI],
353 env->regs[R_EDX],
354 env->regs[10],
355 env->regs[8],
356 env->regs[9]);
357 env->eip = env->exception_next_eip;
358 break;
359 #endif
360 case EXCP0B_NOSEG:
361 case EXCP0C_STACK:
362 info.si_signo = SIGBUS;
363 info.si_errno = 0;
364 info.si_code = TARGET_SI_KERNEL;
365 info._sifields._sigfault._addr = 0;
366 queue_signal(env, info.si_signo, &info);
367 break;
368 case EXCP0D_GPF:
369 /* XXX: potential problem if ABI32 */
370 #ifndef TARGET_X86_64
371 if (env->eflags & VM_MASK) {
372 handle_vm86_fault(env);
373 } else
374 #endif
375 {
376 info.si_signo = SIGSEGV;
377 info.si_errno = 0;
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 queue_signal(env, info.si_signo, &info);
381 }
382 break;
383 case EXCP0E_PAGE:
384 info.si_signo = SIGSEGV;
385 info.si_errno = 0;
386 if (!(env->error_code & 1))
387 info.si_code = TARGET_SEGV_MAPERR;
388 else
389 info.si_code = TARGET_SEGV_ACCERR;
390 info._sifields._sigfault._addr = env->cr[2];
391 queue_signal(env, info.si_signo, &info);
392 break;
393 case EXCP00_DIVZ:
394 #ifndef TARGET_X86_64
395 if (env->eflags & VM_MASK) {
396 handle_vm86_trap(env, trapnr);
397 } else
398 #endif
399 {
400 /* division by zero */
401 info.si_signo = SIGFPE;
402 info.si_errno = 0;
403 info.si_code = TARGET_FPE_INTDIV;
404 info._sifields._sigfault._addr = env->eip;
405 queue_signal(env, info.si_signo, &info);
406 }
407 break;
408 case EXCP01_SSTP:
409 case EXCP03_INT3:
410 #ifndef TARGET_X86_64
411 if (env->eflags & VM_MASK) {
412 handle_vm86_trap(env, trapnr);
413 } else
414 #endif
415 {
416 info.si_signo = SIGTRAP;
417 info.si_errno = 0;
418 if (trapnr == EXCP01_SSTP) {
419 info.si_code = TARGET_TRAP_BRKPT;
420 info._sifields._sigfault._addr = env->eip;
421 } else {
422 info.si_code = TARGET_SI_KERNEL;
423 info._sifields._sigfault._addr = 0;
424 }
425 queue_signal(env, info.si_signo, &info);
426 }
427 break;
428 case EXCP04_INTO:
429 case EXCP05_BOUND:
430 #ifndef TARGET_X86_64
431 if (env->eflags & VM_MASK) {
432 handle_vm86_trap(env, trapnr);
433 } else
434 #endif
435 {
436 info.si_signo = SIGSEGV;
437 info.si_errno = 0;
438 info.si_code = TARGET_SI_KERNEL;
439 info._sifields._sigfault._addr = 0;
440 queue_signal(env, info.si_signo, &info);
441 }
442 break;
443 case EXCP06_ILLOP:
444 info.si_signo = SIGILL;
445 info.si_errno = 0;
446 info.si_code = TARGET_ILL_ILLOPN;
447 info._sifields._sigfault._addr = env->eip;
448 queue_signal(env, info.si_signo, &info);
449 break;
450 case EXCP_INTERRUPT:
451 /* just indicate that signals should be handled asap */
452 break;
453 case EXCP_DEBUG:
454 {
455 int sig;
456
457 sig = gdb_handlesig (env, TARGET_SIGTRAP);
458 if (sig)
459 {
460 info.si_signo = sig;
461 info.si_errno = 0;
462 info.si_code = TARGET_TRAP_BRKPT;
463 queue_signal(env, info.si_signo, &info);
464 }
465 }
466 break;
467 default:
468 pc = env->segs[R_CS].base + env->eip;
469 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
470 (long)pc, trapnr);
471 abort();
472 }
473 process_pending_signals(env);
474 }
475 }
476 #endif
477
478 #ifdef TARGET_ARM
479
480 static void arm_cache_flush(abi_ulong start, abi_ulong last)
481 {
482 abi_ulong addr, last1;
483
484 if (last < start)
485 return;
486 addr = start;
487 for(;;) {
488 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
489 if (last1 > last)
490 last1 = last;
491 tb_invalidate_page_range(addr, last1 + 1);
492 if (last1 == last)
493 break;
494 addr = last1 + 1;
495 }
496 }
497
498 /* Handle a jump to the kernel code page. */
499 static int
500 do_kernel_trap(CPUARMState *env)
501 {
502 uint32_t addr;
503 uint32_t cpsr;
504 uint32_t val;
505
506 switch (env->regs[15]) {
507 case 0xffff0fa0: /* __kernel_memory_barrier */
508 /* ??? No-op. Will need to do better for SMP. */
509 break;
510 case 0xffff0fc0: /* __kernel_cmpxchg */
511 /* XXX: This only works between threads, not between processes.
512 It's probably possible to implement this with native host
513 operations. However things like ldrex/strex are much harder so
514 there's not much point trying. */
515 start_exclusive();
516 cpsr = cpsr_read(env);
517 addr = env->regs[2];
518 /* FIXME: This should SEGV if the access fails. */
519 if (get_user_u32(val, addr))
520 val = ~env->regs[0];
521 if (val == env->regs[0]) {
522 val = env->regs[1];
523 /* FIXME: Check for segfaults. */
524 put_user_u32(val, addr);
525 env->regs[0] = 0;
526 cpsr |= CPSR_C;
527 } else {
528 env->regs[0] = -1;
529 cpsr &= ~CPSR_C;
530 }
531 cpsr_write(env, cpsr, CPSR_C);
532 end_exclusive();
533 break;
534 case 0xffff0fe0: /* __kernel_get_tls */
535 env->regs[0] = env->cp15.c13_tls2;
536 break;
537 default:
538 return 1;
539 }
540 /* Jump back to the caller. */
541 addr = env->regs[14];
542 if (addr & 1) {
543 env->thumb = 1;
544 addr &= ~1;
545 }
546 env->regs[15] = addr;
547
548 return 0;
549 }
550
551 void cpu_loop(CPUARMState *env)
552 {
553 int trapnr;
554 unsigned int n, insn;
555 target_siginfo_t info;
556 uint32_t addr;
557
558 for(;;) {
559 cpu_exec_start(env);
560 trapnr = cpu_arm_exec(env);
561 cpu_exec_end(env);
562 switch(trapnr) {
563 case EXCP_UDEF:
564 {
565 TaskState *ts = env->opaque;
566 uint32_t opcode;
567 int rc;
568
569 /* we handle the FPU emulation here, as Linux */
570 /* we get the opcode */
571 /* FIXME - what to do if get_user() fails? */
572 get_user_u32(opcode, env->regs[15]);
573
574 rc = EmulateAll(opcode, &ts->fpa, env);
575 if (rc == 0) { /* illegal instruction */
576 info.si_signo = SIGILL;
577 info.si_errno = 0;
578 info.si_code = TARGET_ILL_ILLOPN;
579 info._sifields._sigfault._addr = env->regs[15];
580 queue_signal(env, info.si_signo, &info);
581 } else if (rc < 0) { /* FP exception */
582 int arm_fpe=0;
583
584 /* translate softfloat flags to FPSR flags */
585 if (-rc & float_flag_invalid)
586 arm_fpe |= BIT_IOC;
587 if (-rc & float_flag_divbyzero)
588 arm_fpe |= BIT_DZC;
589 if (-rc & float_flag_overflow)
590 arm_fpe |= BIT_OFC;
591 if (-rc & float_flag_underflow)
592 arm_fpe |= BIT_UFC;
593 if (-rc & float_flag_inexact)
594 arm_fpe |= BIT_IXC;
595
596 FPSR fpsr = ts->fpa.fpsr;
597 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
598
599 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
600 info.si_signo = SIGFPE;
601 info.si_errno = 0;
602
603 /* ordered by priority, least first */
604 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
605 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
606 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
607 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
608 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
609
610 info._sifields._sigfault._addr = env->regs[15];
611 queue_signal(env, info.si_signo, &info);
612 } else {
613 env->regs[15] += 4;
614 }
615
616 /* accumulate unenabled exceptions */
617 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
618 fpsr |= BIT_IXC;
619 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
620 fpsr |= BIT_UFC;
621 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
622 fpsr |= BIT_OFC;
623 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
624 fpsr |= BIT_DZC;
625 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
626 fpsr |= BIT_IOC;
627 ts->fpa.fpsr=fpsr;
628 } else { /* everything OK */
629 /* increment PC */
630 env->regs[15] += 4;
631 }
632 }
633 break;
634 case EXCP_SWI:
635 case EXCP_BKPT:
636 {
637 env->eabi = 1;
638 /* system call */
639 if (trapnr == EXCP_BKPT) {
640 if (env->thumb) {
641 /* FIXME - what to do if get_user() fails? */
642 get_user_u16(insn, env->regs[15]);
643 n = insn & 0xff;
644 env->regs[15] += 2;
645 } else {
646 /* FIXME - what to do if get_user() fails? */
647 get_user_u32(insn, env->regs[15]);
648 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
649 env->regs[15] += 4;
650 }
651 } else {
652 if (env->thumb) {
653 /* FIXME - what to do if get_user() fails? */
654 get_user_u16(insn, env->regs[15] - 2);
655 n = insn & 0xff;
656 } else {
657 /* FIXME - what to do if get_user() fails? */
658 get_user_u32(insn, env->regs[15] - 4);
659 n = insn & 0xffffff;
660 }
661 }
662
663 if (n == ARM_NR_cacheflush) {
664 arm_cache_flush(env->regs[0], env->regs[1]);
665 } else if (n == ARM_NR_semihosting
666 || n == ARM_NR_thumb_semihosting) {
667 env->regs[0] = do_arm_semihosting (env);
668 } else if (n == 0 || n >= ARM_SYSCALL_BASE
669 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
670 /* linux syscall */
671 if (env->thumb || n == 0) {
672 n = env->regs[7];
673 } else {
674 n -= ARM_SYSCALL_BASE;
675 env->eabi = 0;
676 }
677 if ( n > ARM_NR_BASE) {
678 switch (n) {
679 case ARM_NR_cacheflush:
680 arm_cache_flush(env->regs[0], env->regs[1]);
681 break;
682 case ARM_NR_set_tls:
683 cpu_set_tls(env, env->regs[0]);
684 env->regs[0] = 0;
685 break;
686 default:
687 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
688 n);
689 env->regs[0] = -TARGET_ENOSYS;
690 break;
691 }
692 } else {
693 env->regs[0] = do_syscall(env,
694 n,
695 env->regs[0],
696 env->regs[1],
697 env->regs[2],
698 env->regs[3],
699 env->regs[4],
700 env->regs[5]);
701 }
702 } else {
703 goto error;
704 }
705 }
706 break;
707 case EXCP_INTERRUPT:
708 /* just indicate that signals should be handled asap */
709 break;
710 case EXCP_PREFETCH_ABORT:
711 addr = env->cp15.c6_insn;
712 goto do_segv;
713 case EXCP_DATA_ABORT:
714 addr = env->cp15.c6_data;
715 goto do_segv;
716 do_segv:
717 {
718 info.si_signo = SIGSEGV;
719 info.si_errno = 0;
720 /* XXX: check env->error_code */
721 info.si_code = TARGET_SEGV_MAPERR;
722 info._sifields._sigfault._addr = addr;
723 queue_signal(env, info.si_signo, &info);
724 }
725 break;
726 case EXCP_DEBUG:
727 {
728 int sig;
729
730 sig = gdb_handlesig (env, TARGET_SIGTRAP);
731 if (sig)
732 {
733 info.si_signo = sig;
734 info.si_errno = 0;
735 info.si_code = TARGET_TRAP_BRKPT;
736 queue_signal(env, info.si_signo, &info);
737 }
738 }
739 break;
740 case EXCP_KERNEL_TRAP:
741 if (do_kernel_trap(env))
742 goto error;
743 break;
744 default:
745 error:
746 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
747 trapnr);
748 cpu_dump_state(env, stderr, fprintf, 0);
749 abort();
750 }
751 process_pending_signals(env);
752 }
753 }
754
755 #endif
756
757 #ifdef TARGET_SPARC
758 #define SPARC64_STACK_BIAS 2047
759
760 //#define DEBUG_WIN
761
762 /* WARNING: dealing with register windows _is_ complicated. More info
763 can be found at http://www.sics.se/~psm/sparcstack.html */
764 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
765 {
766 index = (index + cwp * 16) % (16 * env->nwindows);
767 /* wrap handling : if cwp is on the last window, then we use the
768 registers 'after' the end */
769 if (index < 8 && env->cwp == env->nwindows - 1)
770 index += 16 * env->nwindows;
771 return index;
772 }
773
774 /* save the register window 'cwp1' */
775 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
776 {
777 unsigned int i;
778 abi_ulong sp_ptr;
779
780 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
781 #ifdef TARGET_SPARC64
782 if (sp_ptr & 3)
783 sp_ptr += SPARC64_STACK_BIAS;
784 #endif
785 #if defined(DEBUG_WIN)
786 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
787 sp_ptr, cwp1);
788 #endif
789 for(i = 0; i < 16; i++) {
790 /* FIXME - what to do if put_user() fails? */
791 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
792 sp_ptr += sizeof(abi_ulong);
793 }
794 }
795
796 static void save_window(CPUSPARCState *env)
797 {
798 #ifndef TARGET_SPARC64
799 unsigned int new_wim;
800 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
801 ((1LL << env->nwindows) - 1);
802 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
803 env->wim = new_wim;
804 #else
805 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
806 env->cansave++;
807 env->canrestore--;
808 #endif
809 }
810
811 static void restore_window(CPUSPARCState *env)
812 {
813 #ifndef TARGET_SPARC64
814 unsigned int new_wim;
815 #endif
816 unsigned int i, cwp1;
817 abi_ulong sp_ptr;
818
819 #ifndef TARGET_SPARC64
820 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
821 ((1LL << env->nwindows) - 1);
822 #endif
823
824 /* restore the invalid window */
825 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
826 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
827 #ifdef TARGET_SPARC64
828 if (sp_ptr & 3)
829 sp_ptr += SPARC64_STACK_BIAS;
830 #endif
831 #if defined(DEBUG_WIN)
832 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
833 sp_ptr, cwp1);
834 #endif
835 for(i = 0; i < 16; i++) {
836 /* FIXME - what to do if get_user() fails? */
837 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
838 sp_ptr += sizeof(abi_ulong);
839 }
840 #ifdef TARGET_SPARC64
841 env->canrestore++;
842 if (env->cleanwin < env->nwindows - 1)
843 env->cleanwin++;
844 env->cansave--;
845 #else
846 env->wim = new_wim;
847 #endif
848 }
849
850 static void flush_windows(CPUSPARCState *env)
851 {
852 int offset, cwp1;
853
854 offset = 1;
855 for(;;) {
856 /* if restore would invoke restore_window(), then we can stop */
857 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
858 #ifndef TARGET_SPARC64
859 if (env->wim & (1 << cwp1))
860 break;
861 #else
862 if (env->canrestore == 0)
863 break;
864 env->cansave++;
865 env->canrestore--;
866 #endif
867 save_window_offset(env, cwp1);
868 offset++;
869 }
870 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
871 #ifndef TARGET_SPARC64
872 /* set wim so that restore will reload the registers */
873 env->wim = 1 << cwp1;
874 #endif
875 #if defined(DEBUG_WIN)
876 printf("flush_windows: nb=%d\n", offset - 1);
877 #endif
878 }
879
880 void cpu_loop (CPUSPARCState *env)
881 {
882 int trapnr, ret;
883 target_siginfo_t info;
884
885 while (1) {
886 trapnr = cpu_sparc_exec (env);
887
888 switch (trapnr) {
889 #ifndef TARGET_SPARC64
890 case 0x88:
891 case 0x90:
892 #else
893 case 0x110:
894 case 0x16d:
895 #endif
896 ret = do_syscall (env, env->gregs[1],
897 env->regwptr[0], env->regwptr[1],
898 env->regwptr[2], env->regwptr[3],
899 env->regwptr[4], env->regwptr[5]);
900 if ((unsigned int)ret >= (unsigned int)(-515)) {
901 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
902 env->xcc |= PSR_CARRY;
903 #else
904 env->psr |= PSR_CARRY;
905 #endif
906 ret = -ret;
907 } else {
908 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
909 env->xcc &= ~PSR_CARRY;
910 #else
911 env->psr &= ~PSR_CARRY;
912 #endif
913 }
914 env->regwptr[0] = ret;
915 /* next instruction */
916 env->pc = env->npc;
917 env->npc = env->npc + 4;
918 break;
919 case 0x83: /* flush windows */
920 #ifdef TARGET_ABI32
921 case 0x103:
922 #endif
923 flush_windows(env);
924 /* next instruction */
925 env->pc = env->npc;
926 env->npc = env->npc + 4;
927 break;
928 #ifndef TARGET_SPARC64
929 case TT_WIN_OVF: /* window overflow */
930 save_window(env);
931 break;
932 case TT_WIN_UNF: /* window underflow */
933 restore_window(env);
934 break;
935 case TT_TFAULT:
936 case TT_DFAULT:
937 {
938 info.si_signo = SIGSEGV;
939 info.si_errno = 0;
940 /* XXX: check env->error_code */
941 info.si_code = TARGET_SEGV_MAPERR;
942 info._sifields._sigfault._addr = env->mmuregs[4];
943 queue_signal(env, info.si_signo, &info);
944 }
945 break;
946 #else
947 case TT_SPILL: /* window overflow */
948 save_window(env);
949 break;
950 case TT_FILL: /* window underflow */
951 restore_window(env);
952 break;
953 case TT_TFAULT:
954 case TT_DFAULT:
955 {
956 info.si_signo = SIGSEGV;
957 info.si_errno = 0;
958 /* XXX: check env->error_code */
959 info.si_code = TARGET_SEGV_MAPERR;
960 if (trapnr == TT_DFAULT)
961 info._sifields._sigfault._addr = env->dmmuregs[4];
962 else
963 info._sifields._sigfault._addr = env->tsptr->tpc;
964 queue_signal(env, info.si_signo, &info);
965 }
966 break;
967 #ifndef TARGET_ABI32
968 case 0x16e:
969 flush_windows(env);
970 sparc64_get_context(env);
971 break;
972 case 0x16f:
973 flush_windows(env);
974 sparc64_set_context(env);
975 break;
976 #endif
977 #endif
978 case EXCP_INTERRUPT:
979 /* just indicate that signals should be handled asap */
980 break;
981 case EXCP_DEBUG:
982 {
983 int sig;
984
985 sig = gdb_handlesig (env, TARGET_SIGTRAP);
986 if (sig)
987 {
988 info.si_signo = sig;
989 info.si_errno = 0;
990 info.si_code = TARGET_TRAP_BRKPT;
991 queue_signal(env, info.si_signo, &info);
992 }
993 }
994 break;
995 default:
996 printf ("Unhandled trap: 0x%x\n", trapnr);
997 cpu_dump_state(env, stderr, fprintf, 0);
998 exit (1);
999 }
1000 process_pending_signals (env);
1001 }
1002 }
1003
1004 #endif
1005
1006 #ifdef TARGET_PPC
1007 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1008 {
1009 /* TO FIX */
1010 return 0;
1011 }
1012
1013 uint32_t cpu_ppc_load_tbl (CPUState *env)
1014 {
1015 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1016 }
1017
1018 uint32_t cpu_ppc_load_tbu (CPUState *env)
1019 {
1020 return cpu_ppc_get_tb(env) >> 32;
1021 }
1022
1023 uint32_t cpu_ppc_load_atbl (CPUState *env)
1024 {
1025 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1026 }
1027
1028 uint32_t cpu_ppc_load_atbu (CPUState *env)
1029 {
1030 return cpu_ppc_get_tb(env) >> 32;
1031 }
1032
1033 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1034 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1035
1036 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1037 {
1038 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1039 }
1040
1041 /* XXX: to be fixed */
1042 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1043 {
1044 return -1;
1045 }
1046
1047 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1048 {
1049 return -1;
1050 }
1051
1052 #define EXCP_DUMP(env, fmt, args...) \
1053 do { \
1054 fprintf(stderr, fmt , ##args); \
1055 cpu_dump_state(env, stderr, fprintf, 0); \
1056 if (loglevel != 0) { \
1057 fprintf(logfile, fmt , ##args); \
1058 cpu_dump_state(env, logfile, fprintf, 0); \
1059 } \
1060 } while (0)
1061
1062 void cpu_loop(CPUPPCState *env)
1063 {
1064 target_siginfo_t info;
1065 int trapnr;
1066 uint32_t ret;
1067
1068 for(;;) {
1069 trapnr = cpu_ppc_exec(env);
1070 switch(trapnr) {
1071 case POWERPC_EXCP_NONE:
1072 /* Just go on */
1073 break;
1074 case POWERPC_EXCP_CRITICAL: /* Critical input */
1075 cpu_abort(env, "Critical interrupt while in user mode. "
1076 "Aborting\n");
1077 break;
1078 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1079 cpu_abort(env, "Machine check exception while in user mode. "
1080 "Aborting\n");
1081 break;
1082 case POWERPC_EXCP_DSI: /* Data storage exception */
1083 EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
1084 env->spr[SPR_DAR]);
1085 /* XXX: check this. Seems bugged */
1086 switch (env->error_code & 0xFF000000) {
1087 case 0x40000000:
1088 info.si_signo = TARGET_SIGSEGV;
1089 info.si_errno = 0;
1090 info.si_code = TARGET_SEGV_MAPERR;
1091 break;
1092 case 0x04000000:
1093 info.si_signo = TARGET_SIGILL;
1094 info.si_errno = 0;
1095 info.si_code = TARGET_ILL_ILLADR;
1096 break;
1097 case 0x08000000:
1098 info.si_signo = TARGET_SIGSEGV;
1099 info.si_errno = 0;
1100 info.si_code = TARGET_SEGV_ACCERR;
1101 break;
1102 default:
1103 /* Let's send a regular segfault... */
1104 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1105 env->error_code);
1106 info.si_signo = TARGET_SIGSEGV;
1107 info.si_errno = 0;
1108 info.si_code = TARGET_SEGV_MAPERR;
1109 break;
1110 }
1111 info._sifields._sigfault._addr = env->nip;
1112 queue_signal(env, info.si_signo, &info);
1113 break;
1114 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1115 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
1116 env->spr[SPR_SRR0]);
1117 /* XXX: check this */
1118 switch (env->error_code & 0xFF000000) {
1119 case 0x40000000:
1120 info.si_signo = TARGET_SIGSEGV;
1121 info.si_errno = 0;
1122 info.si_code = TARGET_SEGV_MAPERR;
1123 break;
1124 case 0x10000000:
1125 case 0x08000000:
1126 info.si_signo = TARGET_SIGSEGV;
1127 info.si_errno = 0;
1128 info.si_code = TARGET_SEGV_ACCERR;
1129 break;
1130 default:
1131 /* Let's send a regular segfault... */
1132 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1133 env->error_code);
1134 info.si_signo = TARGET_SIGSEGV;
1135 info.si_errno = 0;
1136 info.si_code = TARGET_SEGV_MAPERR;
1137 break;
1138 }
1139 info._sifields._sigfault._addr = env->nip - 4;
1140 queue_signal(env, info.si_signo, &info);
1141 break;
1142 case POWERPC_EXCP_EXTERNAL: /* External input */
1143 cpu_abort(env, "External interrupt while in user mode. "
1144 "Aborting\n");
1145 break;
1146 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1147 EXCP_DUMP(env, "Unaligned memory access\n");
1148 /* XXX: check this */
1149 info.si_signo = TARGET_SIGBUS;
1150 info.si_errno = 0;
1151 info.si_code = TARGET_BUS_ADRALN;
1152 info._sifields._sigfault._addr = env->nip - 4;
1153 queue_signal(env, info.si_signo, &info);
1154 break;
1155 case POWERPC_EXCP_PROGRAM: /* Program exception */
1156 /* XXX: check this */
1157 switch (env->error_code & ~0xF) {
1158 case POWERPC_EXCP_FP:
1159 EXCP_DUMP(env, "Floating point program exception\n");
1160 info.si_signo = TARGET_SIGFPE;
1161 info.si_errno = 0;
1162 switch (env->error_code & 0xF) {
1163 case POWERPC_EXCP_FP_OX:
1164 info.si_code = TARGET_FPE_FLTOVF;
1165 break;
1166 case POWERPC_EXCP_FP_UX:
1167 info.si_code = TARGET_FPE_FLTUND;
1168 break;
1169 case POWERPC_EXCP_FP_ZX:
1170 case POWERPC_EXCP_FP_VXZDZ:
1171 info.si_code = TARGET_FPE_FLTDIV;
1172 break;
1173 case POWERPC_EXCP_FP_XX:
1174 info.si_code = TARGET_FPE_FLTRES;
1175 break;
1176 case POWERPC_EXCP_FP_VXSOFT:
1177 info.si_code = TARGET_FPE_FLTINV;
1178 break;
1179 case POWERPC_EXCP_FP_VXSNAN:
1180 case POWERPC_EXCP_FP_VXISI:
1181 case POWERPC_EXCP_FP_VXIDI:
1182 case POWERPC_EXCP_FP_VXIMZ:
1183 case POWERPC_EXCP_FP_VXVC:
1184 case POWERPC_EXCP_FP_VXSQRT:
1185 case POWERPC_EXCP_FP_VXCVI:
1186 info.si_code = TARGET_FPE_FLTSUB;
1187 break;
1188 default:
1189 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1190 env->error_code);
1191 break;
1192 }
1193 break;
1194 case POWERPC_EXCP_INVAL:
1195 EXCP_DUMP(env, "Invalid instruction\n");
1196 info.si_signo = TARGET_SIGILL;
1197 info.si_errno = 0;
1198 switch (env->error_code & 0xF) {
1199 case POWERPC_EXCP_INVAL_INVAL:
1200 info.si_code = TARGET_ILL_ILLOPC;
1201 break;
1202 case POWERPC_EXCP_INVAL_LSWX:
1203 info.si_code = TARGET_ILL_ILLOPN;
1204 break;
1205 case POWERPC_EXCP_INVAL_SPR:
1206 info.si_code = TARGET_ILL_PRVREG;
1207 break;
1208 case POWERPC_EXCP_INVAL_FP:
1209 info.si_code = TARGET_ILL_COPROC;
1210 break;
1211 default:
1212 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1213 env->error_code & 0xF);
1214 info.si_code = TARGET_ILL_ILLADR;
1215 break;
1216 }
1217 break;
1218 case POWERPC_EXCP_PRIV:
1219 EXCP_DUMP(env, "Privilege violation\n");
1220 info.si_signo = TARGET_SIGILL;
1221 info.si_errno = 0;
1222 switch (env->error_code & 0xF) {
1223 case POWERPC_EXCP_PRIV_OPC:
1224 info.si_code = TARGET_ILL_PRVOPC;
1225 break;
1226 case POWERPC_EXCP_PRIV_REG:
1227 info.si_code = TARGET_ILL_PRVREG;
1228 break;
1229 default:
1230 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1231 env->error_code & 0xF);
1232 info.si_code = TARGET_ILL_PRVOPC;
1233 break;
1234 }
1235 break;
1236 case POWERPC_EXCP_TRAP:
1237 cpu_abort(env, "Tried to call a TRAP\n");
1238 break;
1239 default:
1240 /* Should not happen ! */
1241 cpu_abort(env, "Unknown program exception (%02x)\n",
1242 env->error_code);
1243 break;
1244 }
1245 info._sifields._sigfault._addr = env->nip - 4;
1246 queue_signal(env, info.si_signo, &info);
1247 break;
1248 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1249 EXCP_DUMP(env, "No floating point allowed\n");
1250 info.si_signo = TARGET_SIGILL;
1251 info.si_errno = 0;
1252 info.si_code = TARGET_ILL_COPROC;
1253 info._sifields._sigfault._addr = env->nip - 4;
1254 queue_signal(env, info.si_signo, &info);
1255 break;
1256 case POWERPC_EXCP_SYSCALL: /* System call exception */
1257 cpu_abort(env, "Syscall exception while in user mode. "
1258 "Aborting\n");
1259 break;
1260 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1261 EXCP_DUMP(env, "No APU instruction allowed\n");
1262 info.si_signo = TARGET_SIGILL;
1263 info.si_errno = 0;
1264 info.si_code = TARGET_ILL_COPROC;
1265 info._sifields._sigfault._addr = env->nip - 4;
1266 queue_signal(env, info.si_signo, &info);
1267 break;
1268 case POWERPC_EXCP_DECR: /* Decrementer exception */
1269 cpu_abort(env, "Decrementer interrupt while in user mode. "
1270 "Aborting\n");
1271 break;
1272 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1273 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1274 "Aborting\n");
1275 break;
1276 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1277 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1278 "Aborting\n");
1279 break;
1280 case POWERPC_EXCP_DTLB: /* Data TLB error */
1281 cpu_abort(env, "Data TLB exception while in user mode. "
1282 "Aborting\n");
1283 break;
1284 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1285 cpu_abort(env, "Instruction TLB exception while in user mode. "
1286 "Aborting\n");
1287 break;
1288 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
1289 /* XXX: check this */
1290 {
1291 int sig;
1292
1293 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1294 if (sig) {
1295 info.si_signo = sig;
1296 info.si_errno = 0;
1297 info.si_code = TARGET_TRAP_BRKPT;
1298 queue_signal(env, info.si_signo, &info);
1299 }
1300 }
1301 break;
1302 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1303 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1304 info.si_signo = TARGET_SIGILL;
1305 info.si_errno = 0;
1306 info.si_code = TARGET_ILL_COPROC;
1307 info._sifields._sigfault._addr = env->nip - 4;
1308 queue_signal(env, info.si_signo, &info);
1309 break;
1310 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1311 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1312 break;
1313 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1314 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1315 break;
1316 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1317 cpu_abort(env, "Performance monitor exception not handled\n");
1318 break;
1319 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1320 cpu_abort(env, "Doorbell interrupt while in user mode. "
1321 "Aborting\n");
1322 break;
1323 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1324 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1325 "Aborting\n");
1326 break;
1327 case POWERPC_EXCP_RESET: /* System reset exception */
1328 cpu_abort(env, "Reset interrupt while in user mode. "
1329 "Aborting\n");
1330 break;
1331 case POWERPC_EXCP_DSEG: /* Data segment exception */
1332 cpu_abort(env, "Data segment exception while in user mode. "
1333 "Aborting\n");
1334 break;
1335 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1336 cpu_abort(env, "Instruction segment exception "
1337 "while in user mode. Aborting\n");
1338 break;
1339 /* PowerPC 64 with hypervisor mode support */
1340 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1341 cpu_abort(env, "Hypervisor decrementer interrupt "
1342 "while in user mode. Aborting\n");
1343 break;
1344 case POWERPC_EXCP_TRACE: /* Trace exception */
1345 /* Nothing to do:
1346 * we use this exception to emulate step-by-step execution mode.
1347 */
1348 break;
1349 /* PowerPC 64 with hypervisor mode support */
1350 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1351 cpu_abort(env, "Hypervisor data storage exception "
1352 "while in user mode. Aborting\n");
1353 break;
1354 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1355 cpu_abort(env, "Hypervisor instruction storage exception "
1356 "while in user mode. Aborting\n");
1357 break;
1358 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1359 cpu_abort(env, "Hypervisor data segment exception "
1360 "while in user mode. Aborting\n");
1361 break;
1362 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1363 cpu_abort(env, "Hypervisor instruction segment exception "
1364 "while in user mode. Aborting\n");
1365 break;
1366 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1367 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1368 info.si_signo = TARGET_SIGILL;
1369 info.si_errno = 0;
1370 info.si_code = TARGET_ILL_COPROC;
1371 info._sifields._sigfault._addr = env->nip - 4;
1372 queue_signal(env, info.si_signo, &info);
1373 break;
1374 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1375 cpu_abort(env, "Programable interval timer interrupt "
1376 "while in user mode. Aborting\n");
1377 break;
1378 case POWERPC_EXCP_IO: /* IO error exception */
1379 cpu_abort(env, "IO error exception while in user mode. "
1380 "Aborting\n");
1381 break;
1382 case POWERPC_EXCP_RUNM: /* Run mode exception */
1383 cpu_abort(env, "Run mode exception while in user mode. "
1384 "Aborting\n");
1385 break;
1386 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1387 cpu_abort(env, "Emulation trap exception not handled\n");
1388 break;
1389 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1390 cpu_abort(env, "Instruction fetch TLB exception "
1391 "while in user-mode. Aborting");
1392 break;
1393 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1394 cpu_abort(env, "Data load TLB exception while in user-mode. "
1395 "Aborting");
1396 break;
1397 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1398 cpu_abort(env, "Data store TLB exception while in user-mode. "
1399 "Aborting");
1400 break;
1401 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1402 cpu_abort(env, "Floating-point assist exception not handled\n");
1403 break;
1404 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1405 cpu_abort(env, "Instruction address breakpoint exception "
1406 "not handled\n");
1407 break;
1408 case POWERPC_EXCP_SMI: /* System management interrupt */
1409 cpu_abort(env, "System management interrupt while in user mode. "
1410 "Aborting\n");
1411 break;
1412 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1413 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1414 "Aborting\n");
1415 break;
1416 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1417 cpu_abort(env, "Performance monitor exception not handled\n");
1418 break;
1419 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1420 cpu_abort(env, "Vector assist exception not handled\n");
1421 break;
1422 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1423 cpu_abort(env, "Soft patch exception not handled\n");
1424 break;
1425 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1426 cpu_abort(env, "Maintenance exception while in user mode. "
1427 "Aborting\n");
1428 break;
1429 case POWERPC_EXCP_STOP: /* stop translation */
1430 /* We did invalidate the instruction cache. Go on */
1431 break;
1432 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1433 /* We just stopped because of a branch. Go on */
1434 break;
1435 case POWERPC_EXCP_SYSCALL_USER:
1436 /* system call in user-mode emulation */
1437 /* WARNING:
1438 * PPC ABI uses overflow flag in cr0 to signal an error
1439 * in syscalls.
1440 */
1441 #if 0
1442 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1443 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1444 #endif
1445 env->crf[0] &= ~0x1;
1446 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1447 env->gpr[5], env->gpr[6], env->gpr[7],
1448 env->gpr[8]);
1449 if (ret > (uint32_t)(-515)) {
1450 env->crf[0] |= 0x1;
1451 ret = -ret;
1452 }
1453 env->gpr[3] = ret;
1454 #if 0
1455 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1456 #endif
1457 break;
1458 case EXCP_INTERRUPT:
1459 /* just indicate that signals should be handled asap */
1460 break;
1461 default:
1462 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1463 break;
1464 }
1465 process_pending_signals(env);
1466 }
1467 }
1468 #endif
1469
1470 #ifdef TARGET_MIPS
1471
1472 #define MIPS_SYS(name, args) args,
1473
1474 static const uint8_t mips_syscall_args[] = {
1475 MIPS_SYS(sys_syscall , 0) /* 4000 */
1476 MIPS_SYS(sys_exit , 1)
1477 MIPS_SYS(sys_fork , 0)
1478 MIPS_SYS(sys_read , 3)
1479 MIPS_SYS(sys_write , 3)
1480 MIPS_SYS(sys_open , 3) /* 4005 */
1481 MIPS_SYS(sys_close , 1)
1482 MIPS_SYS(sys_waitpid , 3)
1483 MIPS_SYS(sys_creat , 2)
1484 MIPS_SYS(sys_link , 2)
1485 MIPS_SYS(sys_unlink , 1) /* 4010 */
1486 MIPS_SYS(sys_execve , 0)
1487 MIPS_SYS(sys_chdir , 1)
1488 MIPS_SYS(sys_time , 1)
1489 MIPS_SYS(sys_mknod , 3)
1490 MIPS_SYS(sys_chmod , 2) /* 4015 */
1491 MIPS_SYS(sys_lchown , 3)
1492 MIPS_SYS(sys_ni_syscall , 0)
1493 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1494 MIPS_SYS(sys_lseek , 3)
1495 MIPS_SYS(sys_getpid , 0) /* 4020 */
1496 MIPS_SYS(sys_mount , 5)
1497 MIPS_SYS(sys_oldumount , 1)
1498 MIPS_SYS(sys_setuid , 1)
1499 MIPS_SYS(sys_getuid , 0)
1500 MIPS_SYS(sys_stime , 1) /* 4025 */
1501 MIPS_SYS(sys_ptrace , 4)
1502 MIPS_SYS(sys_alarm , 1)
1503 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1504 MIPS_SYS(sys_pause , 0)
1505 MIPS_SYS(sys_utime , 2) /* 4030 */
1506 MIPS_SYS(sys_ni_syscall , 0)
1507 MIPS_SYS(sys_ni_syscall , 0)
1508 MIPS_SYS(sys_access , 2)
1509 MIPS_SYS(sys_nice , 1)
1510 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1511 MIPS_SYS(sys_sync , 0)
1512 MIPS_SYS(sys_kill , 2)
1513 MIPS_SYS(sys_rename , 2)
1514 MIPS_SYS(sys_mkdir , 2)
1515 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1516 MIPS_SYS(sys_dup , 1)
1517 MIPS_SYS(sys_pipe , 0)
1518 MIPS_SYS(sys_times , 1)
1519 MIPS_SYS(sys_ni_syscall , 0)
1520 MIPS_SYS(sys_brk , 1) /* 4045 */
1521 MIPS_SYS(sys_setgid , 1)
1522 MIPS_SYS(sys_getgid , 0)
1523 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1524 MIPS_SYS(sys_geteuid , 0)
1525 MIPS_SYS(sys_getegid , 0) /* 4050 */
1526 MIPS_SYS(sys_acct , 0)
1527 MIPS_SYS(sys_umount , 2)
1528 MIPS_SYS(sys_ni_syscall , 0)
1529 MIPS_SYS(sys_ioctl , 3)
1530 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1531 MIPS_SYS(sys_ni_syscall , 2)
1532 MIPS_SYS(sys_setpgid , 2)
1533 MIPS_SYS(sys_ni_syscall , 0)
1534 MIPS_SYS(sys_olduname , 1)
1535 MIPS_SYS(sys_umask , 1) /* 4060 */
1536 MIPS_SYS(sys_chroot , 1)
1537 MIPS_SYS(sys_ustat , 2)
1538 MIPS_SYS(sys_dup2 , 2)
1539 MIPS_SYS(sys_getppid , 0)
1540 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1541 MIPS_SYS(sys_setsid , 0)
1542 MIPS_SYS(sys_sigaction , 3)
1543 MIPS_SYS(sys_sgetmask , 0)
1544 MIPS_SYS(sys_ssetmask , 1)
1545 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1546 MIPS_SYS(sys_setregid , 2)
1547 MIPS_SYS(sys_sigsuspend , 0)
1548 MIPS_SYS(sys_sigpending , 1)
1549 MIPS_SYS(sys_sethostname , 2)
1550 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1551 MIPS_SYS(sys_getrlimit , 2)
1552 MIPS_SYS(sys_getrusage , 2)
1553 MIPS_SYS(sys_gettimeofday, 2)
1554 MIPS_SYS(sys_settimeofday, 2)
1555 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1556 MIPS_SYS(sys_setgroups , 2)
1557 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1558 MIPS_SYS(sys_symlink , 2)
1559 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1560 MIPS_SYS(sys_readlink , 3) /* 4085 */
1561 MIPS_SYS(sys_uselib , 1)
1562 MIPS_SYS(sys_swapon , 2)
1563 MIPS_SYS(sys_reboot , 3)
1564 MIPS_SYS(old_readdir , 3)
1565 MIPS_SYS(old_mmap , 6) /* 4090 */
1566 MIPS_SYS(sys_munmap , 2)
1567 MIPS_SYS(sys_truncate , 2)
1568 MIPS_SYS(sys_ftruncate , 2)
1569 MIPS_SYS(sys_fchmod , 2)
1570 MIPS_SYS(sys_fchown , 3) /* 4095 */
1571 MIPS_SYS(sys_getpriority , 2)
1572 MIPS_SYS(sys_setpriority , 3)
1573 MIPS_SYS(sys_ni_syscall , 0)
1574 MIPS_SYS(sys_statfs , 2)
1575 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1576 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1577 MIPS_SYS(sys_socketcall , 2)
1578 MIPS_SYS(sys_syslog , 3)
1579 MIPS_SYS(sys_setitimer , 3)
1580 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1581 MIPS_SYS(sys_newstat , 2)
1582 MIPS_SYS(sys_newlstat , 2)
1583 MIPS_SYS(sys_newfstat , 2)
1584 MIPS_SYS(sys_uname , 1)
1585 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1586 MIPS_SYS(sys_vhangup , 0)
1587 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1588 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1589 MIPS_SYS(sys_wait4 , 4)
1590 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1591 MIPS_SYS(sys_sysinfo , 1)
1592 MIPS_SYS(sys_ipc , 6)
1593 MIPS_SYS(sys_fsync , 1)
1594 MIPS_SYS(sys_sigreturn , 0)
1595 MIPS_SYS(sys_clone , 0) /* 4120 */
1596 MIPS_SYS(sys_setdomainname, 2)
1597 MIPS_SYS(sys_newuname , 1)
1598 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1599 MIPS_SYS(sys_adjtimex , 1)
1600 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1601 MIPS_SYS(sys_sigprocmask , 3)
1602 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1603 MIPS_SYS(sys_init_module , 5)
1604 MIPS_SYS(sys_delete_module, 1)
1605 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1606 MIPS_SYS(sys_quotactl , 0)
1607 MIPS_SYS(sys_getpgid , 1)
1608 MIPS_SYS(sys_fchdir , 1)
1609 MIPS_SYS(sys_bdflush , 2)
1610 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1611 MIPS_SYS(sys_personality , 1)
1612 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1613 MIPS_SYS(sys_setfsuid , 1)
1614 MIPS_SYS(sys_setfsgid , 1)
1615 MIPS_SYS(sys_llseek , 5) /* 4140 */
1616 MIPS_SYS(sys_getdents , 3)
1617 MIPS_SYS(sys_select , 5)
1618 MIPS_SYS(sys_flock , 2)
1619 MIPS_SYS(sys_msync , 3)
1620 MIPS_SYS(sys_readv , 3) /* 4145 */
1621 MIPS_SYS(sys_writev , 3)
1622 MIPS_SYS(sys_cacheflush , 3)
1623 MIPS_SYS(sys_cachectl , 3)
1624 MIPS_SYS(sys_sysmips , 4)
1625 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1626 MIPS_SYS(sys_getsid , 1)
1627 MIPS_SYS(sys_fdatasync , 0)
1628 MIPS_SYS(sys_sysctl , 1)
1629 MIPS_SYS(sys_mlock , 2)
1630 MIPS_SYS(sys_munlock , 2) /* 4155 */
1631 MIPS_SYS(sys_mlockall , 1)
1632 MIPS_SYS(sys_munlockall , 0)
1633 MIPS_SYS(sys_sched_setparam, 2)
1634 MIPS_SYS(sys_sched_getparam, 2)
1635 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1636 MIPS_SYS(sys_sched_getscheduler, 1)
1637 MIPS_SYS(sys_sched_yield , 0)
1638 MIPS_SYS(sys_sched_get_priority_max, 1)
1639 MIPS_SYS(sys_sched_get_priority_min, 1)
1640 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1641 MIPS_SYS(sys_nanosleep, 2)
1642 MIPS_SYS(sys_mremap , 4)
1643 MIPS_SYS(sys_accept , 3)
1644 MIPS_SYS(sys_bind , 3)
1645 MIPS_SYS(sys_connect , 3) /* 4170 */
1646 MIPS_SYS(sys_getpeername , 3)
1647 MIPS_SYS(sys_getsockname , 3)
1648 MIPS_SYS(sys_getsockopt , 5)
1649 MIPS_SYS(sys_listen , 2)
1650 MIPS_SYS(sys_recv , 4) /* 4175 */
1651 MIPS_SYS(sys_recvfrom , 6)
1652 MIPS_SYS(sys_recvmsg , 3)
1653 MIPS_SYS(sys_send , 4)
1654 MIPS_SYS(sys_sendmsg , 3)
1655 MIPS_SYS(sys_sendto , 6) /* 4180 */
1656 MIPS_SYS(sys_setsockopt , 5)
1657 MIPS_SYS(sys_shutdown , 2)
1658 MIPS_SYS(sys_socket , 3)
1659 MIPS_SYS(sys_socketpair , 4)
1660 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1661 MIPS_SYS(sys_getresuid , 3)
1662 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1663 MIPS_SYS(sys_poll , 3)
1664 MIPS_SYS(sys_nfsservctl , 3)
1665 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1666 MIPS_SYS(sys_getresgid , 3)
1667 MIPS_SYS(sys_prctl , 5)
1668 MIPS_SYS(sys_rt_sigreturn, 0)
1669 MIPS_SYS(sys_rt_sigaction, 4)
1670 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1671 MIPS_SYS(sys_rt_sigpending, 2)
1672 MIPS_SYS(sys_rt_sigtimedwait, 4)
1673 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1674 MIPS_SYS(sys_rt_sigsuspend, 0)
1675 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1676 MIPS_SYS(sys_pwrite64 , 6)
1677 MIPS_SYS(sys_chown , 3)
1678 MIPS_SYS(sys_getcwd , 2)
1679 MIPS_SYS(sys_capget , 2)
1680 MIPS_SYS(sys_capset , 2) /* 4205 */
1681 MIPS_SYS(sys_sigaltstack , 0)
1682 MIPS_SYS(sys_sendfile , 4)
1683 MIPS_SYS(sys_ni_syscall , 0)
1684 MIPS_SYS(sys_ni_syscall , 0)
1685 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1686 MIPS_SYS(sys_truncate64 , 4)
1687 MIPS_SYS(sys_ftruncate64 , 4)
1688 MIPS_SYS(sys_stat64 , 2)
1689 MIPS_SYS(sys_lstat64 , 2)
1690 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1691 MIPS_SYS(sys_pivot_root , 2)
1692 MIPS_SYS(sys_mincore , 3)
1693 MIPS_SYS(sys_madvise , 3)
1694 MIPS_SYS(sys_getdents64 , 3)
1695 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1696 MIPS_SYS(sys_ni_syscall , 0)
1697 MIPS_SYS(sys_gettid , 0)
1698 MIPS_SYS(sys_readahead , 5)
1699 MIPS_SYS(sys_setxattr , 5)
1700 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1701 MIPS_SYS(sys_fsetxattr , 5)
1702 MIPS_SYS(sys_getxattr , 4)
1703 MIPS_SYS(sys_lgetxattr , 4)
1704 MIPS_SYS(sys_fgetxattr , 4)
1705 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1706 MIPS_SYS(sys_llistxattr , 3)
1707 MIPS_SYS(sys_flistxattr , 3)
1708 MIPS_SYS(sys_removexattr , 2)
1709 MIPS_SYS(sys_lremovexattr, 2)
1710 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1711 MIPS_SYS(sys_tkill , 2)
1712 MIPS_SYS(sys_sendfile64 , 5)
1713 MIPS_SYS(sys_futex , 2)
1714 MIPS_SYS(sys_sched_setaffinity, 3)
1715 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1716 MIPS_SYS(sys_io_setup , 2)
1717 MIPS_SYS(sys_io_destroy , 1)
1718 MIPS_SYS(sys_io_getevents, 5)
1719 MIPS_SYS(sys_io_submit , 3)
1720 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1721 MIPS_SYS(sys_exit_group , 1)
1722 MIPS_SYS(sys_lookup_dcookie, 3)
1723 MIPS_SYS(sys_epoll_create, 1)
1724 MIPS_SYS(sys_epoll_ctl , 4)
1725 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1726 MIPS_SYS(sys_remap_file_pages, 5)
1727 MIPS_SYS(sys_set_tid_address, 1)
1728 MIPS_SYS(sys_restart_syscall, 0)
1729 MIPS_SYS(sys_fadvise64_64, 7)
1730 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1731 MIPS_SYS(sys_fstatfs64 , 2)
1732 MIPS_SYS(sys_timer_create, 3)
1733 MIPS_SYS(sys_timer_settime, 4)
1734 MIPS_SYS(sys_timer_gettime, 2)
1735 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1736 MIPS_SYS(sys_timer_delete, 1)
1737 MIPS_SYS(sys_clock_settime, 2)
1738 MIPS_SYS(sys_clock_gettime, 2)
1739 MIPS_SYS(sys_clock_getres, 2)
1740 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1741 MIPS_SYS(sys_tgkill , 3)
1742 MIPS_SYS(sys_utimes , 2)
1743 MIPS_SYS(sys_mbind , 4)
1744 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1745 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1746 MIPS_SYS(sys_mq_open , 4)
1747 MIPS_SYS(sys_mq_unlink , 1)
1748 MIPS_SYS(sys_mq_timedsend, 5)
1749 MIPS_SYS(sys_mq_timedreceive, 5)
1750 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1751 MIPS_SYS(sys_mq_getsetattr, 3)
1752 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1753 MIPS_SYS(sys_waitid , 4)
1754 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1755 MIPS_SYS(sys_add_key , 5)
1756 MIPS_SYS(sys_request_key, 4)
1757 MIPS_SYS(sys_keyctl , 5)
1758 MIPS_SYS(sys_set_thread_area, 1)
1759 MIPS_SYS(sys_inotify_init, 0)
1760 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1761 MIPS_SYS(sys_inotify_rm_watch, 2)
1762 MIPS_SYS(sys_migrate_pages, 4)
1763 MIPS_SYS(sys_openat, 4)
1764 MIPS_SYS(sys_mkdirat, 3)
1765 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1766 MIPS_SYS(sys_fchownat, 5)
1767 MIPS_SYS(sys_futimesat, 3)
1768 MIPS_SYS(sys_fstatat64, 4)
1769 MIPS_SYS(sys_unlinkat, 3)
1770 MIPS_SYS(sys_renameat, 4) /* 4295 */
1771 MIPS_SYS(sys_linkat, 5)
1772 MIPS_SYS(sys_symlinkat, 3)
1773 MIPS_SYS(sys_readlinkat, 4)
1774 MIPS_SYS(sys_fchmodat, 3)
1775 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1776 MIPS_SYS(sys_pselect6, 6)
1777 MIPS_SYS(sys_ppoll, 5)
1778 MIPS_SYS(sys_unshare, 1)
1779 MIPS_SYS(sys_splice, 4)
1780 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1781 MIPS_SYS(sys_tee, 4)
1782 MIPS_SYS(sys_vmsplice, 4)
1783 MIPS_SYS(sys_move_pages, 6)
1784 MIPS_SYS(sys_set_robust_list, 2)
1785 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1786 MIPS_SYS(sys_kexec_load, 4)
1787 MIPS_SYS(sys_getcpu, 3)
1788 MIPS_SYS(sys_epoll_pwait, 6)
1789 MIPS_SYS(sys_ioprio_set, 3)
1790 MIPS_SYS(sys_ioprio_get, 2)
1791 };
1792
1793 #undef MIPS_SYS
1794
1795 void cpu_loop(CPUMIPSState *env)
1796 {
1797 target_siginfo_t info;
1798 int trapnr, ret;
1799 unsigned int syscall_num;
1800
1801 for(;;) {
1802 trapnr = cpu_mips_exec(env);
1803 switch(trapnr) {
1804 case EXCP_SYSCALL:
1805 syscall_num = env->active_tc.gpr[2] - 4000;
1806 env->active_tc.PC += 4;
1807 if (syscall_num >= sizeof(mips_syscall_args)) {
1808 ret = -ENOSYS;
1809 } else {
1810 int nb_args;
1811 abi_ulong sp_reg;
1812 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1813
1814 nb_args = mips_syscall_args[syscall_num];
1815 sp_reg = env->active_tc.gpr[29];
1816 switch (nb_args) {
1817 /* these arguments are taken from the stack */
1818 /* FIXME - what to do if get_user() fails? */
1819 case 8: get_user_ual(arg8, sp_reg + 28);
1820 case 7: get_user_ual(arg7, sp_reg + 24);
1821 case 6: get_user_ual(arg6, sp_reg + 20);
1822 case 5: get_user_ual(arg5, sp_reg + 16);
1823 default:
1824 break;
1825 }
1826 ret = do_syscall(env, env->active_tc.gpr[2],
1827 env->active_tc.gpr[4],
1828 env->active_tc.gpr[5],
1829 env->active_tc.gpr[6],
1830 env->active_tc.gpr[7],
1831 arg5, arg6/*, arg7, arg8*/);
1832 }
1833 if ((unsigned int)ret >= (unsigned int)(-1133)) {
1834 env->active_tc.gpr[7] = 1; /* error flag */
1835 ret = -ret;
1836 } else {
1837 env->active_tc.gpr[7] = 0; /* error flag */
1838 }
1839 env->active_tc.gpr[2] = ret;
1840 break;
1841 case EXCP_TLBL:
1842 case EXCP_TLBS:
1843 case EXCP_CpU:
1844 case EXCP_RI:
1845 info.si_signo = TARGET_SIGILL;
1846 info.si_errno = 0;
1847 info.si_code = 0;
1848 queue_signal(env, info.si_signo, &info);
1849 break;
1850 case EXCP_INTERRUPT:
1851 /* just indicate that signals should be handled asap */
1852 break;
1853 case EXCP_DEBUG:
1854 {
1855 int sig;
1856
1857 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1858 if (sig)
1859 {
1860 info.si_signo = sig;
1861 info.si_errno = 0;
1862 info.si_code = TARGET_TRAP_BRKPT;
1863 queue_signal(env, info.si_signo, &info);
1864 }
1865 }
1866 break;
1867 default:
1868 // error:
1869 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1870 trapnr);
1871 cpu_dump_state(env, stderr, fprintf, 0);
1872 abort();
1873 }
1874 process_pending_signals(env);
1875 }
1876 }
1877 #endif
1878
1879 #ifdef TARGET_SH4
1880 void cpu_loop (CPUState *env)
1881 {
1882 int trapnr, ret;
1883 target_siginfo_t info;
1884
1885 while (1) {
1886 trapnr = cpu_sh4_exec (env);
1887
1888 switch (trapnr) {
1889 case 0x160:
1890 env->pc += 2;
1891 ret = do_syscall(env,
1892 env->gregs[3],
1893 env->gregs[4],
1894 env->gregs[5],
1895 env->gregs[6],
1896 env->gregs[7],
1897 env->gregs[0],
1898 env->gregs[1]);
1899 env->gregs[0] = ret;
1900 break;
1901 case EXCP_INTERRUPT:
1902 /* just indicate that signals should be handled asap */
1903 break;
1904 case EXCP_DEBUG:
1905 {
1906 int sig;
1907
1908 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1909 if (sig)
1910 {
1911 info.si_signo = sig;
1912 info.si_errno = 0;
1913 info.si_code = TARGET_TRAP_BRKPT;
1914 queue_signal(env, info.si_signo, &info);
1915 }
1916 }
1917 break;
1918 case 0xa0:
1919 case 0xc0:
1920 info.si_signo = SIGSEGV;
1921 info.si_errno = 0;
1922 info.si_code = TARGET_SEGV_MAPERR;
1923 info._sifields._sigfault._addr = env->tea;
1924 queue_signal(env, info.si_signo, &info);
1925 break;
1926
1927 default:
1928 printf ("Unhandled trap: 0x%x\n", trapnr);
1929 cpu_dump_state(env, stderr, fprintf, 0);
1930 exit (1);
1931 }
1932 process_pending_signals (env);
1933 }
1934 }
1935 #endif
1936
1937 #ifdef TARGET_CRIS
1938 void cpu_loop (CPUState *env)
1939 {
1940 int trapnr, ret;
1941 target_siginfo_t info;
1942
1943 while (1) {
1944 trapnr = cpu_cris_exec (env);
1945 switch (trapnr) {
1946 case 0xaa:
1947 {
1948 info.si_signo = SIGSEGV;
1949 info.si_errno = 0;
1950 /* XXX: check env->error_code */
1951 info.si_code = TARGET_SEGV_MAPERR;
1952 info._sifields._sigfault._addr = env->pregs[PR_EDA];
1953 queue_signal(env, info.si_signo, &info);
1954 }
1955 break;
1956 case EXCP_INTERRUPT:
1957 /* just indicate that signals should be handled asap */
1958 break;
1959 case EXCP_BREAK:
1960 ret = do_syscall(env,
1961 env->regs[9],
1962 env->regs[10],
1963 env->regs[11],
1964 env->regs[12],
1965 env->regs[13],
1966 env->pregs[7],
1967 env->pregs[11]);
1968 env->regs[10] = ret;
1969 break;
1970 case EXCP_DEBUG:
1971 {
1972 int sig;
1973
1974 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1975 if (sig)
1976 {
1977 info.si_signo = sig;
1978 info.si_errno = 0;
1979 info.si_code = TARGET_TRAP_BRKPT;
1980 queue_signal(env, info.si_signo, &info);
1981 }
1982 }
1983 break;
1984 default:
1985 printf ("Unhandled trap: 0x%x\n", trapnr);
1986 cpu_dump_state(env, stderr, fprintf, 0);
1987 exit (1);
1988 }
1989 process_pending_signals (env);
1990 }
1991 }
1992 #endif
1993
1994 #ifdef TARGET_M68K
1995
1996 void cpu_loop(CPUM68KState *env)
1997 {
1998 int trapnr;
1999 unsigned int n;
2000 target_siginfo_t info;
2001 TaskState *ts = env->opaque;
2002
2003 for(;;) {
2004 trapnr = cpu_m68k_exec(env);
2005 switch(trapnr) {
2006 case EXCP_ILLEGAL:
2007 {
2008 if (ts->sim_syscalls) {
2009 uint16_t nr;
2010 nr = lduw(env->pc + 2);
2011 env->pc += 4;
2012 do_m68k_simcall(env, nr);
2013 } else {
2014 goto do_sigill;
2015 }
2016 }
2017 break;
2018 case EXCP_HALT_INSN:
2019 /* Semihosing syscall. */
2020 env->pc += 4;
2021 do_m68k_semihosting(env, env->dregs[0]);
2022 break;
2023 case EXCP_LINEA:
2024 case EXCP_LINEF:
2025 case EXCP_UNSUPPORTED:
2026 do_sigill:
2027 info.si_signo = SIGILL;
2028 info.si_errno = 0;
2029 info.si_code = TARGET_ILL_ILLOPN;
2030 info._sifields._sigfault._addr = env->pc;
2031 queue_signal(env, info.si_signo, &info);
2032 break;
2033 case EXCP_TRAP0:
2034 {
2035 ts->sim_syscalls = 0;
2036 n = env->dregs[0];
2037 env->pc += 2;
2038 env->dregs[0] = do_syscall(env,
2039 n,
2040 env->dregs[1],
2041 env->dregs[2],
2042 env->dregs[3],
2043 env->dregs[4],
2044 env->dregs[5],
2045 env->aregs[0]);
2046 }
2047 break;
2048 case EXCP_INTERRUPT:
2049 /* just indicate that signals should be handled asap */
2050 break;
2051 case EXCP_ACCESS:
2052 {
2053 info.si_signo = SIGSEGV;
2054 info.si_errno = 0;
2055 /* XXX: check env->error_code */
2056 info.si_code = TARGET_SEGV_MAPERR;
2057 info._sifields._sigfault._addr = env->mmu.ar;
2058 queue_signal(env, info.si_signo, &info);
2059 }
2060 break;
2061 case EXCP_DEBUG:
2062 {
2063 int sig;
2064
2065 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2066 if (sig)
2067 {
2068 info.si_signo = sig;
2069 info.si_errno = 0;
2070 info.si_code = TARGET_TRAP_BRKPT;
2071 queue_signal(env, info.si_signo, &info);
2072 }
2073 }
2074 break;
2075 default:
2076 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2077 trapnr);
2078 cpu_dump_state(env, stderr, fprintf, 0);
2079 abort();
2080 }
2081 process_pending_signals(env);
2082 }
2083 }
2084 #endif /* TARGET_M68K */
2085
2086 #ifdef TARGET_ALPHA
2087 void cpu_loop (CPUState *env)
2088 {
2089 int trapnr;
2090 target_siginfo_t info;
2091
2092 while (1) {
2093 trapnr = cpu_alpha_exec (env);
2094
2095 switch (trapnr) {
2096 case EXCP_RESET:
2097 fprintf(stderr, "Reset requested. Exit\n");
2098 exit(1);
2099 break;
2100 case EXCP_MCHK:
2101 fprintf(stderr, "Machine check exception. Exit\n");
2102 exit(1);
2103 break;
2104 case EXCP_ARITH:
2105 fprintf(stderr, "Arithmetic trap.\n");
2106 exit(1);
2107 break;
2108 case EXCP_HW_INTERRUPT:
2109 fprintf(stderr, "External interrupt. Exit\n");
2110 exit(1);
2111 break;
2112 case EXCP_DFAULT:
2113 fprintf(stderr, "MMU data fault\n");
2114 exit(1);
2115 break;
2116 case EXCP_DTB_MISS_PAL:
2117 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2118 exit(1);
2119 break;
2120 case EXCP_ITB_MISS:
2121 fprintf(stderr, "MMU instruction TLB miss\n");
2122 exit(1);
2123 break;
2124 case EXCP_ITB_ACV:
2125 fprintf(stderr, "MMU instruction access violation\n");
2126 exit(1);
2127 break;
2128 case EXCP_DTB_MISS_NATIVE:
2129 fprintf(stderr, "MMU data TLB miss\n");
2130 exit(1);
2131 break;
2132 case EXCP_UNALIGN:
2133 fprintf(stderr, "Unaligned access\n");
2134 exit(1);
2135 break;
2136 case EXCP_OPCDEC:
2137 fprintf(stderr, "Invalid instruction\n");
2138 exit(1);
2139 break;
2140 case EXCP_FEN:
2141 fprintf(stderr, "Floating-point not allowed\n");
2142 exit(1);
2143 break;
2144 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2145 call_pal(env, (trapnr >> 6) | 0x80);
2146 break;
2147 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2148 fprintf(stderr, "Privileged call to PALcode\n");
2149 exit(1);
2150 break;
2151 case EXCP_DEBUG:
2152 {
2153 int sig;
2154
2155 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2156 if (sig)
2157 {
2158 info.si_signo = sig;
2159 info.si_errno = 0;
2160 info.si_code = TARGET_TRAP_BRKPT;
2161 queue_signal(env, info.si_signo, &info);
2162 }
2163 }
2164 break;
2165 default:
2166 printf ("Unhandled trap: 0x%x\n", trapnr);
2167 cpu_dump_state(env, stderr, fprintf, 0);
2168 exit (1);
2169 }
2170 process_pending_signals (env);
2171 }
2172 }
2173 #endif /* TARGET_ALPHA */
2174
2175 static void usage(void)
2176 {
2177 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2178 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2179 "Linux CPU emulator (compiled for %s emulation)\n"
2180 "\n"
2181 "Standard options:\n"
2182 "-h print this help\n"
2183 "-g port wait gdb connection to port\n"
2184 "-L path set the elf interpreter prefix (default=%s)\n"
2185 "-s size set the stack size in bytes (default=%ld)\n"
2186 "-cpu model select CPU (-cpu ? for list)\n"
2187 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2188 "\n"
2189 "Debug options:\n"
2190 "-d options activate log (logfile=%s)\n"
2191 "-p pagesize set the host page size to 'pagesize'\n"
2192 "-strace log system calls\n"
2193 "\n"
2194 "Environment variables:\n"
2195 "QEMU_STRACE Print system calls and arguments similar to the\n"
2196 " 'strace' program. Enable by setting to any value.\n"
2197 ,
2198 TARGET_ARCH,
2199 interp_prefix,
2200 x86_stack_size,
2201 DEBUG_LOGFILE);
2202 _exit(1);
2203 }
2204
2205 THREAD CPUState *thread_env;
2206
2207 /* Assumes contents are already zeroed. */
2208 void init_task_state(TaskState *ts)
2209 {
2210 int i;
2211
2212 ts->used = 1;
2213 ts->first_free = ts->sigqueue_table;
2214 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2215 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2216 }
2217 ts->sigqueue_table[i].next = NULL;
2218 }
2219
2220 int main(int argc, char **argv)
2221 {
2222 const char *filename;
2223 const char *cpu_model;
2224 struct target_pt_regs regs1, *regs = &regs1;
2225 struct image_info info1, *info = &info1;
2226 TaskState ts1, *ts = &ts1;
2227 CPUState *env;
2228 int optind;
2229 const char *r;
2230 int gdbstub_port = 0;
2231 int drop_ld_preload = 0, environ_count = 0;
2232 char **target_environ, **wrk, **dst;
2233
2234 if (argc <= 1)
2235 usage();
2236
2237 /* init debug */
2238 cpu_set_log_filename(DEBUG_LOGFILE);
2239
2240 cpu_model = NULL;
2241 optind = 1;
2242 for(;;) {
2243 if (optind >= argc)
2244 break;
2245 r = argv[optind];
2246 if (r[0] != '-')
2247 break;
2248 optind++;
2249 r++;
2250 if (!strcmp(r, "-")) {
2251 break;
2252 } else if (!strcmp(r, "d")) {
2253 int mask;
2254 const CPULogItem *item;
2255
2256 if (optind >= argc)
2257 break;
2258
2259 r = argv[optind++];
2260 mask = cpu_str_to_log_mask(r);
2261 if (!mask) {
2262 printf("Log items (comma separated):\n");
2263 for(item = cpu_log_items; item->mask != 0; item++) {
2264 printf("%-10s %s\n", item->name, item->help);
2265 }
2266 exit(1);
2267 }
2268 cpu_set_log(mask);
2269 } else if (!strcmp(r, "s")) {
2270 r = argv[optind++];
2271 x86_stack_size = strtol(r, (char **)&r, 0);
2272 if (x86_stack_size <= 0)
2273 usage();
2274 if (*r == 'M')
2275 x86_stack_size *= 1024 * 1024;
2276 else if (*r == 'k' || *r == 'K')
2277 x86_stack_size *= 1024;
2278 } else if (!strcmp(r, "L")) {
2279 interp_prefix = argv[optind++];
2280 } else if (!strcmp(r, "p")) {
2281 qemu_host_page_size = atoi(argv[optind++]);
2282 if (qemu_host_page_size == 0 ||
2283 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2284 fprintf(stderr, "page size must be a power of two\n");
2285 exit(1);
2286 }
2287 } else if (!strcmp(r, "g")) {
2288 gdbstub_port = atoi(argv[optind++]);
2289 } else if (!strcmp(r, "r")) {
2290 qemu_uname_release = argv[optind++];
2291 } else if (!strcmp(r, "cpu")) {
2292 cpu_model = argv[optind++];
2293 if (strcmp(cpu_model, "?") == 0) {
2294 /* XXX: implement xxx_cpu_list for targets that still miss it */
2295 #if defined(cpu_list)
2296 cpu_list(stdout, &fprintf);
2297 #endif
2298 _exit(1);
2299 }
2300 } else if (!strcmp(r, "drop-ld-preload")) {
2301 drop_ld_preload = 1;
2302 } else if (!strcmp(r, "strace")) {
2303 do_strace = 1;
2304 } else
2305 {
2306 usage();
2307 }
2308 }
2309 if (optind >= argc)
2310 usage();
2311 filename = argv[optind];
2312
2313 /* Zero out regs */
2314 memset(regs, 0, sizeof(struct target_pt_regs));
2315
2316 /* Zero out image_info */
2317 memset(info, 0, sizeof(struct image_info));
2318
2319 /* Scan interp_prefix dir for replacement files. */
2320 init_paths(interp_prefix);
2321
2322 if (cpu_model == NULL) {
2323 #if defined(TARGET_I386)
2324 #ifdef TARGET_X86_64
2325 cpu_model = "qemu64";
2326 #else
2327 cpu_model = "qemu32";
2328 #endif
2329 #elif defined(TARGET_ARM)
2330 cpu_model = "arm926";
2331 #elif defined(TARGET_M68K)
2332 cpu_model = "any";
2333 #elif defined(TARGET_SPARC)
2334 #ifdef TARGET_SPARC64
2335 cpu_model = "TI UltraSparc II";
2336 #else
2337 cpu_model = "Fujitsu MB86904";
2338 #endif
2339 #elif defined(TARGET_MIPS)
2340 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2341 cpu_model = "20Kc";
2342 #else
2343 cpu_model = "24Kf";
2344 #endif
2345 #elif defined(TARGET_PPC)
2346 #ifdef TARGET_PPC64
2347 cpu_model = "970";
2348 #else
2349 cpu_model = "750";
2350 #endif
2351 #else
2352 cpu_model = "any";
2353 #endif
2354 }
2355 cpu_exec_init_all(0);
2356 /* NOTE: we need to init the CPU at this stage to get
2357 qemu_host_page_size */
2358 env = cpu_init(cpu_model);
2359 if (!env) {
2360 fprintf(stderr, "Unable to find CPU definition\n");
2361 exit(1);
2362 }
2363 thread_env = env;
2364
2365 if (getenv("QEMU_STRACE")) {
2366 do_strace = 1;
2367 }
2368
2369 wrk = environ;
2370 while (*(wrk++))
2371 environ_count++;
2372
2373 target_environ = malloc((environ_count + 1) * sizeof(char *));
2374 if (!target_environ)
2375 abort();
2376 for (wrk = environ, dst = target_environ; *wrk; wrk++) {
2377 if (drop_ld_preload && !strncmp(*wrk, "LD_PRELOAD=", 11))
2378 continue;
2379 *(dst++) = strdup(*wrk);
2380 }
2381 *dst = NULL; /* NULL terminate target_environ */
2382
2383 if (loader_exec(filename, argv+optind, target_environ, regs, info) != 0) {
2384 printf("Error loading %s\n", filename);
2385 _exit(1);
2386 }
2387
2388 for (wrk = target_environ; *wrk; wrk++) {
2389 free(*wrk);
2390 }
2391
2392 free(target_environ);
2393
2394 if (loglevel) {
2395 page_dump(logfile);
2396
2397 fprintf(logfile, "start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2398 fprintf(logfile, "end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2399 fprintf(logfile, "start_code 0x" TARGET_ABI_FMT_lx "\n",
2400 info->start_code);
2401 fprintf(logfile, "start_data 0x" TARGET_ABI_FMT_lx "\n",
2402 info->start_data);
2403 fprintf(logfile, "end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2404 fprintf(logfile, "start_stack 0x" TARGET_ABI_FMT_lx "\n",
2405 info->start_stack);
2406 fprintf(logfile, "brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2407 fprintf(logfile, "entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2408 }
2409
2410 target_set_brk(info->brk);
2411 syscall_init();
2412 signal_init();
2413
2414 /* build Task State */
2415 memset(ts, 0, sizeof(TaskState));
2416 init_task_state(ts);
2417 ts->info = info;
2418 env->opaque = ts;
2419 env->user_mode_only = 1;
2420
2421 #if defined(TARGET_I386)
2422 cpu_x86_set_cpl(env, 3);
2423
2424 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2425 env->hflags |= HF_PE_MASK;
2426 if (env->cpuid_features & CPUID_SSE) {
2427 env->cr[4] |= CR4_OSFXSR_MASK;
2428 env->hflags |= HF_OSFXSR_MASK;
2429 }
2430 #ifndef TARGET_ABI32
2431 /* enable 64 bit mode if possible */
2432 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2433 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2434 exit(1);
2435 }
2436 env->cr[4] |= CR4_PAE_MASK;
2437 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2438 env->hflags |= HF_LMA_MASK;
2439 #endif
2440
2441 /* flags setup : we activate the IRQs by default as in user mode */
2442 env->eflags |= IF_MASK;
2443
2444 /* linux register setup */
2445 #ifndef TARGET_ABI32
2446 env->regs[R_EAX] = regs->rax;
2447 env->regs[R_EBX] = regs->rbx;
2448 env->regs[R_ECX] = regs->rcx;
2449 env->regs[R_EDX] = regs->rdx;
2450 env->regs[R_ESI] = regs->rsi;
2451 env->regs[R_EDI] = regs->rdi;
2452 env->regs[R_EBP] = regs->rbp;
2453 env->regs[R_ESP] = regs->rsp;
2454 env->eip = regs->rip;
2455 #else
2456 env->regs[R_EAX] = regs->eax;
2457 env->regs[R_EBX] = regs->ebx;
2458 env->regs[R_ECX] = regs->ecx;
2459 env->regs[R_EDX] = regs->edx;
2460 env->regs[R_ESI] = regs->esi;
2461 env->regs[R_EDI] = regs->edi;
2462 env->regs[R_EBP] = regs->ebp;
2463 env->regs[R_ESP] = regs->esp;
2464 env->eip = regs->eip;
2465 #endif
2466
2467 /* linux interrupt setup */
2468 env->idt.base = h2g(idt_table);
2469 env->idt.limit = sizeof(idt_table) - 1;
2470 set_idt(0, 0);
2471 set_idt(1, 0);
2472 set_idt(2, 0);
2473 set_idt(3, 3);
2474 set_idt(4, 3);
2475 set_idt(5, 0);
2476 set_idt(6, 0);
2477 set_idt(7, 0);
2478 set_idt(8, 0);
2479 set_idt(9, 0);
2480 set_idt(10, 0);
2481 set_idt(11, 0);
2482 set_idt(12, 0);
2483 set_idt(13, 0);
2484 set_idt(14, 0);
2485 set_idt(15, 0);
2486 set_idt(16, 0);
2487 set_idt(17, 0);
2488 set_idt(18, 0);
2489 set_idt(19, 0);
2490 set_idt(0x80, 3);
2491
2492 /* linux segment setup */
2493 {
2494 uint64_t *gdt_table;
2495 gdt_table = qemu_mallocz(sizeof(uint64_t) * TARGET_GDT_ENTRIES);
2496 env->gdt.base = h2g((unsigned long)gdt_table);
2497 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
2498 #ifdef TARGET_ABI32
2499 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2500 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2501 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2502 #else
2503 /* 64 bit code segment */
2504 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2505 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2506 DESC_L_MASK |
2507 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2508 #endif
2509 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
2510 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2511 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
2512 }
2513 cpu_x86_load_seg(env, R_CS, __USER_CS);
2514 cpu_x86_load_seg(env, R_SS, __USER_DS);
2515 #ifdef TARGET_ABI32
2516 cpu_x86_load_seg(env, R_DS, __USER_DS);
2517 cpu_x86_load_seg(env, R_ES, __USER_DS);
2518 cpu_x86_load_seg(env, R_FS, __USER_DS);
2519 cpu_x86_load_seg(env, R_GS, __USER_DS);
2520 /* This hack makes Wine work... */
2521 env->segs[R_FS].selector = 0;
2522 #else
2523 cpu_x86_load_seg(env, R_DS, 0);
2524 cpu_x86_load_seg(env, R_ES, 0);
2525 cpu_x86_load_seg(env, R_FS, 0);
2526 cpu_x86_load_seg(env, R_GS, 0);
2527 #endif
2528 #elif defined(TARGET_ARM)
2529 {
2530 int i;
2531 cpsr_write(env, regs->uregs[16], 0xffffffff);
2532 for(i = 0; i < 16; i++) {
2533 env->regs[i] = regs->uregs[i];
2534 }
2535 }
2536 #elif defined(TARGET_SPARC)
2537 {
2538 int i;
2539 env->pc = regs->pc;
2540 env->npc = regs->npc;
2541 env->y = regs->y;
2542 for(i = 0; i < 8; i++)
2543 env->gregs[i] = regs->u_regs[i];
2544 for(i = 0; i < 8; i++)
2545 env->regwptr[i] = regs->u_regs[i + 8];
2546 }
2547 #elif defined(TARGET_PPC)
2548 {
2549 int i;
2550
2551 #if defined(TARGET_PPC64)
2552 #if defined(TARGET_ABI32)
2553 env->msr &= ~((target_ulong)1 << MSR_SF);
2554 #else
2555 env->msr |= (target_ulong)1 << MSR_SF;
2556 #endif
2557 #endif
2558 env->nip = regs->nip;
2559 for(i = 0; i < 32; i++) {
2560 env->gpr[i] = regs->gpr[i];
2561 }
2562 }
2563 #elif defined(TARGET_M68K)
2564 {
2565 env->pc = regs->pc;
2566 env->dregs[0] = regs->d0;
2567 env->dregs[1] = regs->d1;
2568 env->dregs[2] = regs->d2;
2569 env->dregs[3] = regs->d3;
2570 env->dregs[4] = regs->d4;
2571 env->dregs[5] = regs->d5;
2572 env->dregs[6] = regs->d6;
2573 env->dregs[7] = regs->d7;
2574 env->aregs[0] = regs->a0;
2575 env->aregs[1] = regs->a1;
2576 env->aregs[2] = regs->a2;
2577 env->aregs[3] = regs->a3;
2578 env->aregs[4] = regs->a4;
2579 env->aregs[5] = regs->a5;
2580 env->aregs[6] = regs->a6;
2581 env->aregs[7] = regs->usp;
2582 env->sr = regs->sr;
2583 ts->sim_syscalls = 1;
2584 }
2585 #elif defined(TARGET_MIPS)
2586 {
2587 int i;
2588
2589 for(i = 0; i < 32; i++) {
2590 env->active_tc.gpr[i] = regs->regs[i];
2591 }
2592 env->active_tc.PC = regs->cp0_epc;
2593 }
2594 #elif defined(TARGET_SH4)
2595 {
2596 int i;
2597
2598 for(i = 0; i < 16; i++) {
2599 env->gregs[i] = regs->regs[i];
2600 }
2601 env->pc = regs->pc;
2602 }
2603 #elif defined(TARGET_ALPHA)
2604 {
2605 int i;
2606
2607 for(i = 0; i < 28; i++) {
2608 env->ir[i] = ((abi_ulong *)regs)[i];
2609 }
2610 env->ipr[IPR_USP] = regs->usp;
2611 env->ir[30] = regs->usp;
2612 env->pc = regs->pc;
2613 env->unique = regs->unique;
2614 }
2615 #elif defined(TARGET_CRIS)
2616 {
2617 env->regs[0] = regs->r0;
2618 env->regs[1] = regs->r1;
2619 env->regs[2] = regs->r2;
2620 env->regs[3] = regs->r3;
2621 env->regs[4] = regs->r4;
2622 env->regs[5] = regs->r5;
2623 env->regs[6] = regs->r6;
2624 env->regs[7] = regs->r7;
2625 env->regs[8] = regs->r8;
2626 env->regs[9] = regs->r9;
2627 env->regs[10] = regs->r10;
2628 env->regs[11] = regs->r11;
2629 env->regs[12] = regs->r12;
2630 env->regs[13] = regs->r13;
2631 env->regs[14] = info->start_stack;
2632 env->regs[15] = regs->acr;
2633 env->pc = regs->erp;
2634 }
2635 #else
2636 #error unsupported target CPU
2637 #endif
2638
2639 #if defined(TARGET_ARM) || defined(TARGET_M68K)
2640 ts->stack_base = info->start_stack;
2641 ts->heap_base = info->brk;
2642 /* This will be filled in on the first SYS_HEAPINFO call. */
2643 ts->heap_limit = 0;
2644 #endif
2645
2646 if (gdbstub_port) {
2647 gdbserver_start (gdbstub_port);
2648 gdb_handlesig(env, 0);
2649 }
2650 cpu_loop(env);
2651 /* never exits */
2652 return 0;
2653 }
jz4740 based target emulation