tcg/sparc/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  26     "%g0",
  27     "%g1",
  28     "%g2",
  29     "%g3",
  30     "%g4",
  31     "%g5",
  32     "%g6",
  33     "%g7",
  34     "%o0",
  35     "%o1",
  36     "%o2",
  37     "%o3",
  38     "%o4",
  39     "%o5",
  40     "%o6",
  41     "%o7",
  42     "%l0",
  43     "%l1",
  44     "%l2",
  45     "%l3",
  46     "%l4",
  47     "%l5",
  48     "%l6",
  49     "%l7",
  50     "%i0",
  51     "%i1",
  52     "%i2",
  53     "%i3",
  54     "%i4",
  55     "%i5",
  56     "%i6",
  57     "%i7",
  58 };
  59
  60 static const int tcg_target_reg_alloc_order[] = {
  61     TCG_REG_L0,
  62     TCG_REG_L1,
  63     TCG_REG_L2,
  64     TCG_REG_L3,
  65     TCG_REG_L4,
  66     TCG_REG_L5,
  67     TCG_REG_L6,
  68     TCG_REG_L7,
  69     TCG_REG_I0,
  70     TCG_REG_I1,
  71     TCG_REG_I2,
  72     TCG_REG_I3,
  73     TCG_REG_I4,
  74 };
  75
  76 static const int tcg_target_call_iarg_regs[6] = {
  77     TCG_REG_O0,
  78     TCG_REG_O1,
  79     TCG_REG_O2,
  80     TCG_REG_O3,
  81     TCG_REG_O4,
  82     TCG_REG_O5,
  83 };
  84
  85 static const int tcg_target_call_oarg_regs[2] = {
  86     TCG_REG_O0,
  87     TCG_REG_O1,
  88 };
  89
  90 static void patch_reloc(uint8_t *code_ptr, int type,
  91                         tcg_target_long value, tcg_target_long addend)
  92 {
  93     value += addend;
  94     switch (type) {
  95     case R_SPARC_32:
  96         if (value != (uint32_t)value)
  97             tcg_abort();
  98         *(uint32_t *)code_ptr = value;
  99         break;
 100     default:
 101         tcg_abort();
 102     }
 103 }
 104
 105 /* maximum number of register used for input function arguments */
 106 static inline int tcg_target_get_call_iarg_regs_count(int flags)
 107 {
 108     return 6;
 109 }
 110
 111 /* parse target specific constraints */
 112 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 113 {
 114     const char *ct_str;
 115
 116     ct_str = *pct_str;
 117     switch (ct_str[0]) {
 118     case 'r':
 119     case 'L': /* qemu_ld/st constraint */
 120         ct->ct |= TCG_CT_REG;
 121         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 122         break;
 123     case 'I':
 124         ct->ct |= TCG_CT_CONST_S11;
 125         break;
 126     case 'J':
 127         ct->ct |= TCG_CT_CONST_S13;
 128         break;
 129     default:
 130         return -1;
 131     }
 132     ct_str++;
 133     *pct_str = ct_str;
 134     return 0;
 135 }
 136
 137 #define ABS(x) ((x) < 0? -(x) : (x))
 138 /* test if a constant matches the constraint */
 139 static inline int tcg_target_const_match(tcg_target_long val,
 140                                          const TCGArgConstraint *arg_ct)
 141 {
 142     int ct;
 143
 144     ct = arg_ct->ct;
 145     if (ct & TCG_CT_CONST)
 146         return 1;
 147     else if ((ct & TCG_CT_CONST_S11) && ABS(val) == (ABS(val) & 0x3ff))
 148         return 1;
 149     else if ((ct & TCG_CT_CONST_S13) && ABS(val) == (ABS(val) & 0xfff))
 150         return 1;
 151     else
 152         return 0;
 153 }
 154
 155 #define INSN_OP(x)  ((x) << 30)
 156 #define INSN_OP2(x) ((x) << 22)
 157 #define INSN_OP3(x) ((x) << 19)
 158 #define INSN_OPF(x) ((x) << 5)
 159 #define INSN_RD(x)  ((x) << 25)
 160 #define INSN_RS1(x) ((x) << 14)
 161 #define INSN_RS2(x) (x)
 162
 163 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
 164 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
 165
 166 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
 167 #define COND_A     0x8
 168 #define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
 169
 170 #define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
 171 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
 172 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 173 #define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
 174 #define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x08))
 175 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
 176 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
 177 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
 178 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
 179 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
 180 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
 181 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
 182 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
 183
 184 #define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
 185 #define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
 186 #define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
 187
 188 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
 189 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
 190 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
 191
 192 #define WRY        (INSN_OP(2) | INSN_OP3(0x30))
 193 #define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
 194 #define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
 195 #define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
 196 #define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
 197 #define CALL       INSN_OP(1)
 198 #define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
 199 #define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
 200 #define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
 201 #define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
 202 #define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
 203 #define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
 204 #define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
 205 #define STB        (INSN_OP(3) | INSN_OP3(0x05))
 206 #define STH        (INSN_OP(3) | INSN_OP3(0x06))
 207 #define STW        (INSN_OP(3) | INSN_OP3(0x04))
 208 #define STX        (INSN_OP(3) | INSN_OP3(0x0e))
 209
 210 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
 211 {
 212     tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(arg) |
 213               INSN_RS2(TCG_REG_G0));
 214 }
 215
 216 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 217                                 int ret, tcg_target_long arg)
 218 {
 219 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 220     if (arg != (arg & 0xffffffff))
 221         fprintf(stderr, "unimplemented %s with constant %ld\n", __func__, arg);
 222 #endif
 223     if (arg == (arg & 0xfff))
 224         tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(TCG_REG_G0) |
 225                   INSN_IMM13(arg));
 226     else {
 227         tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
 228         if (arg & 0x3ff)
 229             tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(ret) |
 230                       INSN_IMM13(arg & 0x3ff));
 231     }
 232 }
 233
 234 static inline void tcg_out_ld_raw(TCGContext *s, int ret,
 235                                   tcg_target_long arg)
 236 {
 237     tcg_out32(s, SETHI | INSN_RD(ret) | (((uint32_t)arg & 0xfffffc00) >> 10));
 238     tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 239               INSN_IMM13(arg & 0x3ff));
 240 }
 241
 242 static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
 243                                   tcg_target_long arg)
 244 {
 245 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 246     if (arg != (arg & 0xffffffff))
 247         fprintf(stderr, "unimplemented %s with offset %ld\n", __func__, arg);
 248     if (arg != (arg & 0xfff))
 249         tcg_out32(s, SETHI | INSN_RD(ret) | (((uint32_t)arg & 0xfffffc00) >> 10));
 250     tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
 251               INSN_IMM13(arg & 0x3ff));
 252 #else
 253     tcg_out_ld_raw(s, ret, arg);
 254 #endif
 255 }
 256
 257 static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
 258 {
 259     if (offset == (offset & 0xfff))
 260         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
 261                   INSN_IMM13(offset));
 262     else
 263         fprintf(stderr, "unimplemented %s with offset %d\n", __func__, offset);
 264 }
 265
 266 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
 267                               int arg1, tcg_target_long arg2)
 268 {
 269     fprintf(stderr, "unimplemented %s\n", __func__);
 270 }
 271
 272 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
 273                               int arg1, tcg_target_long arg2)
 274 {
 275     fprintf(stderr, "unimplemented %s\n", __func__);
 276 }
 277
 278 static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
 279                                  int op)
 280 {
 281     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 282               INSN_RS2(rs2));
 283 }
 284
 285 static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset,
 286                                   int op)
 287 {
 288     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 289               INSN_IMM13(offset));
 290 }
 291
 292 static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
 293 {
 294     if (val == 0 || val == -1)
 295         tcg_out32(s, WRY | INSN_IMM13(val));
 296     else
 297         fprintf(stderr, "unimplemented sety %ld\n", (long)val);
 298 }
 299
 300 static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
 301 {
 302     if (val != 0) {
 303         if (val == (val & 0xfff))
 304             tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
 305         else
 306             fprintf(stderr, "unimplemented addi %ld\n", (long)val);
 307     }
 308 }
 309
 310 static inline void tcg_out_nop(TCGContext *s)
 311 {
 312     tcg_out32(s, SETHI | INSN_RD(TCG_REG_G0) | 0);
 313 }
 314
 315 static inline void tcg_target_prologue(TCGContext *s)
 316 {
 317     tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
 318               INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
 319 }
 320
 321 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
 322                               const int *const_args)
 323 {
 324     int c;
 325
 326     switch (opc) {
 327     case INDEX_op_exit_tb:
 328         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
 329         tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
 330                   INSN_IMM13(8));
 331         tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
 332                       INSN_RS2(TCG_REG_G0));
 333         break;
 334     case INDEX_op_goto_tb:
 335         if (s->tb_jmp_offset) {
 336             /* direct jump method */
 337             if (ABS(args[0] - (unsigned long)s->code_ptr) ==
 338                 (ABS(args[0] - (unsigned long)s->code_ptr) & 0x1fffff)) {
 339                 tcg_out32(s, BA |
 340                           INSN_OFF22(args[0] - (unsigned long)s->code_ptr));
 341             } else {
 342                 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, args[0]);
 343                 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
 344                           INSN_RS2(TCG_REG_G0));
 345             }
 346             s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
 347         } else {
 348             /* indirect jump method */
 349             tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
 350             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
 351                       INSN_RS2(TCG_REG_G0));
 352         }
 353         tcg_out_nop(s);
 354         s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
 355         break;
 356     case INDEX_op_call:
 357         if (const_args[0]) {
 358             tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
 359                                   - (tcg_target_ulong)s->code_ptr) >> 2)
 360                                  & 0x3fffffff));
 361             tcg_out_nop(s);
 362         } else {
 363             tcg_out_ld_ptr(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
 364             tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) |
 365                       INSN_RS2(TCG_REG_G0));
 366             tcg_out_nop(s);
 367         }
 368         break;
 369     case INDEX_op_jmp:
 370         fprintf(stderr, "unimplemented jmp\n");
 371         break;
 372     case INDEX_op_br:
 373         fprintf(stderr, "unimplemented br\n");
 374         break;
 375     case INDEX_op_movi_i32:
 376         tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
 377         break;
 378
 379 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 380 #define OP_32_64(x)                             \
 381         glue(glue(case INDEX_op_, x), _i32:)    \
 382         glue(glue(case INDEX_op_, x), _i64:)
 383 #else
 384 #define OP_32_64(x)                             \
 385         glue(glue(case INDEX_op_, x), _i32:)
 386 #endif
 387         OP_32_64(ld8u);
 388         tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
 389         break;
 390         OP_32_64(ld8s);
 391         tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
 392         break;
 393         OP_32_64(ld16u);
 394         tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
 395         break;
 396         OP_32_64(ld16s);
 397         tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
 398         break;
 399     case INDEX_op_ld_i32:
 400 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 401     case INDEX_op_ld32u_i64:
 402 #endif
 403         tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
 404         break;
 405         OP_32_64(st8);
 406         tcg_out_ldst(s, args[0], args[1], args[2], STB);
 407         break;
 408         OP_32_64(st16);
 409         tcg_out_ldst(s, args[0], args[1], args[2], STH);
 410         break;
 411     case INDEX_op_st_i32:
 412 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 413     case INDEX_op_st32_i64:
 414 #endif
 415         tcg_out_ldst(s, args[0], args[1], args[2], STW);
 416         break;
 417         OP_32_64(add);
 418         c = ARITH_ADD;
 419         goto gen_arith32;
 420         OP_32_64(sub);
 421         c = ARITH_SUB;
 422         goto gen_arith32;
 423         OP_32_64(and);
 424         c = ARITH_AND;
 425         goto gen_arith32;
 426         OP_32_64(or);
 427         c = ARITH_OR;
 428         goto gen_arith32;
 429         OP_32_64(xor);
 430         c = ARITH_XOR;
 431         goto gen_arith32;
 432     case INDEX_op_shl_i32:
 433         c = SHIFT_SLL;
 434         goto gen_arith32;
 435     case INDEX_op_shr_i32:
 436         c = SHIFT_SRL;
 437         goto gen_arith32;
 438     case INDEX_op_sar_i32:
 439         c = SHIFT_SRA;
 440         goto gen_arith32;
 441     case INDEX_op_mul_i32:
 442         c = ARITH_UMUL;
 443         goto gen_arith32;
 444     case INDEX_op_div2_i32:
 445 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
 446         c = ARITH_SDIVX;
 447         goto gen_arith32;
 448 #else
 449         tcg_out_sety(s, 0);
 450         c = ARITH_SDIV;
 451         goto gen_arith32;
 452 #endif
 453     case INDEX_op_divu2_i32:
 454 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
 455         c = ARITH_UDIVX;
 456         goto gen_arith32;
 457 #else
 458         tcg_out_sety(s, 0);
 459         c = ARITH_UDIV;
 460         goto gen_arith32;
 461 #endif
 462
 463     case INDEX_op_brcond_i32:
 464         fprintf(stderr, "unimplemented brcond\n");
 465         break;
 466
 467     case INDEX_op_qemu_ld8u:
 468         fprintf(stderr, "unimplemented qld\n");
 469         break;
 470     case INDEX_op_qemu_ld8s:
 471         fprintf(stderr, "unimplemented qld\n");
 472         break;
 473     case INDEX_op_qemu_ld16u:
 474         fprintf(stderr, "unimplemented qld\n");
 475         break;
 476     case INDEX_op_qemu_ld16s:
 477         fprintf(stderr, "unimplemented qld\n");
 478         break;
 479     case INDEX_op_qemu_ld32u:
 480         fprintf(stderr, "unimplemented qld\n");
 481         break;
 482     case INDEX_op_qemu_ld32s:
 483         fprintf(stderr, "unimplemented qld\n");
 484         break;
 485     case INDEX_op_qemu_st8:
 486         fprintf(stderr, "unimplemented qst\n");
 487         break;
 488     case INDEX_op_qemu_st16:
 489         fprintf(stderr, "unimplemented qst\n");
 490         break;
 491     case INDEX_op_qemu_st32:
 492         fprintf(stderr, "unimplemented qst\n");
 493         break;
 494
 495 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 496     case INDEX_op_movi_i64:
 497         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
 498         break;
 499     case INDEX_op_ld32s_i64:
 500         tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
 501         break;
 502     case INDEX_op_ld_i64:
 503         tcg_out_ldst(s, args[0], args[1], args[2], LDX);
 504         break;
 505     case INDEX_op_st_i64:
 506         tcg_out_ldst(s, args[0], args[1], args[2], STX);
 507         break;
 508     case INDEX_op_shl_i64:
 509         c = SHIFT_SLLX;
 510         goto gen_arith32;
 511     case INDEX_op_shr_i64:
 512         c = SHIFT_SRLX;
 513         goto gen_arith32;
 514     case INDEX_op_sar_i64:
 515         c = SHIFT_SRAX;
 516         goto gen_arith32;
 517     case INDEX_op_mul_i64:
 518         c = ARITH_MULX;
 519         goto gen_arith32;
 520     case INDEX_op_div2_i64:
 521         c = ARITH_SDIVX;
 522         goto gen_arith32;
 523     case INDEX_op_divu2_i64:
 524         c = ARITH_UDIVX;
 525         goto gen_arith32;
 526
 527     case INDEX_op_brcond_i64:
 528         fprintf(stderr, "unimplemented brcond\n");
 529         break;
 530     case INDEX_op_qemu_ld64:
 531         fprintf(stderr, "unimplemented qld\n");
 532         break;
 533     case INDEX_op_qemu_st64:
 534         fprintf(stderr, "unimplemented qst\n");
 535         break;
 536
 537 #endif
 538     gen_arith32:
 539         if (const_args[2]) {
 540             tcg_out_arithi(s, args[0], args[1], args[2], c);
 541         } else {
 542             tcg_out_arith(s, args[0], args[1], args[2], c);
 543         }
 544         break;
 545
 546     default:
 547         fprintf(stderr, "unknown opcode 0x%x\n", opc);
 548         tcg_abort();
 549     }
 550 }
 551
 552 static const TCGTargetOpDef sparc_op_defs[] = {
 553     { INDEX_op_exit_tb, { } },
 554     { INDEX_op_goto_tb, { } },
 555     { INDEX_op_call, { "ri" } },
 556     { INDEX_op_jmp, { "ri" } },
 557     { INDEX_op_br, { } },
 558
 559     { INDEX_op_mov_i32, { "r", "r" } },
 560     { INDEX_op_movi_i32, { "r" } },
 561     { INDEX_op_ld8u_i32, { "r", "r" } },
 562     { INDEX_op_ld8s_i32, { "r", "r" } },
 563     { INDEX_op_ld16u_i32, { "r", "r" } },
 564     { INDEX_op_ld16s_i32, { "r", "r" } },
 565     { INDEX_op_ld_i32, { "r", "r" } },
 566     { INDEX_op_st8_i32, { "r", "r" } },
 567     { INDEX_op_st16_i32, { "r", "r" } },
 568     { INDEX_op_st_i32, { "r", "r" } },
 569
 570     { INDEX_op_add_i32, { "r", "r", "rJ" } },
 571     { INDEX_op_mul_i32, { "r", "r", "rJ" } },
 572     { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
 573     { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
 574     { INDEX_op_sub_i32, { "r", "r", "rJ" } },
 575     { INDEX_op_and_i32, { "r", "r", "rJ" } },
 576     { INDEX_op_or_i32, { "r", "r", "rJ" } },
 577     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
 578
 579     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
 580     { INDEX_op_shr_i32, { "r", "r", "rJ" } },
 581     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
 582
 583     { INDEX_op_brcond_i32, { "r", "ri" } },
 584
 585     { INDEX_op_qemu_ld8u, { "r", "L" } },
 586     { INDEX_op_qemu_ld8s, { "r", "L" } },
 587     { INDEX_op_qemu_ld16u, { "r", "L" } },
 588     { INDEX_op_qemu_ld16s, { "r", "L" } },
 589     { INDEX_op_qemu_ld32u, { "r", "L" } },
 590     { INDEX_op_qemu_ld32s, { "r", "L" } },
 591
 592     { INDEX_op_qemu_st8, { "L", "L" } },
 593     { INDEX_op_qemu_st16, { "L", "L" } },
 594     { INDEX_op_qemu_st32, { "L", "L" } },
 595
 596 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 597     { INDEX_op_mov_i64, { "r", "r" } },
 598     { INDEX_op_movi_i64, { "r" } },
 599     { INDEX_op_ld8u_i64, { "r", "r" } },
 600     { INDEX_op_ld8s_i64, { "r", "r" } },
 601     { INDEX_op_ld16u_i64, { "r", "r" } },
 602     { INDEX_op_ld16s_i64, { "r", "r" } },
 603     { INDEX_op_ld32u_i64, { "r", "r" } },
 604     { INDEX_op_ld32s_i64, { "r", "r" } },
 605     { INDEX_op_ld_i64, { "r", "r" } },
 606     { INDEX_op_st8_i64, { "r", "r" } },
 607     { INDEX_op_st16_i64, { "r", "r" } },
 608     { INDEX_op_st32_i64, { "r", "r" } },
 609     { INDEX_op_st_i64, { "r", "r" } },
 610
 611     { INDEX_op_add_i64, { "r", "r", "rJ" } },
 612     { INDEX_op_mul_i64, { "r", "r", "rJ" } },
 613     { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
 614     { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
 615     { INDEX_op_sub_i64, { "r", "r", "rJ" } },
 616     { INDEX_op_and_i64, { "r", "r", "rJ" } },
 617     { INDEX_op_or_i64, { "r", "r", "rJ" } },
 618     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
 619
 620     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
 621     { INDEX_op_shr_i64, { "r", "r", "rJ" } },
 622     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
 623
 624     { INDEX_op_brcond_i64, { "r", "ri" } },
 625 #endif
 626     { -1 },
 627 };
 628
 629 void tcg_target_init(TCGContext *s)
 630 {
 631     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
 632 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
 633     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
 634 #endif
 635     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
 636                      (1 << TCG_REG_G1) |
 637                      (1 << TCG_REG_G2) |
 638                      (1 << TCG_REG_G3) |
 639                      (1 << TCG_REG_G4) |
 640                      (1 << TCG_REG_G5) |
 641                      (1 << TCG_REG_G6) |
 642                      (1 << TCG_REG_G7) |
 643                      (1 << TCG_REG_O0) |
 644                      (1 << TCG_REG_O1) |
 645                      (1 << TCG_REG_O2) |
 646                      (1 << TCG_REG_O3) |
 647                      (1 << TCG_REG_O4) |
 648                      (1 << TCG_REG_O5) |
 649                      (1 << TCG_REG_O7));
 650
 651     tcg_regset_clear(s->reserved_regs);
 652     tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
 653     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
 654     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
 655     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
 656     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
 657     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
 658     tcg_add_target_add_op_defs(sparc_op_defs);
 659 }