4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifdef CONFIG_USER_ONLY
32 #include "qemu-common.h"
33 #include "qemu-char.h"
38 #include "qemu_socket.h"
40 /* XXX: these constants may be independent of the host ones even for Unix */
60 typedef struct GDBState
{
61 CPUState
*env
; /* current CPU */
62 enum RSState state
; /* parsing state */
66 uint8_t last_packet
[4100];
68 #ifdef CONFIG_USER_ONLY
76 /* By default use no IRQs and no timers while single stepping so as to
77 * make single stepping like an ICE HW step.
79 static int sstep_flags
= SSTEP_ENABLE
|SSTEP_NOIRQ
|SSTEP_NOTIMER
;
81 #ifdef CONFIG_USER_ONLY
82 /* XXX: This is not thread safe. Do we care? */
83 static int gdbserver_fd
= -1;
85 /* XXX: remove this hack. */
86 static GDBState gdbserver_state
;
88 static int get_char(GDBState
*s
)
94 ret
= recv(s
->fd
, &ch
, 1, 0);
96 if (errno
!= EINTR
&& errno
!= EAGAIN
)
98 } else if (ret
== 0) {
108 /* GDB stub state for use by semihosting syscalls. */
109 static GDBState
*gdb_syscall_state
;
110 static gdb_syscall_complete_cb gdb_current_syscall_cb
;
118 /* If gdb is connected when the first semihosting syscall occurs then use
119 remote gdb syscalls. Otherwise use native file IO. */
120 int use_gdb_syscalls(void)
122 if (gdb_syscall_mode
== GDB_SYS_UNKNOWN
) {
123 gdb_syscall_mode
= (gdb_syscall_state
? GDB_SYS_ENABLED
126 return gdb_syscall_mode
== GDB_SYS_ENABLED
;
129 /* Resume execution. */
130 static inline void gdb_continue(GDBState
*s
)
132 #ifdef CONFIG_USER_ONLY
133 s
->running_state
= 1;
139 static void put_buffer(GDBState
*s
, const uint8_t *buf
, int len
)
141 #ifdef CONFIG_USER_ONLY
145 ret
= send(s
->fd
, buf
, len
, 0);
147 if (errno
!= EINTR
&& errno
!= EAGAIN
)
155 qemu_chr_write(s
->chr
, buf
, len
);
159 static inline int fromhex(int v
)
161 if (v
>= '0' && v
<= '9')
163 else if (v
>= 'A' && v
<= 'F')
165 else if (v
>= 'a' && v
<= 'f')
171 static inline int tohex(int v
)
179 static void memtohex(char *buf
, const uint8_t *mem
, int len
)
184 for(i
= 0; i
< len
; i
++) {
186 *q
++ = tohex(c
>> 4);
187 *q
++ = tohex(c
& 0xf);
192 static void hextomem(uint8_t *mem
, const char *buf
, int len
)
196 for(i
= 0; i
< len
; i
++) {
197 mem
[i
] = (fromhex(buf
[0]) << 4) | fromhex(buf
[1]);
202 /* return -1 if error, 0 if OK */
203 static int put_packet(GDBState
*s
, char *buf
)
209 printf("reply='%s'\n", buf
);
219 for(i
= 0; i
< len
; i
++) {
223 *(p
++) = tohex((csum
>> 4) & 0xf);
224 *(p
++) = tohex((csum
) & 0xf);
226 s
->last_packet_len
= p
- s
->last_packet
;
227 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
229 #ifdef CONFIG_USER_ONLY
242 #if defined(TARGET_I386)
245 static const uint8_t gdb_x86_64_regs
[16] = {
246 R_EAX
, R_EBX
, R_ECX
, R_EDX
, R_ESI
, R_EDI
, R_EBP
, R_ESP
,
247 8, 9, 10, 11, 12, 13, 14, 15,
251 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
253 int i
, fpus
, nb_regs
;
258 if (env
->hflags
& HF_CS64_MASK
) {
260 for(i
= 0; i
< 16; i
++) {
261 *(uint64_t *)p
= tswap64(env
->regs
[gdb_x86_64_regs
[i
]]);
264 *(uint64_t *)p
= tswap64(env
->eip
);
270 for(i
= 0; i
< 8; i
++) {
271 *(uint32_t *)p
= tswap32(env
->regs
[i
]);
274 *(uint32_t *)p
= tswap32(env
->eip
);
278 *(uint32_t *)p
= tswap32(env
->eflags
);
280 *(uint32_t *)p
= tswap32(env
->segs
[R_CS
].selector
);
282 *(uint32_t *)p
= tswap32(env
->segs
[R_SS
].selector
);
284 *(uint32_t *)p
= tswap32(env
->segs
[R_DS
].selector
);
286 *(uint32_t *)p
= tswap32(env
->segs
[R_ES
].selector
);
288 *(uint32_t *)p
= tswap32(env
->segs
[R_FS
].selector
);
290 *(uint32_t *)p
= tswap32(env
->segs
[R_GS
].selector
);
292 for(i
= 0; i
< 8; i
++) {
293 /* XXX: convert floats */
294 #ifdef USE_X86LDOUBLE
295 memcpy(p
, &env
->fpregs
[i
], 10);
301 *(uint32_t *)p
= tswap32(env
->fpuc
); /* fctrl */
303 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
304 *(uint32_t *)p
= tswap32(fpus
); /* fstat */
306 *(uint32_t *)p
= 0; /* ftag */
308 *(uint32_t *)p
= 0; /* fiseg */
310 *(uint32_t *)p
= 0; /* fioff */
312 *(uint32_t *)p
= 0; /* foseg */
314 *(uint32_t *)p
= 0; /* fooff */
316 *(uint32_t *)p
= 0; /* fop */
318 for(i
= 0; i
< nb_regs
; i
++) {
319 *(uint64_t *)p
= tswap64(env
->xmm_regs
[i
].XMM_Q(0));
321 *(uint64_t *)p
= tswap64(env
->xmm_regs
[i
].XMM_Q(1));
324 *(uint32_t *)p
= tswap32(env
->mxcsr
);
329 static inline void cpu_gdb_load_seg(CPUState
*env
, const uint8_t **pp
,
335 sel
= tswap32(*(uint32_t *)p
);
337 if (sel
!= env
->segs
[sreg
].selector
) {
338 #if defined(CONFIG_USER_ONLY)
339 cpu_x86_load_seg(env
, sreg
, sel
);
341 /* XXX: do it with a debug function which does not raise an
348 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
350 const uint8_t *p
= mem_buf
;
355 if (env
->hflags
& HF_CS64_MASK
) {
357 for(i
= 0; i
< 16; i
++) {
358 env
->regs
[gdb_x86_64_regs
[i
]] = tswap64(*(uint64_t *)p
);
361 env
->eip
= tswap64(*(uint64_t *)p
);
367 for(i
= 0; i
< 8; i
++) {
368 env
->regs
[i
] = tswap32(*(uint32_t *)p
);
371 env
->eip
= tswap32(*(uint32_t *)p
);
374 env
->eflags
= tswap32(*(uint32_t *)p
);
376 cpu_gdb_load_seg(env
, &p
, R_CS
);
377 cpu_gdb_load_seg(env
, &p
, R_SS
);
378 cpu_gdb_load_seg(env
, &p
, R_DS
);
379 cpu_gdb_load_seg(env
, &p
, R_ES
);
380 cpu_gdb_load_seg(env
, &p
, R_FS
);
381 cpu_gdb_load_seg(env
, &p
, R_GS
);
384 for(i
= 0; i
< 8; i
++) {
385 /* XXX: convert floats */
386 #ifdef USE_X86LDOUBLE
387 memcpy(&env
->fpregs
[i
], p
, 10);
391 env
->fpuc
= tswap32(*(uint32_t *)p
); /* fctrl */
393 fpus
= tswap32(*(uint32_t *)p
);
395 env
->fpstt
= (fpus
>> 11) & 7;
396 env
->fpus
= fpus
& ~0x3800;
399 if (size
>= ((p
- mem_buf
) + 16 * nb_regs
+ 4)) {
401 for(i
= 0; i
< nb_regs
; i
++) {
402 env
->xmm_regs
[i
].XMM_Q(0) = tswap64(*(uint64_t *)p
);
404 env
->xmm_regs
[i
].XMM_Q(1) = tswap64(*(uint64_t *)p
);
407 env
->mxcsr
= tswap32(*(uint32_t *)p
);
412 #elif defined (TARGET_PPC)
413 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
415 uint32_t *registers
= (uint32_t *)mem_buf
, tmp
;
419 for(i
= 0; i
< 32; i
++) {
420 registers
[i
] = tswapl(env
->gpr
[i
]);
423 for (i
= 0; i
< 32; i
++) {
424 registers
[(i
* 2) + 32] = tswapl(*((uint32_t *)&env
->fpr
[i
]));
425 registers
[(i
* 2) + 33] = tswapl(*((uint32_t *)&env
->fpr
[i
] + 1));
427 /* nip, msr, ccr, lnk, ctr, xer, mq */
428 registers
[96] = tswapl(env
->nip
);
429 registers
[97] = tswapl(env
->msr
);
431 for (i
= 0; i
< 8; i
++)
432 tmp
|= env
->crf
[i
] << (32 - ((i
+ 1) * 4));
433 registers
[98] = tswapl(tmp
);
434 registers
[99] = tswapl(env
->lr
);
435 registers
[100] = tswapl(env
->ctr
);
436 registers
[101] = tswapl(ppc_load_xer(env
));
442 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
444 uint32_t *registers
= (uint32_t *)mem_buf
;
448 for (i
= 0; i
< 32; i
++) {
449 env
->gpr
[i
] = tswapl(registers
[i
]);
452 for (i
= 0; i
< 32; i
++) {
453 *((uint32_t *)&env
->fpr
[i
]) = tswapl(registers
[(i
* 2) + 32]);
454 *((uint32_t *)&env
->fpr
[i
] + 1) = tswapl(registers
[(i
* 2) + 33]);
456 /* nip, msr, ccr, lnk, ctr, xer, mq */
457 env
->nip
= tswapl(registers
[96]);
458 ppc_store_msr(env
, tswapl(registers
[97]));
459 registers
[98] = tswapl(registers
[98]);
460 for (i
= 0; i
< 8; i
++)
461 env
->crf
[i
] = (registers
[98] >> (32 - ((i
+ 1) * 4))) & 0xF;
462 env
->lr
= tswapl(registers
[99]);
463 env
->ctr
= tswapl(registers
[100]);
464 ppc_store_xer(env
, tswapl(registers
[101]));
466 #elif defined (TARGET_SPARC)
467 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
469 target_ulong
*registers
= (target_ulong
*)mem_buf
;
473 for(i
= 0; i
< 8; i
++) {
474 registers
[i
] = tswapl(env
->gregs
[i
]);
476 /* fill in register window */
477 for(i
= 0; i
< 24; i
++) {
478 registers
[i
+ 8] = tswapl(env
->regwptr
[i
]);
480 #ifndef TARGET_SPARC64
482 for (i
= 0; i
< 32; i
++) {
483 registers
[i
+ 32] = tswapl(*((uint32_t *)&env
->fpr
[i
]));
485 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
486 registers
[64] = tswapl(env
->y
);
491 registers
[65] = tswapl(tmp
);
493 registers
[66] = tswapl(env
->wim
);
494 registers
[67] = tswapl(env
->tbr
);
495 registers
[68] = tswapl(env
->pc
);
496 registers
[69] = tswapl(env
->npc
);
497 registers
[70] = tswapl(env
->fsr
);
498 registers
[71] = 0; /* csr */
500 return 73 * sizeof(target_ulong
);
503 for (i
= 0; i
< 64; i
+= 2) {
506 tmp
= ((uint64_t)*(uint32_t *)&env
->fpr
[i
]) << 32;
507 tmp
|= *(uint32_t *)&env
->fpr
[i
+ 1];
508 registers
[i
/ 2 + 32] = tswap64(tmp
);
510 registers
[64] = tswapl(env
->pc
);
511 registers
[65] = tswapl(env
->npc
);
512 registers
[66] = tswapl(((uint64_t)GET_CCR(env
) << 32) |
513 ((env
->asi
& 0xff) << 24) |
514 ((env
->pstate
& 0xfff) << 8) |
516 registers
[67] = tswapl(env
->fsr
);
517 registers
[68] = tswapl(env
->fprs
);
518 registers
[69] = tswapl(env
->y
);
519 return 70 * sizeof(target_ulong
);
523 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
525 target_ulong
*registers
= (target_ulong
*)mem_buf
;
529 for(i
= 0; i
< 7; i
++) {
530 env
->gregs
[i
] = tswapl(registers
[i
]);
532 /* fill in register window */
533 for(i
= 0; i
< 24; i
++) {
534 env
->regwptr
[i
] = tswapl(registers
[i
+ 8]);
536 #ifndef TARGET_SPARC64
538 for (i
= 0; i
< 32; i
++) {
539 *((uint32_t *)&env
->fpr
[i
]) = tswapl(registers
[i
+ 32]);
541 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
542 env
->y
= tswapl(registers
[64]);
543 PUT_PSR(env
, tswapl(registers
[65]));
544 env
->wim
= tswapl(registers
[66]);
545 env
->tbr
= tswapl(registers
[67]);
546 env
->pc
= tswapl(registers
[68]);
547 env
->npc
= tswapl(registers
[69]);
548 env
->fsr
= tswapl(registers
[70]);
550 for (i
= 0; i
< 64; i
+= 2) {
553 tmp
= tswap64(registers
[i
/ 2 + 32]);
554 *((uint32_t *)&env
->fpr
[i
]) = tmp
>> 32;
555 *((uint32_t *)&env
->fpr
[i
+ 1]) = tmp
& 0xffffffff;
557 env
->pc
= tswapl(registers
[64]);
558 env
->npc
= tswapl(registers
[65]);
560 uint64_t tmp
= tswapl(registers
[66]);
562 PUT_CCR(env
, tmp
>> 32);
563 env
->asi
= (tmp
>> 24) & 0xff;
564 env
->pstate
= (tmp
>> 8) & 0xfff;
565 PUT_CWP64(env
, tmp
& 0xff);
567 env
->fsr
= tswapl(registers
[67]);
568 env
->fprs
= tswapl(registers
[68]);
569 env
->y
= tswapl(registers
[69]);
572 #elif defined (TARGET_ARM)
573 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
579 /* 16 core integer registers (4 bytes each). */
580 for (i
= 0; i
< 16; i
++)
582 *(uint32_t *)ptr
= tswapl(env
->regs
[i
]);
585 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
586 Not yet implemented. */
587 memset (ptr
, 0, 8 * 12 + 4);
589 /* CPSR (4 bytes). */
590 *(uint32_t *)ptr
= tswapl (cpsr_read(env
));
593 return ptr
- mem_buf
;
596 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
602 /* Core integer registers. */
603 for (i
= 0; i
< 16; i
++)
605 env
->regs
[i
] = tswapl(*(uint32_t *)ptr
);
608 /* Ignore FPA regs and scr. */
610 cpsr_write (env
, tswapl(*(uint32_t *)ptr
), 0xffffffff);
612 #elif defined (TARGET_M68K)
613 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
621 for (i
= 0; i
< 8; i
++) {
622 *(uint32_t *)ptr
= tswapl(env
->dregs
[i
]);
626 for (i
= 0; i
< 8; i
++) {
627 *(uint32_t *)ptr
= tswapl(env
->aregs
[i
]);
630 *(uint32_t *)ptr
= tswapl(env
->sr
);
632 *(uint32_t *)ptr
= tswapl(env
->pc
);
634 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
635 ColdFire has 8-bit double precision registers. */
636 for (i
= 0; i
< 8; i
++) {
638 *(uint32_t *)ptr
= tswap32(u
.l
.upper
);
639 *(uint32_t *)ptr
= tswap32(u
.l
.lower
);
641 /* FP control regs (not implemented). */
642 memset (ptr
, 0, 3 * 4);
645 return ptr
- mem_buf
;
648 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
656 for (i
= 0; i
< 8; i
++) {
657 env
->dregs
[i
] = tswapl(*(uint32_t *)ptr
);
661 for (i
= 0; i
< 8; i
++) {
662 env
->aregs
[i
] = tswapl(*(uint32_t *)ptr
);
665 env
->sr
= tswapl(*(uint32_t *)ptr
);
667 env
->pc
= tswapl(*(uint32_t *)ptr
);
669 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
670 ColdFire has 8-bit double precision registers. */
671 for (i
= 0; i
< 8; i
++) {
672 u
.l
.upper
= tswap32(*(uint32_t *)ptr
);
673 u
.l
.lower
= tswap32(*(uint32_t *)ptr
);
676 /* FP control regs (not implemented). */
679 #elif defined (TARGET_MIPS)
680 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
686 for (i
= 0; i
< 32; i
++)
688 *(target_ulong
*)ptr
= tswapl(env
->gpr
[env
->current_tc
][i
]);
689 ptr
+= sizeof(target_ulong
);
692 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_Status
);
693 ptr
+= sizeof(target_ulong
);
695 *(target_ulong
*)ptr
= tswapl(env
->LO
[env
->current_tc
][0]);
696 ptr
+= sizeof(target_ulong
);
698 *(target_ulong
*)ptr
= tswapl(env
->HI
[env
->current_tc
][0]);
699 ptr
+= sizeof(target_ulong
);
701 *(target_ulong
*)ptr
= tswapl(env
->CP0_BadVAddr
);
702 ptr
+= sizeof(target_ulong
);
704 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_Cause
);
705 ptr
+= sizeof(target_ulong
);
707 *(target_ulong
*)ptr
= tswapl(env
->PC
[env
->current_tc
]);
708 ptr
+= sizeof(target_ulong
);
710 if (env
->CP0_Config1
& (1 << CP0C1_FP
))
712 for (i
= 0; i
< 32; i
++)
714 if (env
->CP0_Status
& (1 << CP0St_FR
))
715 *(target_ulong
*)ptr
= tswapl(env
->fpu
->fpr
[i
].d
);
717 *(target_ulong
*)ptr
= tswap32(env
->fpu
->fpr
[i
].w
[FP_ENDIAN_IDX
]);
718 ptr
+= sizeof(target_ulong
);
721 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->fpu
->fcr31
);
722 ptr
+= sizeof(target_ulong
);
724 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->fpu
->fcr0
);
725 ptr
+= sizeof(target_ulong
);
728 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
729 *(target_ulong
*)ptr
= 0;
730 ptr
+= sizeof(target_ulong
);
732 /* Registers for embedded use, we just pad them. */
733 for (i
= 0; i
< 16; i
++)
735 *(target_ulong
*)ptr
= 0;
736 ptr
+= sizeof(target_ulong
);
740 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_PRid
);
741 ptr
+= sizeof(target_ulong
);
743 return ptr
- mem_buf
;
746 /* convert MIPS rounding mode in FCR31 to IEEE library */
747 static unsigned int ieee_rm
[] =
749 float_round_nearest_even
,
754 #define RESTORE_ROUNDING_MODE \
755 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
757 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
763 for (i
= 0; i
< 32; i
++)
765 env
->gpr
[env
->current_tc
][i
] = tswapl(*(target_ulong
*)ptr
);
766 ptr
+= sizeof(target_ulong
);
769 env
->CP0_Status
= tswapl(*(target_ulong
*)ptr
);
770 ptr
+= sizeof(target_ulong
);
772 env
->LO
[env
->current_tc
][0] = tswapl(*(target_ulong
*)ptr
);
773 ptr
+= sizeof(target_ulong
);
775 env
->HI
[env
->current_tc
][0] = tswapl(*(target_ulong
*)ptr
);
776 ptr
+= sizeof(target_ulong
);
778 env
->CP0_BadVAddr
= tswapl(*(target_ulong
*)ptr
);
779 ptr
+= sizeof(target_ulong
);
781 env
->CP0_Cause
= tswapl(*(target_ulong
*)ptr
);
782 ptr
+= sizeof(target_ulong
);
784 env
->PC
[env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
785 ptr
+= sizeof(target_ulong
);
787 if (env
->CP0_Config1
& (1 << CP0C1_FP
))
789 for (i
= 0; i
< 32; i
++)
791 if (env
->CP0_Status
& (1 << CP0St_FR
))
792 env
->fpu
->fpr
[i
].d
= tswapl(*(target_ulong
*)ptr
);
794 env
->fpu
->fpr
[i
].w
[FP_ENDIAN_IDX
] = tswapl(*(target_ulong
*)ptr
);
795 ptr
+= sizeof(target_ulong
);
798 env
->fpu
->fcr31
= tswapl(*(target_ulong
*)ptr
) & 0xFF83FFFF;
799 ptr
+= sizeof(target_ulong
);
801 /* The remaining registers are assumed to be read-only. */
803 /* set rounding mode */
804 RESTORE_ROUNDING_MODE
;
806 #ifndef CONFIG_SOFTFLOAT
807 /* no floating point exception for native float */
808 SET_FP_ENABLE(env
->fcr31
, 0);
812 #elif defined (TARGET_SH4)
814 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
816 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
818 uint32_t *ptr
= (uint32_t *)mem_buf
;
821 #define SAVE(x) *ptr++=tswapl(x)
822 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
823 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
+ 16]);
825 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
]);
827 for (i
= 8; i
< 16; i
++) SAVE(env
->gregs
[i
]);
837 for (i
= 0; i
< 16; i
++)
838 SAVE(env
->fregs
[i
+ ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
841 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
]);
842 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
+ 16]);
843 return ((uint8_t *)ptr
- mem_buf
);
846 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
848 uint32_t *ptr
= (uint32_t *)mem_buf
;
851 #define LOAD(x) (x)=*ptr++;
852 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
853 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
+ 16]);
855 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
]);
857 for (i
= 8; i
< 16; i
++) LOAD(env
->gregs
[i
]);
867 for (i
= 0; i
< 16; i
++)
868 LOAD(env
->fregs
[i
+ ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
871 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
]);
872 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
+ 16]);
874 #elif defined (TARGET_CRIS)
876 static int cris_save_32 (unsigned char *d
, uint32_t value
)
879 *d
++ = (value
>>= 8);
880 *d
++ = (value
>>= 8);
881 *d
++ = (value
>>= 8);
884 static int cris_save_16 (unsigned char *d
, uint32_t value
)
887 *d
++ = (value
>>= 8);
890 static int cris_save_8 (unsigned char *d
, uint32_t value
)
896 /* FIXME: this will bug on archs not supporting unaligned word accesses. */
897 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
899 uint8_t *ptr
= mem_buf
;
903 for (i
= 0; i
< 16; i
++)
904 ptr
+= cris_save_32 (ptr
, env
->regs
[i
]);
906 srs
= env
->pregs
[PR_SRS
];
908 ptr
+= cris_save_8 (ptr
, env
->pregs
[0]);
909 ptr
+= cris_save_8 (ptr
, env
->pregs
[1]);
910 ptr
+= cris_save_32 (ptr
, env
->pregs
[2]);
911 ptr
+= cris_save_8 (ptr
, srs
);
912 ptr
+= cris_save_16 (ptr
, env
->pregs
[4]);
914 for (i
= 5; i
< 16; i
++)
915 ptr
+= cris_save_32 (ptr
, env
->pregs
[i
]);
917 ptr
+= cris_save_32 (ptr
, env
->pc
);
919 for (i
= 0; i
< 16; i
++)
920 ptr
+= cris_save_32 (ptr
, env
->sregs
[srs
][i
]);
922 return ((uint8_t *)ptr
- mem_buf
);
925 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
927 uint32_t *ptr
= (uint32_t *)mem_buf
;
930 #define LOAD(x) (x)=*ptr++;
931 for (i
= 0; i
< 16; i
++) LOAD(env
->regs
[i
]);
935 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
940 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
946 static int gdb_handle_packet(GDBState
*s
, CPUState
*env
, const char *line_buf
)
949 int ch
, reg_size
, type
;
951 uint8_t mem_buf
[4096];
953 target_ulong addr
, len
;
956 printf("command='%s'\n", line_buf
);
962 /* TODO: Make this return the correct value for user-mode. */
963 snprintf(buf
, sizeof(buf
), "S%02x", SIGTRAP
);
968 addr
= strtoull(p
, (char **)&p
, 16);
969 #if defined(TARGET_I386)
971 #elif defined (TARGET_PPC)
973 #elif defined (TARGET_SPARC)
976 #elif defined (TARGET_ARM)
977 env
->regs
[15] = addr
;
978 #elif defined (TARGET_SH4)
980 #elif defined (TARGET_MIPS)
981 env
->PC
[env
->current_tc
] = addr
;
982 #elif defined (TARGET_CRIS)
990 addr
= strtoull(p
, (char **)&p
, 16);
991 #if defined(TARGET_I386)
993 #elif defined (TARGET_PPC)
995 #elif defined (TARGET_SPARC)
998 #elif defined (TARGET_ARM)
999 env
->regs
[15] = addr
;
1000 #elif defined (TARGET_SH4)
1002 #elif defined (TARGET_MIPS)
1003 env
->PC
[env
->current_tc
] = addr
;
1004 #elif defined (TARGET_CRIS)
1008 cpu_single_step(env
, sstep_flags
);
1016 ret
= strtoull(p
, (char **)&p
, 16);
1019 err
= strtoull(p
, (char **)&p
, 16);
1026 if (gdb_current_syscall_cb
)
1027 gdb_current_syscall_cb(s
->env
, ret
, err
);
1029 put_packet(s
, "T02");
1036 reg_size
= cpu_gdb_read_registers(env
, mem_buf
);
1037 memtohex(buf
, mem_buf
, reg_size
);
1041 registers
= (void *)mem_buf
;
1042 len
= strlen(p
) / 2;
1043 hextomem((uint8_t *)registers
, p
, len
);
1044 cpu_gdb_write_registers(env
, mem_buf
, len
);
1045 put_packet(s
, "OK");
1048 addr
= strtoull(p
, (char **)&p
, 16);
1051 len
= strtoull(p
, NULL
, 16);
1052 if (cpu_memory_rw_debug(env
, addr
, mem_buf
, len
, 0) != 0) {
1053 put_packet (s
, "E14");
1055 memtohex(buf
, mem_buf
, len
);
1060 addr
= strtoull(p
, (char **)&p
, 16);
1063 len
= strtoull(p
, (char **)&p
, 16);
1066 hextomem(mem_buf
, p
, len
);
1067 if (cpu_memory_rw_debug(env
, addr
, mem_buf
, len
, 1) != 0)
1068 put_packet(s
, "E14");
1070 put_packet(s
, "OK");
1073 type
= strtoul(p
, (char **)&p
, 16);
1076 addr
= strtoull(p
, (char **)&p
, 16);
1079 len
= strtoull(p
, (char **)&p
, 16);
1080 if (type
== 0 || type
== 1) {
1081 if (cpu_breakpoint_insert(env
, addr
) < 0)
1082 goto breakpoint_error
;
1083 put_packet(s
, "OK");
1084 #ifndef CONFIG_USER_ONLY
1085 } else if (type
== 2) {
1086 if (cpu_watchpoint_insert(env
, addr
) < 0)
1087 goto breakpoint_error
;
1088 put_packet(s
, "OK");
1092 put_packet(s
, "E22");
1096 type
= strtoul(p
, (char **)&p
, 16);
1099 addr
= strtoull(p
, (char **)&p
, 16);
1102 len
= strtoull(p
, (char **)&p
, 16);
1103 if (type
== 0 || type
== 1) {
1104 cpu_breakpoint_remove(env
, addr
);
1105 put_packet(s
, "OK");
1106 #ifndef CONFIG_USER_ONLY
1107 } else if (type
== 2) {
1108 cpu_watchpoint_remove(env
, addr
);
1109 put_packet(s
, "OK");
1112 goto breakpoint_error
;
1117 /* parse any 'q' packets here */
1118 if (!strcmp(p
,"qemu.sstepbits")) {
1119 /* Query Breakpoint bit definitions */
1120 sprintf(buf
,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1126 } else if (strncmp(p
,"qemu.sstep",10) == 0) {
1127 /* Display or change the sstep_flags */
1130 /* Display current setting */
1131 sprintf(buf
,"0x%x", sstep_flags
);
1136 type
= strtoul(p
, (char **)&p
, 16);
1138 put_packet(s
, "OK");
1141 #ifdef CONFIG_LINUX_USER
1142 else if (strncmp(p
, "Offsets", 7) == 0) {
1143 TaskState
*ts
= env
->opaque
;
1146 "Text=" TARGET_ABI_FMT_lx
";Data=" TARGET_ABI_FMT_lx
1147 ";Bss=" TARGET_ABI_FMT_lx
,
1148 ts
->info
->code_offset
,
1149 ts
->info
->data_offset
,
1150 ts
->info
->data_offset
);
1157 /* put empty packet */
1165 extern void tb_flush(CPUState
*env
);
1167 #ifndef CONFIG_USER_ONLY
1168 static void gdb_vm_stopped(void *opaque
, int reason
)
1170 GDBState
*s
= opaque
;
1174 if (s
->state
== RS_SYSCALL
)
1177 /* disable single step if it was enable */
1178 cpu_single_step(s
->env
, 0);
1180 if (reason
== EXCP_DEBUG
) {
1181 if (s
->env
->watchpoint_hit
) {
1182 snprintf(buf
, sizeof(buf
), "T%02xwatch:" TARGET_FMT_lx
";",
1184 s
->env
->watchpoint
[s
->env
->watchpoint_hit
- 1].vaddr
);
1186 s
->env
->watchpoint_hit
= 0;
1191 } else if (reason
== EXCP_INTERRUPT
) {
1196 snprintf(buf
, sizeof(buf
), "S%02x", ret
);
1201 /* Send a gdb syscall request.
1202 This accepts limited printf-style format specifiers, specifically:
1203 %x - target_ulong argument printed in hex.
1204 %lx - 64-bit argument printed in hex.
1205 %s - string pointer (target_ulong) and length (int) pair. */
1206 void gdb_do_syscall(gdb_syscall_complete_cb cb
, char *fmt
, ...)
1215 s
= gdb_syscall_state
;
1218 gdb_current_syscall_cb
= cb
;
1219 s
->state
= RS_SYSCALL
;
1220 #ifndef CONFIG_USER_ONLY
1221 vm_stop(EXCP_DEBUG
);
1232 addr
= va_arg(va
, target_ulong
);
1233 p
+= sprintf(p
, TARGET_FMT_lx
, addr
);
1236 if (*(fmt
++) != 'x')
1238 i64
= va_arg(va
, uint64_t);
1239 p
+= sprintf(p
, "%" PRIx64
, i64
);
1242 addr
= va_arg(va
, target_ulong
);
1243 p
+= sprintf(p
, TARGET_FMT_lx
"/%x", addr
, va_arg(va
, int));
1247 fprintf(stderr
, "gdbstub: Bad syscall format string '%s'\n",
1258 #ifdef CONFIG_USER_ONLY
1259 gdb_handlesig(s
->env
, 0);
1261 cpu_interrupt(s
->env
, CPU_INTERRUPT_EXIT
);
1265 static void gdb_read_byte(GDBState
*s
, int ch
)
1267 CPUState
*env
= s
->env
;
1271 #ifndef CONFIG_USER_ONLY
1272 if (s
->last_packet_len
) {
1273 /* Waiting for a response to the last packet. If we see the start
1274 of a new command then abandon the previous response. */
1277 printf("Got NACK, retransmitting\n");
1279 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
1283 printf("Got ACK\n");
1285 printf("Got '%c' when expecting ACK/NACK\n", ch
);
1287 if (ch
== '+' || ch
== '$')
1288 s
->last_packet_len
= 0;
1293 /* when the CPU is running, we cannot do anything except stop
1294 it when receiving a char */
1295 vm_stop(EXCP_INTERRUPT
);
1302 s
->line_buf_index
= 0;
1303 s
->state
= RS_GETLINE
;
1308 s
->state
= RS_CHKSUM1
;
1309 } else if (s
->line_buf_index
>= sizeof(s
->line_buf
) - 1) {
1312 s
->line_buf
[s
->line_buf_index
++] = ch
;
1316 s
->line_buf
[s
->line_buf_index
] = '\0';
1317 s
->line_csum
= fromhex(ch
) << 4;
1318 s
->state
= RS_CHKSUM2
;
1321 s
->line_csum
|= fromhex(ch
);
1323 for(i
= 0; i
< s
->line_buf_index
; i
++) {
1324 csum
+= s
->line_buf
[i
];
1326 if (s
->line_csum
!= (csum
& 0xff)) {
1328 put_buffer(s
, &reply
, 1);
1332 put_buffer(s
, &reply
, 1);
1333 s
->state
= gdb_handle_packet(s
, env
, s
->line_buf
);
1342 #ifdef CONFIG_USER_ONLY
1344 gdb_handlesig (CPUState
*env
, int sig
)
1350 if (gdbserver_fd
< 0)
1353 s
= &gdbserver_state
;
1355 /* disable single step if it was enabled */
1356 cpu_single_step(env
, 0);
1361 snprintf(buf
, sizeof(buf
), "S%02x", sig
);
1367 s
->running_state
= 0;
1368 while (s
->running_state
== 0) {
1369 n
= read (s
->fd
, buf
, 256);
1374 for (i
= 0; i
< n
; i
++)
1375 gdb_read_byte (s
, buf
[i
]);
1377 else if (n
== 0 || errno
!= EAGAIN
)
1379 /* XXX: Connection closed. Should probably wait for annother
1380 connection before continuing. */
1387 /* Tell the remote gdb that the process has exited. */
1388 void gdb_exit(CPUState
*env
, int code
)
1393 if (gdbserver_fd
< 0)
1396 s
= &gdbserver_state
;
1398 snprintf(buf
, sizeof(buf
), "W%02x", code
);
1403 static void gdb_accept(void *opaque
)
1406 struct sockaddr_in sockaddr
;
1411 len
= sizeof(sockaddr
);
1412 fd
= accept(gdbserver_fd
, (struct sockaddr
*)&sockaddr
, &len
);
1413 if (fd
< 0 && errno
!= EINTR
) {
1416 } else if (fd
>= 0) {
1421 /* set short latency */
1423 setsockopt(fd
, IPPROTO_TCP
, TCP_NODELAY
, (char *)&val
, sizeof(val
));
1425 s
= &gdbserver_state
;
1426 memset (s
, 0, sizeof (GDBState
));
1427 s
->env
= first_cpu
; /* XXX: allow to change CPU */
1430 gdb_syscall_state
= s
;
1432 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
1435 static int gdbserver_open(int port
)
1437 struct sockaddr_in sockaddr
;
1440 fd
= socket(PF_INET
, SOCK_STREAM
, 0);
1446 /* allow fast reuse */
1448 setsockopt(fd
, SOL_SOCKET
, SO_REUSEADDR
, (char *)&val
, sizeof(val
));
1450 sockaddr
.sin_family
= AF_INET
;
1451 sockaddr
.sin_port
= htons(port
);
1452 sockaddr
.sin_addr
.s_addr
= 0;
1453 ret
= bind(fd
, (struct sockaddr
*)&sockaddr
, sizeof(sockaddr
));
1458 ret
= listen(fd
, 0);
1466 int gdbserver_start(int port
)
1468 gdbserver_fd
= gdbserver_open(port
);
1469 if (gdbserver_fd
< 0)
1471 /* accept connections */
1476 static int gdb_chr_can_receive(void *opaque
)
1481 static void gdb_chr_receive(void *opaque
, const uint8_t *buf
, int size
)
1483 GDBState
*s
= opaque
;
1486 for (i
= 0; i
< size
; i
++) {
1487 gdb_read_byte(s
, buf
[i
]);
1491 static void gdb_chr_event(void *opaque
, int event
)
1494 case CHR_EVENT_RESET
:
1495 vm_stop(EXCP_INTERRUPT
);
1496 gdb_syscall_state
= opaque
;
1503 int gdbserver_start(const char *port
)
1506 char gdbstub_port_name
[128];
1509 CharDriverState
*chr
;
1511 if (!port
|| !*port
)
1514 port_num
= strtol(port
, &p
, 10);
1516 /* A numeric value is interpreted as a port number. */
1517 snprintf(gdbstub_port_name
, sizeof(gdbstub_port_name
),
1518 "tcp::%d,nowait,nodelay,server", port_num
);
1519 port
= gdbstub_port_name
;
1522 chr
= qemu_chr_open(port
);
1526 s
= qemu_mallocz(sizeof(GDBState
));
1530 s
->env
= first_cpu
; /* XXX: allow to change CPU */
1532 qemu_chr_add_handlers(chr
, gdb_chr_can_receive
, gdb_chr_receive
,
1534 qemu_add_vm_stop_handler(gdb_vm_stopped
, s
);