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Move sun4c to its own hwdef (Robert Reif)
[qemu/qemu-JZ.git] / hw / sun4m.c
blob83963d9827fa2465d82f06b6a91f720b691e72f9
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38
39 //#define DEBUG_IRQ
40
41 /*
42 * Sun4m architecture was used in the following machines:
43 *
44 * SPARCserver 6xxMP/xx
45 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
46 * SPARCclassic X (4/10)
47 * SPARCstation LX/ZX (4/30)
48 * SPARCstation Voyager
49 * SPARCstation 10/xx, SPARCserver 10/xx
50 * SPARCstation 5, SPARCserver 5
51 * SPARCstation 20/xx, SPARCserver 20
52 * SPARCstation 4
53 *
54 * Sun4d architecture was used in the following machines:
55 *
56 * SPARCcenter 2000
57 * SPARCserver 1000
58 *
59 * Sun4c architecture was used in the following machines:
60 * SPARCstation 1/1+, SPARCserver 1/1+
61 * SPARCstation SLC
62 * SPARCstation IPC
63 * SPARCstation ELC
64 * SPARCstation IPX
65 *
66 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 */
68
69 #ifdef DEBUG_IRQ
70 #define DPRINTF(fmt, args...) \
71 do { printf("CPUIRQ: " fmt , ##args); } while (0)
72 #else
73 #define DPRINTF(fmt, args...)
74 #endif
75
76 #define KERNEL_LOAD_ADDR 0x00004000
77 #define CMDLINE_ADDR 0x007ff000
78 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_SIZE_MAX (512 * 1024)
80 #define PROM_VADDR 0xffd00000
81 #define PROM_FILENAME "openbios-sparc32"
82 #define CFG_ADDR 0xd00000510ULL
83 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
84
85 // Control plane, 8-bit and 24-bit planes
86 #define TCX_SIZE (9 * 1024 * 1024)
87
88 #define MAX_CPUS 16
89 #define MAX_PILS 16
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_run (void) {}
168 void DMA_init (int high_page_enable) {}
169 void DMA_register_channel (int nchan,
170 DMA_transfer_handler transfer_handler,
171 void *opaque)
172 {
173 }
174
175 static int nvram_boot_set(void *opaque, const char *boot_device)
176 {
177 unsigned int i;
178 uint8_t image[sizeof(ohwcfg_v3_t)];
179 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
180 m48t59_t *nvram = (m48t59_t *)opaque;
181
182 for (i = 0; i < sizeof(image); i++)
183 image[i] = m48t59_read(nvram, i) & 0xff;
184
185 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
186 boot_device);
187 header->nboot_devices = strlen(boot_device) & 0xff;
188 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
189
190 for (i = 0; i < sizeof(image); i++)
191 m48t59_write(nvram, i, image[i]);
192
193 return 0;
194 }
195
196 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
197 const char *boot_devices, ram_addr_t RAM_size,
198 uint32_t kernel_size,
199 int width, int height, int depth,
200 int nvram_machine_id, const char *arch)
201 {
202 unsigned int i;
203 uint32_t start, end;
204 uint8_t image[0x1ff0];
205 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
206 struct sparc_arch_cfg *sparc_header;
207 struct OpenBIOS_nvpart_v1 *part_header;
208
209 memset(image, '\0', sizeof(image));
210
211 // Try to match PPC NVRAM
212 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
213 "QEMU_BIOS");
214 header->struct_version = cpu_to_be32(3); /* structure v3 */
215
216 header->nvram_size = cpu_to_be16(0x2000);
217 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
218 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
219 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
220 header->nb_cpus = smp_cpus & 0xff;
221 header->RAM0_base = 0;
222 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
223 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
224 boot_devices);
225 header->nboot_devices = strlen(boot_devices) & 0xff;
226 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
227 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
228 if (cmdline) {
229 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
230 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
231 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
232 }
233 // XXX add initrd_image, initrd_size
234 header->width = cpu_to_be16(width);
235 header->height = cpu_to_be16(height);
236 header->depth = cpu_to_be16(depth);
237 if (nographic)
238 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
239
240 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
241
242 // Architecture specific header
243 start = sizeof(ohwcfg_v3_t);
244 sparc_header = (struct sparc_arch_cfg *)&image[start];
245 sparc_header->valid = 0;
246 start += sizeof(struct sparc_arch_cfg);
247
248 // OpenBIOS nvram variables
249 // Variable partition
250 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
251 part_header->signature = OPENBIOS_PART_SYSTEM;
252 pstrcpy(part_header->name, sizeof(part_header->name), "system");
253
254 end = start + sizeof(struct OpenBIOS_nvpart_v1);
255 for (i = 0; i < nb_prom_envs; i++)
256 end = OpenBIOS_set_var(image, end, prom_envs[i]);
257
258 // End marker
259 image[end++] = '\0';
260
261 end = start + ((end - start + 15) & ~15);
262 OpenBIOS_finish_partition(part_header, end - start);
263
264 // free partition
265 start = end;
266 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
267 part_header->signature = OPENBIOS_PART_FREE;
268 pstrcpy(part_header->name, sizeof(part_header->name), "free");
269
270 end = 0x1fd0;
271 OpenBIOS_finish_partition(part_header, end - start);
272
273 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
274 nvram_machine_id);
275
276 for (i = 0; i < sizeof(image); i++)
277 m48t59_write(nvram, i, image[i]);
278
279 qemu_register_boot_set(nvram_boot_set, nvram);
280 }
281
282 static void *slavio_intctl;
283
284 void pic_info(void)
285 {
286 if (slavio_intctl)
287 slavio_pic_info(slavio_intctl);
288 }
289
290 void irq_info(void)
291 {
292 if (slavio_intctl)
293 slavio_irq_info(slavio_intctl);
294 }
295
296 void cpu_check_irqs(CPUState *env)
297 {
298 if (env->pil_in && (env->interrupt_index == 0 ||
299 (env->interrupt_index & ~15) == TT_EXTINT)) {
300 unsigned int i;
301
302 for (i = 15; i > 0; i--) {
303 if (env->pil_in & (1 << i)) {
304 int old_interrupt = env->interrupt_index;
305
306 env->interrupt_index = TT_EXTINT | i;
307 if (old_interrupt != env->interrupt_index) {
308 DPRINTF("Set CPU IRQ %d\n", i);
309 cpu_interrupt(env, CPU_INTERRUPT_HARD);
310 }
311 break;
312 }
313 }
314 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
315 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
316 env->interrupt_index = 0;
317 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
318 }
319 }
320
321 static void cpu_set_irq(void *opaque, int irq, int level)
322 {
323 CPUState *env = opaque;
324
325 if (level) {
326 DPRINTF("Raise CPU IRQ %d\n", irq);
327 env->halted = 0;
328 env->pil_in |= 1 << irq;
329 cpu_check_irqs(env);
330 } else {
331 DPRINTF("Lower CPU IRQ %d\n", irq);
332 env->pil_in &= ~(1 << irq);
333 cpu_check_irqs(env);
334 }
335 }
336
337 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
338 {
339 }
340
341 static void *slavio_misc;
342
343 void qemu_system_powerdown(void)
344 {
345 slavio_set_power_fail(slavio_misc, 1);
346 }
347
348 static void main_cpu_reset(void *opaque)
349 {
350 CPUState *env = opaque;
351
352 cpu_reset(env);
353 env->halted = 0;
354 }
355
356 static void secondary_cpu_reset(void *opaque)
357 {
358 CPUState *env = opaque;
359
360 cpu_reset(env);
361 env->halted = 1;
362 }
363
364 static unsigned long sun4m_load_kernel(const char *kernel_filename,
365 const char *initrd_filename,
366 ram_addr_t RAM_size)
367 {
368 int linux_boot;
369 unsigned int i;
370 long initrd_size, kernel_size;
371
372 linux_boot = (kernel_filename != NULL);
373
374 kernel_size = 0;
375 if (linux_boot) {
376 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
377 NULL);
378 if (kernel_size < 0)
379 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
380 RAM_size - KERNEL_LOAD_ADDR);
381 if (kernel_size < 0)
382 kernel_size = load_image_targphys(kernel_filename,
383 KERNEL_LOAD_ADDR,
384 RAM_size - KERNEL_LOAD_ADDR);
385 if (kernel_size < 0) {
386 fprintf(stderr, "qemu: could not load kernel '%s'\n",
387 kernel_filename);
388 exit(1);
389 }
390
391 /* load initrd */
392 initrd_size = 0;
393 if (initrd_filename) {
394 initrd_size = load_image_targphys(initrd_filename,
395 INITRD_LOAD_ADDR,
396 RAM_size - INITRD_LOAD_ADDR);
397 if (initrd_size < 0) {
398 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
399 initrd_filename);
400 exit(1);
401 }
402 }
403 if (initrd_size > 0) {
404 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
405 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
406 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
407 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
408 break;
409 }
410 }
411 }
412 }
413 return kernel_size;
414 }
415
416 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
417 const char *boot_device,
418 DisplayState *ds, const char *kernel_filename,
419 const char *kernel_cmdline,
420 const char *initrd_filename, const char *cpu_model)
421
422 {
423 CPUState *env, *envs[MAX_CPUS];
424 unsigned int i;
425 void *iommu, *espdma, *ledma, *main_esp, *nvram;
426 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
427 *espdma_irq, *ledma_irq;
428 qemu_irq *esp_reset, *le_reset;
429 qemu_irq *fdc_tc;
430 unsigned long prom_offset, kernel_size;
431 int ret;
432 char buf[1024];
433 BlockDriverState *fd[MAX_FD];
434 int drive_index;
435 void *fw_cfg;
436
437 /* init CPUs */
438 if (!cpu_model)
439 cpu_model = hwdef->default_cpu_model;
440
441 for(i = 0; i < smp_cpus; i++) {
442 env = cpu_init(cpu_model);
443 if (!env) {
444 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
445 exit(1);
446 }
447 cpu_sparc_set_id(env, i);
448 envs[i] = env;
449 if (i == 0) {
450 qemu_register_reset(main_cpu_reset, env);
451 } else {
452 qemu_register_reset(secondary_cpu_reset, env);
453 env->halted = 1;
454 }
455 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
456 env->prom_addr = hwdef->slavio_base;
457 }
458
459 for (i = smp_cpus; i < MAX_CPUS; i++)
460 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
461
462
463 /* allocate RAM */
464 if ((uint64_t)RAM_size > hwdef->max_mem) {
465 fprintf(stderr,
466 "qemu: Too much memory for this machine: %d, maximum %d\n",
467 (unsigned int)(RAM_size / (1024 * 1024)),
468 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
469 exit(1);
470 }
471 cpu_register_physical_memory(0, RAM_size, 0);
472
473 /* load boot prom */
474 prom_offset = RAM_size + hwdef->vram_size;
475 cpu_register_physical_memory(hwdef->slavio_base,
476 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
477 TARGET_PAGE_MASK,
478 prom_offset | IO_MEM_ROM);
479
480 if (bios_name == NULL)
481 bios_name = PROM_FILENAME;
482 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
483 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
484 if (ret < 0 || ret > PROM_SIZE_MAX)
485 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
486 if (ret < 0 || ret > PROM_SIZE_MAX) {
487 fprintf(stderr, "qemu: could not load prom '%s'\n",
488 buf);
489 exit(1);
490 }
491 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
492
493 /* set up devices */
494 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
495 hwdef->intctl_base + 0x10000ULL,
496 &hwdef->intbit_to_level[0],
497 &slavio_irq, &slavio_cpu_irq,
498 cpu_irqs,
499 hwdef->clock_irq);
500
501 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
502 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
503
504 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
505 prom_offset | IO_MEM_ROM);
506 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
507 sizeof(idreg_data));
508 }
509
510 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
511 slavio_irq[hwdef->me_irq]);
512
513 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
514 iommu, &espdma_irq, &esp_reset);
515
516 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
517 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
518 &le_reset);
519
520 if (graphic_depth != 8 && graphic_depth != 24) {
521 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
522 exit (1);
523 }
524 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
525 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
526
527 if (nd_table[0].model == NULL
528 || strcmp(nd_table[0].model, "lance") == 0) {
529 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
530 } else if (strcmp(nd_table[0].model, "?") == 0) {
531 fprintf(stderr, "qemu: Supported NICs: lance\n");
532 exit (1);
533 } else {
534 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
535 exit (1);
536 }
537
538 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
539 hwdef->nvram_size, 8);
540
541 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
542 slavio_cpu_irq, smp_cpus);
543
544 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
545 nographic);
546 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
547 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
548 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
549 serial_hds[1], serial_hds[0]);
550
551 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
552 hwdef->aux1_base, hwdef->aux2_base,
553 slavio_irq[hwdef->me_irq], envs[0],
554 &fdc_tc);
555
556 if (hwdef->fd_base != (target_phys_addr_t)-1) {
557 /* there is zero or one floppy drive */
558 memset(fd, 0, sizeof(fd));
559 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
560 if (drive_index != -1)
561 fd[0] = drives_table[drive_index].bdrv;
562
563 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
564 fdc_tc);
565 }
566
567 if (drive_get_max_bus(IF_SCSI) > 0) {
568 fprintf(stderr, "qemu: too many SCSI bus\n");
569 exit(1);
570 }
571
572 main_esp = esp_init(hwdef->esp_base, 2,
573 espdma_memory_read, espdma_memory_write,
574 espdma, *espdma_irq, esp_reset);
575
576 for (i = 0; i < ESP_MAX_DEVS; i++) {
577 drive_index = drive_get_index(IF_SCSI, 0, i);
578 if (drive_index == -1)
579 continue;
580 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
581 }
582
583 if (hwdef->cs_base != (target_phys_addr_t)-1)
584 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
585
586 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
587 RAM_size);
588
589 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
590 boot_device, RAM_size, kernel_size, graphic_width,
591 graphic_height, graphic_depth, hwdef->nvram_machine_id,
592 "Sun4m");
593
594 if (hwdef->ecc_base != (target_phys_addr_t)-1)
595 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
596 hwdef->ecc_version);
597
598 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
599 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
600 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
601 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
602 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
603 }
604
605 enum {
606 ss2_id = 0,
607 ss5_id = 32,
608 vger_id,
609 lx_id,
610 ss4_id,
611 scls_id,
612 sbook_id,
613 ss10_id = 64,
614 ss20_id,
615 ss600mp_id,
616 ss1000_id = 96,
617 ss2000_id,
618 };
619
620 static const struct sun4m_hwdef sun4m_hwdefs[] = {
621 /* SS-5 */
622 {
623 .iommu_base = 0x10000000,
624 .tcx_base = 0x50000000,
625 .cs_base = 0x6c000000,
626 .slavio_base = 0x70000000,
627 .ms_kb_base = 0x71000000,
628 .serial_base = 0x71100000,
629 .nvram_base = 0x71200000,
630 .fd_base = 0x71400000,
631 .counter_base = 0x71d00000,
632 .intctl_base = 0x71e00000,
633 .idreg_base = 0x78000000,
634 .dma_base = 0x78400000,
635 .esp_base = 0x78800000,
636 .le_base = 0x78c00000,
637 .apc_base = 0x6a000000,
638 .aux1_base = 0x71900000,
639 .aux2_base = 0x71910000,
640 .ecc_base = -1,
641 .vram_size = 0x00100000,
642 .nvram_size = 0x2000,
643 .esp_irq = 18,
644 .le_irq = 16,
645 .clock_irq = 7,
646 .clock1_irq = 19,
647 .ms_kb_irq = 14,
648 .ser_irq = 15,
649 .fd_irq = 22,
650 .me_irq = 30,
651 .cs_irq = 5,
652 .nvram_machine_id = 0x80,
653 .machine_id = ss5_id,
654 .iommu_version = 0x05000000,
655 .intbit_to_level = {
656 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
657 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
658 },
659 .max_mem = 0x10000000,
660 .default_cpu_model = "Fujitsu MB86904",
661 },
662 /* SS-10 */
663 {
664 .iommu_base = 0xfe0000000ULL,
665 .tcx_base = 0xe20000000ULL,
666 .cs_base = -1,
667 .slavio_base = 0xff0000000ULL,
668 .ms_kb_base = 0xff1000000ULL,
669 .serial_base = 0xff1100000ULL,
670 .nvram_base = 0xff1200000ULL,
671 .fd_base = 0xff1700000ULL,
672 .counter_base = 0xff1300000ULL,
673 .intctl_base = 0xff1400000ULL,
674 .idreg_base = 0xef0000000ULL,
675 .dma_base = 0xef0400000ULL,
676 .esp_base = 0xef0800000ULL,
677 .le_base = 0xef0c00000ULL,
678 .apc_base = 0xefa000000ULL, // XXX should not exist
679 .aux1_base = 0xff1800000ULL,
680 .aux2_base = 0xff1a01000ULL,
681 .ecc_base = 0xf00000000ULL,
682 .ecc_version = 0x10000000, // version 0, implementation 1
683 .vram_size = 0x00100000,
684 .nvram_size = 0x2000,
685 .esp_irq = 18,
686 .le_irq = 16,
687 .clock_irq = 7,
688 .clock1_irq = 19,
689 .ms_kb_irq = 14,
690 .ser_irq = 15,
691 .fd_irq = 22,
692 .me_irq = 30,
693 .cs_irq = -1,
694 .ecc_irq = 28,
695 .nvram_machine_id = 0x72,
696 .machine_id = ss10_id,
697 .iommu_version = 0x03000000,
698 .intbit_to_level = {
699 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
700 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
701 },
702 .max_mem = 0xf00000000ULL,
703 .default_cpu_model = "TI SuperSparc II",
704 },
705 /* SS-600MP */
706 {
707 .iommu_base = 0xfe0000000ULL,
708 .tcx_base = 0xe20000000ULL,
709 .cs_base = -1,
710 .slavio_base = 0xff0000000ULL,
711 .ms_kb_base = 0xff1000000ULL,
712 .serial_base = 0xff1100000ULL,
713 .nvram_base = 0xff1200000ULL,
714 .fd_base = -1,
715 .counter_base = 0xff1300000ULL,
716 .intctl_base = 0xff1400000ULL,
717 .idreg_base = -1,
718 .dma_base = 0xef0081000ULL,
719 .esp_base = 0xef0080000ULL,
720 .le_base = 0xef0060000ULL,
721 .apc_base = 0xefa000000ULL, // XXX should not exist
722 .aux1_base = 0xff1800000ULL,
723 .aux2_base = 0xff1a01000ULL, // XXX should not exist
724 .ecc_base = 0xf00000000ULL,
725 .ecc_version = 0x00000000, // version 0, implementation 0
726 .vram_size = 0x00100000,
727 .nvram_size = 0x2000,
728 .esp_irq = 18,
729 .le_irq = 16,
730 .clock_irq = 7,
731 .clock1_irq = 19,
732 .ms_kb_irq = 14,
733 .ser_irq = 15,
734 .fd_irq = 22,
735 .me_irq = 30,
736 .cs_irq = -1,
737 .ecc_irq = 28,
738 .nvram_machine_id = 0x71,
739 .machine_id = ss600mp_id,
740 .iommu_version = 0x01000000,
741 .intbit_to_level = {
742 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
743 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
744 },
745 .max_mem = 0xf00000000ULL,
746 .default_cpu_model = "TI SuperSparc II",
747 },
748 /* SS-20 */
749 {
750 .iommu_base = 0xfe0000000ULL,
751 .tcx_base = 0xe20000000ULL,
752 .cs_base = -1,
753 .slavio_base = 0xff0000000ULL,
754 .ms_kb_base = 0xff1000000ULL,
755 .serial_base = 0xff1100000ULL,
756 .nvram_base = 0xff1200000ULL,
757 .fd_base = 0xff1700000ULL,
758 .counter_base = 0xff1300000ULL,
759 .intctl_base = 0xff1400000ULL,
760 .idreg_base = 0xef0000000ULL,
761 .dma_base = 0xef0400000ULL,
762 .esp_base = 0xef0800000ULL,
763 .le_base = 0xef0c00000ULL,
764 .apc_base = 0xefa000000ULL, // XXX should not exist
765 .aux1_base = 0xff1800000ULL,
766 .aux2_base = 0xff1a01000ULL,
767 .ecc_base = 0xf00000000ULL,
768 .ecc_version = 0x20000000, // version 0, implementation 2
769 .vram_size = 0x00100000,
770 .nvram_size = 0x2000,
771 .esp_irq = 18,
772 .le_irq = 16,
773 .clock_irq = 7,
774 .clock1_irq = 19,
775 .ms_kb_irq = 14,
776 .ser_irq = 15,
777 .fd_irq = 22,
778 .me_irq = 30,
779 .cs_irq = -1,
780 .ecc_irq = 28,
781 .nvram_machine_id = 0x72,
782 .machine_id = ss20_id,
783 .iommu_version = 0x13000000,
784 .intbit_to_level = {
785 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
786 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
787 },
788 .max_mem = 0xf00000000ULL,
789 .default_cpu_model = "TI SuperSparc II",
790 },
791 /* Voyager */
792 {
793 .iommu_base = 0x10000000,
794 .tcx_base = 0x50000000,
795 .cs_base = -1,
796 .slavio_base = 0x70000000,
797 .ms_kb_base = 0x71000000,
798 .serial_base = 0x71100000,
799 .nvram_base = 0x71200000,
800 .fd_base = 0x71400000,
801 .counter_base = 0x71d00000,
802 .intctl_base = 0x71e00000,
803 .idreg_base = 0x78000000,
804 .dma_base = 0x78400000,
805 .esp_base = 0x78800000,
806 .le_base = 0x78c00000,
807 .apc_base = 0x71300000, // pmc
808 .aux1_base = 0x71900000,
809 .aux2_base = 0x71910000,
810 .ecc_base = -1,
811 .vram_size = 0x00100000,
812 .nvram_size = 0x2000,
813 .esp_irq = 18,
814 .le_irq = 16,
815 .clock_irq = 7,
816 .clock1_irq = 19,
817 .ms_kb_irq = 14,
818 .ser_irq = 15,
819 .fd_irq = 22,
820 .me_irq = 30,
821 .cs_irq = -1,
822 .nvram_machine_id = 0x80,
823 .machine_id = vger_id,
824 .iommu_version = 0x05000000,
825 .intbit_to_level = {
826 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
827 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
828 },
829 .max_mem = 0x10000000,
830 .default_cpu_model = "Fujitsu MB86904",
831 },
832 /* LX */
833 {
834 .iommu_base = 0x10000000,
835 .tcx_base = 0x50000000,
836 .cs_base = -1,
837 .slavio_base = 0x70000000,
838 .ms_kb_base = 0x71000000,
839 .serial_base = 0x71100000,
840 .nvram_base = 0x71200000,
841 .fd_base = 0x71400000,
842 .counter_base = 0x71d00000,
843 .intctl_base = 0x71e00000,
844 .idreg_base = 0x78000000,
845 .dma_base = 0x78400000,
846 .esp_base = 0x78800000,
847 .le_base = 0x78c00000,
848 .apc_base = -1,
849 .aux1_base = 0x71900000,
850 .aux2_base = 0x71910000,
851 .ecc_base = -1,
852 .vram_size = 0x00100000,
853 .nvram_size = 0x2000,
854 .esp_irq = 18,
855 .le_irq = 16,
856 .clock_irq = 7,
857 .clock1_irq = 19,
858 .ms_kb_irq = 14,
859 .ser_irq = 15,
860 .fd_irq = 22,
861 .me_irq = 30,
862 .cs_irq = -1,
863 .nvram_machine_id = 0x80,
864 .machine_id = lx_id,
865 .iommu_version = 0x04000000,
866 .intbit_to_level = {
867 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
868 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
869 },
870 .max_mem = 0x10000000,
871 .default_cpu_model = "TI MicroSparc I",
872 },
873 /* SS-4 */
874 {
875 .iommu_base = 0x10000000,
876 .tcx_base = 0x50000000,
877 .cs_base = 0x6c000000,
878 .slavio_base = 0x70000000,
879 .ms_kb_base = 0x71000000,
880 .serial_base = 0x71100000,
881 .nvram_base = 0x71200000,
882 .fd_base = 0x71400000,
883 .counter_base = 0x71d00000,
884 .intctl_base = 0x71e00000,
885 .idreg_base = 0x78000000,
886 .dma_base = 0x78400000,
887 .esp_base = 0x78800000,
888 .le_base = 0x78c00000,
889 .apc_base = 0x6a000000,
890 .aux1_base = 0x71900000,
891 .aux2_base = 0x71910000,
892 .ecc_base = -1,
893 .vram_size = 0x00100000,
894 .nvram_size = 0x2000,
895 .esp_irq = 18,
896 .le_irq = 16,
897 .clock_irq = 7,
898 .clock1_irq = 19,
899 .ms_kb_irq = 14,
900 .ser_irq = 15,
901 .fd_irq = 22,
902 .me_irq = 30,
903 .cs_irq = 5,
904 .nvram_machine_id = 0x80,
905 .machine_id = ss4_id,
906 .iommu_version = 0x05000000,
907 .intbit_to_level = {
908 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
909 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
910 },
911 .max_mem = 0x10000000,
912 .default_cpu_model = "Fujitsu MB86904",
913 },
914 /* SPARCClassic */
915 {
916 .iommu_base = 0x10000000,
917 .tcx_base = 0x50000000,
918 .cs_base = -1,
919 .slavio_base = 0x70000000,
920 .ms_kb_base = 0x71000000,
921 .serial_base = 0x71100000,
922 .nvram_base = 0x71200000,
923 .fd_base = 0x71400000,
924 .counter_base = 0x71d00000,
925 .intctl_base = 0x71e00000,
926 .idreg_base = 0x78000000,
927 .dma_base = 0x78400000,
928 .esp_base = 0x78800000,
929 .le_base = 0x78c00000,
930 .apc_base = 0x6a000000,
931 .aux1_base = 0x71900000,
932 .aux2_base = 0x71910000,
933 .ecc_base = -1,
934 .vram_size = 0x00100000,
935 .nvram_size = 0x2000,
936 .esp_irq = 18,
937 .le_irq = 16,
938 .clock_irq = 7,
939 .clock1_irq = 19,
940 .ms_kb_irq = 14,
941 .ser_irq = 15,
942 .fd_irq = 22,
943 .me_irq = 30,
944 .cs_irq = -1,
945 .nvram_machine_id = 0x80,
946 .machine_id = scls_id,
947 .iommu_version = 0x05000000,
948 .intbit_to_level = {
949 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
950 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
951 },
952 .max_mem = 0x10000000,
953 .default_cpu_model = "TI MicroSparc I",
954 },
955 /* SPARCbook */
956 {
957 .iommu_base = 0x10000000,
958 .tcx_base = 0x50000000, // XXX
959 .cs_base = -1,
960 .slavio_base = 0x70000000,
961 .ms_kb_base = 0x71000000,
962 .serial_base = 0x71100000,
963 .nvram_base = 0x71200000,
964 .fd_base = 0x71400000,
965 .counter_base = 0x71d00000,
966 .intctl_base = 0x71e00000,
967 .idreg_base = 0x78000000,
968 .dma_base = 0x78400000,
969 .esp_base = 0x78800000,
970 .le_base = 0x78c00000,
971 .apc_base = 0x6a000000,
972 .aux1_base = 0x71900000,
973 .aux2_base = 0x71910000,
974 .ecc_base = -1,
975 .vram_size = 0x00100000,
976 .nvram_size = 0x2000,
977 .esp_irq = 18,
978 .le_irq = 16,
979 .clock_irq = 7,
980 .clock1_irq = 19,
981 .ms_kb_irq = 14,
982 .ser_irq = 15,
983 .fd_irq = 22,
984 .me_irq = 30,
985 .cs_irq = -1,
986 .nvram_machine_id = 0x80,
987 .machine_id = sbook_id,
988 .iommu_version = 0x05000000,
989 .intbit_to_level = {
990 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
991 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
992 },
993 .max_mem = 0x10000000,
994 .default_cpu_model = "TI MicroSparc I",
995 },
996 };
997
998 /* SPARCstation 5 hardware initialisation */
999 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1000 const char *boot_device, DisplayState *ds,
1001 const char *kernel_filename, const char *kernel_cmdline,
1002 const char *initrd_filename, const char *cpu_model)
1003 {
1004 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1005 kernel_cmdline, initrd_filename, cpu_model);
1006 }
1007
1008 /* SPARCstation 10 hardware initialisation */
1009 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1010 const char *boot_device, DisplayState *ds,
1011 const char *kernel_filename, const char *kernel_cmdline,
1012 const char *initrd_filename, const char *cpu_model)
1013 {
1014 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1015 kernel_cmdline, initrd_filename, cpu_model);
1016 }
1017
1018 /* SPARCserver 600MP hardware initialisation */
1019 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1020 const char *boot_device, DisplayState *ds,
1021 const char *kernel_filename,
1022 const char *kernel_cmdline,
1023 const char *initrd_filename, const char *cpu_model)
1024 {
1025 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1026 kernel_cmdline, initrd_filename, cpu_model);
1027 }
1028
1029 /* SPARCstation 20 hardware initialisation */
1030 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1031 const char *boot_device, DisplayState *ds,
1032 const char *kernel_filename, const char *kernel_cmdline,
1033 const char *initrd_filename, const char *cpu_model)
1034 {
1035 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1036 kernel_cmdline, initrd_filename, cpu_model);
1037 }
1038
1039 /* SPARCstation Voyager hardware initialisation */
1040 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1041 const char *boot_device, DisplayState *ds,
1042 const char *kernel_filename, const char *kernel_cmdline,
1043 const char *initrd_filename, const char *cpu_model)
1044 {
1045 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1046 kernel_cmdline, initrd_filename, cpu_model);
1047 }
1048
1049 /* SPARCstation LX hardware initialisation */
1050 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1051 const char *boot_device, DisplayState *ds,
1052 const char *kernel_filename, const char *kernel_cmdline,
1053 const char *initrd_filename, const char *cpu_model)
1054 {
1055 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1056 kernel_cmdline, initrd_filename, cpu_model);
1057 }
1058
1059 /* SPARCstation 4 hardware initialisation */
1060 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1061 const char *boot_device, DisplayState *ds,
1062 const char *kernel_filename, const char *kernel_cmdline,
1063 const char *initrd_filename, const char *cpu_model)
1064 {
1065 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1066 kernel_cmdline, initrd_filename, cpu_model);
1067 }
1068
1069 /* SPARCClassic hardware initialisation */
1070 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1071 const char *boot_device, DisplayState *ds,
1072 const char *kernel_filename, const char *kernel_cmdline,
1073 const char *initrd_filename, const char *cpu_model)
1074 {
1075 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1076 kernel_cmdline, initrd_filename, cpu_model);
1077 }
1078
1079 /* SPARCbook hardware initialisation */
1080 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1081 const char *boot_device, DisplayState *ds,
1082 const char *kernel_filename, const char *kernel_cmdline,
1083 const char *initrd_filename, const char *cpu_model)
1084 {
1085 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1086 kernel_cmdline, initrd_filename, cpu_model);
1087 }
1088
1089 QEMUMachine ss5_machine = {
1090 .name = "SS-5",
1091 .desc = "Sun4m platform, SPARCstation 5",
1092 .init = ss5_init,
1093 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1094 .nodisk_ok = 1,
1095 .use_scsi = 1,
1096 .max_cpus = 16,
1097 };
1098
1099 QEMUMachine ss10_machine = {
1100 .name = "SS-10",
1101 .desc = "Sun4m platform, SPARCstation 10",
1102 .init = ss10_init,
1103 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1104 .nodisk_ok = 1,
1105 .use_scsi = 1,
1106 .max_cpus = 16,
1107 };
1108
1109 QEMUMachine ss600mp_machine = {
1110 .name = "SS-600MP",
1111 .desc = "Sun4m platform, SPARCserver 600MP",
1112 .init = ss600mp_init,
1113 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1114 .nodisk_ok = 1,
1115 .use_scsi = 1,
1116 .max_cpus = 16,
1117 };
1118
1119 QEMUMachine ss20_machine = {
1120 .name = "SS-20",
1121 .desc = "Sun4m platform, SPARCstation 20",
1122 .init = ss20_init,
1123 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1124 .nodisk_ok = 1,
1125 .use_scsi = 1,
1126 .max_cpus = 16,
1127 };
1128
1129 QEMUMachine voyager_machine = {
1130 .name = "Voyager",
1131 .desc = "Sun4m platform, SPARCstation Voyager",
1132 .init = vger_init,
1133 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1134 .nodisk_ok = 1,
1135 .use_scsi = 1,
1136 .max_cpus = 16,
1137 };
1138
1139 QEMUMachine ss_lx_machine = {
1140 .name = "LX",
1141 .desc = "Sun4m platform, SPARCstation LX",
1142 .init = ss_lx_init,
1143 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1144 .nodisk_ok = 1,
1145 .use_scsi = 1,
1146 .max_cpus = 16,
1147 };
1148
1149 QEMUMachine ss4_machine = {
1150 .name = "SS-4",
1151 .desc = "Sun4m platform, SPARCstation 4",
1152 .init = ss4_init,
1153 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1154 .nodisk_ok = 1,
1155 .use_scsi = 1,
1156 .max_cpus = 16,
1157 };
1158
1159 QEMUMachine scls_machine = {
1160 .name = "SPARCClassic",
1161 .desc = "Sun4m platform, SPARCClassic",
1162 .init = scls_init,
1163 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1164 .nodisk_ok = 1,
1165 .use_scsi = 1,
1166 .max_cpus = 16,
1167 };
1168
1169 QEMUMachine sbook_machine = {
1170 .name = "SPARCbook",
1171 .desc = "Sun4m platform, SPARCbook",
1172 .init = sbook_init,
1173 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1174 .nodisk_ok = 1,
1175 .use_scsi = 1,
1176 .max_cpus = 16,
1177 };
1178
1179 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1180 /* SS-1000 */
1181 {
1182 .iounit_bases = {
1183 0xfe0200000ULL,
1184 0xfe1200000ULL,
1185 0xfe2200000ULL,
1186 0xfe3200000ULL,
1187 -1,
1188 },
1189 .tcx_base = 0x820000000ULL,
1190 .slavio_base = 0xf00000000ULL,
1191 .ms_kb_base = 0xf00240000ULL,
1192 .serial_base = 0xf00200000ULL,
1193 .nvram_base = 0xf00280000ULL,
1194 .counter_base = 0xf00300000ULL,
1195 .espdma_base = 0x800081000ULL,
1196 .esp_base = 0x800080000ULL,
1197 .ledma_base = 0x800040000ULL,
1198 .le_base = 0x800060000ULL,
1199 .sbi_base = 0xf02800000ULL,
1200 .vram_size = 0x00100000,
1201 .nvram_size = 0x2000,
1202 .esp_irq = 3,
1203 .le_irq = 4,
1204 .clock_irq = 14,
1205 .clock1_irq = 10,
1206 .ms_kb_irq = 12,
1207 .ser_irq = 12,
1208 .nvram_machine_id = 0x80,
1209 .machine_id = ss1000_id,
1210 .iounit_version = 0x03000000,
1211 .max_mem = 0xf00000000ULL,
1212 .default_cpu_model = "TI SuperSparc II",
1213 },
1214 /* SS-2000 */
1215 {
1216 .iounit_bases = {
1217 0xfe0200000ULL,
1218 0xfe1200000ULL,
1219 0xfe2200000ULL,
1220 0xfe3200000ULL,
1221 0xfe4200000ULL,
1222 },
1223 .tcx_base = 0x820000000ULL,
1224 .slavio_base = 0xf00000000ULL,
1225 .ms_kb_base = 0xf00240000ULL,
1226 .serial_base = 0xf00200000ULL,
1227 .nvram_base = 0xf00280000ULL,
1228 .counter_base = 0xf00300000ULL,
1229 .espdma_base = 0x800081000ULL,
1230 .esp_base = 0x800080000ULL,
1231 .ledma_base = 0x800040000ULL,
1232 .le_base = 0x800060000ULL,
1233 .sbi_base = 0xf02800000ULL,
1234 .vram_size = 0x00100000,
1235 .nvram_size = 0x2000,
1236 .esp_irq = 3,
1237 .le_irq = 4,
1238 .clock_irq = 14,
1239 .clock1_irq = 10,
1240 .ms_kb_irq = 12,
1241 .ser_irq = 12,
1242 .nvram_machine_id = 0x80,
1243 .machine_id = ss2000_id,
1244 .iounit_version = 0x03000000,
1245 .max_mem = 0xf00000000ULL,
1246 .default_cpu_model = "TI SuperSparc II",
1247 },
1248 };
1249
1250 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1251 const char *boot_device,
1252 DisplayState *ds, const char *kernel_filename,
1253 const char *kernel_cmdline,
1254 const char *initrd_filename, const char *cpu_model)
1255 {
1256 CPUState *env, *envs[MAX_CPUS];
1257 unsigned int i;
1258 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1259 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1260 *espdma_irq, *ledma_irq;
1261 qemu_irq *esp_reset, *le_reset;
1262 unsigned long prom_offset, kernel_size;
1263 int ret;
1264 char buf[1024];
1265 int drive_index;
1266 void *fw_cfg;
1267
1268 /* init CPUs */
1269 if (!cpu_model)
1270 cpu_model = hwdef->default_cpu_model;
1271
1272 for (i = 0; i < smp_cpus; i++) {
1273 env = cpu_init(cpu_model);
1274 if (!env) {
1275 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1276 exit(1);
1277 }
1278 cpu_sparc_set_id(env, i);
1279 envs[i] = env;
1280 if (i == 0) {
1281 qemu_register_reset(main_cpu_reset, env);
1282 } else {
1283 qemu_register_reset(secondary_cpu_reset, env);
1284 env->halted = 1;
1285 }
1286 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1287 env->prom_addr = hwdef->slavio_base;
1288 }
1289
1290 for (i = smp_cpus; i < MAX_CPUS; i++)
1291 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1292
1293 /* allocate RAM */
1294 if ((uint64_t)RAM_size > hwdef->max_mem) {
1295 fprintf(stderr,
1296 "qemu: Too much memory for this machine: %d, maximum %d\n",
1297 (unsigned int)(RAM_size / (1024 * 1024)),
1298 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1299 exit(1);
1300 }
1301 cpu_register_physical_memory(0, RAM_size, 0);
1302
1303 /* load boot prom */
1304 prom_offset = RAM_size + hwdef->vram_size;
1305 cpu_register_physical_memory(hwdef->slavio_base,
1306 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1307 TARGET_PAGE_MASK,
1308 prom_offset | IO_MEM_ROM);
1309
1310 if (bios_name == NULL)
1311 bios_name = PROM_FILENAME;
1312 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1313 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1314 if (ret < 0 || ret > PROM_SIZE_MAX)
1315 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1316 if (ret < 0 || ret > PROM_SIZE_MAX) {
1317 fprintf(stderr, "qemu: could not load prom '%s'\n",
1318 buf);
1319 exit(1);
1320 }
1321
1322 /* set up devices */
1323 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1324
1325 for (i = 0; i < MAX_IOUNITS; i++)
1326 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1327 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1328 hwdef->iounit_version,
1329 sbi_irq[hwdef->me_irq]);
1330
1331 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1332 iounits[0], &espdma_irq, &esp_reset);
1333
1334 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1335 iounits[0], &ledma_irq, &le_reset);
1336
1337 if (graphic_depth != 8 && graphic_depth != 24) {
1338 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1339 exit (1);
1340 }
1341 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1342 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1343
1344 if (nd_table[0].model == NULL
1345 || strcmp(nd_table[0].model, "lance") == 0) {
1346 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1347 } else if (strcmp(nd_table[0].model, "?") == 0) {
1348 fprintf(stderr, "qemu: Supported NICs: lance\n");
1349 exit (1);
1350 } else {
1351 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1352 exit (1);
1353 }
1354
1355 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1356 hwdef->nvram_size, 8);
1357
1358 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1359 sbi_cpu_irq, smp_cpus);
1360
1361 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1362 nographic);
1363 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1364 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1365 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1366 serial_hds[1], serial_hds[0]);
1367
1368 if (drive_get_max_bus(IF_SCSI) > 0) {
1369 fprintf(stderr, "qemu: too many SCSI bus\n");
1370 exit(1);
1371 }
1372
1373 main_esp = esp_init(hwdef->esp_base, 2,
1374 espdma_memory_read, espdma_memory_write,
1375 espdma, *espdma_irq, esp_reset);
1376
1377 for (i = 0; i < ESP_MAX_DEVS; i++) {
1378 drive_index = drive_get_index(IF_SCSI, 0, i);
1379 if (drive_index == -1)
1380 continue;
1381 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1382 }
1383
1384 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1385 RAM_size);
1386
1387 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1388 boot_device, RAM_size, kernel_size, graphic_width,
1389 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1390 "Sun4d");
1391
1392 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1393 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1394 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1395 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1396 }
1397
1398 /* SPARCserver 1000 hardware initialisation */
1399 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1400 const char *boot_device, DisplayState *ds,
1401 const char *kernel_filename, const char *kernel_cmdline,
1402 const char *initrd_filename, const char *cpu_model)
1403 {
1404 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1405 kernel_cmdline, initrd_filename, cpu_model);
1406 }
1407
1408 /* SPARCcenter 2000 hardware initialisation */
1409 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1410 const char *boot_device, DisplayState *ds,
1411 const char *kernel_filename, const char *kernel_cmdline,
1412 const char *initrd_filename, const char *cpu_model)
1413 {
1414 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1415 kernel_cmdline, initrd_filename, cpu_model);
1416 }
1417
1418 QEMUMachine ss1000_machine = {
1419 .name = "SS-1000",
1420 .desc = "Sun4d platform, SPARCserver 1000",
1421 .init = ss1000_init,
1422 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1423 .nodisk_ok = 1,
1424 .use_scsi = 1,
1425 .max_cpus = 16,
1426 };
1427
1428 QEMUMachine ss2000_machine = {
1429 .name = "SS-2000",
1430 .desc = "Sun4d platform, SPARCcenter 2000",
1431 .init = ss2000_init,
1432 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1433 .nodisk_ok = 1,
1434 .use_scsi = 1,
1435 .max_cpus = 16,
1436 };
1437
1438 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1439 /* SS-2 */
1440 {
1441 .iommu_base = 0xf8000000,
1442 .tcx_base = 0xfe000000,
1443 .cs_base = -1,
1444 .slavio_base = 0xf6000000,
1445 .intctl_base = 0xf5000000,
1446 .counter_base = 0xf3000000,
1447 .ms_kb_base = 0xf0000000,
1448 .serial_base = 0xf1000000,
1449 .nvram_base = 0xf2000000,
1450 .fd_base = 0xf7200000,
1451 .dma_base = 0xf8400000,
1452 .esp_base = 0xf8800000,
1453 .le_base = 0xf8c00000,
1454 .apc_base = -1,
1455 .aux1_base = 0xf7400003,
1456 .aux2_base = -1,
1457 .vram_size = 0x00100000,
1458 .nvram_size = 0x800,
1459 .esp_irq = 2,
1460 .le_irq = 3,
1461 .clock_irq = 5,
1462 .clock1_irq = 7,
1463 .ms_kb_irq = 1,
1464 .ser_irq = 1,
1465 .fd_irq = 1,
1466 .me_irq = 1,
1467 .cs_irq = -1,
1468 .nvram_machine_id = 0x55,
1469 .machine_id = ss2_id,
1470 .max_mem = 0x10000000,
1471 .default_cpu_model = "Cypress CY7C601",
1472 },
1473 };
1474
1475 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1476 const char *boot_device,
1477 DisplayState *ds, const char *kernel_filename,
1478 const char *kernel_cmdline,
1479 const char *initrd_filename, const char *cpu_model)
1480 {
1481 CPUState *env;
1482 unsigned int i;
1483 void *iommu, *espdma, *ledma, *main_esp, *nvram;
1484 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1485 qemu_irq *esp_reset, *le_reset;
1486 qemu_irq *fdc_tc;
1487 unsigned long prom_offset, kernel_size;
1488 int ret;
1489 char buf[1024];
1490 BlockDriverState *fd[MAX_FD];
1491 int drive_index;
1492 void *fw_cfg;
1493
1494 /* init CPU */
1495 if (!cpu_model)
1496 cpu_model = hwdef->default_cpu_model;
1497
1498 env = cpu_init(cpu_model);
1499 if (!env) {
1500 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1501 exit(1);
1502 }
1503
1504 cpu_sparc_set_id(env, 0);
1505
1506 qemu_register_reset(main_cpu_reset, env);
1507 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1508 env->prom_addr = hwdef->slavio_base;
1509
1510 /* allocate RAM */
1511 if ((uint64_t)RAM_size > hwdef->max_mem) {
1512 fprintf(stderr,
1513 "qemu: Too much memory for this machine: %d, maximum %d\n",
1514 (unsigned int)(RAM_size / (1024 * 1024)),
1515 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1516 exit(1);
1517 }
1518 cpu_register_physical_memory(0, RAM_size, 0);
1519
1520 /* load boot prom */
1521 prom_offset = RAM_size + hwdef->vram_size;
1522 cpu_register_physical_memory(hwdef->slavio_base,
1523 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1524 TARGET_PAGE_MASK,
1525 prom_offset | IO_MEM_ROM);
1526
1527 if (bios_name == NULL)
1528 bios_name = PROM_FILENAME;
1529 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1530 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1531 if (ret < 0 || ret > PROM_SIZE_MAX)
1532 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1533 if (ret < 0 || ret > PROM_SIZE_MAX) {
1534 fprintf(stderr, "qemu: could not load prom '%s'\n",
1535 buf);
1536 exit(1);
1537 }
1538 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
1539
1540 /* set up devices */
1541 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1542 &slavio_irq, cpu_irqs);
1543
1544 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1545 slavio_irq[hwdef->me_irq]);
1546
1547 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1548 iommu, &espdma_irq, &esp_reset);
1549
1550 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1551 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1552 &le_reset);
1553
1554 if (graphic_depth != 8 && graphic_depth != 24) {
1555 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1556 exit (1);
1557 }
1558 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1559 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1560
1561 if (nd_table[0].model == NULL
1562 || strcmp(nd_table[0].model, "lance") == 0) {
1563 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1564 } else if (strcmp(nd_table[0].model, "?") == 0) {
1565 fprintf(stderr, "qemu: Supported NICs: lance\n");
1566 exit (1);
1567 } else {
1568 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1569 exit (1);
1570 }
1571
1572 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1573 hwdef->nvram_size, 2);
1574
1575 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1576 nographic);
1577 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1578 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1579 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1580 serial_hds[1], serial_hds[0]);
1581
1582 slavio_misc = slavio_misc_init(0, hwdef->apc_base,
1583 hwdef->aux1_base, hwdef->aux2_base,
1584 slavio_irq[hwdef->me_irq], env, &fdc_tc);
1585
1586 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1587 /* there is zero or one floppy drive */
1588 fd[1] = fd[0] = NULL;
1589 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1590 if (drive_index != -1)
1591 fd[0] = drives_table[drive_index].bdrv;
1592
1593 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1594 fdc_tc);
1595 }
1596
1597 if (drive_get_max_bus(IF_SCSI) > 0) {
1598 fprintf(stderr, "qemu: too many SCSI bus\n");
1599 exit(1);
1600 }
1601
1602 main_esp = esp_init(hwdef->esp_base, 2,
1603 espdma_memory_read, espdma_memory_write,
1604 espdma, *espdma_irq, esp_reset);
1605
1606 for (i = 0; i < ESP_MAX_DEVS; i++) {
1607 drive_index = drive_get_index(IF_SCSI, 0, i);
1608 if (drive_index == -1)
1609 continue;
1610 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1611 }
1612
1613 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1614 RAM_size);
1615
1616 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1617 boot_device, RAM_size, kernel_size, graphic_width,
1618 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1619 "Sun4c");
1620
1621 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1622 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1623 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1624 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1625 }
1626
1627 /* SPARCstation 2 hardware initialisation */
1628 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1629 const char *boot_device, DisplayState *ds,
1630 const char *kernel_filename, const char *kernel_cmdline,
1631 const char *initrd_filename, const char *cpu_model)
1632 {
1633 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1634 kernel_cmdline, initrd_filename, cpu_model);
1635 }
1636
1637 QEMUMachine ss2_machine = {
1638 .name = "SS-2",
1639 .desc = "Sun4c platform, SPARCstation 2",
1640 .init = ss2_init,
1641 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1642 .nodisk_ok = 1,
1643 .use_scsi = 1,
1644 .max_cpus = 16,
1645 };
1646
jz4740 based target emulation