softmmu_template.h

   1 /*
   2  *  Software MMU support
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #define DATA_SIZE (1 << SHIFT)
  21
  22 #if DATA_SIZE == 8
  23 #define SUFFIX q
  24 #define USUFFIX q
  25 #define DATA_TYPE uint64_t
  26 #elif DATA_SIZE == 4
  27 #define SUFFIX l
  28 #define USUFFIX l
  29 #define DATA_TYPE uint32_t
  30 #elif DATA_SIZE == 2
  31 #define SUFFIX w
  32 #define USUFFIX uw
  33 #define DATA_TYPE uint16_t
  34 #elif DATA_SIZE == 1
  35 #define SUFFIX b
  36 #define USUFFIX ub
  37 #define DATA_TYPE uint8_t
  38 #else
  39 #error unsupported data size
  40 #endif
  41
  42 #ifdef SOFTMMU_CODE_ACCESS
  43 #define READ_ACCESS_TYPE 2
  44 #define ADDR_READ addr_code
  45 #else
  46 #define READ_ACCESS_TYPE 0
  47 #define ADDR_READ addr_read
  48 #endif
  49
  50 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  51                                                         int mmu_idx,
  52                                                         void *retaddr);
  53 static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
  54                                               target_ulong tlb_addr)
  55 {
  56     DATA_TYPE res;
  57     int index;
  58
  59     index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
  60 #if SHIFT <= 2
  61     res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
  62 #else
  63 #ifdef TARGET_WORDS_BIGENDIAN
  64     res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
  65     res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
  66 #else
  67     res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
  68     res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
  69 #endif
  70 #endif /* SHIFT > 2 */
  71 #ifdef USE_KQEMU
  72     env->last_io_time = cpu_get_time_fast();
  73 #endif
  74     return res;
  75 }
  76
  77 /* handle all cases except unaligned access which span two pages */
  78 DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  79                                                       int mmu_idx)
  80 {
  81     DATA_TYPE res;
  82     int index;
  83     target_ulong tlb_addr;
  84     target_phys_addr_t physaddr;
  85     void *retaddr;
  86
  87     /* test if there is match for unaligned or IO access */
  88     /* XXX: could done more in memory macro in a non portable way */
  89     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
  90  redo:
  91     tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
  92     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
  93         physaddr = addr + env->tlb_table[mmu_idx][index].addend;
  94         if (tlb_addr & ~TARGET_PAGE_MASK) {
  95             /* IO access */
  96             if ((addr & (DATA_SIZE - 1)) != 0)
  97                 goto do_unaligned_access;
  98             res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
  99         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 100             /* slow unaligned access (it spans two pages or IO) */
 101         do_unaligned_access:
 102             retaddr = GETPC();
 103 #ifdef ALIGNED_ONLY
 104             do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 105 #endif
 106             res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
 107                                                          mmu_idx, retaddr);
 108         } else {
 109             /* unaligned/aligned access in the same page */
 110 #ifdef ALIGNED_ONLY
 111             if ((addr & (DATA_SIZE - 1)) != 0) {
 112                 retaddr = GETPC();
 113                 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 114             }
 115 #endif
 116             res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
 117         }
 118     } else {
 119         /* the page is not in the TLB : fill it */
 120         retaddr = GETPC();
 121 #ifdef ALIGNED_ONLY
 122         if ((addr & (DATA_SIZE - 1)) != 0)
 123             do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 124 #endif
 125         tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 126         goto redo;
 127     }
 128     return res;
 129 }
 130
 131 /* handle all unaligned cases */
 132 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
 133                                                         int mmu_idx,
 134                                                         void *retaddr)
 135 {
 136     DATA_TYPE res, res1, res2;
 137     int index, shift;
 138     target_phys_addr_t physaddr;
 139     target_ulong tlb_addr, addr1, addr2;
 140
 141     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 142  redo:
 143     tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 144     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 145         physaddr = addr + env->tlb_table[mmu_idx][index].addend;
 146         if (tlb_addr & ~TARGET_PAGE_MASK) {
 147             /* IO access */
 148             if ((addr & (DATA_SIZE - 1)) != 0)
 149                 goto do_unaligned_access;
 150             res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
 151         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 152         do_unaligned_access:
 153             /* slow unaligned access (it spans two pages) */
 154             addr1 = addr & ~(DATA_SIZE - 1);
 155             addr2 = addr1 + DATA_SIZE;
 156             res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
 157                                                           mmu_idx, retaddr);
 158             res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
 159                                                           mmu_idx, retaddr);
 160             shift = (addr & (DATA_SIZE - 1)) * 8;
 161 #ifdef TARGET_WORDS_BIGENDIAN
 162             res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
 163 #else
 164             res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
 165 #endif
 166             res = (DATA_TYPE)res;
 167         } else {
 168             /* unaligned/aligned access in the same page */
 169             res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
 170         }
 171     } else {
 172         /* the page is not in the TLB : fill it */
 173         tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 174         goto redo;
 175     }
 176     return res;
 177 }
 178
 179 #ifndef SOFTMMU_CODE_ACCESS
 180
 181 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 182                                                    DATA_TYPE val,
 183                                                    int mmu_idx,
 184                                                    void *retaddr);
 185
 186 static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
 187                                           DATA_TYPE val,
 188                                           target_ulong tlb_addr,
 189                                           void *retaddr)
 190 {
 191     int index;
 192
 193     index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
 194     env->mem_write_vaddr = tlb_addr;
 195     env->mem_write_pc = (unsigned long)retaddr;
 196 #if SHIFT <= 2
 197     io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
 198 #else
 199 #ifdef TARGET_WORDS_BIGENDIAN
 200     io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
 201     io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
 202 #else
 203     io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
 204     io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
 205 #endif
 206 #endif /* SHIFT > 2 */
 207 #ifdef USE_KQEMU
 208     env->last_io_time = cpu_get_time_fast();
 209 #endif
 210 }
 211
 212 void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 213                                                  DATA_TYPE val,
 214                                                  int mmu_idx)
 215 {
 216     target_phys_addr_t physaddr;
 217     target_ulong tlb_addr;
 218     void *retaddr;
 219     int index;
 220
 221     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 222  redo:
 223     tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 224     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 225         physaddr = addr + env->tlb_table[mmu_idx][index].addend;
 226         if (tlb_addr & ~TARGET_PAGE_MASK) {
 227             /* IO access */
 228             if ((addr & (DATA_SIZE - 1)) != 0)
 229                 goto do_unaligned_access;
 230             retaddr = GETPC();
 231             glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
 232         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 233         do_unaligned_access:
 234             retaddr = GETPC();
 235 #ifdef ALIGNED_ONLY
 236             do_unaligned_access(addr, 1, mmu_idx, retaddr);
 237 #endif
 238             glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
 239                                                    mmu_idx, retaddr);
 240         } else {
 241             /* aligned/unaligned access in the same page */
 242 #ifdef ALIGNED_ONLY
 243             if ((addr & (DATA_SIZE - 1)) != 0) {
 244                 retaddr = GETPC();
 245                 do_unaligned_access(addr, 1, mmu_idx, retaddr);
 246             }
 247 #endif
 248             glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
 249         }
 250     } else {
 251         /* the page is not in the TLB : fill it */
 252         retaddr = GETPC();
 253 #ifdef ALIGNED_ONLY
 254         if ((addr & (DATA_SIZE - 1)) != 0)
 255             do_unaligned_access(addr, 1, mmu_idx, retaddr);
 256 #endif
 257         tlb_fill(addr, 1, mmu_idx, retaddr);
 258         goto redo;
 259     }
 260 }
 261
 262 /* handles all unaligned cases */
 263 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 264                                                    DATA_TYPE val,
 265                                                    int mmu_idx,
 266                                                    void *retaddr)
 267 {
 268     target_phys_addr_t physaddr;
 269     target_ulong tlb_addr;
 270     int index, i;
 271
 272     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 273  redo:
 274     tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 275     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 276         physaddr = addr + env->tlb_table[mmu_idx][index].addend;
 277         if (tlb_addr & ~TARGET_PAGE_MASK) {
 278             /* IO access */
 279             if ((addr & (DATA_SIZE - 1)) != 0)
 280                 goto do_unaligned_access;
 281             glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
 282         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 283         do_unaligned_access:
 284             /* XXX: not efficient, but simple */
 285             /* Note: relies on the fact that tlb_fill() does not remove the
 286              * previous page from the TLB cache.  */
 287             for(i = DATA_SIZE - 1; i >= 0; i--) {
 288 #ifdef TARGET_WORDS_BIGENDIAN
 289                 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
 290                                           mmu_idx, retaddr);
 291 #else
 292                 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
 293                                           mmu_idx, retaddr);
 294 #endif
 295             }
 296         } else {
 297             /* aligned/unaligned access in the same page */
 298             glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
 299         }
 300     } else {
 301         /* the page is not in the TLB : fill it */
 302         tlb_fill(addr, 1, mmu_idx, retaddr);
 303         goto redo;
 304     }
 305 }
 306
 307 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
 308
 309 #undef READ_ACCESS_TYPE
 310 #undef SHIFT
 311 #undef DATA_TYPE
 312 #undef SUFFIX
 313 #undef USUFFIX
 314 #undef DATA_SIZE
 315 #undef ADDR_READ