2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
4 * Copyright (c) 2006-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 //#define DEBUG_GRACKLE
34 #define GRACKLE_DPRINTF(fmt, args...) \
35 do { printf("GRACKLE: " fmt , ##args); } while (0)
37 #define GRACKLE_DPRINTF(fmt, args...)
40 typedef target_phys_addr_t pci_addr_t
;
43 typedef PCIHostState GrackleState
;
45 static void pci_grackle_config_writel (void *opaque
, target_phys_addr_t addr
,
48 GrackleState
*s
= opaque
;
50 GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx
" val %x\n", addr
,
52 #ifdef TARGET_WORDS_BIGENDIAN
58 static uint32_t pci_grackle_config_readl (void *opaque
, target_phys_addr_t addr
)
60 GrackleState
*s
= opaque
;
64 #ifdef TARGET_WORDS_BIGENDIAN
67 GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx
" val %x\n", addr
,
72 static CPUWriteMemoryFunc
*pci_grackle_config_write
[] = {
73 &pci_grackle_config_writel
,
74 &pci_grackle_config_writel
,
75 &pci_grackle_config_writel
,
78 static CPUReadMemoryFunc
*pci_grackle_config_read
[] = {
79 &pci_grackle_config_readl
,
80 &pci_grackle_config_readl
,
81 &pci_grackle_config_readl
,
84 static CPUWriteMemoryFunc
*pci_grackle_write
[] = {
85 &pci_host_data_writeb
,
86 &pci_host_data_writew
,
87 &pci_host_data_writel
,
90 static CPUReadMemoryFunc
*pci_grackle_read
[] = {
96 /* Don't know if this matches real hardware, but it agrees with OHW. */
97 static int pci_grackle_map_irq(PCIDevice
*pci_dev
, int irq_num
)
99 return (irq_num
+ (pci_dev
->devfn
>> 3)) & 3;
102 static void pci_grackle_set_irq(qemu_irq
*pic
, int irq_num
, int level
)
104 GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num
, level
);
105 qemu_set_irq(pic
[irq_num
+ 0x15], level
);
108 static void pci_grackle_reset(void *opaque
)
112 PCIBus
*pci_grackle_init(uint32_t base
, qemu_irq
*pic
)
116 int pci_mem_config
, pci_mem_data
;
118 s
= qemu_mallocz(sizeof(GrackleState
));
119 s
->bus
= pci_register_bus(pci_grackle_set_irq
, pci_grackle_map_irq
,
122 pci_mem_config
= cpu_register_io_memory(0, pci_grackle_config_read
,
123 pci_grackle_config_write
, s
);
124 pci_mem_data
= cpu_register_io_memory(0, pci_grackle_read
,
125 pci_grackle_write
, s
);
126 cpu_register_physical_memory(base
, 0x1000, pci_mem_config
);
127 cpu_register_physical_memory(base
+ 0x00200000, 0x1000, pci_mem_data
);
128 d
= pci_register_device(s
->bus
, "Grackle host bridge", sizeof(PCIDevice
),
130 d
->config
[0x00] = 0x57; // vendor_id
131 d
->config
[0x01] = 0x10;
132 d
->config
[0x02] = 0x02; // device_id
133 d
->config
[0x03] = 0x00;
134 d
->config
[0x08] = 0x00; // revision
135 d
->config
[0x09] = 0x01;
136 d
->config
[0x0a] = 0x00; // class_sub = host
137 d
->config
[0x0b] = 0x06; // class_base = PCI_bridge
138 d
->config
[0x0e] = 0x00; // header_type
141 /* PCI2PCI bridge same values as PearPC - check this */
142 d
->config
[0x00] = 0x11; // vendor_id
143 d
->config
[0x01] = 0x10;
144 d
->config
[0x02] = 0x26; // device_id
145 d
->config
[0x03] = 0x00;
146 d
->config
[0x08] = 0x02; // revision
147 d
->config
[0x0a] = 0x04; // class_sub = pci2pci
148 d
->config
[0x0b] = 0x06; // class_base = PCI_bridge
149 d
->config
[0x0e] = 0x01; // header_type
151 d
->config
[0x18] = 0x0; // primary_bus
152 d
->config
[0x19] = 0x1; // secondary_bus
153 d
->config
[0x1a] = 0x1; // subordinate_bus
154 d
->config
[0x1c] = 0x10; // io_base
155 d
->config
[0x1d] = 0x20; // io_limit
157 d
->config
[0x20] = 0x80; // memory_base
158 d
->config
[0x21] = 0x80;
159 d
->config
[0x22] = 0x90; // memory_limit
160 d
->config
[0x23] = 0x80;
162 d
->config
[0x24] = 0x00; // prefetchable_memory_base
163 d
->config
[0x25] = 0x84;
164 d
->config
[0x26] = 0x00; // prefetchable_memory_limit
165 d
->config
[0x27] = 0x85;
167 qemu_register_reset(pci_grackle_reset
, d
);
168 pci_grackle_reset(d
);