?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-ppc: fix tcg fatal error on i386 host
[qemu/qemu-JZ.git] / target-cris / translate.c
blobf5a7bf45a7e6e00c74fb160f646dfed291e02911
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 * FIXME:
24 * The condition code translation is in need of attention.
25 */
26
27 #include <stdarg.h>
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <string.h>
31 #include <inttypes.h>
32 #include <assert.h>
33
34 #include "cpu.h"
35 #include "exec-all.h"
36 #include "disas.h"
37 #include "tcg-op.h"
38 #include "helper.h"
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
41
42 #define DISAS_CRIS 0
43 #if DISAS_CRIS
44 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
45 #else
46 #define DIS(x)
47 #endif
48
49 #define D(x)
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
52
53 #define DISAS_SWI 5
54
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
58
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
63
64 static TCGv cpu_env;
65 static TCGv cpu_R[16];
66 static TCGv cpu_PR[16];
67 static TCGv cc_x;
68 static TCGv cc_src;
69 static TCGv cc_dest;
70 static TCGv cc_result;
71 static TCGv cc_op;
72 static TCGv cc_size;
73 static TCGv cc_mask;
74
75 static TCGv env_btaken;
76 static TCGv env_btarget;
77 static TCGv env_pc;
78
79 #include "gen-icount.h"
80
81 /* This is the state at translation time. */
82 typedef struct DisasContext {
83 CPUState *env;
84 target_ulong pc, ppc;
85
86 /* Decoder. */
87 uint32_t ir;
88 uint32_t opcode;
89 unsigned int op1;
90 unsigned int op2;
91 unsigned int zsize, zzsize;
92 unsigned int mode;
93 unsigned int postinc;
94
95 int update_cc;
96 int cc_op;
97 int cc_size;
98 uint32_t cc_mask;
99
100 int cc_size_uptodate; /* -1 invalid or last written value. */
101
102 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
103 int flags_uptodate; /* Wether or not $ccs is uptodate. */
104 int flagx_known; /* Wether or not flags_x has the x flag known at
105 translation time. */
106 int flags_x;
107
108 int clear_x; /* Clear x after this insn? */
109 int cpustate_changed;
110 unsigned int tb_flags; /* tb dependent flags. */
111 int is_jmp;
112
113 #define JMP_NOJMP 0
114 #define JMP_DIRECT 1
115 #define JMP_INDIRECT 2
116 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
117 uint32_t jmp_pc;
118
119 int delayed_branch;
120
121 struct TranslationBlock *tb;
122 int singlestep_enabled;
123 } DisasContext;
124
125 static void gen_BUG(DisasContext *dc, const char *file, int line)
126 {
127 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
128 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
129 cpu_abort(dc->env, "%s:%d\n", file, line);
130 }
131
132 static const char *regnames[] =
133 {
134 "$r0", "$r1", "$r2", "$r3",
135 "$r4", "$r5", "$r6", "$r7",
136 "$r8", "$r9", "$r10", "$r11",
137 "$r12", "$r13", "$sp", "$acr",
138 };
139 static const char *pregnames[] =
140 {
141 "$bz", "$vr", "$pid", "$srs",
142 "$wz", "$exs", "$eda", "$mof",
143 "$dz", "$ebp", "$erp", "$srp",
144 "$nrp", "$ccs", "$usp", "$spc",
145 };
146
147 /* We need this table to handle preg-moves with implicit width. */
148 static int preg_sizes[] = {
149 1, /* bz. */
150 1, /* vr. */
151 4, /* pid. */
152 1, /* srs. */
153 2, /* wz. */
154 4, 4, 4,
155 4, 4, 4, 4,
156 4, 4, 4, 4,
157 };
158
159 #define t_gen_mov_TN_env(tn, member) \
160 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
161 #define t_gen_mov_env_TN(member, tn) \
162 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
163
164 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
165 {
166 if (r < 0 || r > 15)
167 fprintf(stderr, "wrong register read $r%d\n", r);
168 tcg_gen_mov_tl(tn, cpu_R[r]);
169 }
170 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
171 {
172 if (r < 0 || r > 15)
173 fprintf(stderr, "wrong register write $r%d\n", r);
174 tcg_gen_mov_tl(cpu_R[r], tn);
175 }
176
177 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
178 {
179 if (offset > sizeof (CPUState))
180 fprintf(stderr, "wrong load from env from off=%d\n", offset);
181 tcg_gen_ld_tl(tn, cpu_env, offset);
182 }
183 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
184 {
185 if (offset > sizeof (CPUState))
186 fprintf(stderr, "wrong store to env at off=%d\n", offset);
187 tcg_gen_st_tl(tn, cpu_env, offset);
188 }
189
190 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
191 {
192 if (r < 0 || r > 15)
193 fprintf(stderr, "wrong register read $p%d\n", r);
194 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
195 tcg_gen_mov_tl(tn, tcg_const_tl(0));
196 else if (r == PR_VR)
197 tcg_gen_mov_tl(tn, tcg_const_tl(32));
198 else if (r == PR_EDA) {
199 printf("read from EDA!\n");
200 tcg_gen_mov_tl(tn, cpu_PR[r]);
201 }
202 else
203 tcg_gen_mov_tl(tn, cpu_PR[r]);
204 }
205 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
206 {
207 if (r < 0 || r > 15)
208 fprintf(stderr, "wrong register write $p%d\n", r);
209 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
210 return;
211 else if (r == PR_SRS)
212 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
213 else {
214 if (r == PR_PID)
215 tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
216 if (dc->tb_flags & S_FLAG && r == PR_SPC)
217 tcg_gen_helper_0_1(helper_spc_write, tn);
218 else if (r == PR_CCS)
219 dc->cpustate_changed = 1;
220 tcg_gen_mov_tl(cpu_PR[r], tn);
221 }
222 }
223
224 static inline void t_gen_raise_exception(uint32_t index)
225 {
226 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
227 }
228
229 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
230 {
231 TCGv t0, t_31;
232
233 t0 = tcg_temp_new(TCG_TYPE_TL);
234 t_31 = tcg_const_tl(31);
235 tcg_gen_shl_tl(d, a, b);
236
237 tcg_gen_sub_tl(t0, t_31, b);
238 tcg_gen_sar_tl(t0, t0, t_31);
239 tcg_gen_and_tl(t0, t0, d);
240 tcg_gen_xor_tl(d, d, t0);
241 tcg_temp_free(t0);
242 tcg_temp_free(t_31);
243 }
244
245 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
246 {
247 TCGv t0, t_31;
248
249 t0 = tcg_temp_new(TCG_TYPE_TL);
250 t_31 = tcg_temp_new(TCG_TYPE_TL);
251 tcg_gen_shr_tl(d, a, b);
252
253 tcg_gen_movi_tl(t_31, 31);
254 tcg_gen_sub_tl(t0, t_31, b);
255 tcg_gen_sar_tl(t0, t0, t_31);
256 tcg_gen_and_tl(t0, t0, d);
257 tcg_gen_xor_tl(d, d, t0);
258 tcg_temp_free(t0);
259 tcg_temp_free(t_31);
260 }
261
262 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
263 {
264 TCGv t0, t_31;
265
266 t0 = tcg_temp_new(TCG_TYPE_TL);
267 t_31 = tcg_temp_new(TCG_TYPE_TL);
268 tcg_gen_sar_tl(d, a, b);
269
270 tcg_gen_movi_tl(t_31, 31);
271 tcg_gen_sub_tl(t0, t_31, b);
272 tcg_gen_sar_tl(t0, t0, t_31);
273 tcg_gen_or_tl(d, d, t0);
274 tcg_temp_free(t0);
275 tcg_temp_free(t_31);
276 }
277
278 /* 64-bit signed mul, lower result in d and upper in d2. */
279 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
280 {
281 TCGv t0, t1;
282
283 t0 = tcg_temp_new(TCG_TYPE_I64);
284 t1 = tcg_temp_new(TCG_TYPE_I64);
285
286 tcg_gen_ext32s_i64(t0, a);
287 tcg_gen_ext32s_i64(t1, b);
288 tcg_gen_mul_i64(t0, t0, t1);
289
290 tcg_gen_trunc_i64_i32(d, t0);
291 tcg_gen_shri_i64(t0, t0, 32);
292 tcg_gen_trunc_i64_i32(d2, t0);
293
294 tcg_temp_free(t0);
295 tcg_temp_free(t1);
296 }
297
298 /* 64-bit unsigned muls, lower result in d and upper in d2. */
299 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
300 {
301 TCGv t0, t1;
302
303 t0 = tcg_temp_new(TCG_TYPE_I64);
304 t1 = tcg_temp_new(TCG_TYPE_I64);
305
306 tcg_gen_extu_i32_i64(t0, a);
307 tcg_gen_extu_i32_i64(t1, b);
308 tcg_gen_mul_i64(t0, t0, t1);
309
310 tcg_gen_trunc_i64_i32(d, t0);
311 tcg_gen_shri_i64(t0, t0, 32);
312 tcg_gen_trunc_i64_i32(d2, t0);
313
314 tcg_temp_free(t0);
315 tcg_temp_free(t1);
316 }
317
318 /* 32bit branch-free binary search for counting leading zeros. */
319 static void t_gen_lz_i32(TCGv d, TCGv x)
320 {
321 TCGv y, m, n;
322
323 y = tcg_temp_new(TCG_TYPE_I32);
324 m = tcg_temp_new(TCG_TYPE_I32);
325 n = tcg_temp_new(TCG_TYPE_I32);
326
327 /* y = -(x >> 16) */
328 tcg_gen_shri_i32(y, x, 16);
329 tcg_gen_neg_i32(y, y);
330
331 /* m = (y >> 16) & 16 */
332 tcg_gen_sari_i32(m, y, 16);
333 tcg_gen_andi_i32(m, m, 16);
334
335 /* n = 16 - m */
336 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
337 /* x = x >> m */
338 tcg_gen_shr_i32(x, x, m);
339
340 /* y = x - 0x100 */
341 tcg_gen_subi_i32(y, x, 0x100);
342 /* m = (y >> 16) & 8 */
343 tcg_gen_sari_i32(m, y, 16);
344 tcg_gen_andi_i32(m, m, 8);
345 /* n = n + m */
346 tcg_gen_add_i32(n, n, m);
347 /* x = x << m */
348 tcg_gen_shl_i32(x, x, m);
349
350 /* y = x - 0x1000 */
351 tcg_gen_subi_i32(y, x, 0x1000);
352 /* m = (y >> 16) & 4 */
353 tcg_gen_sari_i32(m, y, 16);
354 tcg_gen_andi_i32(m, m, 4);
355 /* n = n + m */
356 tcg_gen_add_i32(n, n, m);
357 /* x = x << m */
358 tcg_gen_shl_i32(x, x, m);
359
360 /* y = x - 0x4000 */
361 tcg_gen_subi_i32(y, x, 0x4000);
362 /* m = (y >> 16) & 2 */
363 tcg_gen_sari_i32(m, y, 16);
364 tcg_gen_andi_i32(m, m, 2);
365 /* n = n + m */
366 tcg_gen_add_i32(n, n, m);
367 /* x = x << m */
368 tcg_gen_shl_i32(x, x, m);
369
370 /* y = x >> 14 */
371 tcg_gen_shri_i32(y, x, 14);
372 /* m = y & ~(y >> 1) */
373 tcg_gen_sari_i32(m, y, 1);
374 tcg_gen_not_i32(m, m);
375 tcg_gen_and_i32(m, m, y);
376
377 /* d = n + 2 - m */
378 tcg_gen_addi_i32(d, n, 2);
379 tcg_gen_sub_i32(d, d, m);
380
381 tcg_temp_free(y);
382 tcg_temp_free(m);
383 tcg_temp_free(n);
384 }
385
386 static void t_gen_btst(TCGv d, TCGv a, TCGv b)
387 {
388 TCGv sbit;
389 TCGv bset;
390 TCGv t0;
391 int l1;
392
393 /* des ref:
394 The N flag is set according to the selected bit in the dest reg.
395 The Z flag is set if the selected bit and all bits to the right are
396 zero.
397 The X flag is cleared.
398 Other flags are left untouched.
399 The destination reg is not affected.
400
401 unsigned int fz, sbit, bset, mask, masked_t0;
402
403 sbit = T1 & 31;
404 bset = !!(T0 & (1 << sbit));
405 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
406 masked_t0 = T0 & mask;
407 fz = !(masked_t0 | bset);
408
409 // Clear the X, N and Z flags.
410 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
411 // Set the N and Z flags accordingly.
412 T0 |= (bset << 3) | (fz << 2);
413 */
414
415 l1 = gen_new_label();
416 sbit = tcg_temp_new(TCG_TYPE_TL);
417 bset = tcg_temp_new(TCG_TYPE_TL);
418 t0 = tcg_temp_new(TCG_TYPE_TL);
419
420 /* Compute bset and sbit. */
421 tcg_gen_andi_tl(sbit, b, 31);
422 tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
423 tcg_gen_and_tl(bset, a, t0);
424 tcg_gen_shr_tl(bset, bset, sbit);
425 /* Displace to N_FLAG. */
426 tcg_gen_shli_tl(bset, bset, 3);
427
428 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
429 tcg_gen_subi_tl(sbit, sbit, 1);
430 tcg_gen_and_tl(sbit, a, sbit);
431
432 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
433 /* or in the N_FLAG. */
434 tcg_gen_or_tl(d, d, bset);
435 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
436 /* or in the Z_FLAG. */
437 tcg_gen_ori_tl(d, d, Z_FLAG);
438 gen_set_label(l1);
439
440 tcg_temp_free(sbit);
441 tcg_temp_free(bset);
442 }
443
444 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
445 {
446 int l1;
447
448 l1 = gen_new_label();
449
450 /*
451 * d <<= 1
452 * if (d >= s)
453 * d -= s;
454 */
455 tcg_gen_shli_tl(d, a, 1);
456 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
457 tcg_gen_sub_tl(d, d, b);
458 gen_set_label(l1);
459 }
460
461 /* Extended arithmetics on CRIS. */
462 static inline void t_gen_add_flag(TCGv d, int flag)
463 {
464 TCGv c;
465
466 c = tcg_temp_new(TCG_TYPE_TL);
467 t_gen_mov_TN_preg(c, PR_CCS);
468 /* Propagate carry into d. */
469 tcg_gen_andi_tl(c, c, 1 << flag);
470 if (flag)
471 tcg_gen_shri_tl(c, c, flag);
472 tcg_gen_add_tl(d, d, c);
473 tcg_temp_free(c);
474 }
475
476 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
477 {
478 if (dc->flagx_known) {
479 if (dc->flags_x) {
480 TCGv c;
481
482 c = tcg_temp_new(TCG_TYPE_TL);
483 t_gen_mov_TN_preg(c, PR_CCS);
484 /* C flag is already at bit 0. */
485 tcg_gen_andi_tl(c, c, C_FLAG);
486 tcg_gen_add_tl(d, d, c);
487 tcg_temp_free(c);
488 }
489 } else {
490 TCGv x, c;
491
492 x = tcg_temp_new(TCG_TYPE_TL);
493 c = tcg_temp_new(TCG_TYPE_TL);
494 t_gen_mov_TN_preg(x, PR_CCS);
495 tcg_gen_mov_tl(c, x);
496
497 /* Propagate carry into d if X is set. Branch free. */
498 tcg_gen_andi_tl(c, c, C_FLAG);
499 tcg_gen_andi_tl(x, x, X_FLAG);
500 tcg_gen_shri_tl(x, x, 4);
501
502 tcg_gen_and_tl(x, x, c);
503 tcg_gen_add_tl(d, d, x);
504 tcg_temp_free(x);
505 tcg_temp_free(c);
506 }
507 }
508
509 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
510 {
511 if (dc->flagx_known) {
512 if (dc->flags_x) {
513 TCGv c;
514
515 c = tcg_temp_new(TCG_TYPE_TL);
516 t_gen_mov_TN_preg(c, PR_CCS);
517 /* C flag is already at bit 0. */
518 tcg_gen_andi_tl(c, c, C_FLAG);
519 tcg_gen_sub_tl(d, d, c);
520 tcg_temp_free(c);
521 }
522 } else {
523 TCGv x, c;
524
525 x = tcg_temp_new(TCG_TYPE_TL);
526 c = tcg_temp_new(TCG_TYPE_TL);
527 t_gen_mov_TN_preg(x, PR_CCS);
528 tcg_gen_mov_tl(c, x);
529
530 /* Propagate carry into d if X is set. Branch free. */
531 tcg_gen_andi_tl(c, c, C_FLAG);
532 tcg_gen_andi_tl(x, x, X_FLAG);
533 tcg_gen_shri_tl(x, x, 4);
534
535 tcg_gen_and_tl(x, x, c);
536 tcg_gen_sub_tl(d, d, x);
537 tcg_temp_free(x);
538 tcg_temp_free(c);
539 }
540 }
541
542 /* Swap the two bytes within each half word of the s operand.
543 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
544 static inline void t_gen_swapb(TCGv d, TCGv s)
545 {
546 TCGv t, org_s;
547
548 t = tcg_temp_new(TCG_TYPE_TL);
549 org_s = tcg_temp_new(TCG_TYPE_TL);
550
551 /* d and s may refer to the same object. */
552 tcg_gen_mov_tl(org_s, s);
553 tcg_gen_shli_tl(t, org_s, 8);
554 tcg_gen_andi_tl(d, t, 0xff00ff00);
555 tcg_gen_shri_tl(t, org_s, 8);
556 tcg_gen_andi_tl(t, t, 0x00ff00ff);
557 tcg_gen_or_tl(d, d, t);
558 tcg_temp_free(t);
559 tcg_temp_free(org_s);
560 }
561
562 /* Swap the halfwords of the s operand. */
563 static inline void t_gen_swapw(TCGv d, TCGv s)
564 {
565 TCGv t;
566 /* d and s refer the same object. */
567 t = tcg_temp_new(TCG_TYPE_TL);
568 tcg_gen_mov_tl(t, s);
569 tcg_gen_shli_tl(d, t, 16);
570 tcg_gen_shri_tl(t, t, 16);
571 tcg_gen_or_tl(d, d, t);
572 tcg_temp_free(t);
573 }
574
575 /* Reverse the within each byte.
576 T0 = (((T0 << 7) & 0x80808080) |
577 ((T0 << 5) & 0x40404040) |
578 ((T0 << 3) & 0x20202020) |
579 ((T0 << 1) & 0x10101010) |
580 ((T0 >> 1) & 0x08080808) |
581 ((T0 >> 3) & 0x04040404) |
582 ((T0 >> 5) & 0x02020202) |
583 ((T0 >> 7) & 0x01010101));
584 */
585 static inline void t_gen_swapr(TCGv d, TCGv s)
586 {
587 struct {
588 int shift; /* LSL when positive, LSR when negative. */
589 uint32_t mask;
590 } bitrev [] = {
591 {7, 0x80808080},
592 {5, 0x40404040},
593 {3, 0x20202020},
594 {1, 0x10101010},
595 {-1, 0x08080808},
596 {-3, 0x04040404},
597 {-5, 0x02020202},
598 {-7, 0x01010101}
599 };
600 int i;
601 TCGv t, org_s;
602
603 /* d and s refer the same object. */
604 t = tcg_temp_new(TCG_TYPE_TL);
605 org_s = tcg_temp_new(TCG_TYPE_TL);
606 tcg_gen_mov_tl(org_s, s);
607
608 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
609 tcg_gen_andi_tl(d, t, bitrev[0].mask);
610 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
611 if (bitrev[i].shift >= 0) {
612 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
613 } else {
614 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
615 }
616 tcg_gen_andi_tl(t, t, bitrev[i].mask);
617 tcg_gen_or_tl(d, d, t);
618 }
619 tcg_temp_free(t);
620 tcg_temp_free(org_s);
621 }
622
623 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
624 {
625 TCGv btaken;
626 int l1;
627
628 l1 = gen_new_label();
629 btaken = tcg_temp_new(TCG_TYPE_TL);
630
631 /* Conditional jmp. */
632 tcg_gen_mov_tl(btaken, env_btaken);
633 tcg_gen_mov_tl(env_pc, pc_false);
634 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
635 tcg_gen_mov_tl(env_pc, pc_true);
636 gen_set_label(l1);
637
638 tcg_temp_free(btaken);
639 }
640
641 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
642 {
643 TranslationBlock *tb;
644 tb = dc->tb;
645 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
646 tcg_gen_goto_tb(n);
647 tcg_gen_movi_tl(env_pc, dest);
648 tcg_gen_exit_tb((long)tb + n);
649 } else {
650 tcg_gen_movi_tl(env_pc, dest);
651 tcg_gen_exit_tb(0);
652 }
653 }
654
655 /* Sign extend at translation time. */
656 static int sign_extend(unsigned int val, unsigned int width)
657 {
658 int sval;
659
660 /* LSL. */
661 val <<= 31 - width;
662 sval = val;
663 /* ASR. */
664 sval >>= 31 - width;
665 return sval;
666 }
667
668 static inline void cris_clear_x_flag(DisasContext *dc)
669 {
670 if (dc->flagx_known && dc->flags_x)
671 dc->flags_uptodate = 0;
672
673 dc->flagx_known = 1;
674 dc->flags_x = 0;
675 }
676
677 static void cris_flush_cc_state(DisasContext *dc)
678 {
679 if (dc->cc_size_uptodate != dc->cc_size) {
680 tcg_gen_movi_tl(cc_size, dc->cc_size);
681 dc->cc_size_uptodate = dc->cc_size;
682 }
683 tcg_gen_movi_tl(cc_op, dc->cc_op);
684 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
685 }
686
687 static void cris_evaluate_flags(DisasContext *dc)
688 {
689 if (!dc->flags_uptodate) {
690 cris_flush_cc_state(dc);
691
692 switch (dc->cc_op)
693 {
694 case CC_OP_MCP:
695 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
696 break;
697 case CC_OP_MULS:
698 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
699 break;
700 case CC_OP_MULU:
701 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
702 break;
703 case CC_OP_MOVE:
704 case CC_OP_AND:
705 case CC_OP_OR:
706 case CC_OP_XOR:
707 case CC_OP_ASR:
708 case CC_OP_LSR:
709 case CC_OP_LSL:
710 switch (dc->cc_size)
711 {
712 case 4:
713 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
714 break;
715 case 2:
716 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
717 break;
718 default:
719 tcg_gen_helper_0_0(helper_evaluate_flags);
720 break;
721 }
722 break;
723 case CC_OP_FLAGS:
724 /* live. */
725 break;
726 default:
727 {
728 switch (dc->cc_size)
729 {
730 case 4:
731 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
732 break;
733 default:
734 tcg_gen_helper_0_0(helper_evaluate_flags);
735 break;
736 }
737 }
738 break;
739 }
740 if (dc->flagx_known) {
741 if (dc->flags_x)
742 tcg_gen_ori_tl(cpu_PR[PR_CCS],
743 cpu_PR[PR_CCS], X_FLAG);
744 else
745 tcg_gen_andi_tl(cpu_PR[PR_CCS],
746 cpu_PR[PR_CCS], ~X_FLAG);
747 }
748
749 dc->flags_uptodate = 1;
750 }
751 }
752
753 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
754 {
755 uint32_t ovl;
756
757 if (!mask) {
758 dc->update_cc = 0;
759 return;
760 }
761
762 /* Check if we need to evaluate the condition codes due to
763 CC overlaying. */
764 ovl = (dc->cc_mask ^ mask) & ~mask;
765 if (ovl) {
766 /* TODO: optimize this case. It trigs all the time. */
767 cris_evaluate_flags (dc);
768 }
769 dc->cc_mask = mask;
770 dc->update_cc = 1;
771 }
772
773 static void cris_update_cc_op(DisasContext *dc, int op, int size)
774 {
775 dc->cc_op = op;
776 dc->cc_size = size;
777 dc->flags_uptodate = 0;
778 }
779
780 static inline void cris_update_cc_x(DisasContext *dc)
781 {
782 /* Save the x flag state at the time of the cc snapshot. */
783 if (dc->flagx_known) {
784 if (dc->cc_x_uptodate == (2 | dc->flags_x))
785 return;
786 tcg_gen_movi_tl(cc_x, dc->flags_x);
787 dc->cc_x_uptodate = 2 | dc->flags_x;
788 }
789 else {
790 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
791 dc->cc_x_uptodate = 1;
792 }
793 }
794
795 /* Update cc prior to executing ALU op. Needs source operands untouched. */
796 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
797 TCGv dst, TCGv src, int size)
798 {
799 if (dc->update_cc) {
800 cris_update_cc_op(dc, op, size);
801 tcg_gen_mov_tl(cc_src, src);
802
803 if (op != CC_OP_MOVE
804 && op != CC_OP_AND
805 && op != CC_OP_OR
806 && op != CC_OP_XOR
807 && op != CC_OP_ASR
808 && op != CC_OP_LSR
809 && op != CC_OP_LSL)
810 tcg_gen_mov_tl(cc_dest, dst);
811
812 cris_update_cc_x(dc);
813 }
814 }
815
816 /* Update cc after executing ALU op. needs the result. */
817 static inline void cris_update_result(DisasContext *dc, TCGv res)
818 {
819 if (dc->update_cc) {
820 if (dc->cc_size == 4 &&
821 (dc->cc_op == CC_OP_SUB
822 || dc->cc_op == CC_OP_ADD))
823 return;
824 tcg_gen_mov_tl(cc_result, res);
825 }
826 }
827
828 /* Returns one if the write back stage should execute. */
829 static void cris_alu_op_exec(DisasContext *dc, int op,
830 TCGv dst, TCGv a, TCGv b, int size)
831 {
832 /* Emit the ALU insns. */
833 switch (op)
834 {
835 case CC_OP_ADD:
836 tcg_gen_add_tl(dst, a, b);
837 /* Extended arithmetics. */
838 t_gen_addx_carry(dc, dst);
839 break;
840 case CC_OP_ADDC:
841 tcg_gen_add_tl(dst, a, b);
842 t_gen_add_flag(dst, 0); /* C_FLAG. */
843 break;
844 case CC_OP_MCP:
845 tcg_gen_add_tl(dst, a, b);
846 t_gen_add_flag(dst, 8); /* R_FLAG. */
847 break;
848 case CC_OP_SUB:
849 tcg_gen_sub_tl(dst, a, b);
850 /* Extended arithmetics. */
851 t_gen_subx_carry(dc, dst);
852 break;
853 case CC_OP_MOVE:
854 tcg_gen_mov_tl(dst, b);
855 break;
856 case CC_OP_OR:
857 tcg_gen_or_tl(dst, a, b);
858 break;
859 case CC_OP_AND:
860 tcg_gen_and_tl(dst, a, b);
861 break;
862 case CC_OP_XOR:
863 tcg_gen_xor_tl(dst, a, b);
864 break;
865 case CC_OP_LSL:
866 t_gen_lsl(dst, a, b);
867 break;
868 case CC_OP_LSR:
869 t_gen_lsr(dst, a, b);
870 break;
871 case CC_OP_ASR:
872 t_gen_asr(dst, a, b);
873 break;
874 case CC_OP_NEG:
875 tcg_gen_neg_tl(dst, b);
876 /* Extended arithmetics. */
877 t_gen_subx_carry(dc, dst);
878 break;
879 case CC_OP_LZ:
880 t_gen_lz_i32(dst, b);
881 break;
882 case CC_OP_BTST:
883 t_gen_btst(dst, a, b);
884 break;
885 case CC_OP_MULS:
886 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
887 break;
888 case CC_OP_MULU:
889 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
890 break;
891 case CC_OP_DSTEP:
892 t_gen_cris_dstep(dst, a, b);
893 break;
894 case CC_OP_BOUND:
895 {
896 int l1;
897 l1 = gen_new_label();
898 tcg_gen_mov_tl(dst, a);
899 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
900 tcg_gen_mov_tl(dst, b);
901 gen_set_label(l1);
902 }
903 break;
904 case CC_OP_CMP:
905 tcg_gen_sub_tl(dst, a, b);
906 /* Extended arithmetics. */
907 t_gen_subx_carry(dc, dst);
908 break;
909 default:
910 fprintf (logfile, "illegal ALU op.\n");
911 BUG();
912 break;
913 }
914
915 if (size == 1)
916 tcg_gen_andi_tl(dst, dst, 0xff);
917 else if (size == 2)
918 tcg_gen_andi_tl(dst, dst, 0xffff);
919 }
920
921 static void cris_alu(DisasContext *dc, int op,
922 TCGv d, TCGv op_a, TCGv op_b, int size)
923 {
924 TCGv tmp;
925 int writeback;
926
927 writeback = 1;
928
929 if (op == CC_OP_BOUND || op == CC_OP_BTST)
930 tmp = tcg_temp_local_new(TCG_TYPE_TL);
931
932 if (op == CC_OP_CMP) {
933 tmp = tcg_temp_new(TCG_TYPE_TL);
934 writeback = 0;
935 } else if (size == 4) {
936 tmp = d;
937 writeback = 0;
938 } else
939 tmp = tcg_temp_new(TCG_TYPE_TL);
940
941
942 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
943 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
944 cris_update_result(dc, tmp);
945
946 /* Writeback. */
947 if (writeback) {
948 if (size == 1)
949 tcg_gen_andi_tl(d, d, ~0xff);
950 else
951 tcg_gen_andi_tl(d, d, ~0xffff);
952 tcg_gen_or_tl(d, d, tmp);
953 }
954 if (GET_TCGV(tmp) != GET_TCGV(d))
955 tcg_temp_free(tmp);
956 }
957
958 static int arith_cc(DisasContext *dc)
959 {
960 if (dc->update_cc) {
961 switch (dc->cc_op) {
962 case CC_OP_ADDC: return 1;
963 case CC_OP_ADD: return 1;
964 case CC_OP_SUB: return 1;
965 case CC_OP_DSTEP: return 1;
966 case CC_OP_LSL: return 1;
967 case CC_OP_LSR: return 1;
968 case CC_OP_ASR: return 1;
969 case CC_OP_CMP: return 1;
970 case CC_OP_NEG: return 1;
971 case CC_OP_OR: return 1;
972 case CC_OP_XOR: return 1;
973 case CC_OP_MULU: return 1;
974 case CC_OP_MULS: return 1;
975 default:
976 return 0;
977 }
978 }
979 return 0;
980 }
981
982 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
983 {
984 int arith_opt, move_opt;
985
986 /* TODO: optimize more condition codes. */
987
988 /*
989 * If the flags are live, we've gotta look into the bits of CCS.
990 * Otherwise, if we just did an arithmetic operation we try to
991 * evaluate the condition code faster.
992 *
993 * When this function is done, T0 should be non-zero if the condition
994 * code is true.
995 */
996 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
997 move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;
998 switch (cond) {
999 case CC_EQ:
1000 if (arith_opt || move_opt) {
1001 /* If cc_result is zero, T0 should be
1002 non-zero otherwise T0 should be zero. */
1003 int l1;
1004 l1 = gen_new_label();
1005 tcg_gen_movi_tl(cc, 0);
1006 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
1007 0, l1);
1008 tcg_gen_movi_tl(cc, 1);
1009 gen_set_label(l1);
1010 }
1011 else {
1012 cris_evaluate_flags(dc);
1013 tcg_gen_andi_tl(cc,
1014 cpu_PR[PR_CCS], Z_FLAG);
1015 }
1016 break;
1017 case CC_NE:
1018 if (arith_opt || move_opt)
1019 tcg_gen_mov_tl(cc, cc_result);
1020 else {
1021 cris_evaluate_flags(dc);
1022 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1023 Z_FLAG);
1024 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1025 }
1026 break;
1027 case CC_CS:
1028 cris_evaluate_flags(dc);
1029 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
1030 break;
1031 case CC_CC:
1032 cris_evaluate_flags(dc);
1033 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
1034 tcg_gen_andi_tl(cc, cc, C_FLAG);
1035 break;
1036 case CC_VS:
1037 cris_evaluate_flags(dc);
1038 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
1039 break;
1040 case CC_VC:
1041 cris_evaluate_flags(dc);
1042 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1043 V_FLAG);
1044 tcg_gen_andi_tl(cc, cc, V_FLAG);
1045 break;
1046 case CC_PL:
1047 if (arith_opt || move_opt) {
1048 int bits = 31;
1049
1050 if (dc->cc_size == 1)
1051 bits = 7;
1052 else if (dc->cc_size == 2)
1053 bits = 15;
1054
1055 tcg_gen_shri_tl(cc, cc_result, bits);
1056 tcg_gen_xori_tl(cc, cc, 1);
1057 } else {
1058 cris_evaluate_flags(dc);
1059 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1060 N_FLAG);
1061 tcg_gen_andi_tl(cc, cc, N_FLAG);
1062 }
1063 break;
1064 case CC_MI:
1065 if (arith_opt || move_opt) {
1066 int bits = 31;
1067
1068 if (dc->cc_size == 1)
1069 bits = 7;
1070 else if (dc->cc_size == 2)
1071 bits = 15;
1072
1073 tcg_gen_shri_tl(cc, cc_result, 31);
1074 }
1075 else {
1076 cris_evaluate_flags(dc);
1077 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1078 N_FLAG);
1079 }
1080 break;
1081 case CC_LS:
1082 cris_evaluate_flags(dc);
1083 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1084 C_FLAG | Z_FLAG);
1085 break;
1086 case CC_HI:
1087 cris_evaluate_flags(dc);
1088 {
1089 TCGv tmp;
1090
1091 tmp = tcg_temp_new(TCG_TYPE_TL);
1092 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1093 C_FLAG | Z_FLAG);
1094 /* Overlay the C flag on top of the Z. */
1095 tcg_gen_shli_tl(cc, tmp, 2);
1096 tcg_gen_and_tl(cc, tmp, cc);
1097 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1098
1099 tcg_temp_free(tmp);
1100 }
1101 break;
1102 case CC_GE:
1103 cris_evaluate_flags(dc);
1104 /* Overlay the V flag on top of the N. */
1105 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1106 tcg_gen_xor_tl(cc,
1107 cpu_PR[PR_CCS], cc);
1108 tcg_gen_andi_tl(cc, cc, N_FLAG);
1109 tcg_gen_xori_tl(cc, cc, N_FLAG);
1110 break;
1111 case CC_LT:
1112 cris_evaluate_flags(dc);
1113 /* Overlay the V flag on top of the N. */
1114 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1115 tcg_gen_xor_tl(cc,
1116 cpu_PR[PR_CCS], cc);
1117 tcg_gen_andi_tl(cc, cc, N_FLAG);
1118 break;
1119 case CC_GT:
1120 cris_evaluate_flags(dc);
1121 {
1122 TCGv n, z;
1123
1124 n = tcg_temp_new(TCG_TYPE_TL);
1125 z = tcg_temp_new(TCG_TYPE_TL);
1126
1127 /* To avoid a shift we overlay everything on
1128 the V flag. */
1129 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1130 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1131 /* invert Z. */
1132 tcg_gen_xori_tl(z, z, 2);
1133
1134 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1135 tcg_gen_xori_tl(n, n, 2);
1136 tcg_gen_and_tl(cc, z, n);
1137 tcg_gen_andi_tl(cc, cc, 2);
1138
1139 tcg_temp_free(n);
1140 tcg_temp_free(z);
1141 }
1142 break;
1143 case CC_LE:
1144 cris_evaluate_flags(dc);
1145 {
1146 TCGv n, z;
1147
1148 n = tcg_temp_new(TCG_TYPE_TL);
1149 z = tcg_temp_new(TCG_TYPE_TL);
1150
1151 /* To avoid a shift we overlay everything on
1152 the V flag. */
1153 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1154 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1155
1156 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1157 tcg_gen_or_tl(cc, z, n);
1158 tcg_gen_andi_tl(cc, cc, 2);
1159
1160 tcg_temp_free(n);
1161 tcg_temp_free(z);
1162 }
1163 break;
1164 case CC_P:
1165 cris_evaluate_flags(dc);
1166 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1167 break;
1168 case CC_A:
1169 tcg_gen_movi_tl(cc, 1);
1170 break;
1171 default:
1172 BUG();
1173 break;
1174 };
1175 }
1176
1177 static void cris_store_direct_jmp(DisasContext *dc)
1178 {
1179 /* Store the direct jmp state into the cpu-state. */
1180 if (dc->jmp == JMP_DIRECT) {
1181 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1182 tcg_gen_movi_tl(env_btaken, 1);
1183 }
1184 }
1185
1186 static void cris_prepare_cc_branch (DisasContext *dc,
1187 int offset, int cond)
1188 {
1189 /* This helps us re-schedule the micro-code to insns in delay-slots
1190 before the actual jump. */
1191 dc->delayed_branch = 2;
1192 dc->jmp_pc = dc->pc + offset;
1193
1194 if (cond != CC_A)
1195 {
1196 dc->jmp = JMP_INDIRECT;
1197 gen_tst_cc (dc, env_btaken, cond);
1198 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1199 } else {
1200 /* Allow chaining. */
1201 dc->jmp = JMP_DIRECT;
1202 }
1203 }
1204
1205
1206 /* jumps, when the dest is in a live reg for example. Direct should be set
1207 when the dest addr is constant to allow tb chaining. */
1208 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1209 {
1210 /* This helps us re-schedule the micro-code to insns in delay-slots
1211 before the actual jump. */
1212 dc->delayed_branch = 2;
1213 dc->jmp = type;
1214 if (type == JMP_INDIRECT)
1215 tcg_gen_movi_tl(env_btaken, 1);
1216 }
1217
1218 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1219 unsigned int size, int sign)
1220 {
1221 int mem_index = cpu_mmu_index(dc->env);
1222
1223 /* If we get a fault on a delayslot we must keep the jmp state in
1224 the cpu-state to be able to re-execute the jmp. */
1225 if (dc->delayed_branch == 1)
1226 cris_store_direct_jmp(dc);
1227
1228 if (size == 1) {
1229 if (sign)
1230 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1231 else
1232 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1233 }
1234 else if (size == 2) {
1235 if (sign)
1236 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1237 else
1238 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1239 }
1240 else if (size == 4) {
1241 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1242 }
1243 else if (size == 8) {
1244 tcg_gen_qemu_ld64(dst, addr, mem_index);
1245 }
1246 }
1247
1248 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1249 unsigned int size)
1250 {
1251 int mem_index = cpu_mmu_index(dc->env);
1252
1253 /* If we get a fault on a delayslot we must keep the jmp state in
1254 the cpu-state to be able to re-execute the jmp. */
1255 if (dc->delayed_branch == 1)
1256 cris_store_direct_jmp(dc);
1257
1258
1259 /* Conditional writes. We only support the kind were X and P are known
1260 at translation time. */
1261 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1262 dc->postinc = 0;
1263 cris_evaluate_flags(dc);
1264 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1265 return;
1266 }
1267
1268 if (size == 1)
1269 tcg_gen_qemu_st8(val, addr, mem_index);
1270 else if (size == 2)
1271 tcg_gen_qemu_st16(val, addr, mem_index);
1272 else
1273 tcg_gen_qemu_st32(val, addr, mem_index);
1274
1275 if (dc->flagx_known && dc->flags_x) {
1276 cris_evaluate_flags(dc);
1277 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1278 }
1279 }
1280
1281 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1282 {
1283 if (size == 1)
1284 tcg_gen_ext8s_i32(d, s);
1285 else if (size == 2)
1286 tcg_gen_ext16s_i32(d, s);
1287 else if(GET_TCGV(d) != GET_TCGV(s))
1288 tcg_gen_mov_tl(d, s);
1289 }
1290
1291 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1292 {
1293 if (size == 1)
1294 tcg_gen_ext8u_i32(d, s);
1295 else if (size == 2)
1296 tcg_gen_ext16u_i32(d, s);
1297 else if (GET_TCGV(d) != GET_TCGV(s))
1298 tcg_gen_mov_tl(d, s);
1299 }
1300
1301 #if DISAS_CRIS
1302 static char memsize_char(int size)
1303 {
1304 switch (size)
1305 {
1306 case 1: return 'b'; break;
1307 case 2: return 'w'; break;
1308 case 4: return 'd'; break;
1309 default:
1310 return 'x';
1311 break;
1312 }
1313 }
1314 #endif
1315
1316 static inline unsigned int memsize_z(DisasContext *dc)
1317 {
1318 return dc->zsize + 1;
1319 }
1320
1321 static inline unsigned int memsize_zz(DisasContext *dc)
1322 {
1323 switch (dc->zzsize)
1324 {
1325 case 0: return 1;
1326 case 1: return 2;
1327 default:
1328 return 4;
1329 }
1330 }
1331
1332 static inline void do_postinc (DisasContext *dc, int size)
1333 {
1334 if (dc->postinc)
1335 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1336 }
1337
1338 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1339 int size, int s_ext, TCGv dst)
1340 {
1341 if (s_ext)
1342 t_gen_sext(dst, cpu_R[rs], size);
1343 else
1344 t_gen_zext(dst, cpu_R[rs], size);
1345 }
1346
1347 /* Prepare T0 and T1 for a register alu operation.
1348 s_ext decides if the operand1 should be sign-extended or zero-extended when
1349 needed. */
1350 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1351 int size, int s_ext, TCGv dst, TCGv src)
1352 {
1353 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1354
1355 if (s_ext)
1356 t_gen_sext(dst, cpu_R[rd], size);
1357 else
1358 t_gen_zext(dst, cpu_R[rd], size);
1359 }
1360
1361 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1362 TCGv dst)
1363 {
1364 unsigned int rs, rd;
1365 uint32_t imm;
1366 int is_imm;
1367 int insn_len = 2;
1368
1369 rs = dc->op1;
1370 rd = dc->op2;
1371 is_imm = rs == 15 && dc->postinc;
1372
1373 /* Load [$rs] onto T1. */
1374 if (is_imm) {
1375 insn_len = 2 + memsize;
1376 if (memsize == 1)
1377 insn_len++;
1378
1379 if (memsize != 4) {
1380 if (s_ext) {
1381 if (memsize == 1)
1382 imm = ldsb_code(dc->pc + 2);
1383 else
1384 imm = ldsw_code(dc->pc + 2);
1385 } else {
1386 if (memsize == 1)
1387 imm = ldub_code(dc->pc + 2);
1388 else
1389 imm = lduw_code(dc->pc + 2);
1390 }
1391 } else
1392 imm = ldl_code(dc->pc + 2);
1393
1394 tcg_gen_movi_tl(dst, imm);
1395 dc->postinc = 0;
1396 } else {
1397 cris_flush_cc_state(dc);
1398 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1399 if (s_ext)
1400 t_gen_sext(dst, dst, memsize);
1401 else
1402 t_gen_zext(dst, dst, memsize);
1403 }
1404 return insn_len;
1405 }
1406
1407 /* Prepare T0 and T1 for a memory + alu operation.
1408 s_ext decides if the operand1 should be sign-extended or zero-extended when
1409 needed. */
1410 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1411 TCGv dst, TCGv src)
1412 {
1413 int insn_len;
1414
1415 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1416 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1417 return insn_len;
1418 }
1419
1420 #if DISAS_CRIS
1421 static const char *cc_name(int cc)
1422 {
1423 static const char *cc_names[16] = {
1424 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1425 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1426 };
1427 assert(cc < 16);
1428 return cc_names[cc];
1429 }
1430 #endif
1431
1432 /* Start of insn decoders. */
1433
1434 static unsigned int dec_bccq(DisasContext *dc)
1435 {
1436 int32_t offset;
1437 int sign;
1438 uint32_t cond = dc->op2;
1439 int tmp;
1440
1441 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1442 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1443
1444 offset *= 2;
1445 offset |= sign << 8;
1446 tmp = offset;
1447 offset = sign_extend(offset, 8);
1448
1449 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1450
1451 /* op2 holds the condition-code. */
1452 cris_cc_mask(dc, 0);
1453 cris_prepare_cc_branch (dc, offset, cond);
1454 return 2;
1455 }
1456 static unsigned int dec_addoq(DisasContext *dc)
1457 {
1458 int32_t imm;
1459
1460 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1461 imm = sign_extend(dc->op1, 7);
1462
1463 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1464 cris_cc_mask(dc, 0);
1465 /* Fetch register operand, */
1466 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1467
1468 return 2;
1469 }
1470 static unsigned int dec_addq(DisasContext *dc)
1471 {
1472 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1473
1474 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1475
1476 cris_cc_mask(dc, CC_MASK_NZVC);
1477
1478 cris_alu(dc, CC_OP_ADD,
1479 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1480 return 2;
1481 }
1482 static unsigned int dec_moveq(DisasContext *dc)
1483 {
1484 uint32_t imm;
1485
1486 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1487 imm = sign_extend(dc->op1, 5);
1488 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1489
1490 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1491 return 2;
1492 }
1493 static unsigned int dec_subq(DisasContext *dc)
1494 {
1495 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1496
1497 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1498
1499 cris_cc_mask(dc, CC_MASK_NZVC);
1500 cris_alu(dc, CC_OP_SUB,
1501 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1502 return 2;
1503 }
1504 static unsigned int dec_cmpq(DisasContext *dc)
1505 {
1506 uint32_t imm;
1507 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1508 imm = sign_extend(dc->op1, 5);
1509
1510 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1511 cris_cc_mask(dc, CC_MASK_NZVC);
1512
1513 cris_alu(dc, CC_OP_CMP,
1514 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1515 return 2;
1516 }
1517 static unsigned int dec_andq(DisasContext *dc)
1518 {
1519 uint32_t imm;
1520 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1521 imm = sign_extend(dc->op1, 5);
1522
1523 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1524 cris_cc_mask(dc, CC_MASK_NZ);
1525
1526 cris_alu(dc, CC_OP_AND,
1527 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1528 return 2;
1529 }
1530 static unsigned int dec_orq(DisasContext *dc)
1531 {
1532 uint32_t imm;
1533 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1534 imm = sign_extend(dc->op1, 5);
1535 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1536 cris_cc_mask(dc, CC_MASK_NZ);
1537
1538 cris_alu(dc, CC_OP_OR,
1539 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1540 return 2;
1541 }
1542 static unsigned int dec_btstq(DisasContext *dc)
1543 {
1544 TCGv l0;
1545 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1546 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1547
1548 cris_cc_mask(dc, CC_MASK_NZ);
1549 l0 = tcg_temp_local_new(TCG_TYPE_TL);
1550 cris_alu(dc, CC_OP_BTST,
1551 l0, cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1552 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1553 t_gen_mov_preg_TN(dc, PR_CCS, l0);
1554 dc->flags_uptodate = 1;
1555 tcg_temp_free(l0);
1556 return 2;
1557 }
1558 static unsigned int dec_asrq(DisasContext *dc)
1559 {
1560 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1561 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1562 cris_cc_mask(dc, CC_MASK_NZ);
1563
1564 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1565 cris_alu(dc, CC_OP_MOVE,
1566 cpu_R[dc->op2],
1567 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1568 return 2;
1569 }
1570 static unsigned int dec_lslq(DisasContext *dc)
1571 {
1572 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1573 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1574
1575 cris_cc_mask(dc, CC_MASK_NZ);
1576
1577 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1578
1579 cris_alu(dc, CC_OP_MOVE,
1580 cpu_R[dc->op2],
1581 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1582 return 2;
1583 }
1584 static unsigned int dec_lsrq(DisasContext *dc)
1585 {
1586 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1587 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1588
1589 cris_cc_mask(dc, CC_MASK_NZ);
1590
1591 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1592 cris_alu(dc, CC_OP_MOVE,
1593 cpu_R[dc->op2],
1594 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1595 return 2;
1596 }
1597
1598 static unsigned int dec_move_r(DisasContext *dc)
1599 {
1600 int size = memsize_zz(dc);
1601
1602 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1603 memsize_char(size), dc->op1, dc->op2));
1604
1605 cris_cc_mask(dc, CC_MASK_NZ);
1606 if (size == 4) {
1607 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1608 cris_cc_mask(dc, CC_MASK_NZ);
1609 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1610 cris_update_cc_x(dc);
1611 cris_update_result(dc, cpu_R[dc->op2]);
1612 }
1613 else {
1614 TCGv t0;
1615
1616 t0 = tcg_temp_new(TCG_TYPE_TL);
1617 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1618 cris_alu(dc, CC_OP_MOVE,
1619 cpu_R[dc->op2],
1620 cpu_R[dc->op2], t0, size);
1621 tcg_temp_free(t0);
1622 }
1623 return 2;
1624 }
1625
1626 static unsigned int dec_scc_r(DisasContext *dc)
1627 {
1628 int cond = dc->op2;
1629
1630 DIS(fprintf (logfile, "s%s $r%u\n",
1631 cc_name(cond), dc->op1));
1632
1633 if (cond != CC_A)
1634 {
1635 int l1;
1636
1637 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1638 l1 = gen_new_label();
1639 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1640 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1641 gen_set_label(l1);
1642 }
1643 else
1644 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1645
1646 cris_cc_mask(dc, 0);
1647 return 2;
1648 }
1649
1650 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1651 {
1652 if (size == 4) {
1653 t[0] = cpu_R[dc->op2];
1654 t[1] = cpu_R[dc->op1];
1655 } else {
1656 t[0] = tcg_temp_new(TCG_TYPE_TL);
1657 t[1] = tcg_temp_new(TCG_TYPE_TL);
1658 }
1659 }
1660
1661 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1662 {
1663 if (size != 4) {
1664 tcg_temp_free(t[0]);
1665 tcg_temp_free(t[1]);
1666 }
1667 }
1668
1669 static unsigned int dec_and_r(DisasContext *dc)
1670 {
1671 TCGv t[2];
1672 int size = memsize_zz(dc);
1673
1674 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1675 memsize_char(size), dc->op1, dc->op2));
1676
1677 cris_cc_mask(dc, CC_MASK_NZ);
1678
1679 cris_alu_alloc_temps(dc, size, t);
1680 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1681 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1682 cris_alu_free_temps(dc, size, t);
1683 return 2;
1684 }
1685
1686 static unsigned int dec_lz_r(DisasContext *dc)
1687 {
1688 TCGv t0;
1689 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1690 dc->op1, dc->op2));
1691 cris_cc_mask(dc, CC_MASK_NZ);
1692 t0 = tcg_temp_new(TCG_TYPE_TL);
1693 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1694 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1695 tcg_temp_free(t0);
1696 return 2;
1697 }
1698
1699 static unsigned int dec_lsl_r(DisasContext *dc)
1700 {
1701 TCGv t[2];
1702 int size = memsize_zz(dc);
1703
1704 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1705 memsize_char(size), dc->op1, dc->op2));
1706
1707 cris_cc_mask(dc, CC_MASK_NZ);
1708 cris_alu_alloc_temps(dc, size, t);
1709 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1710 tcg_gen_andi_tl(t[1], t[1], 63);
1711 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1712 cris_alu_alloc_temps(dc, size, t);
1713 return 2;
1714 }
1715
1716 static unsigned int dec_lsr_r(DisasContext *dc)
1717 {
1718 TCGv t[2];
1719 int size = memsize_zz(dc);
1720
1721 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1722 memsize_char(size), dc->op1, dc->op2));
1723
1724 cris_cc_mask(dc, CC_MASK_NZ);
1725 cris_alu_alloc_temps(dc, size, t);
1726 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1727 tcg_gen_andi_tl(t[1], t[1], 63);
1728 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1729 cris_alu_free_temps(dc, size, t);
1730 return 2;
1731 }
1732
1733 static unsigned int dec_asr_r(DisasContext *dc)
1734 {
1735 TCGv t[2];
1736 int size = memsize_zz(dc);
1737
1738 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1739 memsize_char(size), dc->op1, dc->op2));
1740
1741 cris_cc_mask(dc, CC_MASK_NZ);
1742 cris_alu_alloc_temps(dc, size, t);
1743 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1744 tcg_gen_andi_tl(t[1], t[1], 63);
1745 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1746 cris_alu_free_temps(dc, size, t);
1747 return 2;
1748 }
1749
1750 static unsigned int dec_muls_r(DisasContext *dc)
1751 {
1752 TCGv t[2];
1753 int size = memsize_zz(dc);
1754
1755 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1756 memsize_char(size), dc->op1, dc->op2));
1757 cris_cc_mask(dc, CC_MASK_NZV);
1758 cris_alu_alloc_temps(dc, size, t);
1759 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1760
1761 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1762 cris_alu_free_temps(dc, size, t);
1763 return 2;
1764 }
1765
1766 static unsigned int dec_mulu_r(DisasContext *dc)
1767 {
1768 TCGv t[2];
1769 int size = memsize_zz(dc);
1770
1771 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1772 memsize_char(size), dc->op1, dc->op2));
1773 cris_cc_mask(dc, CC_MASK_NZV);
1774 cris_alu_alloc_temps(dc, size, t);
1775 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1776
1777 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1778 cris_alu_alloc_temps(dc, size, t);
1779 return 2;
1780 }
1781
1782
1783 static unsigned int dec_dstep_r(DisasContext *dc)
1784 {
1785 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1786 cris_cc_mask(dc, CC_MASK_NZ);
1787 cris_alu(dc, CC_OP_DSTEP,
1788 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1789 return 2;
1790 }
1791
1792 static unsigned int dec_xor_r(DisasContext *dc)
1793 {
1794 TCGv t[2];
1795 int size = memsize_zz(dc);
1796 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1797 memsize_char(size), dc->op1, dc->op2));
1798 BUG_ON(size != 4); /* xor is dword. */
1799 cris_cc_mask(dc, CC_MASK_NZ);
1800 cris_alu_alloc_temps(dc, size, t);
1801 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1802
1803 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1804 cris_alu_free_temps(dc, size, t);
1805 return 2;
1806 }
1807
1808 static unsigned int dec_bound_r(DisasContext *dc)
1809 {
1810 TCGv l0;
1811 int size = memsize_zz(dc);
1812 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1813 memsize_char(size), dc->op1, dc->op2));
1814 cris_cc_mask(dc, CC_MASK_NZ);
1815 l0 = tcg_temp_local_new(TCG_TYPE_TL);
1816 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1817 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1818 tcg_temp_free(l0);
1819 return 2;
1820 }
1821
1822 static unsigned int dec_cmp_r(DisasContext *dc)
1823 {
1824 TCGv t[2];
1825 int size = memsize_zz(dc);
1826 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1827 memsize_char(size), dc->op1, dc->op2));
1828 cris_cc_mask(dc, CC_MASK_NZVC);
1829 cris_alu_alloc_temps(dc, size, t);
1830 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1831
1832 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1833 cris_alu_free_temps(dc, size, t);
1834 return 2;
1835 }
1836
1837 static unsigned int dec_abs_r(DisasContext *dc)
1838 {
1839 TCGv t0;
1840
1841 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1842 dc->op1, dc->op2));
1843 cris_cc_mask(dc, CC_MASK_NZ);
1844
1845 t0 = tcg_temp_new(TCG_TYPE_TL);
1846 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1847 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1848 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1849 tcg_temp_free(t0);
1850
1851 cris_alu(dc, CC_OP_MOVE,
1852 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1853 return 2;
1854 }
1855
1856 static unsigned int dec_add_r(DisasContext *dc)
1857 {
1858 TCGv t[2];
1859 int size = memsize_zz(dc);
1860 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1861 memsize_char(size), dc->op1, dc->op2));
1862 cris_cc_mask(dc, CC_MASK_NZVC);
1863 cris_alu_alloc_temps(dc, size, t);
1864 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1865
1866 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1867 cris_alu_free_temps(dc, size, t);
1868 return 2;
1869 }
1870
1871 static unsigned int dec_addc_r(DisasContext *dc)
1872 {
1873 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1874 dc->op1, dc->op2));
1875 cris_evaluate_flags(dc);
1876 cris_cc_mask(dc, CC_MASK_NZVC);
1877 cris_alu(dc, CC_OP_ADDC,
1878 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1879 return 2;
1880 }
1881
1882 static unsigned int dec_mcp_r(DisasContext *dc)
1883 {
1884 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1885 dc->op2, dc->op1));
1886 cris_evaluate_flags(dc);
1887 cris_cc_mask(dc, CC_MASK_RNZV);
1888 cris_alu(dc, CC_OP_MCP,
1889 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1890 return 2;
1891 }
1892
1893 #if DISAS_CRIS
1894 static char * swapmode_name(int mode, char *modename) {
1895 int i = 0;
1896 if (mode & 8)
1897 modename[i++] = 'n';
1898 if (mode & 4)
1899 modename[i++] = 'w';
1900 if (mode & 2)
1901 modename[i++] = 'b';
1902 if (mode & 1)
1903 modename[i++] = 'r';
1904 modename[i++] = 0;
1905 return modename;
1906 }
1907 #endif
1908
1909 static unsigned int dec_swap_r(DisasContext *dc)
1910 {
1911 TCGv t0;
1912 #if DISAS_CRIS
1913 char modename[4];
1914 #endif
1915 DIS(fprintf (logfile, "swap%s $r%u\n",
1916 swapmode_name(dc->op2, modename), dc->op1));
1917
1918 cris_cc_mask(dc, CC_MASK_NZ);
1919 t0 = tcg_temp_new(TCG_TYPE_TL);
1920 t_gen_mov_TN_reg(t0, dc->op1);
1921 if (dc->op2 & 8)
1922 tcg_gen_not_tl(t0, t0);
1923 if (dc->op2 & 4)
1924 t_gen_swapw(t0, t0);
1925 if (dc->op2 & 2)
1926 t_gen_swapb(t0, t0);
1927 if (dc->op2 & 1)
1928 t_gen_swapr(t0, t0);
1929 cris_alu(dc, CC_OP_MOVE,
1930 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1931 tcg_temp_free(t0);
1932 return 2;
1933 }
1934
1935 static unsigned int dec_or_r(DisasContext *dc)
1936 {
1937 TCGv t[2];
1938 int size = memsize_zz(dc);
1939 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1940 memsize_char(size), dc->op1, dc->op2));
1941 cris_cc_mask(dc, CC_MASK_NZ);
1942 cris_alu_alloc_temps(dc, size, t);
1943 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1944 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1945 cris_alu_free_temps(dc, size, t);
1946 return 2;
1947 }
1948
1949 static unsigned int dec_addi_r(DisasContext *dc)
1950 {
1951 TCGv t0;
1952 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1953 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1954 cris_cc_mask(dc, 0);
1955 t0 = tcg_temp_new(TCG_TYPE_TL);
1956 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1957 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1958 tcg_temp_free(t0);
1959 return 2;
1960 }
1961
1962 static unsigned int dec_addi_acr(DisasContext *dc)
1963 {
1964 TCGv t0;
1965 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1966 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1967 cris_cc_mask(dc, 0);
1968 t0 = tcg_temp_new(TCG_TYPE_TL);
1969 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1970 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1971 tcg_temp_free(t0);
1972 return 2;
1973 }
1974
1975 static unsigned int dec_neg_r(DisasContext *dc)
1976 {
1977 TCGv t[2];
1978 int size = memsize_zz(dc);
1979 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1980 memsize_char(size), dc->op1, dc->op2));
1981 cris_cc_mask(dc, CC_MASK_NZVC);
1982 cris_alu_alloc_temps(dc, size, t);
1983 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1984
1985 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1986 cris_alu_free_temps(dc, size, t);
1987 return 2;
1988 }
1989
1990 static unsigned int dec_btst_r(DisasContext *dc)
1991 {
1992 TCGv l0;
1993 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1994 dc->op1, dc->op2));
1995 cris_cc_mask(dc, CC_MASK_NZ);
1996
1997 l0 = tcg_temp_local_new(TCG_TYPE_TL);
1998 cris_alu(dc, CC_OP_BTST, l0, cpu_R[dc->op2], cpu_R[dc->op1], 4);
1999 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2000 t_gen_mov_preg_TN(dc, PR_CCS, l0);
2001 dc->flags_uptodate = 1;
2002 tcg_temp_free(l0);
2003 return 2;
2004 }
2005
2006 static unsigned int dec_sub_r(DisasContext *dc)
2007 {
2008 TCGv t[2];
2009 int size = memsize_zz(dc);
2010 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
2011 memsize_char(size), dc->op1, dc->op2));
2012 cris_cc_mask(dc, CC_MASK_NZVC);
2013 cris_alu_alloc_temps(dc, size, t);
2014 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
2015 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
2016 cris_alu_free_temps(dc, size, t);
2017 return 2;
2018 }
2019
2020 /* Zero extension. From size to dword. */
2021 static unsigned int dec_movu_r(DisasContext *dc)
2022 {
2023 TCGv t0;
2024 int size = memsize_z(dc);
2025 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
2026 memsize_char(size),
2027 dc->op1, dc->op2));
2028
2029 cris_cc_mask(dc, CC_MASK_NZ);
2030 t0 = tcg_temp_new(TCG_TYPE_TL);
2031 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
2032 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2033 tcg_temp_free(t0);
2034 return 2;
2035 }
2036
2037 /* Sign extension. From size to dword. */
2038 static unsigned int dec_movs_r(DisasContext *dc)
2039 {
2040 TCGv t0;
2041 int size = memsize_z(dc);
2042 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
2043 memsize_char(size),
2044 dc->op1, dc->op2));
2045
2046 cris_cc_mask(dc, CC_MASK_NZ);
2047 t0 = tcg_temp_new(TCG_TYPE_TL);
2048 /* Size can only be qi or hi. */
2049 t_gen_sext(t0, cpu_R[dc->op1], size);
2050 cris_alu(dc, CC_OP_MOVE,
2051 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
2052 tcg_temp_free(t0);
2053 return 2;
2054 }
2055
2056 /* zero extension. From size to dword. */
2057 static unsigned int dec_addu_r(DisasContext *dc)
2058 {
2059 TCGv t0;
2060 int size = memsize_z(dc);
2061 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
2062 memsize_char(size),
2063 dc->op1, dc->op2));
2064
2065 cris_cc_mask(dc, CC_MASK_NZVC);
2066 t0 = tcg_temp_new(TCG_TYPE_TL);
2067 /* Size can only be qi or hi. */
2068 t_gen_zext(t0, cpu_R[dc->op1], size);
2069 cris_alu(dc, CC_OP_ADD,
2070 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2071 tcg_temp_free(t0);
2072 return 2;
2073 }
2074
2075 /* Sign extension. From size to dword. */
2076 static unsigned int dec_adds_r(DisasContext *dc)
2077 {
2078 TCGv t0;
2079 int size = memsize_z(dc);
2080 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
2081 memsize_char(size),
2082 dc->op1, dc->op2));
2083
2084 cris_cc_mask(dc, CC_MASK_NZVC);
2085 t0 = tcg_temp_new(TCG_TYPE_TL);
2086 /* Size can only be qi or hi. */
2087 t_gen_sext(t0, cpu_R[dc->op1], size);
2088 cris_alu(dc, CC_OP_ADD,
2089 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2090 tcg_temp_free(t0);
2091 return 2;
2092 }
2093
2094 /* Zero extension. From size to dword. */
2095 static unsigned int dec_subu_r(DisasContext *dc)
2096 {
2097 TCGv t0;
2098 int size = memsize_z(dc);
2099 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2100 memsize_char(size),
2101 dc->op1, dc->op2));
2102
2103 cris_cc_mask(dc, CC_MASK_NZVC);
2104 t0 = tcg_temp_new(TCG_TYPE_TL);
2105 /* Size can only be qi or hi. */
2106 t_gen_zext(t0, cpu_R[dc->op1], size);
2107 cris_alu(dc, CC_OP_SUB,
2108 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2109 tcg_temp_free(t0);
2110 return 2;
2111 }
2112
2113 /* Sign extension. From size to dword. */
2114 static unsigned int dec_subs_r(DisasContext *dc)
2115 {
2116 TCGv t0;
2117 int size = memsize_z(dc);
2118 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2119 memsize_char(size),
2120 dc->op1, dc->op2));
2121
2122 cris_cc_mask(dc, CC_MASK_NZVC);
2123 t0 = tcg_temp_new(TCG_TYPE_TL);
2124 /* Size can only be qi or hi. */
2125 t_gen_sext(t0, cpu_R[dc->op1], size);
2126 cris_alu(dc, CC_OP_SUB,
2127 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2128 tcg_temp_free(t0);
2129 return 2;
2130 }
2131
2132 static unsigned int dec_setclrf(DisasContext *dc)
2133 {
2134 uint32_t flags;
2135 int set = (~dc->opcode >> 2) & 1;
2136
2137
2138 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2139 | EXTRACT_FIELD(dc->ir, 0, 3);
2140 if (set && flags == 0) {
2141 DIS(fprintf (logfile, "nop\n"));
2142 return 2;
2143 } else if (!set && (flags & 0x20)) {
2144 DIS(fprintf (logfile, "di\n"));
2145 }
2146 else {
2147 DIS(fprintf (logfile, "%sf %x\n",
2148 set ? "set" : "clr",
2149 flags));
2150 }
2151
2152 /* User space is not allowed to touch these. Silently ignore. */
2153 if (dc->tb_flags & U_FLAG) {
2154 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2155 }
2156
2157 if (flags & X_FLAG) {
2158 dc->flagx_known = 1;
2159 if (set)
2160 dc->flags_x = X_FLAG;
2161 else
2162 dc->flags_x = 0;
2163 }
2164
2165 /* Break the TB if the P flag changes. */
2166 if (flags & P_FLAG) {
2167 if ((set && !(dc->tb_flags & P_FLAG))
2168 || (!set && (dc->tb_flags & P_FLAG))) {
2169 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2170 dc->is_jmp = DISAS_UPDATE;
2171 dc->cpustate_changed = 1;
2172 }
2173 }
2174 if (flags & S_FLAG) {
2175 dc->cpustate_changed = 1;
2176 }
2177
2178
2179 /* Simply decode the flags. */
2180 cris_evaluate_flags (dc);
2181 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2182 cris_update_cc_x(dc);
2183 tcg_gen_movi_tl(cc_op, dc->cc_op);
2184
2185 if (set) {
2186 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2187 /* Enter user mode. */
2188 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2189 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2190 dc->cpustate_changed = 1;
2191 }
2192 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2193 }
2194 else
2195 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2196
2197 dc->flags_uptodate = 1;
2198 dc->clear_x = 0;
2199 return 2;
2200 }
2201
2202 static unsigned int dec_move_rs(DisasContext *dc)
2203 {
2204 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2205 cris_cc_mask(dc, 0);
2206 tcg_gen_helper_0_2(helper_movl_sreg_reg,
2207 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2208 return 2;
2209 }
2210 static unsigned int dec_move_sr(DisasContext *dc)
2211 {
2212 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
2213 cris_cc_mask(dc, 0);
2214 tcg_gen_helper_0_2(helper_movl_reg_sreg,
2215 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2216 return 2;
2217 }
2218
2219 static unsigned int dec_move_rp(DisasContext *dc)
2220 {
2221 TCGv t[2];
2222 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2223 cris_cc_mask(dc, 0);
2224
2225 t[0] = tcg_temp_new(TCG_TYPE_TL);
2226 if (dc->op2 == PR_CCS) {
2227 cris_evaluate_flags(dc);
2228 t_gen_mov_TN_reg(t[0], dc->op1);
2229 if (dc->tb_flags & U_FLAG) {
2230 t[1] = tcg_temp_new(TCG_TYPE_TL);
2231 /* User space is not allowed to touch all flags. */
2232 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2233 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2234 tcg_gen_or_tl(t[0], t[1], t[0]);
2235 tcg_temp_free(t[1]);
2236 }
2237 }
2238 else
2239 t_gen_mov_TN_reg(t[0], dc->op1);
2240
2241 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2242 if (dc->op2 == PR_CCS) {
2243 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2244 dc->flags_uptodate = 1;
2245 }
2246 tcg_temp_free(t[0]);
2247 return 2;
2248 }
2249 static unsigned int dec_move_pr(DisasContext *dc)
2250 {
2251 TCGv t0;
2252 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2253 cris_cc_mask(dc, 0);
2254
2255 if (dc->op2 == PR_CCS)
2256 cris_evaluate_flags(dc);
2257
2258 t0 = tcg_temp_new(TCG_TYPE_TL);
2259 t_gen_mov_TN_preg(t0, dc->op2);
2260 cris_alu(dc, CC_OP_MOVE,
2261 cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
2262 tcg_temp_free(t0);
2263 return 2;
2264 }
2265
2266 static unsigned int dec_move_mr(DisasContext *dc)
2267 {
2268 int memsize = memsize_zz(dc);
2269 int insn_len;
2270 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2271 memsize_char(memsize),
2272 dc->op1, dc->postinc ? "+]" : "]",
2273 dc->op2));
2274
2275 if (memsize == 4) {
2276 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2277 cris_cc_mask(dc, CC_MASK_NZ);
2278 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2279 cris_update_cc_x(dc);
2280 cris_update_result(dc, cpu_R[dc->op2]);
2281 }
2282 else {
2283 TCGv t0;
2284
2285 t0 = tcg_temp_new(TCG_TYPE_TL);
2286 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2287 cris_cc_mask(dc, CC_MASK_NZ);
2288 cris_alu(dc, CC_OP_MOVE,
2289 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2290 tcg_temp_free(t0);
2291 }
2292 do_postinc(dc, memsize);
2293 return insn_len;
2294 }
2295
2296 static inline void cris_alu_m_alloc_temps(TCGv *t)
2297 {
2298 t[0] = tcg_temp_new(TCG_TYPE_TL);
2299 t[1] = tcg_temp_new(TCG_TYPE_TL);
2300 }
2301
2302 static inline void cris_alu_m_free_temps(TCGv *t)
2303 {
2304 tcg_temp_free(t[0]);
2305 tcg_temp_free(t[1]);
2306 }
2307
2308 static unsigned int dec_movs_m(DisasContext *dc)
2309 {
2310 TCGv t[2];
2311 int memsize = memsize_z(dc);
2312 int insn_len;
2313 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2314 memsize_char(memsize),
2315 dc->op1, dc->postinc ? "+]" : "]",
2316 dc->op2));
2317
2318 cris_alu_m_alloc_temps(t);
2319 /* sign extend. */
2320 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2321 cris_cc_mask(dc, CC_MASK_NZ);
2322 cris_alu(dc, CC_OP_MOVE,
2323 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2324 do_postinc(dc, memsize);
2325 cris_alu_m_free_temps(t);
2326 return insn_len;
2327 }
2328
2329 static unsigned int dec_addu_m(DisasContext *dc)
2330 {
2331 TCGv t[2];
2332 int memsize = memsize_z(dc);
2333 int insn_len;
2334 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2335 memsize_char(memsize),
2336 dc->op1, dc->postinc ? "+]" : "]",
2337 dc->op2));
2338
2339 cris_alu_m_alloc_temps(t);
2340 /* sign extend. */
2341 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2342 cris_cc_mask(dc, CC_MASK_NZVC);
2343 cris_alu(dc, CC_OP_ADD,
2344 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2345 do_postinc(dc, memsize);
2346 cris_alu_m_free_temps(t);
2347 return insn_len;
2348 }
2349
2350 static unsigned int dec_adds_m(DisasContext *dc)
2351 {
2352 TCGv t[2];
2353 int memsize = memsize_z(dc);
2354 int insn_len;
2355 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2356 memsize_char(memsize),
2357 dc->op1, dc->postinc ? "+]" : "]",
2358 dc->op2));
2359
2360 cris_alu_m_alloc_temps(t);
2361 /* sign extend. */
2362 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2363 cris_cc_mask(dc, CC_MASK_NZVC);
2364 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2365 do_postinc(dc, memsize);
2366 cris_alu_m_free_temps(t);
2367 return insn_len;
2368 }
2369
2370 static unsigned int dec_subu_m(DisasContext *dc)
2371 {
2372 TCGv t[2];
2373 int memsize = memsize_z(dc);
2374 int insn_len;
2375 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2376 memsize_char(memsize),
2377 dc->op1, dc->postinc ? "+]" : "]",
2378 dc->op2));
2379
2380 cris_alu_m_alloc_temps(t);
2381 /* sign extend. */
2382 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2383 cris_cc_mask(dc, CC_MASK_NZVC);
2384 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2385 do_postinc(dc, memsize);
2386 cris_alu_m_free_temps(t);
2387 return insn_len;
2388 }
2389
2390 static unsigned int dec_subs_m(DisasContext *dc)
2391 {
2392 TCGv t[2];
2393 int memsize = memsize_z(dc);
2394 int insn_len;
2395 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2396 memsize_char(memsize),
2397 dc->op1, dc->postinc ? "+]" : "]",
2398 dc->op2));
2399
2400 cris_alu_m_alloc_temps(t);
2401 /* sign extend. */
2402 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2403 cris_cc_mask(dc, CC_MASK_NZVC);
2404 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2405 do_postinc(dc, memsize);
2406 cris_alu_m_free_temps(t);
2407 return insn_len;
2408 }
2409
2410 static unsigned int dec_movu_m(DisasContext *dc)
2411 {
2412 TCGv t[2];
2413 int memsize = memsize_z(dc);
2414 int insn_len;
2415
2416 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2417 memsize_char(memsize),
2418 dc->op1, dc->postinc ? "+]" : "]",
2419 dc->op2));
2420
2421 cris_alu_m_alloc_temps(t);
2422 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2423 cris_cc_mask(dc, CC_MASK_NZ);
2424 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2425 do_postinc(dc, memsize);
2426 cris_alu_m_free_temps(t);
2427 return insn_len;
2428 }
2429
2430 static unsigned int dec_cmpu_m(DisasContext *dc)
2431 {
2432 TCGv t[2];
2433 int memsize = memsize_z(dc);
2434 int insn_len;
2435 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2436 memsize_char(memsize),
2437 dc->op1, dc->postinc ? "+]" : "]",
2438 dc->op2));
2439
2440 cris_alu_m_alloc_temps(t);
2441 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2442 cris_cc_mask(dc, CC_MASK_NZVC);
2443 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2444 do_postinc(dc, memsize);
2445 cris_alu_m_free_temps(t);
2446 return insn_len;
2447 }
2448
2449 static unsigned int dec_cmps_m(DisasContext *dc)
2450 {
2451 TCGv t[2];
2452 int memsize = memsize_z(dc);
2453 int insn_len;
2454 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2455 memsize_char(memsize),
2456 dc->op1, dc->postinc ? "+]" : "]",
2457 dc->op2));
2458
2459 cris_alu_m_alloc_temps(t);
2460 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2461 cris_cc_mask(dc, CC_MASK_NZVC);
2462 cris_alu(dc, CC_OP_CMP,
2463 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2464 memsize_zz(dc));
2465 do_postinc(dc, memsize);
2466 cris_alu_m_free_temps(t);
2467 return insn_len;
2468 }
2469
2470 static unsigned int dec_cmp_m(DisasContext *dc)
2471 {
2472 TCGv t[2];
2473 int memsize = memsize_zz(dc);
2474 int insn_len;
2475 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2476 memsize_char(memsize),
2477 dc->op1, dc->postinc ? "+]" : "]",
2478 dc->op2));
2479
2480 cris_alu_m_alloc_temps(t);
2481 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2482 cris_cc_mask(dc, CC_MASK_NZVC);
2483 cris_alu(dc, CC_OP_CMP,
2484 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2485 memsize_zz(dc));
2486 do_postinc(dc, memsize);
2487 cris_alu_m_free_temps(t);
2488 return insn_len;
2489 }
2490
2491 static unsigned int dec_test_m(DisasContext *dc)
2492 {
2493 TCGv t[2];
2494 int memsize = memsize_zz(dc);
2495 int insn_len;
2496 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2497 memsize_char(memsize),
2498 dc->op1, dc->postinc ? "+]" : "]",
2499 dc->op2));
2500
2501 cris_evaluate_flags(dc);
2502
2503 cris_alu_m_alloc_temps(t);
2504 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2505 cris_cc_mask(dc, CC_MASK_NZ);
2506 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2507
2508 cris_alu(dc, CC_OP_CMP,
2509 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2510 do_postinc(dc, memsize);
2511 cris_alu_m_free_temps(t);
2512 return insn_len;
2513 }
2514
2515 static unsigned int dec_and_m(DisasContext *dc)
2516 {
2517 TCGv t[2];
2518 int memsize = memsize_zz(dc);
2519 int insn_len;
2520 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2521 memsize_char(memsize),
2522 dc->op1, dc->postinc ? "+]" : "]",
2523 dc->op2));
2524
2525 cris_alu_m_alloc_temps(t);
2526 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2527 cris_cc_mask(dc, CC_MASK_NZ);
2528 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2529 do_postinc(dc, memsize);
2530 cris_alu_m_free_temps(t);
2531 return insn_len;
2532 }
2533
2534 static unsigned int dec_add_m(DisasContext *dc)
2535 {
2536 TCGv t[2];
2537 int memsize = memsize_zz(dc);
2538 int insn_len;
2539 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2540 memsize_char(memsize),
2541 dc->op1, dc->postinc ? "+]" : "]",
2542 dc->op2));
2543
2544 cris_alu_m_alloc_temps(t);
2545 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2546 cris_cc_mask(dc, CC_MASK_NZVC);
2547 cris_alu(dc, CC_OP_ADD,
2548 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2549 do_postinc(dc, memsize);
2550 cris_alu_m_free_temps(t);
2551 return insn_len;
2552 }
2553
2554 static unsigned int dec_addo_m(DisasContext *dc)
2555 {
2556 TCGv t[2];
2557 int memsize = memsize_zz(dc);
2558 int insn_len;
2559 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2560 memsize_char(memsize),
2561 dc->op1, dc->postinc ? "+]" : "]",
2562 dc->op2));
2563
2564 cris_alu_m_alloc_temps(t);
2565 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2566 cris_cc_mask(dc, 0);
2567 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2568 do_postinc(dc, memsize);
2569 cris_alu_m_free_temps(t);
2570 return insn_len;
2571 }
2572
2573 static unsigned int dec_bound_m(DisasContext *dc)
2574 {
2575 TCGv l[2];
2576 int memsize = memsize_zz(dc);
2577 int insn_len;
2578 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2579 memsize_char(memsize),
2580 dc->op1, dc->postinc ? "+]" : "]",
2581 dc->op2));
2582
2583 l[0] = tcg_temp_local_new(TCG_TYPE_TL);
2584 l[1] = tcg_temp_local_new(TCG_TYPE_TL);
2585 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2586 cris_cc_mask(dc, CC_MASK_NZ);
2587 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2588 do_postinc(dc, memsize);
2589 tcg_temp_free(l[0]);
2590 tcg_temp_free(l[1]);
2591 return insn_len;
2592 }
2593
2594 static unsigned int dec_addc_mr(DisasContext *dc)
2595 {
2596 TCGv t[2];
2597 int insn_len = 2;
2598 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2599 dc->op1, dc->postinc ? "+]" : "]",
2600 dc->op2));
2601
2602 cris_evaluate_flags(dc);
2603 cris_alu_m_alloc_temps(t);
2604 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2605 cris_cc_mask(dc, CC_MASK_NZVC);
2606 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2607 do_postinc(dc, 4);
2608 cris_alu_m_free_temps(t);
2609 return insn_len;
2610 }
2611
2612 static unsigned int dec_sub_m(DisasContext *dc)
2613 {
2614 TCGv t[2];
2615 int memsize = memsize_zz(dc);
2616 int insn_len;
2617 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2618 memsize_char(memsize),
2619 dc->op1, dc->postinc ? "+]" : "]",
2620 dc->op2, dc->ir, dc->zzsize));
2621
2622 cris_alu_m_alloc_temps(t);
2623 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2624 cris_cc_mask(dc, CC_MASK_NZVC);
2625 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2626 do_postinc(dc, memsize);
2627 cris_alu_m_free_temps(t);
2628 return insn_len;
2629 }
2630
2631 static unsigned int dec_or_m(DisasContext *dc)
2632 {
2633 TCGv t[2];
2634 int memsize = memsize_zz(dc);
2635 int insn_len;
2636 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2637 memsize_char(memsize),
2638 dc->op1, dc->postinc ? "+]" : "]",
2639 dc->op2, dc->pc));
2640
2641 cris_alu_m_alloc_temps(t);
2642 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2643 cris_cc_mask(dc, CC_MASK_NZ);
2644 cris_alu(dc, CC_OP_OR,
2645 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2646 do_postinc(dc, memsize);
2647 cris_alu_m_free_temps(t);
2648 return insn_len;
2649 }
2650
2651 static unsigned int dec_move_mp(DisasContext *dc)
2652 {
2653 TCGv t[2];
2654 int memsize = memsize_zz(dc);
2655 int insn_len = 2;
2656
2657 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2658 memsize_char(memsize),
2659 dc->op1,
2660 dc->postinc ? "+]" : "]",
2661 dc->op2));
2662
2663 cris_alu_m_alloc_temps(t);
2664 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2665 cris_cc_mask(dc, 0);
2666 if (dc->op2 == PR_CCS) {
2667 cris_evaluate_flags(dc);
2668 if (dc->tb_flags & U_FLAG) {
2669 /* User space is not allowed to touch all flags. */
2670 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2671 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2672 tcg_gen_or_tl(t[1], t[0], t[1]);
2673 }
2674 }
2675
2676 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2677
2678 do_postinc(dc, memsize);
2679 cris_alu_m_free_temps(t);
2680 return insn_len;
2681 }
2682
2683 static unsigned int dec_move_pm(DisasContext *dc)
2684 {
2685 TCGv t0;
2686 int memsize;
2687
2688 memsize = preg_sizes[dc->op2];
2689
2690 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2691 memsize_char(memsize),
2692 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2693
2694 /* prepare store. Address in T0, value in T1. */
2695 if (dc->op2 == PR_CCS)
2696 cris_evaluate_flags(dc);
2697 t0 = tcg_temp_new(TCG_TYPE_TL);
2698 t_gen_mov_TN_preg(t0, dc->op2);
2699 cris_flush_cc_state(dc);
2700 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2701 tcg_temp_free(t0);
2702
2703 cris_cc_mask(dc, 0);
2704 if (dc->postinc)
2705 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2706 return 2;
2707 }
2708
2709 static unsigned int dec_movem_mr(DisasContext *dc)
2710 {
2711 TCGv tmp[16];
2712 TCGv addr;
2713 int i;
2714 int nr = dc->op2 + 1;
2715
2716 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2717 dc->postinc ? "+]" : "]", dc->op2));
2718
2719 addr = tcg_temp_new(TCG_TYPE_TL);
2720 /* There are probably better ways of doing this. */
2721 cris_flush_cc_state(dc);
2722 for (i = 0; i < (nr >> 1); i++) {
2723 tmp[i] = tcg_temp_new(TCG_TYPE_I64);
2724 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2725 gen_load(dc, tmp[i], addr, 8, 0);
2726 }
2727 if (nr & 1) {
2728 tmp[i] = tcg_temp_new(TCG_TYPE_I32);
2729 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2730 gen_load(dc, tmp[i], addr, 4, 0);
2731 }
2732 tcg_temp_free(addr);
2733
2734 for (i = 0; i < (nr >> 1); i++) {
2735 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2736 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2737 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2738 tcg_temp_free(tmp[i]);
2739 }
2740 if (nr & 1) {
2741 tcg_gen_mov_tl(cpu_R[dc->op2], tmp[i]);
2742 tcg_temp_free(tmp[i]);
2743 }
2744
2745 /* writeback the updated pointer value. */
2746 if (dc->postinc)
2747 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2748
2749 /* gen_load might want to evaluate the previous insns flags. */
2750 cris_cc_mask(dc, 0);
2751 return 2;
2752 }
2753
2754 static unsigned int dec_movem_rm(DisasContext *dc)
2755 {
2756 TCGv tmp;
2757 TCGv addr;
2758 int i;
2759
2760 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2761 dc->postinc ? "+]" : "]"));
2762
2763 cris_flush_cc_state(dc);
2764
2765 tmp = tcg_temp_new(TCG_TYPE_TL);
2766 addr = tcg_temp_new(TCG_TYPE_TL);
2767 tcg_gen_movi_tl(tmp, 4);
2768 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2769 for (i = 0; i <= dc->op2; i++) {
2770 /* Displace addr. */
2771 /* Perform the store. */
2772 gen_store(dc, addr, cpu_R[i], 4);
2773 tcg_gen_add_tl(addr, addr, tmp);
2774 }
2775 if (dc->postinc)
2776 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2777 cris_cc_mask(dc, 0);
2778 tcg_temp_free(tmp);
2779 tcg_temp_free(addr);
2780 return 2;
2781 }
2782
2783 static unsigned int dec_move_rm(DisasContext *dc)
2784 {
2785 int memsize;
2786
2787 memsize = memsize_zz(dc);
2788
2789 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2790 memsize, dc->op2, dc->op1));
2791
2792 /* prepare store. */
2793 cris_flush_cc_state(dc);
2794 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2795
2796 if (dc->postinc)
2797 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2798 cris_cc_mask(dc, 0);
2799 return 2;
2800 }
2801
2802 static unsigned int dec_lapcq(DisasContext *dc)
2803 {
2804 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2805 dc->pc + dc->op1*2, dc->op2));
2806 cris_cc_mask(dc, 0);
2807 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2808 return 2;
2809 }
2810
2811 static unsigned int dec_lapc_im(DisasContext *dc)
2812 {
2813 unsigned int rd;
2814 int32_t imm;
2815 int32_t pc;
2816
2817 rd = dc->op2;
2818
2819 cris_cc_mask(dc, 0);
2820 imm = ldl_code(dc->pc + 2);
2821 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2822
2823 pc = dc->pc;
2824 pc += imm;
2825 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2826 return 6;
2827 }
2828
2829 /* Jump to special reg. */
2830 static unsigned int dec_jump_p(DisasContext *dc)
2831 {
2832 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2833
2834 if (dc->op2 == PR_CCS)
2835 cris_evaluate_flags(dc);
2836 t_gen_mov_TN_preg(env_btarget, dc->op2);
2837 /* rete will often have low bit set to indicate delayslot. */
2838 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2839 cris_cc_mask(dc, 0);
2840 cris_prepare_jmp(dc, JMP_INDIRECT);
2841 return 2;
2842 }
2843
2844 /* Jump and save. */
2845 static unsigned int dec_jas_r(DisasContext *dc)
2846 {
2847 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2848 cris_cc_mask(dc, 0);
2849 /* Store the return address in Pd. */
2850 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2851 if (dc->op2 > 15)
2852 abort();
2853 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2854
2855 cris_prepare_jmp(dc, JMP_INDIRECT);
2856 return 2;
2857 }
2858
2859 static unsigned int dec_jas_im(DisasContext *dc)
2860 {
2861 uint32_t imm;
2862
2863 imm = ldl_code(dc->pc + 2);
2864
2865 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2866 cris_cc_mask(dc, 0);
2867 /* Store the return address in Pd. */
2868 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2869
2870 dc->jmp_pc = imm;
2871 cris_prepare_jmp(dc, JMP_DIRECT);
2872 return 6;
2873 }
2874
2875 static unsigned int dec_jasc_im(DisasContext *dc)
2876 {
2877 uint32_t imm;
2878
2879 imm = ldl_code(dc->pc + 2);
2880
2881 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2882 cris_cc_mask(dc, 0);
2883 /* Store the return address in Pd. */
2884 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2885
2886 dc->jmp_pc = imm;
2887 cris_prepare_jmp(dc, JMP_DIRECT);
2888 return 6;
2889 }
2890
2891 static unsigned int dec_jasc_r(DisasContext *dc)
2892 {
2893 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2894 cris_cc_mask(dc, 0);
2895 /* Store the return address in Pd. */
2896 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2897 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2898 cris_prepare_jmp(dc, JMP_INDIRECT);
2899 return 2;
2900 }
2901
2902 static unsigned int dec_bcc_im(DisasContext *dc)
2903 {
2904 int32_t offset;
2905 uint32_t cond = dc->op2;
2906
2907 offset = ldsw_code(dc->pc + 2);
2908
2909 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2910 cc_name(cond), offset,
2911 dc->pc, dc->pc + offset));
2912
2913 cris_cc_mask(dc, 0);
2914 /* op2 holds the condition-code. */
2915 cris_prepare_cc_branch (dc, offset, cond);
2916 return 4;
2917 }
2918
2919 static unsigned int dec_bas_im(DisasContext *dc)
2920 {
2921 int32_t simm;
2922
2923
2924 simm = ldl_code(dc->pc + 2);
2925
2926 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2927 cris_cc_mask(dc, 0);
2928 /* Store the return address in Pd. */
2929 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2930
2931 dc->jmp_pc = dc->pc + simm;
2932 cris_prepare_jmp(dc, JMP_DIRECT);
2933 return 6;
2934 }
2935
2936 static unsigned int dec_basc_im(DisasContext *dc)
2937 {
2938 int32_t simm;
2939 simm = ldl_code(dc->pc + 2);
2940
2941 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2942 cris_cc_mask(dc, 0);
2943 /* Store the return address in Pd. */
2944 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2945
2946 dc->jmp_pc = dc->pc + simm;
2947 cris_prepare_jmp(dc, JMP_DIRECT);
2948 return 6;
2949 }
2950
2951 static unsigned int dec_rfe_etc(DisasContext *dc)
2952 {
2953 cris_cc_mask(dc, 0);
2954
2955 if (dc->op2 == 15) /* ignore halt. */
2956 return 2;
2957
2958 switch (dc->op2 & 7) {
2959 case 2:
2960 /* rfe. */
2961 DIS(fprintf(logfile, "rfe\n"));
2962 cris_evaluate_flags(dc);
2963 tcg_gen_helper_0_0(helper_rfe);
2964 dc->is_jmp = DISAS_UPDATE;
2965 break;
2966 case 5:
2967 /* rfn. */
2968 DIS(fprintf(logfile, "rfn\n"));
2969 cris_evaluate_flags(dc);
2970 tcg_gen_helper_0_0(helper_rfn);
2971 dc->is_jmp = DISAS_UPDATE;
2972 break;
2973 case 6:
2974 DIS(fprintf(logfile, "break %d\n", dc->op1));
2975 cris_evaluate_flags (dc);
2976 /* break. */
2977 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2978
2979 /* Breaks start at 16 in the exception vector. */
2980 t_gen_mov_env_TN(trap_vector,
2981 tcg_const_tl(dc->op1 + 16));
2982 t_gen_raise_exception(EXCP_BREAK);
2983 dc->is_jmp = DISAS_UPDATE;
2984 break;
2985 default:
2986 printf ("op2=%x\n", dc->op2);
2987 BUG();
2988 break;
2989
2990 }
2991 return 2;
2992 }
2993
2994 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2995 {
2996 return 2;
2997 }
2998
2999 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
3000 {
3001 return 2;
3002 }
3003
3004 static unsigned int dec_null(DisasContext *dc)
3005 {
3006 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
3007 dc->pc, dc->opcode, dc->op1, dc->op2);
3008 fflush(NULL);
3009 BUG();
3010 return 2;
3011 }
3012
3013 static struct decoder_info {
3014 struct {
3015 uint32_t bits;
3016 uint32_t mask;
3017 };
3018 unsigned int (*dec)(DisasContext *dc);
3019 } decinfo[] = {
3020 /* Order matters here. */
3021 {DEC_MOVEQ, dec_moveq},
3022 {DEC_BTSTQ, dec_btstq},
3023 {DEC_CMPQ, dec_cmpq},
3024 {DEC_ADDOQ, dec_addoq},
3025 {DEC_ADDQ, dec_addq},
3026 {DEC_SUBQ, dec_subq},
3027 {DEC_ANDQ, dec_andq},
3028 {DEC_ORQ, dec_orq},
3029 {DEC_ASRQ, dec_asrq},
3030 {DEC_LSLQ, dec_lslq},
3031 {DEC_LSRQ, dec_lsrq},
3032 {DEC_BCCQ, dec_bccq},
3033
3034 {DEC_BCC_IM, dec_bcc_im},
3035 {DEC_JAS_IM, dec_jas_im},
3036 {DEC_JAS_R, dec_jas_r},
3037 {DEC_JASC_IM, dec_jasc_im},
3038 {DEC_JASC_R, dec_jasc_r},
3039 {DEC_BAS_IM, dec_bas_im},
3040 {DEC_BASC_IM, dec_basc_im},
3041 {DEC_JUMP_P, dec_jump_p},
3042 {DEC_LAPC_IM, dec_lapc_im},
3043 {DEC_LAPCQ, dec_lapcq},
3044
3045 {DEC_RFE_ETC, dec_rfe_etc},
3046 {DEC_ADDC_MR, dec_addc_mr},
3047
3048 {DEC_MOVE_MP, dec_move_mp},
3049 {DEC_MOVE_PM, dec_move_pm},
3050 {DEC_MOVEM_MR, dec_movem_mr},
3051 {DEC_MOVEM_RM, dec_movem_rm},
3052 {DEC_MOVE_PR, dec_move_pr},
3053 {DEC_SCC_R, dec_scc_r},
3054 {DEC_SETF, dec_setclrf},
3055 {DEC_CLEARF, dec_setclrf},
3056
3057 {DEC_MOVE_SR, dec_move_sr},
3058 {DEC_MOVE_RP, dec_move_rp},
3059 {DEC_SWAP_R, dec_swap_r},
3060 {DEC_ABS_R, dec_abs_r},
3061 {DEC_LZ_R, dec_lz_r},
3062 {DEC_MOVE_RS, dec_move_rs},
3063 {DEC_BTST_R, dec_btst_r},
3064 {DEC_ADDC_R, dec_addc_r},
3065
3066 {DEC_DSTEP_R, dec_dstep_r},
3067 {DEC_XOR_R, dec_xor_r},
3068 {DEC_MCP_R, dec_mcp_r},
3069 {DEC_CMP_R, dec_cmp_r},
3070
3071 {DEC_ADDI_R, dec_addi_r},
3072 {DEC_ADDI_ACR, dec_addi_acr},
3073
3074 {DEC_ADD_R, dec_add_r},
3075 {DEC_SUB_R, dec_sub_r},
3076
3077 {DEC_ADDU_R, dec_addu_r},
3078 {DEC_ADDS_R, dec_adds_r},
3079 {DEC_SUBU_R, dec_subu_r},
3080 {DEC_SUBS_R, dec_subs_r},
3081 {DEC_LSL_R, dec_lsl_r},
3082
3083 {DEC_AND_R, dec_and_r},
3084 {DEC_OR_R, dec_or_r},
3085 {DEC_BOUND_R, dec_bound_r},
3086 {DEC_ASR_R, dec_asr_r},
3087 {DEC_LSR_R, dec_lsr_r},
3088
3089 {DEC_MOVU_R, dec_movu_r},
3090 {DEC_MOVS_R, dec_movs_r},
3091 {DEC_NEG_R, dec_neg_r},
3092 {DEC_MOVE_R, dec_move_r},
3093
3094 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3095 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3096
3097 {DEC_MULS_R, dec_muls_r},
3098 {DEC_MULU_R, dec_mulu_r},
3099
3100 {DEC_ADDU_M, dec_addu_m},
3101 {DEC_ADDS_M, dec_adds_m},
3102 {DEC_SUBU_M, dec_subu_m},
3103 {DEC_SUBS_M, dec_subs_m},
3104
3105 {DEC_CMPU_M, dec_cmpu_m},
3106 {DEC_CMPS_M, dec_cmps_m},
3107 {DEC_MOVU_M, dec_movu_m},
3108 {DEC_MOVS_M, dec_movs_m},
3109
3110 {DEC_CMP_M, dec_cmp_m},
3111 {DEC_ADDO_M, dec_addo_m},
3112 {DEC_BOUND_M, dec_bound_m},
3113 {DEC_ADD_M, dec_add_m},
3114 {DEC_SUB_M, dec_sub_m},
3115 {DEC_AND_M, dec_and_m},
3116 {DEC_OR_M, dec_or_m},
3117 {DEC_MOVE_RM, dec_move_rm},
3118 {DEC_TEST_M, dec_test_m},
3119 {DEC_MOVE_MR, dec_move_mr},
3120
3121 {{0, 0}, dec_null}
3122 };
3123
3124 static inline unsigned int
3125 cris_decoder(DisasContext *dc)
3126 {
3127 unsigned int insn_len = 2;
3128 int i;
3129
3130 if (unlikely(loglevel & CPU_LOG_TB_OP))
3131 tcg_gen_debug_insn_start(dc->pc);
3132
3133 /* Load a halfword onto the instruction register. */
3134 dc->ir = lduw_code(dc->pc);
3135
3136 /* Now decode it. */
3137 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3138 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3139 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3140 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3141 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3142 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3143
3144 /* Large switch for all insns. */
3145 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
3146 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3147 {
3148 insn_len = decinfo[i].dec(dc);
3149 break;
3150 }
3151 }
3152
3153 #if !defined(CONFIG_USER_ONLY)
3154 /* Single-stepping ? */
3155 if (dc->tb_flags & S_FLAG) {
3156 int l1;
3157
3158 l1 = gen_new_label();
3159 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3160 /* We treat SPC as a break with an odd trap vector. */
3161 cris_evaluate_flags (dc);
3162 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3163 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3164 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3165 t_gen_raise_exception(EXCP_BREAK);
3166 gen_set_label(l1);
3167 }
3168 #endif
3169 return insn_len;
3170 }
3171
3172 static void check_breakpoint(CPUState *env, DisasContext *dc)
3173 {
3174 int j;
3175 if (env->nb_breakpoints > 0) {
3176 for(j = 0; j < env->nb_breakpoints; j++) {
3177 if (env->breakpoints[j] == dc->pc) {
3178 cris_evaluate_flags (dc);
3179 tcg_gen_movi_tl(env_pc, dc->pc);
3180 t_gen_raise_exception(EXCP_DEBUG);
3181 dc->is_jmp = DISAS_UPDATE;
3182 }
3183 }
3184 }
3185 }
3186
3187
3188 /*
3189 * Delay slots on QEMU/CRIS.
3190 *
3191 * If an exception hits on a delayslot, the core will let ERP (the Exception
3192 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3193 * to give SW a hint that the exception actually hit on the dslot.
3194 *
3195 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3196 * the core and any jmp to an odd addresses will mask off that lsb. It is
3197 * simply there to let sw know there was an exception on a dslot.
3198 *
3199 * When the software returns from an exception, the branch will re-execute.
3200 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3201 * and the branch and delayslot dont share pages.
3202 *
3203 * The TB contaning the branch insn will set up env->btarget and evaluate
3204 * env->btaken. When the translation loop exits we will note that the branch
3205 * sequence is broken and let env->dslot be the size of the branch insn (those
3206 * vary in length).
3207 *
3208 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3209 * set). It will also expect to have env->dslot setup with the size of the
3210 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3211 * will execute the dslot and take the branch, either to btarget or just one
3212 * insn ahead.
3213 *
3214 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3215 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3216 * branch and set lsb). Then env->dslot gets cleared so that the exception
3217 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3218 * masked off and we will reexecute the branch insn.
3219 *
3220 */
3221
3222 /* generate intermediate code for basic block 'tb'. */
3223 static void
3224 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3225 int search_pc)
3226 {
3227 uint16_t *gen_opc_end;
3228 uint32_t pc_start;
3229 unsigned int insn_len;
3230 int j, lj;
3231 struct DisasContext ctx;
3232 struct DisasContext *dc = &ctx;
3233 uint32_t next_page_start;
3234 target_ulong npc;
3235 int num_insns;
3236 int max_insns;
3237
3238 if (!logfile)
3239 logfile = stderr;
3240
3241 /* Odd PC indicates that branch is rexecuting due to exception in the
3242 * delayslot, like in real hw.
3243 */
3244 pc_start = tb->pc & ~1;
3245 dc->env = env;
3246 dc->tb = tb;
3247
3248 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3249
3250 dc->is_jmp = DISAS_NEXT;
3251 dc->ppc = pc_start;
3252 dc->pc = pc_start;
3253 dc->singlestep_enabled = env->singlestep_enabled;
3254 dc->flags_uptodate = 1;
3255 dc->flagx_known = 1;
3256 dc->flags_x = tb->flags & X_FLAG;
3257 dc->cc_x_uptodate = 0;
3258 dc->cc_mask = 0;
3259 dc->update_cc = 0;
3260
3261 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3262 dc->cc_size_uptodate = -1;
3263
3264 /* Decode TB flags. */
3265 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3266 dc->delayed_branch = !!(tb->flags & 7);
3267 if (dc->delayed_branch)
3268 dc->jmp = JMP_INDIRECT;
3269 else
3270 dc->jmp = JMP_NOJMP;
3271
3272 dc->cpustate_changed = 0;
3273
3274 if (loglevel & CPU_LOG_TB_IN_ASM) {
3275 fprintf(logfile,
3276 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3277 "pid=%x usp=%x\n"
3278 "%x.%x.%x.%x\n"
3279 "%x.%x.%x.%x\n"
3280 "%x.%x.%x.%x\n"
3281 "%x.%x.%x.%x\n",
3282 search_pc, dc->pc, dc->ppc,
3283 (unsigned long long)tb->flags,
3284 env->btarget, (unsigned)tb->flags & 7,
3285 env->pregs[PR_CCS],
3286 env->pregs[PR_PID], env->pregs[PR_USP],
3287 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3288 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3289 env->regs[8], env->regs[9],
3290 env->regs[10], env->regs[11],
3291 env->regs[12], env->regs[13],
3292 env->regs[14], env->regs[15]);
3293 fprintf(logfile, "--------------\n");
3294 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3295 }
3296
3297 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3298 lj = -1;
3299 num_insns = 0;
3300 max_insns = tb->cflags & CF_COUNT_MASK;
3301 if (max_insns == 0)
3302 max_insns = CF_COUNT_MASK;
3303
3304 gen_icount_start();
3305 do
3306 {
3307 check_breakpoint(env, dc);
3308
3309 if (search_pc) {
3310 j = gen_opc_ptr - gen_opc_buf;
3311 if (lj < j) {
3312 lj++;
3313 while (lj < j)
3314 gen_opc_instr_start[lj++] = 0;
3315 }
3316 if (dc->delayed_branch == 1)
3317 gen_opc_pc[lj] = dc->ppc | 1;
3318 else
3319 gen_opc_pc[lj] = dc->pc;
3320 gen_opc_instr_start[lj] = 1;
3321 gen_opc_icount[lj] = num_insns;
3322 }
3323
3324 /* Pretty disas. */
3325 DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
3326
3327 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3328 gen_io_start();
3329 dc->clear_x = 1;
3330
3331 insn_len = cris_decoder(dc);
3332 dc->ppc = dc->pc;
3333 dc->pc += insn_len;
3334 if (dc->clear_x)
3335 cris_clear_x_flag(dc);
3336
3337 num_insns++;
3338 /* Check for delayed branches here. If we do it before
3339 actually generating any host code, the simulator will just
3340 loop doing nothing for on this program location. */
3341 if (dc->delayed_branch) {
3342 dc->delayed_branch--;
3343 if (dc->delayed_branch == 0)
3344 {
3345 if (tb->flags & 7)
3346 t_gen_mov_env_TN(dslot,
3347 tcg_const_tl(0));
3348 if (dc->jmp == JMP_DIRECT) {
3349 dc->is_jmp = DISAS_NEXT;
3350 } else {
3351 t_gen_cc_jmp(env_btarget,
3352 tcg_const_tl(dc->pc));
3353 dc->is_jmp = DISAS_JUMP;
3354 }
3355 break;
3356 }
3357 }
3358
3359 /* If we are rexecuting a branch due to exceptions on
3360 delay slots dont break. */
3361 if (!(tb->pc & 1) && env->singlestep_enabled)
3362 break;
3363 } while (!dc->is_jmp && !dc->cpustate_changed
3364 && gen_opc_ptr < gen_opc_end
3365 && (dc->pc < next_page_start)
3366 && num_insns < max_insns);
3367
3368 npc = dc->pc;
3369 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3370 npc = dc->jmp_pc;
3371
3372 if (tb->cflags & CF_LAST_IO)
3373 gen_io_end();
3374 /* Force an update if the per-tb cpu state has changed. */
3375 if (dc->is_jmp == DISAS_NEXT
3376 && (dc->cpustate_changed || !dc->flagx_known
3377 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3378 dc->is_jmp = DISAS_UPDATE;
3379 tcg_gen_movi_tl(env_pc, npc);
3380 }
3381 /* Broken branch+delayslot sequence. */
3382 if (dc->delayed_branch == 1) {
3383 /* Set env->dslot to the size of the branch insn. */
3384 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3385 cris_store_direct_jmp(dc);
3386 }
3387
3388 cris_evaluate_flags (dc);
3389
3390 if (unlikely(env->singlestep_enabled)) {
3391 if (dc->is_jmp == DISAS_NEXT)
3392 tcg_gen_movi_tl(env_pc, npc);
3393 t_gen_raise_exception(EXCP_DEBUG);
3394 } else {
3395 switch(dc->is_jmp) {
3396 case DISAS_NEXT:
3397 gen_goto_tb(dc, 1, npc);
3398 break;
3399 default:
3400 case DISAS_JUMP:
3401 case DISAS_UPDATE:
3402 /* indicate that the hash table must be used
3403 to find the next TB */
3404 tcg_gen_exit_tb(0);
3405 break;
3406 case DISAS_SWI:
3407 case DISAS_TB_JUMP:
3408 /* nothing more to generate */
3409 break;
3410 }
3411 }
3412 gen_icount_end(tb, num_insns);
3413 *gen_opc_ptr = INDEX_op_end;
3414 if (search_pc) {
3415 j = gen_opc_ptr - gen_opc_buf;
3416 lj++;
3417 while (lj <= j)
3418 gen_opc_instr_start[lj++] = 0;
3419 } else {
3420 tb->size = dc->pc - pc_start;
3421 tb->icount = num_insns;
3422 }
3423
3424 #ifdef DEBUG_DISAS
3425 #if !DISAS_CRIS
3426 if (loglevel & CPU_LOG_TB_IN_ASM) {
3427 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3428 fprintf(logfile, "\nisize=%d osize=%zd\n",
3429 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3430 }
3431 #endif
3432 #endif
3433 }
3434
3435 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3436 {
3437 gen_intermediate_code_internal(env, tb, 0);
3438 }
3439
3440 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3441 {
3442 gen_intermediate_code_internal(env, tb, 1);
3443 }
3444
3445 void cpu_dump_state (CPUState *env, FILE *f,
3446 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3447 int flags)
3448 {
3449 int i;
3450 uint32_t srs;
3451
3452 if (!env || !f)
3453 return;
3454
3455 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3456 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3457 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3458 env->cc_op,
3459 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3460
3461
3462 for (i = 0; i < 16; i++) {
3463 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3464 if ((i + 1) % 4 == 0)
3465 cpu_fprintf(f, "\n");
3466 }
3467 cpu_fprintf(f, "\nspecial regs:\n");
3468 for (i = 0; i < 16; i++) {
3469 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3470 if ((i + 1) % 4 == 0)
3471 cpu_fprintf(f, "\n");
3472 }
3473 srs = env->pregs[PR_SRS];
3474 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3475 if (srs < 256) {
3476 for (i = 0; i < 16; i++) {
3477 cpu_fprintf(f, "s%2.2d=%8.8x ",
3478 i, env->sregs[srs][i]);
3479 if ((i + 1) % 4 == 0)
3480 cpu_fprintf(f, "\n");
3481 }
3482 }
3483 cpu_fprintf(f, "\n\n");
3484
3485 }
3486
3487 CPUCRISState *cpu_cris_init (const char *cpu_model)
3488 {
3489 CPUCRISState *env;
3490 static int tcg_initialized = 0;
3491 int i;
3492
3493 env = qemu_mallocz(sizeof(CPUCRISState));
3494 if (!env)
3495 return NULL;
3496
3497 cpu_exec_init(env);
3498 cpu_reset(env);
3499
3500 if (tcg_initialized)
3501 return env;
3502
3503 tcg_initialized = 1;
3504
3505 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3506 cc_x = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3507 offsetof(CPUState, cc_x), "cc_x");
3508 cc_src = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3509 offsetof(CPUState, cc_src), "cc_src");
3510 cc_dest = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3511 offsetof(CPUState, cc_dest),
3512 "cc_dest");
3513 cc_result = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3514 offsetof(CPUState, cc_result),
3515 "cc_result");
3516 cc_op = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3517 offsetof(CPUState, cc_op), "cc_op");
3518 cc_size = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3519 offsetof(CPUState, cc_size),
3520 "cc_size");
3521 cc_mask = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3522 offsetof(CPUState, cc_mask),
3523 "cc_mask");
3524
3525 env_pc = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3526 offsetof(CPUState, pc),
3527 "pc");
3528 env_btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3529 offsetof(CPUState, btarget),
3530 "btarget");
3531 env_btaken = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3532 offsetof(CPUState, btaken),
3533 "btaken");
3534 for (i = 0; i < 16; i++) {
3535 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3536 offsetof(CPUState, regs[i]),
3537 regnames[i]);
3538 }
3539 for (i = 0; i < 16; i++) {
3540 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3541 offsetof(CPUState, pregs[i]),
3542 pregnames[i]);
3543 }
3544
3545 TCG_HELPER(helper_raise_exception);
3546 TCG_HELPER(helper_dump);
3547
3548 TCG_HELPER(helper_tlb_flush_pid);
3549 TCG_HELPER(helper_movl_sreg_reg);
3550 TCG_HELPER(helper_movl_reg_sreg);
3551 TCG_HELPER(helper_rfe);
3552 TCG_HELPER(helper_rfn);
3553
3554 TCG_HELPER(helper_evaluate_flags_muls);
3555 TCG_HELPER(helper_evaluate_flags_mulu);
3556 TCG_HELPER(helper_evaluate_flags_mcp);
3557 TCG_HELPER(helper_evaluate_flags_alu_4);
3558 TCG_HELPER(helper_evaluate_flags_move_4);
3559 TCG_HELPER(helper_evaluate_flags_move_2);
3560 TCG_HELPER(helper_evaluate_flags);
3561 TCG_HELPER(helper_top_evaluate_flags);
3562 return env;
3563 }
3564
3565 void cpu_reset (CPUCRISState *env)
3566 {
3567 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3568 tlb_flush(env, 1);
3569
3570 env->pregs[PR_VR] = 32;
3571 #if defined(CONFIG_USER_ONLY)
3572 /* start in user mode with interrupts enabled. */
3573 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3574 #else
3575 env->pregs[PR_CCS] = 0;
3576 #endif
3577 }
3578
3579 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3580 unsigned long searched_pc, int pc_pos, void *puc)
3581 {
3582 env->pc = gen_opc_pc[pc_pos];
3583 }
jz4740 based target emulation