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target-ppc: Convert XER accesses to TCG
[qemu/qemu-JZ.git] / hw / sun4m.c
blobdd0433afca3876719f007a3af48797173955f8c1
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38
39 //#define DEBUG_IRQ
40
41 /*
42 * Sun4m architecture was used in the following machines:
43 *
44 * SPARCserver 6xxMP/xx
45 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
46 * SPARCclassic X (4/10)
47 * SPARCstation LX/ZX (4/30)
48 * SPARCstation Voyager
49 * SPARCstation 10/xx, SPARCserver 10/xx
50 * SPARCstation 5, SPARCserver 5
51 * SPARCstation 20/xx, SPARCserver 20
52 * SPARCstation 4
53 *
54 * Sun4d architecture was used in the following machines:
55 *
56 * SPARCcenter 2000
57 * SPARCserver 1000
58 *
59 * Sun4c architecture was used in the following machines:
60 * SPARCstation 1/1+, SPARCserver 1/1+
61 * SPARCstation SLC
62 * SPARCstation IPC
63 * SPARCstation ELC
64 * SPARCstation IPX
65 *
66 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 */
68
69 #ifdef DEBUG_IRQ
70 #define DPRINTF(fmt, args...) \
71 do { printf("CPUIRQ: " fmt , ##args); } while (0)
72 #else
73 #define DPRINTF(fmt, args...)
74 #endif
75
76 #define KERNEL_LOAD_ADDR 0x00004000
77 #define CMDLINE_ADDR 0x007ff000
78 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_SIZE_MAX (512 * 1024)
80 #define PROM_VADDR 0xffd00000
81 #define PROM_FILENAME "openbios-sparc32"
82 #define CFG_ADDR 0xd00000510ULL
83 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
84
85 // Control plane, 8-bit and 24-bit planes
86 #define TCX_SIZE (9 * 1024 * 1024)
87
88 #define MAX_CPUS 16
89 #define MAX_PILS 16
90
91 struct hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
100 long vram_size, nvram_size;
101 // IRQ numbers are not PIL ones, but master interrupt controller
102 // register bit numbers
103 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
104 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
105 uint8_t nvram_machine_id;
106 uint16_t machine_id;
107 uint32_t iommu_version;
108 uint32_t intbit_to_level[32];
109 uint64_t max_mem;
110 const char * const default_cpu_model;
111 };
112
113 #define MAX_IOUNITS 5
114
115 struct sun4d_hwdef {
116 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
117 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
118 target_phys_addr_t serial_base;
119 target_phys_addr_t espdma_base, esp_base;
120 target_phys_addr_t ledma_base, le_base;
121 target_phys_addr_t tcx_base;
122 target_phys_addr_t sbi_base;
123 unsigned long vram_size, nvram_size;
124 // IRQ numbers are not PIL ones, but SBI register bit numbers
125 int esp_irq, le_irq, clock_irq, clock1_irq;
126 int ser_irq, ms_kb_irq, me_irq;
127 uint8_t nvram_machine_id;
128 uint16_t machine_id;
129 uint32_t iounit_version;
130 uint64_t max_mem;
131 const char * const default_cpu_model;
132 };
133
134 int DMA_get_channel_mode (int nchan)
135 {
136 return 0;
137 }
138 int DMA_read_memory (int nchan, void *buf, int pos, int size)
139 {
140 return 0;
141 }
142 int DMA_write_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 void DMA_hold_DREQ (int nchan) {}
147 void DMA_release_DREQ (int nchan) {}
148 void DMA_schedule(int nchan) {}
149 void DMA_run (void) {}
150 void DMA_init (int high_page_enable) {}
151 void DMA_register_channel (int nchan,
152 DMA_transfer_handler transfer_handler,
153 void *opaque)
154 {
155 }
156
157 static int nvram_boot_set(void *opaque, const char *boot_device)
158 {
159 unsigned int i;
160 uint8_t image[sizeof(ohwcfg_v3_t)];
161 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
162 m48t59_t *nvram = (m48t59_t *)opaque;
163
164 for (i = 0; i < sizeof(image); i++)
165 image[i] = m48t59_read(nvram, i) & 0xff;
166
167 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
168 boot_device);
169 header->nboot_devices = strlen(boot_device) & 0xff;
170 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
171
172 for (i = 0; i < sizeof(image); i++)
173 m48t59_write(nvram, i, image[i]);
174
175 return 0;
176 }
177
178 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
179 const char *boot_devices, ram_addr_t RAM_size,
180 uint32_t kernel_size,
181 int width, int height, int depth,
182 int nvram_machine_id, const char *arch)
183 {
184 unsigned int i;
185 uint32_t start, end;
186 uint8_t image[0x1ff0];
187 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
188 struct sparc_arch_cfg *sparc_header;
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 // Try to match PPC NVRAM
194 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
195 "QEMU_BIOS");
196 header->struct_version = cpu_to_be32(3); /* structure v3 */
197
198 header->nvram_size = cpu_to_be16(0x2000);
199 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
200 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
201 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
202 header->nb_cpus = smp_cpus & 0xff;
203 header->RAM0_base = 0;
204 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
205 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
206 boot_devices);
207 header->nboot_devices = strlen(boot_devices) & 0xff;
208 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
209 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
210 if (cmdline) {
211 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
212 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
213 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
214 }
215 // XXX add initrd_image, initrd_size
216 header->width = cpu_to_be16(width);
217 header->height = cpu_to_be16(height);
218 header->depth = cpu_to_be16(depth);
219 if (nographic)
220 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
221
222 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
223
224 // Architecture specific header
225 start = sizeof(ohwcfg_v3_t);
226 sparc_header = (struct sparc_arch_cfg *)&image[start];
227 sparc_header->valid = 0;
228 start += sizeof(struct sparc_arch_cfg);
229
230 // OpenBIOS nvram variables
231 // Variable partition
232 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
233 part_header->signature = OPENBIOS_PART_SYSTEM;
234 pstrcpy(part_header->name, sizeof(part_header->name), "system");
235
236 end = start + sizeof(struct OpenBIOS_nvpart_v1);
237 for (i = 0; i < nb_prom_envs; i++)
238 end = OpenBIOS_set_var(image, end, prom_envs[i]);
239
240 // End marker
241 image[end++] = '\0';
242
243 end = start + ((end - start + 15) & ~15);
244 OpenBIOS_finish_partition(part_header, end - start);
245
246 // free partition
247 start = end;
248 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
249 part_header->signature = OPENBIOS_PART_FREE;
250 pstrcpy(part_header->name, sizeof(part_header->name), "free");
251
252 end = 0x1fd0;
253 OpenBIOS_finish_partition(part_header, end - start);
254
255 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
256 nvram_machine_id);
257
258 for (i = 0; i < sizeof(image); i++)
259 m48t59_write(nvram, i, image[i]);
260
261 qemu_register_boot_set(nvram_boot_set, nvram);
262 }
263
264 static void *slavio_intctl;
265
266 void pic_info(void)
267 {
268 if (slavio_intctl)
269 slavio_pic_info(slavio_intctl);
270 }
271
272 void irq_info(void)
273 {
274 if (slavio_intctl)
275 slavio_irq_info(slavio_intctl);
276 }
277
278 void cpu_check_irqs(CPUState *env)
279 {
280 if (env->pil_in && (env->interrupt_index == 0 ||
281 (env->interrupt_index & ~15) == TT_EXTINT)) {
282 unsigned int i;
283
284 for (i = 15; i > 0; i--) {
285 if (env->pil_in & (1 << i)) {
286 int old_interrupt = env->interrupt_index;
287
288 env->interrupt_index = TT_EXTINT | i;
289 if (old_interrupt != env->interrupt_index) {
290 DPRINTF("Set CPU IRQ %d\n", i);
291 cpu_interrupt(env, CPU_INTERRUPT_HARD);
292 }
293 break;
294 }
295 }
296 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
297 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
298 env->interrupt_index = 0;
299 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
300 }
301 }
302
303 static void cpu_set_irq(void *opaque, int irq, int level)
304 {
305 CPUState *env = opaque;
306
307 if (level) {
308 DPRINTF("Raise CPU IRQ %d\n", irq);
309 env->halted = 0;
310 env->pil_in |= 1 << irq;
311 cpu_check_irqs(env);
312 } else {
313 DPRINTF("Lower CPU IRQ %d\n", irq);
314 env->pil_in &= ~(1 << irq);
315 cpu_check_irqs(env);
316 }
317 }
318
319 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
320 {
321 }
322
323 static void *slavio_misc;
324
325 void qemu_system_powerdown(void)
326 {
327 slavio_set_power_fail(slavio_misc, 1);
328 }
329
330 static void main_cpu_reset(void *opaque)
331 {
332 CPUState *env = opaque;
333
334 cpu_reset(env);
335 env->halted = 0;
336 }
337
338 static void secondary_cpu_reset(void *opaque)
339 {
340 CPUState *env = opaque;
341
342 cpu_reset(env);
343 env->halted = 1;
344 }
345
346 static unsigned long sun4m_load_kernel(const char *kernel_filename,
347 const char *initrd_filename,
348 ram_addr_t RAM_size)
349 {
350 int linux_boot;
351 unsigned int i;
352 long initrd_size, kernel_size;
353
354 linux_boot = (kernel_filename != NULL);
355
356 kernel_size = 0;
357 if (linux_boot) {
358 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
359 NULL);
360 if (kernel_size < 0)
361 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
362 RAM_size - KERNEL_LOAD_ADDR);
363 if (kernel_size < 0)
364 kernel_size = load_image_targphys(kernel_filename,
365 KERNEL_LOAD_ADDR,
366 RAM_size - KERNEL_LOAD_ADDR);
367 if (kernel_size < 0) {
368 fprintf(stderr, "qemu: could not load kernel '%s'\n",
369 kernel_filename);
370 exit(1);
371 }
372
373 /* load initrd */
374 initrd_size = 0;
375 if (initrd_filename) {
376 initrd_size = load_image_targphys(initrd_filename,
377 INITRD_LOAD_ADDR,
378 RAM_size - INITRD_LOAD_ADDR);
379 if (initrd_size < 0) {
380 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
381 initrd_filename);
382 exit(1);
383 }
384 }
385 if (initrd_size > 0) {
386 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
387 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
388 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
389 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
390 break;
391 }
392 }
393 }
394 }
395 return kernel_size;
396 }
397
398 static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
399 const char *boot_device,
400 DisplayState *ds, const char *kernel_filename,
401 const char *kernel_cmdline,
402 const char *initrd_filename, const char *cpu_model)
403
404 {
405 CPUState *env, *envs[MAX_CPUS];
406 unsigned int i;
407 void *iommu, *espdma, *ledma, *main_esp, *nvram;
408 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
409 *espdma_irq, *ledma_irq;
410 qemu_irq *esp_reset, *le_reset;
411 qemu_irq *fdc_tc;
412 unsigned long prom_offset, kernel_size;
413 int ret;
414 char buf[1024];
415 BlockDriverState *fd[MAX_FD];
416 int drive_index;
417 void *fw_cfg;
418
419 /* init CPUs */
420 if (!cpu_model)
421 cpu_model = hwdef->default_cpu_model;
422
423 for(i = 0; i < smp_cpus; i++) {
424 env = cpu_init(cpu_model);
425 if (!env) {
426 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
427 exit(1);
428 }
429 cpu_sparc_set_id(env, i);
430 envs[i] = env;
431 if (i == 0) {
432 qemu_register_reset(main_cpu_reset, env);
433 } else {
434 qemu_register_reset(secondary_cpu_reset, env);
435 env->halted = 1;
436 }
437 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
438 env->prom_addr = hwdef->slavio_base;
439 }
440
441 for (i = smp_cpus; i < MAX_CPUS; i++)
442 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
443
444
445 /* allocate RAM */
446 if ((uint64_t)RAM_size > hwdef->max_mem) {
447 fprintf(stderr,
448 "qemu: Too much memory for this machine: %d, maximum %d\n",
449 (unsigned int)(RAM_size / (1024 * 1024)),
450 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
451 exit(1);
452 }
453 cpu_register_physical_memory(0, RAM_size, 0);
454
455 /* load boot prom */
456 prom_offset = RAM_size + hwdef->vram_size;
457 cpu_register_physical_memory(hwdef->slavio_base,
458 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
459 TARGET_PAGE_MASK,
460 prom_offset | IO_MEM_ROM);
461
462 if (bios_name == NULL)
463 bios_name = PROM_FILENAME;
464 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
465 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
466 if (ret < 0 || ret > PROM_SIZE_MAX)
467 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
468 if (ret < 0 || ret > PROM_SIZE_MAX) {
469 fprintf(stderr, "qemu: could not load prom '%s'\n",
470 buf);
471 exit(1);
472 }
473 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
474
475 /* set up devices */
476 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
477 hwdef->intctl_base + 0x10000ULL,
478 &hwdef->intbit_to_level[0],
479 &slavio_irq, &slavio_cpu_irq,
480 cpu_irqs,
481 hwdef->clock_irq);
482
483 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
484 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
485
486 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
487 prom_offset | IO_MEM_ROM);
488 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
489 sizeof(idreg_data));
490 }
491
492 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
493 slavio_irq[hwdef->me_irq]);
494
495 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
496 iommu, &espdma_irq, &esp_reset);
497
498 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
499 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
500 &le_reset);
501
502 if (graphic_depth != 8 && graphic_depth != 24) {
503 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
504 exit (1);
505 }
506 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
507 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
508
509 if (nd_table[0].model == NULL
510 || strcmp(nd_table[0].model, "lance") == 0) {
511 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
512 } else if (strcmp(nd_table[0].model, "?") == 0) {
513 fprintf(stderr, "qemu: Supported NICs: lance\n");
514 exit (1);
515 } else {
516 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
517 exit (1);
518 }
519
520 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
521 hwdef->nvram_size, 8);
522
523 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
524 slavio_cpu_irq, smp_cpus);
525
526 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
527 nographic);
528 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
529 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
530 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
531 serial_hds[1], serial_hds[0]);
532
533 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
534 hwdef->aux1_base, hwdef->aux2_base,
535 slavio_irq[hwdef->me_irq], envs[0],
536 &fdc_tc);
537
538 if (hwdef->fd_base != (target_phys_addr_t)-1) {
539 /* there is zero or one floppy drive */
540 memset(fd, 0, sizeof(fd));
541 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
542 if (drive_index != -1)
543 fd[0] = drives_table[drive_index].bdrv;
544
545 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
546 fdc_tc);
547 }
548
549 if (drive_get_max_bus(IF_SCSI) > 0) {
550 fprintf(stderr, "qemu: too many SCSI bus\n");
551 exit(1);
552 }
553
554 main_esp = esp_init(hwdef->esp_base, 2,
555 espdma_memory_read, espdma_memory_write,
556 espdma, *espdma_irq, esp_reset);
557
558 for (i = 0; i < ESP_MAX_DEVS; i++) {
559 drive_index = drive_get_index(IF_SCSI, 0, i);
560 if (drive_index == -1)
561 continue;
562 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
563 }
564
565 if (hwdef->cs_base != (target_phys_addr_t)-1)
566 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
567
568 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
569 RAM_size);
570
571 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
572 boot_device, RAM_size, kernel_size, graphic_width,
573 graphic_height, graphic_depth, hwdef->nvram_machine_id,
574 "Sun4m");
575
576 if (hwdef->ecc_base != (target_phys_addr_t)-1)
577 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
578 hwdef->ecc_version);
579
580 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
581 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
582 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
583 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
584 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
585 }
586
587 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
588 const char *boot_device,
589 DisplayState *ds, const char *kernel_filename,
590 const char *kernel_cmdline,
591 const char *initrd_filename, const char *cpu_model)
592 {
593 CPUState *env;
594 unsigned int i;
595 void *iommu, *espdma, *ledma, *main_esp, *nvram;
596 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
597 qemu_irq *esp_reset, *le_reset;
598 qemu_irq *fdc_tc;
599 unsigned long prom_offset, kernel_size;
600 int ret;
601 char buf[1024];
602 BlockDriverState *fd[MAX_FD];
603 int drive_index;
604 void *fw_cfg;
605
606 /* init CPU */
607 if (!cpu_model)
608 cpu_model = hwdef->default_cpu_model;
609
610 env = cpu_init(cpu_model);
611 if (!env) {
612 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
613 exit(1);
614 }
615
616 cpu_sparc_set_id(env, 0);
617
618 qemu_register_reset(main_cpu_reset, env);
619 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
620 env->prom_addr = hwdef->slavio_base;
621
622 /* allocate RAM */
623 if ((uint64_t)RAM_size > hwdef->max_mem) {
624 fprintf(stderr,
625 "qemu: Too much memory for this machine: %d, maximum %d\n",
626 (unsigned int)(RAM_size / (1024 * 1024)),
627 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
628 exit(1);
629 }
630 cpu_register_physical_memory(0, RAM_size, 0);
631
632 /* load boot prom */
633 prom_offset = RAM_size + hwdef->vram_size;
634 cpu_register_physical_memory(hwdef->slavio_base,
635 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
636 TARGET_PAGE_MASK,
637 prom_offset | IO_MEM_ROM);
638
639 if (bios_name == NULL)
640 bios_name = PROM_FILENAME;
641 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
642 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
643 if (ret < 0 || ret > PROM_SIZE_MAX)
644 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
645 if (ret < 0 || ret > PROM_SIZE_MAX) {
646 fprintf(stderr, "qemu: could not load prom '%s'\n",
647 buf);
648 exit(1);
649 }
650 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
651
652 /* set up devices */
653 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
654 &slavio_irq, cpu_irqs);
655
656 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
657 slavio_irq[hwdef->me_irq]);
658
659 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
660 iommu, &espdma_irq, &esp_reset);
661
662 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
663 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
664 &le_reset);
665
666 if (graphic_depth != 8 && graphic_depth != 24) {
667 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
668 exit (1);
669 }
670 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
671 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
672
673 if (nd_table[0].model == NULL
674 || strcmp(nd_table[0].model, "lance") == 0) {
675 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
676 } else if (strcmp(nd_table[0].model, "?") == 0) {
677 fprintf(stderr, "qemu: Supported NICs: lance\n");
678 exit (1);
679 } else {
680 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
681 exit (1);
682 }
683
684 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
685 hwdef->nvram_size, 2);
686
687 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
688 nographic);
689 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
690 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
691 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
692 serial_hds[1], serial_hds[0]);
693
694 slavio_misc = slavio_misc_init(0, hwdef->apc_base,
695 hwdef->aux1_base, hwdef->aux2_base,
696 slavio_irq[hwdef->me_irq], env, &fdc_tc);
697
698 if (hwdef->fd_base != (target_phys_addr_t)-1) {
699 /* there is zero or one floppy drive */
700 fd[1] = fd[0] = NULL;
701 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
702 if (drive_index != -1)
703 fd[0] = drives_table[drive_index].bdrv;
704
705 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
706 fdc_tc);
707 }
708
709 if (drive_get_max_bus(IF_SCSI) > 0) {
710 fprintf(stderr, "qemu: too many SCSI bus\n");
711 exit(1);
712 }
713
714 main_esp = esp_init(hwdef->esp_base, 2,
715 espdma_memory_read, espdma_memory_write,
716 espdma, *espdma_irq, esp_reset);
717
718 for (i = 0; i < ESP_MAX_DEVS; i++) {
719 drive_index = drive_get_index(IF_SCSI, 0, i);
720 if (drive_index == -1)
721 continue;
722 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
723 }
724
725 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
726 RAM_size);
727
728 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
729 boot_device, RAM_size, kernel_size, graphic_width,
730 graphic_height, graphic_depth, hwdef->nvram_machine_id,
731 "Sun4c");
732
733 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
734 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
735 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
736 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
737 }
738
739 enum {
740 ss2_id = 0,
741 ss5_id = 32,
742 vger_id,
743 lx_id,
744 ss4_id,
745 scls_id,
746 sbook_id,
747 ss10_id = 64,
748 ss20_id,
749 ss600mp_id,
750 ss1000_id = 96,
751 ss2000_id,
752 };
753
754 static const struct hwdef hwdefs[] = {
755 /* SS-5 */
756 {
757 .iommu_base = 0x10000000,
758 .tcx_base = 0x50000000,
759 .cs_base = 0x6c000000,
760 .slavio_base = 0x70000000,
761 .ms_kb_base = 0x71000000,
762 .serial_base = 0x71100000,
763 .nvram_base = 0x71200000,
764 .fd_base = 0x71400000,
765 .counter_base = 0x71d00000,
766 .intctl_base = 0x71e00000,
767 .idreg_base = 0x78000000,
768 .dma_base = 0x78400000,
769 .esp_base = 0x78800000,
770 .le_base = 0x78c00000,
771 .apc_base = 0x6a000000,
772 .aux1_base = 0x71900000,
773 .aux2_base = 0x71910000,
774 .ecc_base = -1,
775 .sun4c_intctl_base = -1,
776 .sun4c_counter_base = -1,
777 .vram_size = 0x00100000,
778 .nvram_size = 0x2000,
779 .esp_irq = 18,
780 .le_irq = 16,
781 .clock_irq = 7,
782 .clock1_irq = 19,
783 .ms_kb_irq = 14,
784 .ser_irq = 15,
785 .fd_irq = 22,
786 .me_irq = 30,
787 .cs_irq = 5,
788 .nvram_machine_id = 0x80,
789 .machine_id = ss5_id,
790 .iommu_version = 0x05000000,
791 .intbit_to_level = {
792 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
793 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
794 },
795 .max_mem = 0x10000000,
796 .default_cpu_model = "Fujitsu MB86904",
797 },
798 /* SS-10 */
799 {
800 .iommu_base = 0xfe0000000ULL,
801 .tcx_base = 0xe20000000ULL,
802 .cs_base = -1,
803 .slavio_base = 0xff0000000ULL,
804 .ms_kb_base = 0xff1000000ULL,
805 .serial_base = 0xff1100000ULL,
806 .nvram_base = 0xff1200000ULL,
807 .fd_base = 0xff1700000ULL,
808 .counter_base = 0xff1300000ULL,
809 .intctl_base = 0xff1400000ULL,
810 .idreg_base = 0xef0000000ULL,
811 .dma_base = 0xef0400000ULL,
812 .esp_base = 0xef0800000ULL,
813 .le_base = 0xef0c00000ULL,
814 .apc_base = 0xefa000000ULL, // XXX should not exist
815 .aux1_base = 0xff1800000ULL,
816 .aux2_base = 0xff1a01000ULL,
817 .ecc_base = 0xf00000000ULL,
818 .ecc_version = 0x10000000, // version 0, implementation 1
819 .sun4c_intctl_base = -1,
820 .sun4c_counter_base = -1,
821 .vram_size = 0x00100000,
822 .nvram_size = 0x2000,
823 .esp_irq = 18,
824 .le_irq = 16,
825 .clock_irq = 7,
826 .clock1_irq = 19,
827 .ms_kb_irq = 14,
828 .ser_irq = 15,
829 .fd_irq = 22,
830 .me_irq = 30,
831 .cs_irq = -1,
832 .ecc_irq = 28,
833 .nvram_machine_id = 0x72,
834 .machine_id = ss10_id,
835 .iommu_version = 0x03000000,
836 .intbit_to_level = {
837 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
838 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
839 },
840 .max_mem = 0xf00000000ULL,
841 .default_cpu_model = "TI SuperSparc II",
842 },
843 /* SS-600MP */
844 {
845 .iommu_base = 0xfe0000000ULL,
846 .tcx_base = 0xe20000000ULL,
847 .cs_base = -1,
848 .slavio_base = 0xff0000000ULL,
849 .ms_kb_base = 0xff1000000ULL,
850 .serial_base = 0xff1100000ULL,
851 .nvram_base = 0xff1200000ULL,
852 .fd_base = -1,
853 .counter_base = 0xff1300000ULL,
854 .intctl_base = 0xff1400000ULL,
855 .idreg_base = -1,
856 .dma_base = 0xef0081000ULL,
857 .esp_base = 0xef0080000ULL,
858 .le_base = 0xef0060000ULL,
859 .apc_base = 0xefa000000ULL, // XXX should not exist
860 .aux1_base = 0xff1800000ULL,
861 .aux2_base = 0xff1a01000ULL, // XXX should not exist
862 .ecc_base = 0xf00000000ULL,
863 .ecc_version = 0x00000000, // version 0, implementation 0
864 .sun4c_intctl_base = -1,
865 .sun4c_counter_base = -1,
866 .vram_size = 0x00100000,
867 .nvram_size = 0x2000,
868 .esp_irq = 18,
869 .le_irq = 16,
870 .clock_irq = 7,
871 .clock1_irq = 19,
872 .ms_kb_irq = 14,
873 .ser_irq = 15,
874 .fd_irq = 22,
875 .me_irq = 30,
876 .cs_irq = -1,
877 .ecc_irq = 28,
878 .nvram_machine_id = 0x71,
879 .machine_id = ss600mp_id,
880 .iommu_version = 0x01000000,
881 .intbit_to_level = {
882 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
883 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
884 },
885 .max_mem = 0xf00000000ULL,
886 .default_cpu_model = "TI SuperSparc II",
887 },
888 /* SS-20 */
889 {
890 .iommu_base = 0xfe0000000ULL,
891 .tcx_base = 0xe20000000ULL,
892 .cs_base = -1,
893 .slavio_base = 0xff0000000ULL,
894 .ms_kb_base = 0xff1000000ULL,
895 .serial_base = 0xff1100000ULL,
896 .nvram_base = 0xff1200000ULL,
897 .fd_base = 0xff1700000ULL,
898 .counter_base = 0xff1300000ULL,
899 .intctl_base = 0xff1400000ULL,
900 .idreg_base = 0xef0000000ULL,
901 .dma_base = 0xef0400000ULL,
902 .esp_base = 0xef0800000ULL,
903 .le_base = 0xef0c00000ULL,
904 .apc_base = 0xefa000000ULL, // XXX should not exist
905 .aux1_base = 0xff1800000ULL,
906 .aux2_base = 0xff1a01000ULL,
907 .ecc_base = 0xf00000000ULL,
908 .ecc_version = 0x20000000, // version 0, implementation 2
909 .sun4c_intctl_base = -1,
910 .sun4c_counter_base = -1,
911 .vram_size = 0x00100000,
912 .nvram_size = 0x2000,
913 .esp_irq = 18,
914 .le_irq = 16,
915 .clock_irq = 7,
916 .clock1_irq = 19,
917 .ms_kb_irq = 14,
918 .ser_irq = 15,
919 .fd_irq = 22,
920 .me_irq = 30,
921 .cs_irq = -1,
922 .ecc_irq = 28,
923 .nvram_machine_id = 0x72,
924 .machine_id = ss20_id,
925 .iommu_version = 0x13000000,
926 .intbit_to_level = {
927 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
928 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
929 },
930 .max_mem = 0xf00000000ULL,
931 .default_cpu_model = "TI SuperSparc II",
932 },
933 /* SS-2 */
934 {
935 .iommu_base = 0xf8000000,
936 .tcx_base = 0xfe000000,
937 .cs_base = -1,
938 .slavio_base = 0xf6000000,
939 .ms_kb_base = 0xf0000000,
940 .serial_base = 0xf1000000,
941 .nvram_base = 0xf2000000,
942 .fd_base = 0xf7200000,
943 .counter_base = -1,
944 .intctl_base = -1,
945 .dma_base = 0xf8400000,
946 .esp_base = 0xf8800000,
947 .le_base = 0xf8c00000,
948 .apc_base = -1,
949 .aux1_base = 0xf7400003,
950 .aux2_base = -1,
951 .sun4c_intctl_base = 0xf5000000,
952 .sun4c_counter_base = 0xf3000000,
953 .vram_size = 0x00100000,
954 .nvram_size = 0x800,
955 .esp_irq = 2,
956 .le_irq = 3,
957 .clock_irq = 5,
958 .clock1_irq = 7,
959 .ms_kb_irq = 1,
960 .ser_irq = 1,
961 .fd_irq = 1,
962 .me_irq = 1,
963 .cs_irq = -1,
964 .nvram_machine_id = 0x55,
965 .machine_id = ss2_id,
966 .max_mem = 0x10000000,
967 .default_cpu_model = "Cypress CY7C601",
968 },
969 /* Voyager */
970 {
971 .iommu_base = 0x10000000,
972 .tcx_base = 0x50000000,
973 .cs_base = -1,
974 .slavio_base = 0x70000000,
975 .ms_kb_base = 0x71000000,
976 .serial_base = 0x71100000,
977 .nvram_base = 0x71200000,
978 .fd_base = 0x71400000,
979 .counter_base = 0x71d00000,
980 .intctl_base = 0x71e00000,
981 .idreg_base = 0x78000000,
982 .dma_base = 0x78400000,
983 .esp_base = 0x78800000,
984 .le_base = 0x78c00000,
985 .apc_base = 0x71300000, // pmc
986 .aux1_base = 0x71900000,
987 .aux2_base = 0x71910000,
988 .ecc_base = -1,
989 .sun4c_intctl_base = -1,
990 .sun4c_counter_base = -1,
991 .vram_size = 0x00100000,
992 .nvram_size = 0x2000,
993 .esp_irq = 18,
994 .le_irq = 16,
995 .clock_irq = 7,
996 .clock1_irq = 19,
997 .ms_kb_irq = 14,
998 .ser_irq = 15,
999 .fd_irq = 22,
1000 .me_irq = 30,
1001 .cs_irq = -1,
1002 .nvram_machine_id = 0x80,
1003 .machine_id = vger_id,
1004 .iommu_version = 0x05000000,
1005 .intbit_to_level = {
1006 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1007 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1008 },
1009 .max_mem = 0x10000000,
1010 .default_cpu_model = "Fujitsu MB86904",
1011 },
1012 /* LX */
1013 {
1014 .iommu_base = 0x10000000,
1015 .tcx_base = 0x50000000,
1016 .cs_base = -1,
1017 .slavio_base = 0x70000000,
1018 .ms_kb_base = 0x71000000,
1019 .serial_base = 0x71100000,
1020 .nvram_base = 0x71200000,
1021 .fd_base = 0x71400000,
1022 .counter_base = 0x71d00000,
1023 .intctl_base = 0x71e00000,
1024 .idreg_base = 0x78000000,
1025 .dma_base = 0x78400000,
1026 .esp_base = 0x78800000,
1027 .le_base = 0x78c00000,
1028 .apc_base = -1,
1029 .aux1_base = 0x71900000,
1030 .aux2_base = 0x71910000,
1031 .ecc_base = -1,
1032 .sun4c_intctl_base = -1,
1033 .sun4c_counter_base = -1,
1034 .vram_size = 0x00100000,
1035 .nvram_size = 0x2000,
1036 .esp_irq = 18,
1037 .le_irq = 16,
1038 .clock_irq = 7,
1039 .clock1_irq = 19,
1040 .ms_kb_irq = 14,
1041 .ser_irq = 15,
1042 .fd_irq = 22,
1043 .me_irq = 30,
1044 .cs_irq = -1,
1045 .nvram_machine_id = 0x80,
1046 .machine_id = lx_id,
1047 .iommu_version = 0x04000000,
1048 .intbit_to_level = {
1049 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1050 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1051 },
1052 .max_mem = 0x10000000,
1053 .default_cpu_model = "TI MicroSparc I",
1054 },
1055 /* SS-4 */
1056 {
1057 .iommu_base = 0x10000000,
1058 .tcx_base = 0x50000000,
1059 .cs_base = 0x6c000000,
1060 .slavio_base = 0x70000000,
1061 .ms_kb_base = 0x71000000,
1062 .serial_base = 0x71100000,
1063 .nvram_base = 0x71200000,
1064 .fd_base = 0x71400000,
1065 .counter_base = 0x71d00000,
1066 .intctl_base = 0x71e00000,
1067 .idreg_base = 0x78000000,
1068 .dma_base = 0x78400000,
1069 .esp_base = 0x78800000,
1070 .le_base = 0x78c00000,
1071 .apc_base = 0x6a000000,
1072 .aux1_base = 0x71900000,
1073 .aux2_base = 0x71910000,
1074 .ecc_base = -1,
1075 .sun4c_intctl_base = -1,
1076 .sun4c_counter_base = -1,
1077 .vram_size = 0x00100000,
1078 .nvram_size = 0x2000,
1079 .esp_irq = 18,
1080 .le_irq = 16,
1081 .clock_irq = 7,
1082 .clock1_irq = 19,
1083 .ms_kb_irq = 14,
1084 .ser_irq = 15,
1085 .fd_irq = 22,
1086 .me_irq = 30,
1087 .cs_irq = 5,
1088 .nvram_machine_id = 0x80,
1089 .machine_id = ss4_id,
1090 .iommu_version = 0x05000000,
1091 .intbit_to_level = {
1092 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1093 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1094 },
1095 .max_mem = 0x10000000,
1096 .default_cpu_model = "Fujitsu MB86904",
1097 },
1098 /* SPARCClassic */
1099 {
1100 .iommu_base = 0x10000000,
1101 .tcx_base = 0x50000000,
1102 .cs_base = -1,
1103 .slavio_base = 0x70000000,
1104 .ms_kb_base = 0x71000000,
1105 .serial_base = 0x71100000,
1106 .nvram_base = 0x71200000,
1107 .fd_base = 0x71400000,
1108 .counter_base = 0x71d00000,
1109 .intctl_base = 0x71e00000,
1110 .idreg_base = 0x78000000,
1111 .dma_base = 0x78400000,
1112 .esp_base = 0x78800000,
1113 .le_base = 0x78c00000,
1114 .apc_base = 0x6a000000,
1115 .aux1_base = 0x71900000,
1116 .aux2_base = 0x71910000,
1117 .ecc_base = -1,
1118 .sun4c_intctl_base = -1,
1119 .sun4c_counter_base = -1,
1120 .vram_size = 0x00100000,
1121 .nvram_size = 0x2000,
1122 .esp_irq = 18,
1123 .le_irq = 16,
1124 .clock_irq = 7,
1125 .clock1_irq = 19,
1126 .ms_kb_irq = 14,
1127 .ser_irq = 15,
1128 .fd_irq = 22,
1129 .me_irq = 30,
1130 .cs_irq = -1,
1131 .nvram_machine_id = 0x80,
1132 .machine_id = scls_id,
1133 .iommu_version = 0x05000000,
1134 .intbit_to_level = {
1135 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1136 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1137 },
1138 .max_mem = 0x10000000,
1139 .default_cpu_model = "TI MicroSparc I",
1140 },
1141 /* SPARCbook */
1142 {
1143 .iommu_base = 0x10000000,
1144 .tcx_base = 0x50000000, // XXX
1145 .cs_base = -1,
1146 .slavio_base = 0x70000000,
1147 .ms_kb_base = 0x71000000,
1148 .serial_base = 0x71100000,
1149 .nvram_base = 0x71200000,
1150 .fd_base = 0x71400000,
1151 .counter_base = 0x71d00000,
1152 .intctl_base = 0x71e00000,
1153 .idreg_base = 0x78000000,
1154 .dma_base = 0x78400000,
1155 .esp_base = 0x78800000,
1156 .le_base = 0x78c00000,
1157 .apc_base = 0x6a000000,
1158 .aux1_base = 0x71900000,
1159 .aux2_base = 0x71910000,
1160 .ecc_base = -1,
1161 .sun4c_intctl_base = -1,
1162 .sun4c_counter_base = -1,
1163 .vram_size = 0x00100000,
1164 .nvram_size = 0x2000,
1165 .esp_irq = 18,
1166 .le_irq = 16,
1167 .clock_irq = 7,
1168 .clock1_irq = 19,
1169 .ms_kb_irq = 14,
1170 .ser_irq = 15,
1171 .fd_irq = 22,
1172 .me_irq = 30,
1173 .cs_irq = -1,
1174 .nvram_machine_id = 0x80,
1175 .machine_id = sbook_id,
1176 .iommu_version = 0x05000000,
1177 .intbit_to_level = {
1178 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1179 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1180 },
1181 .max_mem = 0x10000000,
1182 .default_cpu_model = "TI MicroSparc I",
1183 },
1184 };
1185
1186 /* SPARCstation 5 hardware initialisation */
1187 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1188 const char *boot_device, DisplayState *ds,
1189 const char *kernel_filename, const char *kernel_cmdline,
1190 const char *initrd_filename, const char *cpu_model)
1191 {
1192 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1193 kernel_cmdline, initrd_filename, cpu_model);
1194 }
1195
1196 /* SPARCstation 10 hardware initialisation */
1197 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1198 const char *boot_device, DisplayState *ds,
1199 const char *kernel_filename, const char *kernel_cmdline,
1200 const char *initrd_filename, const char *cpu_model)
1201 {
1202 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1203 kernel_cmdline, initrd_filename, cpu_model);
1204 }
1205
1206 /* SPARCserver 600MP hardware initialisation */
1207 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1208 const char *boot_device, DisplayState *ds,
1209 const char *kernel_filename,
1210 const char *kernel_cmdline,
1211 const char *initrd_filename, const char *cpu_model)
1212 {
1213 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1214 kernel_cmdline, initrd_filename, cpu_model);
1215 }
1216
1217 /* SPARCstation 20 hardware initialisation */
1218 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1219 const char *boot_device, DisplayState *ds,
1220 const char *kernel_filename, const char *kernel_cmdline,
1221 const char *initrd_filename, const char *cpu_model)
1222 {
1223 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1224 kernel_cmdline, initrd_filename, cpu_model);
1225 }
1226
1227 /* SPARCstation 2 hardware initialisation */
1228 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1229 const char *boot_device, DisplayState *ds,
1230 const char *kernel_filename, const char *kernel_cmdline,
1231 const char *initrd_filename, const char *cpu_model)
1232 {
1233 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1234 kernel_cmdline, initrd_filename, cpu_model);
1235 }
1236
1237 /* SPARCstation Voyager hardware initialisation */
1238 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1239 const char *boot_device, DisplayState *ds,
1240 const char *kernel_filename, const char *kernel_cmdline,
1241 const char *initrd_filename, const char *cpu_model)
1242 {
1243 sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1244 kernel_cmdline, initrd_filename, cpu_model);
1245 }
1246
1247 /* SPARCstation LX hardware initialisation */
1248 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1249 const char *boot_device, DisplayState *ds,
1250 const char *kernel_filename, const char *kernel_cmdline,
1251 const char *initrd_filename, const char *cpu_model)
1252 {
1253 sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1254 kernel_cmdline, initrd_filename, cpu_model);
1255 }
1256
1257 /* SPARCstation 4 hardware initialisation */
1258 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1259 const char *boot_device, DisplayState *ds,
1260 const char *kernel_filename, const char *kernel_cmdline,
1261 const char *initrd_filename, const char *cpu_model)
1262 {
1263 sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1264 kernel_cmdline, initrd_filename, cpu_model);
1265 }
1266
1267 /* SPARCClassic hardware initialisation */
1268 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1269 const char *boot_device, DisplayState *ds,
1270 const char *kernel_filename, const char *kernel_cmdline,
1271 const char *initrd_filename, const char *cpu_model)
1272 {
1273 sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1274 kernel_cmdline, initrd_filename, cpu_model);
1275 }
1276
1277 /* SPARCbook hardware initialisation */
1278 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1279 const char *boot_device, DisplayState *ds,
1280 const char *kernel_filename, const char *kernel_cmdline,
1281 const char *initrd_filename, const char *cpu_model)
1282 {
1283 sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1284 kernel_cmdline, initrd_filename, cpu_model);
1285 }
1286
1287 QEMUMachine ss5_machine = {
1288 .name = "SS-5",
1289 .desc = "Sun4m platform, SPARCstation 5",
1290 .init = ss5_init,
1291 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1292 .nodisk_ok = 1,
1293 .use_scsi = 1,
1294 .max_cpus = 16,
1295 };
1296
1297 QEMUMachine ss10_machine = {
1298 .name = "SS-10",
1299 .desc = "Sun4m platform, SPARCstation 10",
1300 .init = ss10_init,
1301 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1302 .nodisk_ok = 1,
1303 .use_scsi = 1,
1304 .max_cpus = 16,
1305 };
1306
1307 QEMUMachine ss600mp_machine = {
1308 .name = "SS-600MP",
1309 .desc = "Sun4m platform, SPARCserver 600MP",
1310 .init = ss600mp_init,
1311 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1312 .nodisk_ok = 1,
1313 .use_scsi = 1,
1314 .max_cpus = 16,
1315 };
1316
1317 QEMUMachine ss20_machine = {
1318 .name = "SS-20",
1319 .desc = "Sun4m platform, SPARCstation 20",
1320 .init = ss20_init,
1321 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1322 .nodisk_ok = 1,
1323 .use_scsi = 1,
1324 .max_cpus = 16,
1325 };
1326
1327 QEMUMachine ss2_machine = {
1328 .name = "SS-2",
1329 .desc = "Sun4c platform, SPARCstation 2",
1330 .init = ss2_init,
1331 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1332 .nodisk_ok = 1,
1333 .use_scsi = 1,
1334 .max_cpus = 16,
1335 };
1336
1337 QEMUMachine voyager_machine = {
1338 .name = "Voyager",
1339 .desc = "Sun4m platform, SPARCstation Voyager",
1340 .init = vger_init,
1341 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1342 .nodisk_ok = 1,
1343 .use_scsi = 1,
1344 .max_cpus = 16,
1345 };
1346
1347 QEMUMachine ss_lx_machine = {
1348 .name = "LX",
1349 .desc = "Sun4m platform, SPARCstation LX",
1350 .init = ss_lx_init,
1351 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1352 .nodisk_ok = 1,
1353 .use_scsi = 1,
1354 .max_cpus = 16,
1355 };
1356
1357 QEMUMachine ss4_machine = {
1358 .name = "SS-4",
1359 .desc = "Sun4m platform, SPARCstation 4",
1360 .init = ss4_init,
1361 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1362 .nodisk_ok = 1,
1363 .use_scsi = 1,
1364 .max_cpus = 16,
1365 };
1366
1367 QEMUMachine scls_machine = {
1368 .name = "SPARCClassic",
1369 .desc = "Sun4m platform, SPARCClassic",
1370 .init = scls_init,
1371 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1372 .nodisk_ok = 1,
1373 .use_scsi = 1,
1374 .max_cpus = 16,
1375 };
1376
1377 QEMUMachine sbook_machine = {
1378 .name = "SPARCbook",
1379 .desc = "Sun4m platform, SPARCbook",
1380 .init = sbook_init,
1381 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1382 .nodisk_ok = 1,
1383 .use_scsi = 1,
1384 .max_cpus = 16,
1385 };
1386
1387 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1388 /* SS-1000 */
1389 {
1390 .iounit_bases = {
1391 0xfe0200000ULL,
1392 0xfe1200000ULL,
1393 0xfe2200000ULL,
1394 0xfe3200000ULL,
1395 -1,
1396 },
1397 .tcx_base = 0x820000000ULL,
1398 .slavio_base = 0xf00000000ULL,
1399 .ms_kb_base = 0xf00240000ULL,
1400 .serial_base = 0xf00200000ULL,
1401 .nvram_base = 0xf00280000ULL,
1402 .counter_base = 0xf00300000ULL,
1403 .espdma_base = 0x800081000ULL,
1404 .esp_base = 0x800080000ULL,
1405 .ledma_base = 0x800040000ULL,
1406 .le_base = 0x800060000ULL,
1407 .sbi_base = 0xf02800000ULL,
1408 .vram_size = 0x00100000,
1409 .nvram_size = 0x2000,
1410 .esp_irq = 3,
1411 .le_irq = 4,
1412 .clock_irq = 14,
1413 .clock1_irq = 10,
1414 .ms_kb_irq = 12,
1415 .ser_irq = 12,
1416 .nvram_machine_id = 0x80,
1417 .machine_id = ss1000_id,
1418 .iounit_version = 0x03000000,
1419 .max_mem = 0xf00000000ULL,
1420 .default_cpu_model = "TI SuperSparc II",
1421 },
1422 /* SS-2000 */
1423 {
1424 .iounit_bases = {
1425 0xfe0200000ULL,
1426 0xfe1200000ULL,
1427 0xfe2200000ULL,
1428 0xfe3200000ULL,
1429 0xfe4200000ULL,
1430 },
1431 .tcx_base = 0x820000000ULL,
1432 .slavio_base = 0xf00000000ULL,
1433 .ms_kb_base = 0xf00240000ULL,
1434 .serial_base = 0xf00200000ULL,
1435 .nvram_base = 0xf00280000ULL,
1436 .counter_base = 0xf00300000ULL,
1437 .espdma_base = 0x800081000ULL,
1438 .esp_base = 0x800080000ULL,
1439 .ledma_base = 0x800040000ULL,
1440 .le_base = 0x800060000ULL,
1441 .sbi_base = 0xf02800000ULL,
1442 .vram_size = 0x00100000,
1443 .nvram_size = 0x2000,
1444 .esp_irq = 3,
1445 .le_irq = 4,
1446 .clock_irq = 14,
1447 .clock1_irq = 10,
1448 .ms_kb_irq = 12,
1449 .ser_irq = 12,
1450 .nvram_machine_id = 0x80,
1451 .machine_id = ss2000_id,
1452 .iounit_version = 0x03000000,
1453 .max_mem = 0xf00000000ULL,
1454 .default_cpu_model = "TI SuperSparc II",
1455 },
1456 };
1457
1458 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1459 const char *boot_device,
1460 DisplayState *ds, const char *kernel_filename,
1461 const char *kernel_cmdline,
1462 const char *initrd_filename, const char *cpu_model)
1463 {
1464 CPUState *env, *envs[MAX_CPUS];
1465 unsigned int i;
1466 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1467 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1468 *espdma_irq, *ledma_irq;
1469 qemu_irq *esp_reset, *le_reset;
1470 unsigned long prom_offset, kernel_size;
1471 int ret;
1472 char buf[1024];
1473 int drive_index;
1474 void *fw_cfg;
1475
1476 /* init CPUs */
1477 if (!cpu_model)
1478 cpu_model = hwdef->default_cpu_model;
1479
1480 for (i = 0; i < smp_cpus; i++) {
1481 env = cpu_init(cpu_model);
1482 if (!env) {
1483 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1484 exit(1);
1485 }
1486 cpu_sparc_set_id(env, i);
1487 envs[i] = env;
1488 if (i == 0) {
1489 qemu_register_reset(main_cpu_reset, env);
1490 } else {
1491 qemu_register_reset(secondary_cpu_reset, env);
1492 env->halted = 1;
1493 }
1494 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1495 env->prom_addr = hwdef->slavio_base;
1496 }
1497
1498 for (i = smp_cpus; i < MAX_CPUS; i++)
1499 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1500
1501 /* allocate RAM */
1502 if ((uint64_t)RAM_size > hwdef->max_mem) {
1503 fprintf(stderr,
1504 "qemu: Too much memory for this machine: %d, maximum %d\n",
1505 (unsigned int)(RAM_size / (1024 * 1024)),
1506 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1507 exit(1);
1508 }
1509 cpu_register_physical_memory(0, RAM_size, 0);
1510
1511 /* load boot prom */
1512 prom_offset = RAM_size + hwdef->vram_size;
1513 cpu_register_physical_memory(hwdef->slavio_base,
1514 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1515 TARGET_PAGE_MASK,
1516 prom_offset | IO_MEM_ROM);
1517
1518 if (bios_name == NULL)
1519 bios_name = PROM_FILENAME;
1520 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1521 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1522 if (ret < 0 || ret > PROM_SIZE_MAX)
1523 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1524 if (ret < 0 || ret > PROM_SIZE_MAX) {
1525 fprintf(stderr, "qemu: could not load prom '%s'\n",
1526 buf);
1527 exit(1);
1528 }
1529
1530 /* set up devices */
1531 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1532
1533 for (i = 0; i < MAX_IOUNITS; i++)
1534 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1535 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1536 hwdef->iounit_version,
1537 sbi_irq[hwdef->me_irq]);
1538
1539 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1540 iounits[0], &espdma_irq, &esp_reset);
1541
1542 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1543 iounits[0], &ledma_irq, &le_reset);
1544
1545 if (graphic_depth != 8 && graphic_depth != 24) {
1546 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1547 exit (1);
1548 }
1549 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1550 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1551
1552 if (nd_table[0].model == NULL
1553 || strcmp(nd_table[0].model, "lance") == 0) {
1554 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1555 } else if (strcmp(nd_table[0].model, "?") == 0) {
1556 fprintf(stderr, "qemu: Supported NICs: lance\n");
1557 exit (1);
1558 } else {
1559 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1560 exit (1);
1561 }
1562
1563 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1564 hwdef->nvram_size, 8);
1565
1566 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1567 sbi_cpu_irq, smp_cpus);
1568
1569 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1570 nographic);
1571 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1572 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1573 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1574 serial_hds[1], serial_hds[0]);
1575
1576 if (drive_get_max_bus(IF_SCSI) > 0) {
1577 fprintf(stderr, "qemu: too many SCSI bus\n");
1578 exit(1);
1579 }
1580
1581 main_esp = esp_init(hwdef->esp_base, 2,
1582 espdma_memory_read, espdma_memory_write,
1583 espdma, *espdma_irq, esp_reset);
1584
1585 for (i = 0; i < ESP_MAX_DEVS; i++) {
1586 drive_index = drive_get_index(IF_SCSI, 0, i);
1587 if (drive_index == -1)
1588 continue;
1589 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1590 }
1591
1592 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1593 RAM_size);
1594
1595 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1596 boot_device, RAM_size, kernel_size, graphic_width,
1597 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1598 "Sun4d");
1599
1600 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1601 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1602 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1603 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1604 }
1605
1606 /* SPARCserver 1000 hardware initialisation */
1607 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1608 const char *boot_device, DisplayState *ds,
1609 const char *kernel_filename, const char *kernel_cmdline,
1610 const char *initrd_filename, const char *cpu_model)
1611 {
1612 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1613 kernel_cmdline, initrd_filename, cpu_model);
1614 }
1615
1616 /* SPARCcenter 2000 hardware initialisation */
1617 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1618 const char *boot_device, DisplayState *ds,
1619 const char *kernel_filename, const char *kernel_cmdline,
1620 const char *initrd_filename, const char *cpu_model)
1621 {
1622 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1623 kernel_cmdline, initrd_filename, cpu_model);
1624 }
1625
1626 QEMUMachine ss1000_machine = {
1627 .name = "SS-1000",
1628 .desc = "Sun4d platform, SPARCserver 1000",
1629 .init = ss1000_init,
1630 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1631 .nodisk_ok = 1,
1632 .use_scsi = 1,
1633 .max_cpus = 16,
1634 };
1635
1636 QEMUMachine ss2000_machine = {
1637 .name = "SS-2000",
1638 .desc = "Sun4d platform, SPARCcenter 2000",
1639 .init = ss2000_init,
1640 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1641 .nodisk_ok = 1,
1642 .use_scsi = 1,
1643 .max_cpus = 16,
1644 };
jz4740 based target emulation