gdbstub.c

   1 /*
   2  * gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #include "qemu-common.h"
  22 #ifdef CONFIG_USER_ONLY
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <stdarg.h>
  26 #include <string.h>
  27 #include <errno.h>
  28 #include <unistd.h>
  29 #include <fcntl.h>
  30
  31 #include "qemu.h"
  32 #else
  33 #include "qemu-char.h"
  34 #include "sysemu.h"
  35 #include "gdbstub.h"
  36 #endif
  37
  38 #define MAX_PACKET_LENGTH 4096
  39
  40 #include "qemu_socket.h"
  41 #ifdef _WIN32
  42 /* XXX: these constants may be independent of the host ones even for Unix */
  43 #ifndef SIGTRAP
  44 #define SIGTRAP 5
  45 #endif
  46 #ifndef SIGINT
  47 #define SIGINT 2
  48 #endif
  49 #else
  50 #include <signal.h>
  51 #endif
  52
  53 //#define DEBUG_GDB
  54
  55 typedef struct GDBRegisterState {
  56     int base_reg;
  57     int num_regs;
  58     gdb_reg_cb get_reg;
  59     gdb_reg_cb set_reg;
  60     const char *xml;
  61     struct GDBRegisterState *next;
  62 } GDBRegisterState;
  63
  64 enum RSState {
  65     RS_IDLE,
  66     RS_GETLINE,
  67     RS_CHKSUM1,
  68     RS_CHKSUM2,
  69     RS_SYSCALL,
  70 };
  71 typedef struct GDBState {
  72     CPUState *env; /* current CPU */
  73     enum RSState state; /* parsing state */
  74     char line_buf[MAX_PACKET_LENGTH];
  75     int line_buf_index;
  76     int line_csum;
  77     uint8_t last_packet[MAX_PACKET_LENGTH + 4];
  78     int last_packet_len;
  79     int signal;
  80 #ifdef CONFIG_USER_ONLY
  81     int fd;
  82     int running_state;
  83 #else
  84     CharDriverState *chr;
  85 #endif
  86 } GDBState;
  87
  88 /* By default use no IRQs and no timers while single stepping so as to
  89  * make single stepping like an ICE HW step.
  90  */
  91 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
  92
  93 /* This is an ugly hack to cope with both new and old gdb.
  94    If gdb sends qXfer:features:read then assume we're talking to a newish
  95    gdb that understands target descriptions.  */
  96 static int gdb_has_xml;
  97
  98 #ifdef CONFIG_USER_ONLY
  99 /* XXX: This is not thread safe.  Do we care?  */
 100 static int gdbserver_fd = -1;
 101
 102 /* XXX: remove this hack.  */
 103 static GDBState gdbserver_state;
 104
 105 static int get_char(GDBState *s)
 106 {
 107     uint8_t ch;
 108     int ret;
 109
 110     for(;;) {
 111         ret = recv(s->fd, &ch, 1, 0);
 112         if (ret < 0) {
 113             if (errno == ECONNRESET)
 114                 s->fd = -1;
 115             if (errno != EINTR && errno != EAGAIN)
 116                 return -1;
 117         } else if (ret == 0) {
 118             close(s->fd);
 119             s->fd = -1;
 120             return -1;
 121         } else {
 122             break;
 123         }
 124     }
 125     return ch;
 126 }
 127 #endif
 128
 129 /* GDB stub state for use by semihosting syscalls.  */
 130 static GDBState *gdb_syscall_state;
 131 static gdb_syscall_complete_cb gdb_current_syscall_cb;
 132
 133 enum {
 134     GDB_SYS_UNKNOWN,
 135     GDB_SYS_ENABLED,
 136     GDB_SYS_DISABLED,
 137 } gdb_syscall_mode;
 138
 139 /* If gdb is connected when the first semihosting syscall occurs then use
 140    remote gdb syscalls.  Otherwise use native file IO.  */
 141 int use_gdb_syscalls(void)
 142 {
 143     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
 144         gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
 145                                               : GDB_SYS_DISABLED);
 146     }
 147     return gdb_syscall_mode == GDB_SYS_ENABLED;
 148 }
 149
 150 /* Resume execution.  */
 151 static inline void gdb_continue(GDBState *s)
 152 {
 153 #ifdef CONFIG_USER_ONLY
 154     s->running_state = 1;
 155 #else
 156     vm_start();
 157 #endif
 158 }
 159
 160 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
 161 {
 162 #ifdef CONFIG_USER_ONLY
 163     int ret;
 164
 165     while (len > 0) {
 166         ret = send(s->fd, buf, len, 0);
 167         if (ret < 0) {
 168             if (errno != EINTR && errno != EAGAIN)
 169                 return;
 170         } else {
 171             buf += ret;
 172             len -= ret;
 173         }
 174     }
 175 #else
 176     qemu_chr_write(s->chr, buf, len);
 177 #endif
 178 }
 179
 180 static inline int fromhex(int v)
 181 {
 182     if (v >= '0' && v <= '9')
 183         return v - '0';
 184     else if (v >= 'A' && v <= 'F')
 185         return v - 'A' + 10;
 186     else if (v >= 'a' && v <= 'f')
 187         return v - 'a' + 10;
 188     else
 189         return 0;
 190 }
 191
 192 static inline int tohex(int v)
 193 {
 194     if (v < 10)
 195         return v + '0';
 196     else
 197         return v - 10 + 'a';
 198 }
 199
 200 static void memtohex(char *buf, const uint8_t *mem, int len)
 201 {
 202     int i, c;
 203     char *q;
 204     q = buf;
 205     for(i = 0; i < len; i++) {
 206         c = mem[i];
 207         *q++ = tohex(c >> 4);
 208         *q++ = tohex(c & 0xf);
 209     }
 210     *q = '\0';
 211 }
 212
 213 static void hextomem(uint8_t *mem, const char *buf, int len)
 214 {
 215     int i;
 216
 217     for(i = 0; i < len; i++) {
 218         mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
 219         buf += 2;
 220     }
 221 }
 222
 223 /* return -1 if error, 0 if OK */
 224 static int put_packet_binary(GDBState *s, const char *buf, int len)
 225 {
 226     int csum, i;
 227     uint8_t *p;
 228
 229     for(;;) {
 230         p = s->last_packet;
 231         *(p++) = '$';
 232         memcpy(p, buf, len);
 233         p += len;
 234         csum = 0;
 235         for(i = 0; i < len; i++) {
 236             csum += buf[i];
 237         }
 238         *(p++) = '#';
 239         *(p++) = tohex((csum >> 4) & 0xf);
 240         *(p++) = tohex((csum) & 0xf);
 241
 242         s->last_packet_len = p - s->last_packet;
 243         put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
 244
 245 #ifdef CONFIG_USER_ONLY
 246         i = get_char(s);
 247         if (i < 0)
 248             return -1;
 249         if (i == '+')
 250             break;
 251 #else
 252         break;
 253 #endif
 254     }
 255     return 0;
 256 }
 257
 258 /* return -1 if error, 0 if OK */
 259 static int put_packet(GDBState *s, const char *buf)
 260 {
 261 #ifdef DEBUG_GDB
 262     printf("reply='%s'\n", buf);
 263 #endif
 264
 265     return put_packet_binary(s, buf, strlen(buf));
 266 }
 267
 268 /* The GDB remote protocol transfers values in target byte order.  This means
 269    we can use the raw memory access routines to access the value buffer.
 270    Conveniently, these also handle the case where the buffer is mis-aligned.
 271  */
 272 #define GET_REG8(val) do { \
 273     stb_p(mem_buf, val); \
 274     return 1; \
 275     } while(0)
 276 #define GET_REG16(val) do { \
 277     stw_p(mem_buf, val); \
 278     return 2; \
 279     } while(0)
 280 #define GET_REG32(val) do { \
 281     stl_p(mem_buf, val); \
 282     return 4; \
 283     } while(0)
 284 #define GET_REG64(val) do { \
 285     stq_p(mem_buf, val); \
 286     return 8; \
 287     } while(0)
 288
 289 #if TARGET_LONG_BITS == 64
 290 #define GET_REGL(val) GET_REG64(val)
 291 #define ldtul_p(addr) ldq_p(addr)
 292 #else
 293 #define GET_REGL(val) GET_REG32(val)
 294 #define ldtul_p(addr) ldl_p(addr)
 295 #endif
 296
 297 #if defined(TARGET_I386)
 298
 299 #ifdef TARGET_X86_64
 300 static const int gpr_map[16] = {
 301     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
 302     8, 9, 10, 11, 12, 13, 14, 15
 303 };
 304 #else
 305 static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
 306 #endif
 307
 308 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
 309
 310 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 311 {
 312     if (n < CPU_NB_REGS) {
 313         GET_REGL(env->regs[gpr_map[n]]);
 314     } else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) {
 315         /* FIXME: byteswap float values.  */
 316 #ifdef USE_X86LDOUBLE
 317         memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10);
 318 #else
 319         memset(mem_buf, 0, 10);
 320 #endif
 321         return 10;
 322     } else if (n >= CPU_NB_REGS + 24) {
 323         n -= CPU_NB_REGS + 24;
 324         if (n < CPU_NB_REGS) {
 325             stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
 326             stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
 327             return 16;
 328         } else if (n == CPU_NB_REGS) {
 329             GET_REG32(env->mxcsr);
 330         }
 331     } else {
 332         n -= CPU_NB_REGS;
 333         switch (n) {
 334         case 0: GET_REGL(env->eip);
 335         case 1: GET_REG32(env->eflags);
 336         case 2: GET_REG32(env->segs[R_CS].selector);
 337         case 3: GET_REG32(env->segs[R_SS].selector);
 338         case 4: GET_REG32(env->segs[R_DS].selector);
 339         case 5: GET_REG32(env->segs[R_ES].selector);
 340         case 6: GET_REG32(env->segs[R_FS].selector);
 341         case 7: GET_REG32(env->segs[R_GS].selector);
 342         /* 8...15 x87 regs.  */
 343         case 16: GET_REG32(env->fpuc);
 344         case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11);
 345         case 18: GET_REG32(0); /* ftag */
 346         case 19: GET_REG32(0); /* fiseg */
 347         case 20: GET_REG32(0); /* fioff */
 348         case 21: GET_REG32(0); /* foseg */
 349         case 22: GET_REG32(0); /* fooff */
 350         case 23: GET_REG32(0); /* fop */
 351         /* 24+ xmm regs.  */
 352         }
 353     }
 354     return 0;
 355 }
 356
 357 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)
 358 {
 359     uint32_t tmp;
 360
 361     if (i < CPU_NB_REGS) {
 362         env->regs[gpr_map[i]] = ldtul_p(mem_buf);
 363         return sizeof(target_ulong);
 364     } else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) {
 365         i -= CPU_NB_REGS + 8;
 366 #ifdef USE_X86LDOUBLE
 367         memcpy(&env->fpregs[i], mem_buf, 10);
 368 #endif
 369         return 10;
 370     } else if (i >= CPU_NB_REGS + 24) {
 371         i -= CPU_NB_REGS + 24;
 372         if (i < CPU_NB_REGS) {
 373             env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf);
 374             env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8);
 375             return 16;
 376         } else if (i == CPU_NB_REGS) {
 377             env->mxcsr = ldl_p(mem_buf);
 378             return 4;
 379         }
 380     } else {
 381         i -= CPU_NB_REGS;
 382         switch (i) {
 383         case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong);
 384         case 1: env->eflags = ldl_p(mem_buf); return 4;
 385 #if defined(CONFIG_USER_ONLY)
 386 #define LOAD_SEG(index, sreg)\
 387             tmp = ldl_p(mem_buf);\
 388             if (tmp != env->segs[sreg].selector)\
 389                 cpu_x86_load_seg(env, sreg, tmp);
 390 #else
 391 /* FIXME: Honor segment registers.  Needs to avoid raising an exception
 392    when the selector is invalid.  */
 393 #define LOAD_SEG(index, sreg) do {} while(0)
 394 #endif
 395         case 2: LOAD_SEG(10, R_CS); return 4;
 396         case 3: LOAD_SEG(11, R_SS); return 4;
 397         case 4: LOAD_SEG(12, R_DS); return 4;
 398         case 5: LOAD_SEG(13, R_ES); return 4;
 399         case 6: LOAD_SEG(14, R_FS); return 4;
 400         case 7: LOAD_SEG(15, R_GS); return 4;
 401         /* 8...15 x87 regs.  */
 402         case 16: env->fpuc = ldl_p(mem_buf); return 4;
 403         case 17:
 404                  tmp = ldl_p(mem_buf);
 405                  env->fpstt = (tmp >> 11) & 7;
 406                  env->fpus = tmp & ~0x3800;
 407                  return 4;
 408         case 18: /* ftag */ return 4;
 409         case 19: /* fiseg */ return 4;
 410         case 20: /* fioff */ return 4;
 411         case 21: /* foseg */ return 4;
 412         case 22: /* fooff */ return 4;
 413         case 23: /* fop */ return 4;
 414         /* 24+ xmm regs.  */
 415         }
 416     }
 417     /* Unrecognised register.  */
 418     return 0;
 419 }
 420
 421 #elif defined (TARGET_PPC)
 422
 423 #define NUM_CORE_REGS 71
 424
 425 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 426 {
 427     if (n < 32) {
 428         /* gprs */
 429         GET_REGL(env->gpr[n]);
 430     } else if (n < 64) {
 431         /* fprs */
 432         stfq_p(mem_buf, env->fpr[n]);
 433         return 8;
 434     } else {
 435         switch (n) {
 436         case 64: GET_REGL(env->nip);
 437         case 65: GET_REGL(env->msr);
 438         case 66:
 439             {
 440                 uint32_t cr = 0;
 441                 int i;
 442                 for (i = 0; i < 8; i++)
 443                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
 444                 GET_REG32(cr);
 445             }
 446         case 67: GET_REGL(env->lr);
 447         case 68: GET_REGL(env->ctr);
 448         case 69: GET_REGL(env->xer);
 449         case 70: GET_REG32(0); /* fpscr */
 450         }
 451     }
 452     return 0;
 453 }
 454
 455 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 456 {
 457     if (n < 32) {
 458         /* gprs */
 459         env->gpr[n] = ldtul_p(mem_buf);
 460         return sizeof(target_ulong);
 461     } else if (n < 64) {
 462         /* fprs */
 463         env->fpr[n] = ldfq_p(mem_buf);
 464         return 8;
 465     } else {
 466         switch (n) {
 467         case 64:
 468             env->nip = ldtul_p(mem_buf);
 469             return sizeof(target_ulong);
 470         case 65:
 471             ppc_store_msr(env, ldtul_p(mem_buf));
 472             return sizeof(target_ulong);
 473         case 66:
 474             {
 475                 uint32_t cr = ldl_p(mem_buf);
 476                 int i;
 477                 for (i = 0; i < 8; i++)
 478                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
 479                 return 4;
 480             }
 481         case 67:
 482             env->lr = ldtul_p(mem_buf);
 483             return sizeof(target_ulong);
 484         case 68:
 485             env->ctr = ldtul_p(mem_buf);
 486             return sizeof(target_ulong);
 487         case 69:
 488             env->xer = ldtul_p(mem_buf);
 489             return sizeof(target_ulong);
 490         case 70:
 491             /* fpscr */
 492             return 4;
 493         }
 494     }
 495     return 0;
 496 }
 497
 498 #elif defined (TARGET_SPARC)
 499
 500 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
 501 #define NUM_CORE_REGS 86
 502 #else
 503 #define NUM_CORE_REGS 73
 504 #endif
 505
 506 #ifdef TARGET_ABI32
 507 #define GET_REGA(val) GET_REG32(val)
 508 #else
 509 #define GET_REGA(val) GET_REGL(val)
 510 #endif
 511
 512 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 513 {
 514     if (n < 8) {
 515         /* g0..g7 */
 516         GET_REGA(env->gregs[n]);
 517     }
 518     if (n < 32) {
 519         /* register window */
 520         GET_REGA(env->regwptr[n - 8]);
 521     }
 522 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 523     if (n < 64) {
 524         /* fprs */
 525         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 526     }
 527     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 528     switch (n) {
 529     case 64: GET_REGA(env->y);
 530     case 65: GET_REGA(GET_PSR(env));
 531     case 66: GET_REGA(env->wim);
 532     case 67: GET_REGA(env->tbr);
 533     case 68: GET_REGA(env->pc);
 534     case 69: GET_REGA(env->npc);
 535     case 70: GET_REGA(env->fsr);
 536     case 71: GET_REGA(0); /* csr */
 537     case 72: GET_REGA(0);
 538     }
 539 #else
 540     if (n < 64) {
 541         /* f0-f31 */
 542         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 543     }
 544     if (n < 80) {
 545         /* f32-f62 (double width, even numbers only) */
 546         uint64_t val;
 547
 548         val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
 549         val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
 550         GET_REG64(val);
 551     }
 552     switch (n) {
 553     case 80: GET_REGL(env->pc);
 554     case 81: GET_REGL(env->npc);
 555     case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
 556                            ((env->asi & 0xff) << 24) |
 557                            ((env->pstate & 0xfff) << 8) |
 558                            GET_CWP64(env));
 559     case 83: GET_REGL(env->fsr);
 560     case 84: GET_REGL(env->fprs);
 561     case 85: GET_REGL(env->y);
 562     }
 563 #endif
 564     return 0;
 565 }
 566
 567 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 568 {
 569 #if defined(TARGET_ABI32)
 570     abi_ulong tmp;
 571
 572     tmp = ldl_p(mem_buf);
 573 #else
 574     target_ulong tmp;
 575
 576     tmp = ldtul_p(mem_buf);
 577 #endif
 578
 579     if (n < 8) {
 580         /* g0..g7 */
 581         env->gregs[n] = tmp;
 582     } else if (n < 32) {
 583         /* register window */
 584         env->regwptr[n - 8] = tmp;
 585     }
 586 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 587     else if (n < 64) {
 588         /* fprs */
 589         *((uint32_t *)&env->fpr[n - 32]) = tmp;
 590     } else {
 591         /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 592         switch (n) {
 593         case 64: env->y = tmp; break;
 594         case 65: PUT_PSR(env, tmp); break;
 595         case 66: env->wim = tmp; break;
 596         case 67: env->tbr = tmp; break;
 597         case 68: env->pc = tmp; break;
 598         case 69: env->npc = tmp; break;
 599         case 70: env->fsr = tmp; break;
 600         default: return 0;
 601         }
 602     }
 603     return 4;
 604 #else
 605     else if (n < 64) {
 606         /* f0-f31 */
 607         env->fpr[n] = ldfl_p(mem_buf);
 608         return 4;
 609     } else if (n < 80) {
 610         /* f32-f62 (double width, even numbers only) */
 611         *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
 612         *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
 613     } else {
 614         switch (n) {
 615         case 80: env->pc = tmp; break;
 616         case 81: env->npc = tmp; break;
 617         case 82:
 618             PUT_CCR(env, tmp >> 32);
 619             env->asi = (tmp >> 24) & 0xff;
 620             env->pstate = (tmp >> 8) & 0xfff;
 621             PUT_CWP64(env, tmp & 0xff);
 622             break;
 623         case 83: env->fsr = tmp; break;
 624         case 84: env->fprs = tmp; break;
 625         case 85: env->y = tmp; break;
 626         default: return 0;
 627         }
 628     }
 629     return 8;
 630 #endif
 631 }
 632 #elif defined (TARGET_ARM)
 633
 634 /* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
 635    whatever the target description contains.  Due to a historical mishap
 636    the FPA registers appear in between core integer regs and the CPSR.
 637    We hack round this by giving the FPA regs zero size when talking to a
 638    newer gdb.  */
 639 #define NUM_CORE_REGS 26
 640 #define GDB_CORE_XML "arm-core.xml"
 641
 642 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 643 {
 644     if (n < 16) {
 645         /* Core integer register.  */
 646         GET_REG32(env->regs[n]);
 647     }
 648     if (n < 24) {
 649         /* FPA registers.  */
 650         if (gdb_has_xml)
 651             return 0;
 652         memset(mem_buf, 0, 12);
 653         return 12;
 654     }
 655     switch (n) {
 656     case 24:
 657         /* FPA status register.  */
 658         if (gdb_has_xml)
 659             return 0;
 660         GET_REG32(0);
 661     case 25:
 662         /* CPSR */
 663         GET_REG32(cpsr_read(env));
 664     }
 665     /* Unknown register.  */
 666     return 0;
 667 }
 668
 669 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 670 {
 671     uint32_t tmp;
 672
 673     tmp = ldl_p(mem_buf);
 674
 675     /* Mask out low bit of PC to workaround gdb bugs.  This will probably
 676        cause problems if we ever implement the Jazelle DBX extensions.  */
 677     if (n == 15)
 678         tmp &= ~1;
 679
 680     if (n < 16) {
 681         /* Core integer register.  */
 682         env->regs[n] = tmp;
 683         return 4;
 684     }
 685     if (n < 24) { /* 16-23 */
 686         /* FPA registers (ignored).  */
 687         if (gdb_has_xml)
 688             return 0;
 689         return 12;
 690     }
 691     switch (n) {
 692     case 24:
 693         /* FPA status register (ignored).  */
 694         if (gdb_has_xml)
 695             return 0;
 696         return 4;
 697     case 25:
 698         /* CPSR */
 699         cpsr_write (env, tmp, 0xffffffff);
 700         return 4;
 701     }
 702     /* Unknown register.  */
 703     return 0;
 704 }
 705
 706 #elif defined (TARGET_M68K)
 707
 708 #define NUM_CORE_REGS 18
 709
 710 #define GDB_CORE_XML "cf-core.xml"
 711
 712 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 713 {
 714     if (n < 8) {
 715         /* D0-D7 */
 716         GET_REG32(env->dregs[n]);
 717     } else if (n < 16) {
 718         /* A0-A7 */
 719         GET_REG32(env->aregs[n - 8]);
 720     } else {
 721         switch (n) {
 722         case 16: GET_REG32(env->sr);
 723         case 17: GET_REG32(env->pc);
 724         }
 725     }
 726     /* FP registers not included here because they vary between
 727        ColdFire and m68k.  Use XML bits for these.  */
 728     return 0;
 729 }
 730
 731 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 732 {
 733     uint32_t tmp;
 734
 735     tmp = ldl_p(mem_buf);
 736
 737     if (n < 8) {
 738         /* D0-D7 */
 739         env->dregs[n] = tmp;
 740     } else if (n < 8) {
 741         /* A0-A7 */
 742         env->aregs[n - 8] = tmp;
 743     } else {
 744         switch (n) {
 745         case 16: env->sr = tmp; break;
 746         case 17: env->pc = tmp; break;
 747         default: return 0;
 748         }
 749     }
 750     return 4;
 751 }
 752 #elif defined (TARGET_MIPS)
 753
 754 #define NUM_CORE_REGS 73
 755
 756 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 757 {
 758     if (n < 32) {
 759         GET_REGL(env->active_tc.gpr[n]);
 760     }
 761     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
 762         if (n >= 38 && n < 70) {
 763             if (env->CP0_Status & (1 << CP0St_FR))
 764                 GET_REGL(env->active_fpu.fpr[n - 38].d);
 765             else
 766                 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
 767         }
 768         switch (n) {
 769         case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
 770         case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
 771         }
 772     }
 773     switch (n) {
 774     case 32: GET_REGL((int32_t)env->CP0_Status);
 775     case 33: GET_REGL(env->active_tc.LO[0]);
 776     case 34: GET_REGL(env->active_tc.HI[0]);
 777     case 35: GET_REGL(env->CP0_BadVAddr);
 778     case 36: GET_REGL((int32_t)env->CP0_Cause);
 779     case 37: GET_REGL(env->active_tc.PC);
 780     case 72: GET_REGL(0); /* fp */
 781     case 89: GET_REGL((int32_t)env->CP0_PRid);
 782     }
 783     if (n >= 73 && n <= 88) {
 784         /* 16 embedded regs.  */
 785         GET_REGL(0);
 786     }
 787
 788     return 0;
 789 }
 790
 791 /* convert MIPS rounding mode in FCR31 to IEEE library */
 792 static unsigned int ieee_rm[] =
 793   {
 794     float_round_nearest_even,
 795     float_round_to_zero,
 796     float_round_up,
 797     float_round_down
 798   };
 799 #define RESTORE_ROUNDING_MODE \
 800     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
 801
 802 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 803 {
 804     target_ulong tmp;
 805
 806     tmp = ldtul_p(mem_buf);
 807
 808     if (n < 32) {
 809         env->active_tc.gpr[n] = tmp;
 810         return sizeof(target_ulong);
 811     }
 812     if (env->CP0_Config1 & (1 << CP0C1_FP)
 813             && n >= 38 && n < 73) {
 814         if (n < 70) {
 815             if (env->CP0_Status & (1 << CP0St_FR))
 816               env->active_fpu.fpr[n - 38].d = tmp;
 817             else
 818               env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
 819         }
 820         switch (n) {
 821         case 70:
 822             env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
 823             /* set rounding mode */
 824             RESTORE_ROUNDING_MODE;
 825 #ifndef CONFIG_SOFTFLOAT
 826             /* no floating point exception for native float */
 827             SET_FP_ENABLE(env->active_fpu.fcr31, 0);
 828 #endif
 829             break;
 830         case 71: env->active_fpu.fcr0 = tmp; break;
 831         }
 832         return sizeof(target_ulong);
 833     }
 834     switch (n) {
 835     case 32: env->CP0_Status = tmp; break;
 836     case 33: env->active_tc.LO[0] = tmp; break;
 837     case 34: env->active_tc.HI[0] = tmp; break;
 838     case 35: env->CP0_BadVAddr = tmp; break;
 839     case 36: env->CP0_Cause = tmp; break;
 840     case 37: env->active_tc.PC = tmp; break;
 841     case 72: /* fp, ignored */ break;
 842     default:
 843         if (n > 89)
 844             return 0;
 845         /* Other registers are readonly.  Ignore writes.  */
 846         break;
 847     }
 848
 849     return sizeof(target_ulong);
 850 }
 851 #elif defined (TARGET_SH4)
 852
 853 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
 854 /* FIXME: We should use XML for this.  */
 855
 856 #define NUM_CORE_REGS 59
 857
 858 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 859 {
 860     if (n < 8) {
 861         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
 862             GET_REGL(env->gregs[n + 16]);
 863         } else {
 864             GET_REGL(env->gregs[n]);
 865         }
 866     } else if (n < 16) {
 867         GET_REGL(env->gregs[n - 8]);
 868     } else if (n >= 25 && n < 41) {
 869         GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
 870     } else if (n >= 43 && n < 51) {
 871         GET_REGL(env->gregs[n - 43]);
 872     } else if (n >= 51 && n < 59) {
 873         GET_REGL(env->gregs[n - (51 - 16)]);
 874     }
 875     switch (n) {
 876     case 16: GET_REGL(env->pc);
 877     case 17: GET_REGL(env->pr);
 878     case 18: GET_REGL(env->gbr);
 879     case 19: GET_REGL(env->vbr);
 880     case 20: GET_REGL(env->mach);
 881     case 21: GET_REGL(env->macl);
 882     case 22: GET_REGL(env->sr);
 883     case 23: GET_REGL(env->fpul);
 884     case 24: GET_REGL(env->fpscr);
 885     case 41: GET_REGL(env->ssr);
 886     case 42: GET_REGL(env->spc);
 887     }
 888
 889     return 0;
 890 }
 891
 892 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 893 {
 894     uint32_t tmp;
 895
 896     tmp = ldl_p(mem_buf);
 897
 898     if (n < 8) {
 899         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
 900             env->gregs[n + 16] = tmp;
 901         } else {
 902             env->gregs[n] = tmp;
 903         }
 904         return 4;
 905     } else if (n < 16) {
 906         env->gregs[n - 8] = tmp;
 907         return 4;
 908     } else if (n >= 25 && n < 41) {
 909         env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
 910     } else if (n >= 43 && n < 51) {
 911         env->gregs[n - 43] = tmp;
 912         return 4;
 913     } else if (n >= 51 && n < 59) {
 914         env->gregs[n - (51 - 16)] = tmp;
 915         return 4;
 916     }
 917     switch (n) {
 918     case 16: env->pc = tmp;
 919     case 17: env->pr = tmp;
 920     case 18: env->gbr = tmp;
 921     case 19: env->vbr = tmp;
 922     case 20: env->mach = tmp;
 923     case 21: env->macl = tmp;
 924     case 22: env->sr = tmp;
 925     case 23: env->fpul = tmp;
 926     case 24: env->fpscr = tmp;
 927     case 41: env->ssr = tmp;
 928     case 42: env->spc = tmp;
 929     default: return 0;
 930     }
 931
 932     return 4;
 933 }
 934 #elif defined (TARGET_CRIS)
 935
 936 #define NUM_CORE_REGS 49
 937
 938 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 939 {
 940     uint8_t srs;
 941
 942     srs = env->pregs[PR_SRS];
 943     if (n < 16) {
 944         GET_REG32(env->regs[n]);
 945     }
 946
 947     if (n >= 21 && n < 32) {
 948         GET_REG32(env->pregs[n - 16]);
 949     }
 950     if (n >= 33 && n < 49) {
 951         GET_REG32(env->sregs[srs][n - 33]);
 952     }
 953     switch (n) {
 954     case 16: GET_REG8(env->pregs[0]);
 955     case 17: GET_REG8(env->pregs[1]);
 956     case 18: GET_REG32(env->pregs[2]);
 957     case 19: GET_REG8(srs);
 958     case 20: GET_REG16(env->pregs[4]);
 959     case 32: GET_REG32(env->pc);
 960     }
 961
 962     return 0;
 963 }
 964
 965 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 966 {
 967     uint32_t tmp;
 968
 969     if (n > 49)
 970         return 0;
 971
 972     tmp = ldl_p(mem_buf);
 973
 974     if (n < 16) {
 975         env->regs[n] = tmp;
 976     }
 977
 978     if (n >= 21 && n < 32) {
 979         env->pregs[n - 16] = tmp;
 980     }
 981
 982     /* FIXME: Should support function regs be writable?  */
 983     switch (n) {
 984     case 16: return 1;
 985     case 17: return 1;
 986     case 18: env->pregs[PR_PID] = tmp; break;
 987     case 19: return 1;
 988     case 20: return 2;
 989     case 32: env->pc = tmp; break;
 990     }
 991
 992     return 4;
 993 }
 994 #else
 995
 996 #define NUM_CORE_REGS 0
 997
 998 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 999 {
1000     return 0;
1001 }
1002
1003 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1004 {
1005     return 0;
1006 }
1007
1008 #endif
1009
1010 static int num_g_regs = NUM_CORE_REGS;
1011
1012 #ifdef GDB_CORE_XML
1013 /* Encode data using the encoding for 'x' packets.  */
1014 static int memtox(char *buf, const char *mem, int len)
1015 {
1016     char *p = buf;
1017     char c;
1018
1019     while (len--) {
1020         c = *(mem++);
1021         switch (c) {
1022         case '#': case '$': case '*': case '}':
1023             *(p++) = '}';
1024             *(p++) = c ^ 0x20;
1025             break;
1026         default:
1027             *(p++) = c;
1028             break;
1029         }
1030     }
1031     return p - buf;
1032 }
1033
1034 const char *get_feature_xml(CPUState *env, const char *p, const char **newp)
1035 {
1036     extern const char *const xml_builtin[][2];
1037     size_t len;
1038     int i;
1039     const char *name;
1040     static char target_xml[1024];
1041
1042     len = 0;
1043     while (p[len] && p[len] != ':')
1044         len++;
1045     *newp = p + len;
1046
1047     name = NULL;
1048     if (strncmp(p, "target.xml", len) == 0) {
1049         /* Generate the XML description for this CPU.  */
1050         if (!target_xml[0]) {
1051             GDBRegisterState *r;
1052
1053             sprintf(target_xml,
1054                     "<?xml version=\"1.0\"?>"
1055                     "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1056                     "<target>"
1057                     "<xi:include href=\"%s\"/>",
1058                     GDB_CORE_XML);
1059
1060             for (r = env->gdb_regs; r; r = r->next) {
1061                 strcat(target_xml, "<xi:include href=\"");
1062                 strcat(target_xml, r->xml);
1063                 strcat(target_xml, "\"/>");
1064             }
1065             strcat(target_xml, "</target>");
1066         }
1067         return target_xml;
1068     }
1069     for (i = 0; ; i++) {
1070         name = xml_builtin[i][0];
1071         if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1072             break;
1073     }
1074     return name ? xml_builtin[i][1] : NULL;
1075 }
1076 #endif
1077
1078 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1079 {
1080     GDBRegisterState *r;
1081
1082     if (reg < NUM_CORE_REGS)
1083         return cpu_gdb_read_register(env, mem_buf, reg);
1084
1085     for (r = env->gdb_regs; r; r = r->next) {
1086         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1087             return r->get_reg(env, mem_buf, reg - r->base_reg);
1088         }
1089     }
1090     return 0;
1091 }
1092
1093 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1094 {
1095     GDBRegisterState *r;
1096
1097     if (reg < NUM_CORE_REGS)
1098         return cpu_gdb_write_register(env, mem_buf, reg);
1099
1100     for (r = env->gdb_regs; r; r = r->next) {
1101         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1102             return r->set_reg(env, mem_buf, reg - r->base_reg);
1103         }
1104     }
1105     return 0;
1106 }
1107
1108 /* Register a supplemental set of CPU registers.  If g_pos is nonzero it
1109    specifies the first register number and these registers are included in
1110    a standard "g" packet.  Direction is relative to gdb, i.e. get_reg is
1111    gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1112  */
1113
1114 void gdb_register_coprocessor(CPUState * env,
1115                              gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1116                              int num_regs, const char *xml, int g_pos)
1117 {
1118     GDBRegisterState *s;
1119     GDBRegisterState **p;
1120     static int last_reg = NUM_CORE_REGS;
1121
1122     s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1123     s->base_reg = last_reg;
1124     s->num_regs = num_regs;
1125     s->get_reg = get_reg;
1126     s->set_reg = set_reg;
1127     s->xml = xml;
1128     p = &env->gdb_regs;
1129     while (*p) {
1130         /* Check for duplicates.  */
1131         if (strcmp((*p)->xml, xml) == 0)
1132             return;
1133         p = &(*p)->next;
1134     }
1135     /* Add to end of list.  */
1136     last_reg += num_regs;
1137     *p = s;
1138     if (g_pos) {
1139         if (g_pos != s->base_reg) {
1140             fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1141                     "Expected %d got %d\n", xml, g_pos, s->base_reg);
1142         } else {
1143             num_g_regs = last_reg;
1144         }
1145     }
1146 }
1147
1148 static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
1149 {
1150     const char *p;
1151     int ch, reg_size, type;
1152     char buf[MAX_PACKET_LENGTH];
1153     uint8_t mem_buf[MAX_PACKET_LENGTH];
1154     uint8_t *registers;
1155     target_ulong addr, len;
1156
1157 #ifdef DEBUG_GDB
1158     printf("command='%s'\n", line_buf);
1159 #endif
1160     p = line_buf;
1161     ch = *p++;
1162     switch(ch) {
1163     case '?':
1164         /* TODO: Make this return the correct value for user-mode.  */
1165         snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
1166         put_packet(s, buf);
1167         /* Remove all the breakpoints when this query is issued,
1168          * because gdb is doing and initial connect and the state
1169          * should be cleaned up.
1170          */
1171         cpu_breakpoint_remove_all(env);
1172         cpu_watchpoint_remove_all(env);
1173         break;
1174     case 'c':
1175         if (*p != '\0') {
1176             addr = strtoull(p, (char **)&p, 16);
1177 #if defined(TARGET_I386)
1178             env->eip = addr;
1179 #elif defined (TARGET_PPC)
1180             env->nip = addr;
1181 #elif defined (TARGET_SPARC)
1182             env->pc = addr;
1183             env->npc = addr + 4;
1184 #elif defined (TARGET_ARM)
1185             env->regs[15] = addr;
1186 #elif defined (TARGET_SH4)
1187             env->pc = addr;
1188 #elif defined (TARGET_MIPS)
1189             env->active_tc.PC = addr;
1190 #elif defined (TARGET_CRIS)
1191             env->pc = addr;
1192 #endif
1193         }
1194         gdb_continue(s);
1195         return RS_IDLE;
1196     case 'C':
1197         s->signal = strtoul(p, (char **)&p, 16);
1198         gdb_continue(s);
1199         return RS_IDLE;
1200     case 'k':
1201         /* Kill the target */
1202         fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1203         exit(0);
1204     case 'D':
1205         /* Detach packet */
1206         cpu_breakpoint_remove_all(env);
1207         cpu_watchpoint_remove_all(env);
1208         gdb_continue(s);
1209         put_packet(s, "OK");
1210         break;
1211     case 's':
1212         if (*p != '\0') {
1213             addr = strtoull(p, (char **)&p, 16);
1214 #if defined(TARGET_I386)
1215             env->eip = addr;
1216 #elif defined (TARGET_PPC)
1217             env->nip = addr;
1218 #elif defined (TARGET_SPARC)
1219             env->pc = addr;
1220             env->npc = addr + 4;
1221 #elif defined (TARGET_ARM)
1222             env->regs[15] = addr;
1223 #elif defined (TARGET_SH4)
1224             env->pc = addr;
1225 #elif defined (TARGET_MIPS)
1226             env->active_tc.PC = addr;
1227 #elif defined (TARGET_CRIS)
1228             env->pc = addr;
1229 #endif
1230         }
1231         cpu_single_step(env, sstep_flags);
1232         gdb_continue(s);
1233         return RS_IDLE;
1234     case 'F':
1235         {
1236             target_ulong ret;
1237             target_ulong err;
1238
1239             ret = strtoull(p, (char **)&p, 16);
1240             if (*p == ',') {
1241                 p++;
1242                 err = strtoull(p, (char **)&p, 16);
1243             } else {
1244                 err = 0;
1245             }
1246             if (*p == ',')
1247                 p++;
1248             type = *p;
1249             if (gdb_current_syscall_cb)
1250                 gdb_current_syscall_cb(s->env, ret, err);
1251             if (type == 'C') {
1252                 put_packet(s, "T02");
1253             } else {
1254                 gdb_continue(s);
1255             }
1256         }
1257         break;
1258     case 'g':
1259         len = 0;
1260         for (addr = 0; addr < num_g_regs; addr++) {
1261             reg_size = gdb_read_register(env, mem_buf + len, addr);
1262             len += reg_size;
1263         }
1264         memtohex(buf, mem_buf, len);
1265         put_packet(s, buf);
1266         break;
1267     case 'G':
1268         registers = mem_buf;
1269         len = strlen(p) / 2;
1270         hextomem((uint8_t *)registers, p, len);
1271         for (addr = 0; addr < num_g_regs && len > 0; addr++) {
1272             reg_size = gdb_write_register(env, registers, addr);
1273             len -= reg_size;
1274             registers += reg_size;
1275         }
1276         put_packet(s, "OK");
1277         break;
1278     case 'm':
1279         addr = strtoull(p, (char **)&p, 16);
1280         if (*p == ',')
1281             p++;
1282         len = strtoull(p, NULL, 16);
1283         if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
1284             put_packet (s, "E14");
1285         } else {
1286             memtohex(buf, mem_buf, len);
1287             put_packet(s, buf);
1288         }
1289         break;
1290     case 'M':
1291         addr = strtoull(p, (char **)&p, 16);
1292         if (*p == ',')
1293             p++;
1294         len = strtoull(p, (char **)&p, 16);
1295         if (*p == ':')
1296             p++;
1297         hextomem(mem_buf, p, len);
1298         if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
1299             put_packet(s, "E14");
1300         else
1301             put_packet(s, "OK");
1302         break;
1303     case 'p':
1304         /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1305            This works, but can be very slow.  Anything new enough to
1306            understand XML also knows how to use this properly.  */
1307         if (!gdb_has_xml)
1308             goto unknown_command;
1309         addr = strtoull(p, (char **)&p, 16);
1310         reg_size = gdb_read_register(env, mem_buf, addr);
1311         if (reg_size) {
1312             memtohex(buf, mem_buf, reg_size);
1313             put_packet(s, buf);
1314         } else {
1315             put_packet(s, "E14");
1316         }
1317         break;
1318     case 'P':
1319         if (!gdb_has_xml)
1320             goto unknown_command;
1321         addr = strtoull(p, (char **)&p, 16);
1322         if (*p == '=')
1323             p++;
1324         reg_size = strlen(p) / 2;
1325         hextomem(mem_buf, p, reg_size);
1326         gdb_write_register(env, mem_buf, addr);
1327         put_packet(s, "OK");
1328         break;
1329     case 'Z':
1330         type = strtoul(p, (char **)&p, 16);
1331         if (*p == ',')
1332             p++;
1333         addr = strtoull(p, (char **)&p, 16);
1334         if (*p == ',')
1335             p++;
1336         len = strtoull(p, (char **)&p, 16);
1337         switch (type) {
1338         case 0:
1339         case 1:
1340             if (cpu_breakpoint_insert(env, addr) < 0)
1341                 goto breakpoint_error;
1342             put_packet(s, "OK");
1343             break;
1344 #ifndef CONFIG_USER_ONLY
1345         case 2:
1346             type = PAGE_WRITE;
1347             goto insert_watchpoint;
1348         case 3:
1349             type = PAGE_READ;
1350             goto insert_watchpoint;
1351         case 4:
1352             type = PAGE_READ | PAGE_WRITE;
1353         insert_watchpoint:
1354             if (cpu_watchpoint_insert(env, addr, type) < 0)
1355                 goto breakpoint_error;
1356             put_packet(s, "OK");
1357             break;
1358 #endif
1359         default:
1360             put_packet(s, "");
1361             break;
1362         }
1363         break;
1364     breakpoint_error:
1365         put_packet(s, "E22");
1366         break;
1367
1368     case 'z':
1369         type = strtoul(p, (char **)&p, 16);
1370         if (*p == ',')
1371             p++;
1372         addr = strtoull(p, (char **)&p, 16);
1373         if (*p == ',')
1374             p++;
1375         len = strtoull(p, (char **)&p, 16);
1376         if (type == 0 || type == 1) {
1377             cpu_breakpoint_remove(env, addr);
1378             put_packet(s, "OK");
1379 #ifndef CONFIG_USER_ONLY
1380         } else if (type >= 2 || type <= 4) {
1381             cpu_watchpoint_remove(env, addr);
1382             put_packet(s, "OK");
1383 #endif
1384         } else {
1385             put_packet(s, "");
1386         }
1387         break;
1388     case 'q':
1389     case 'Q':
1390         /* parse any 'q' packets here */
1391         if (!strcmp(p,"qemu.sstepbits")) {
1392             /* Query Breakpoint bit definitions */
1393             snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1394                      SSTEP_ENABLE,
1395                      SSTEP_NOIRQ,
1396                      SSTEP_NOTIMER);
1397             put_packet(s, buf);
1398             break;
1399         } else if (strncmp(p,"qemu.sstep",10) == 0) {
1400             /* Display or change the sstep_flags */
1401             p += 10;
1402             if (*p != '=') {
1403                 /* Display current setting */
1404                 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
1405                 put_packet(s, buf);
1406                 break;
1407             }
1408             p++;
1409             type = strtoul(p, (char **)&p, 16);
1410             sstep_flags = type;
1411             put_packet(s, "OK");
1412             break;
1413         }
1414 #ifdef CONFIG_LINUX_USER
1415         else if (strncmp(p, "Offsets", 7) == 0) {
1416             TaskState *ts = env->opaque;
1417
1418             snprintf(buf, sizeof(buf),
1419                      "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1420                      ";Bss=" TARGET_ABI_FMT_lx,
1421                      ts->info->code_offset,
1422                      ts->info->data_offset,
1423                      ts->info->data_offset);
1424             put_packet(s, buf);
1425             break;
1426         }
1427 #endif
1428         if (strncmp(p, "Supported", 9) == 0) {
1429             sprintf(buf, "PacketSize=%x", MAX_PACKET_LENGTH);
1430 #ifdef GDB_CORE_XML
1431             strcat(buf, ";qXfer:features:read+");
1432 #endif
1433             put_packet(s, buf);
1434             break;
1435         }
1436 #ifdef GDB_CORE_XML
1437         if (strncmp(p, "Xfer:features:read:", 19) == 0) {
1438             const char *xml;
1439             target_ulong total_len;
1440
1441             gdb_has_xml = 1;
1442             p += 19;
1443             xml = get_feature_xml(env, p, &p);
1444             if (!xml) {
1445                 sprintf(buf, "E00");
1446                 put_packet(s, buf);
1447                 break;
1448             }
1449
1450             if (*p == ':')
1451                 p++;
1452             addr = strtoul(p, (char **)&p, 16);
1453             if (*p == ',')
1454                 p++;
1455             len = strtoul(p, (char **)&p, 16);
1456
1457             total_len = strlen(xml);
1458             if (addr > total_len) {
1459                 sprintf(buf, "E00");
1460                 put_packet(s, buf);
1461                 break;
1462             }
1463             if (len > (MAX_PACKET_LENGTH - 5) / 2)
1464                 len = (MAX_PACKET_LENGTH - 5) / 2;
1465             if (len < total_len - addr) {
1466                 buf[0] = 'm';
1467                 len = memtox(buf + 1, xml + addr, len);
1468             } else {
1469                 buf[0] = 'l';
1470                 len = memtox(buf + 1, xml + addr, total_len - addr);
1471             }
1472             put_packet_binary(s, buf, len + 1);
1473             break;
1474         }
1475 #endif
1476         /* Unrecognised 'q' command.  */
1477         goto unknown_command;
1478
1479     default:
1480     unknown_command:
1481         /* put empty packet */
1482         buf[0] = '\0';
1483         put_packet(s, buf);
1484         break;
1485     }
1486     return RS_IDLE;
1487 }
1488
1489 extern void tb_flush(CPUState *env);
1490
1491 #ifndef CONFIG_USER_ONLY
1492 static void gdb_vm_stopped(void *opaque, int reason)
1493 {
1494     GDBState *s = opaque;
1495     char buf[256];
1496     int ret;
1497
1498     if (s->state == RS_SYSCALL)
1499         return;
1500
1501     /* disable single step if it was enable */
1502     cpu_single_step(s->env, 0);
1503
1504     if (reason == EXCP_DEBUG) {
1505         if (s->env->watchpoint_hit) {
1506             snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1507                      SIGTRAP,
1508                      s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1509             put_packet(s, buf);
1510             s->env->watchpoint_hit = 0;
1511             return;
1512         }
1513         tb_flush(s->env);
1514         ret = SIGTRAP;
1515     } else if (reason == EXCP_INTERRUPT) {
1516         ret = SIGINT;
1517     } else {
1518         ret = 0;
1519     }
1520     snprintf(buf, sizeof(buf), "S%02x", ret);
1521     put_packet(s, buf);
1522 }
1523 #endif
1524
1525 /* Send a gdb syscall request.
1526    This accepts limited printf-style format specifiers, specifically:
1527     %x  - target_ulong argument printed in hex.
1528     %lx - 64-bit argument printed in hex.
1529     %s  - string pointer (target_ulong) and length (int) pair.  */
1530 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
1531 {
1532     va_list va;
1533     char buf[256];
1534     char *p;
1535     target_ulong addr;
1536     uint64_t i64;
1537     GDBState *s;
1538
1539     s = gdb_syscall_state;
1540     if (!s)
1541         return;
1542     gdb_current_syscall_cb = cb;
1543     s->state = RS_SYSCALL;
1544 #ifndef CONFIG_USER_ONLY
1545     vm_stop(EXCP_DEBUG);
1546 #endif
1547     s->state = RS_IDLE;
1548     va_start(va, fmt);
1549     p = buf;
1550     *(p++) = 'F';
1551     while (*fmt) {
1552         if (*fmt == '%') {
1553             fmt++;
1554             switch (*fmt++) {
1555             case 'x':
1556                 addr = va_arg(va, target_ulong);
1557                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
1558                 break;
1559             case 'l':
1560                 if (*(fmt++) != 'x')
1561                     goto bad_format;
1562                 i64 = va_arg(va, uint64_t);
1563                 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
1564                 break;
1565             case 's':
1566                 addr = va_arg(va, target_ulong);
1567                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
1568                               addr, va_arg(va, int));
1569                 break;
1570             default:
1571             bad_format:
1572                 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1573                         fmt - 1);
1574                 break;
1575             }
1576         } else {
1577             *(p++) = *(fmt++);
1578         }
1579     }
1580     *p = 0;
1581     va_end(va);
1582     put_packet(s, buf);
1583 #ifdef CONFIG_USER_ONLY
1584     gdb_handlesig(s->env, 0);
1585 #else
1586     cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1587 #endif
1588 }
1589
1590 static void gdb_read_byte(GDBState *s, int ch)
1591 {
1592     CPUState *env = s->env;
1593     int i, csum;
1594     uint8_t reply;
1595
1596 #ifndef CONFIG_USER_ONLY
1597     if (s->last_packet_len) {
1598         /* Waiting for a response to the last packet.  If we see the start
1599            of a new command then abandon the previous response.  */
1600         if (ch == '-') {
1601 #ifdef DEBUG_GDB
1602             printf("Got NACK, retransmitting\n");
1603 #endif
1604             put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
1605         }
1606 #ifdef DEBUG_GDB
1607         else if (ch == '+')
1608             printf("Got ACK\n");
1609         else
1610             printf("Got '%c' when expecting ACK/NACK\n", ch);
1611 #endif
1612         if (ch == '+' || ch == '$')
1613             s->last_packet_len = 0;
1614         if (ch != '$')
1615             return;
1616     }
1617     if (vm_running) {
1618         /* when the CPU is running, we cannot do anything except stop
1619            it when receiving a char */
1620         vm_stop(EXCP_INTERRUPT);
1621     } else
1622 #endif
1623     {
1624         switch(s->state) {
1625         case RS_IDLE:
1626             if (ch == '$') {
1627                 s->line_buf_index = 0;
1628                 s->state = RS_GETLINE;
1629             }
1630             break;
1631         case RS_GETLINE:
1632             if (ch == '#') {
1633             s->state = RS_CHKSUM1;
1634             } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1635                 s->state = RS_IDLE;
1636             } else {
1637             s->line_buf[s->line_buf_index++] = ch;
1638             }
1639             break;
1640         case RS_CHKSUM1:
1641             s->line_buf[s->line_buf_index] = '\0';
1642             s->line_csum = fromhex(ch) << 4;
1643             s->state = RS_CHKSUM2;
1644             break;
1645         case RS_CHKSUM2:
1646             s->line_csum |= fromhex(ch);
1647             csum = 0;
1648             for(i = 0; i < s->line_buf_index; i++) {
1649                 csum += s->line_buf[i];
1650             }
1651             if (s->line_csum != (csum & 0xff)) {
1652                 reply = '-';
1653                 put_buffer(s, &reply, 1);
1654                 s->state = RS_IDLE;
1655             } else {
1656                 reply = '+';
1657                 put_buffer(s, &reply, 1);
1658                 s->state = gdb_handle_packet(s, env, s->line_buf);
1659             }
1660             break;
1661         default:
1662             abort();
1663         }
1664     }
1665 }
1666
1667 #ifdef CONFIG_USER_ONLY
1668 int
1669 gdb_handlesig (CPUState *env, int sig)
1670 {
1671   GDBState *s;
1672   char buf[256];
1673   int n;
1674
1675   s = &gdbserver_state;
1676   if (gdbserver_fd < 0 || s->fd < 0)
1677     return sig;
1678
1679   /* disable single step if it was enabled */
1680   cpu_single_step(env, 0);
1681   tb_flush(env);
1682
1683   if (sig != 0)
1684     {
1685       snprintf(buf, sizeof(buf), "S%02x", sig);
1686       put_packet(s, buf);
1687     }
1688   /* put_packet() might have detected that the peer terminated the
1689      connection.  */
1690   if (s->fd < 0)
1691       return sig;
1692
1693   sig = 0;
1694   s->state = RS_IDLE;
1695   s->running_state = 0;
1696   while (s->running_state == 0) {
1697       n = read (s->fd, buf, 256);
1698       if (n > 0)
1699         {
1700           int i;
1701
1702           for (i = 0; i < n; i++)
1703             gdb_read_byte (s, buf[i]);
1704         }
1705       else if (n == 0 || errno != EAGAIN)
1706         {
1707           /* XXX: Connection closed.  Should probably wait for annother
1708              connection before continuing.  */
1709           return sig;
1710         }
1711   }
1712   sig = s->signal;
1713   s->signal = 0;
1714   return sig;
1715 }
1716
1717 /* Tell the remote gdb that the process has exited.  */
1718 void gdb_exit(CPUState *env, int code)
1719 {
1720   GDBState *s;
1721   char buf[4];
1722
1723   s = &gdbserver_state;
1724   if (gdbserver_fd < 0 || s->fd < 0)
1725     return;
1726
1727   snprintf(buf, sizeof(buf), "W%02x", code);
1728   put_packet(s, buf);
1729 }
1730
1731
1732 static void gdb_accept(void *opaque)
1733 {
1734     GDBState *s;
1735     struct sockaddr_in sockaddr;
1736     socklen_t len;
1737     int val, fd;
1738
1739     for(;;) {
1740         len = sizeof(sockaddr);
1741         fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1742         if (fd < 0 && errno != EINTR) {
1743             perror("accept");
1744             return;
1745         } else if (fd >= 0) {
1746             break;
1747         }
1748     }
1749
1750     /* set short latency */
1751     val = 1;
1752     setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
1753
1754     s = &gdbserver_state;
1755     memset (s, 0, sizeof (GDBState));
1756     s->env = first_cpu; /* XXX: allow to change CPU */
1757     s->fd = fd;
1758     gdb_has_xml = 0;
1759
1760     gdb_syscall_state = s;
1761
1762     fcntl(fd, F_SETFL, O_NONBLOCK);
1763 }
1764
1765 static int gdbserver_open(int port)
1766 {
1767     struct sockaddr_in sockaddr;
1768     int fd, val, ret;
1769
1770     fd = socket(PF_INET, SOCK_STREAM, 0);
1771     if (fd < 0) {
1772         perror("socket");
1773         return -1;
1774     }
1775
1776     /* allow fast reuse */
1777     val = 1;
1778     setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
1779
1780     sockaddr.sin_family = AF_INET;
1781     sockaddr.sin_port = htons(port);
1782     sockaddr.sin_addr.s_addr = 0;
1783     ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1784     if (ret < 0) {
1785         perror("bind");
1786         return -1;
1787     }
1788     ret = listen(fd, 0);
1789     if (ret < 0) {
1790         perror("listen");
1791         return -1;
1792     }
1793     return fd;
1794 }
1795
1796 int gdbserver_start(int port)
1797 {
1798     gdbserver_fd = gdbserver_open(port);
1799     if (gdbserver_fd < 0)
1800         return -1;
1801     /* accept connections */
1802     gdb_accept (NULL);
1803     return 0;
1804 }
1805 #else
1806 static int gdb_chr_can_receive(void *opaque)
1807 {
1808   /* We can handle an arbitrarily large amount of data.
1809    Pick the maximum packet size, which is as good as anything.  */
1810   return MAX_PACKET_LENGTH;
1811 }
1812
1813 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
1814 {
1815     GDBState *s = opaque;
1816     int i;
1817
1818     for (i = 0; i < size; i++) {
1819         gdb_read_byte(s, buf[i]);
1820     }
1821 }
1822
1823 static void gdb_chr_event(void *opaque, int event)
1824 {
1825     switch (event) {
1826     case CHR_EVENT_RESET:
1827         vm_stop(EXCP_INTERRUPT);
1828         gdb_syscall_state = opaque;
1829         gdb_has_xml = 0;
1830         break;
1831     default:
1832         break;
1833     }
1834 }
1835
1836 int gdbserver_start(const char *port)
1837 {
1838     GDBState *s;
1839     char gdbstub_port_name[128];
1840     int port_num;
1841     char *p;
1842     CharDriverState *chr;
1843
1844     if (!port || !*port)
1845       return -1;
1846
1847     port_num = strtol(port, &p, 10);
1848     if (*p == 0) {
1849         /* A numeric value is interpreted as a port number.  */
1850         snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1851                  "tcp::%d,nowait,nodelay,server", port_num);
1852         port = gdbstub_port_name;
1853     }
1854
1855     chr = qemu_chr_open(port);
1856     if (!chr)
1857         return -1;
1858
1859     s = qemu_mallocz(sizeof(GDBState));
1860     if (!s) {
1861         return -1;
1862     }
1863     s->env = first_cpu; /* XXX: allow to change CPU */
1864     s->chr = chr;
1865     qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
1866                           gdb_chr_event, s);
1867     qemu_add_vm_stop_handler(gdb_vm_stopped, s);
1868     return 0;
1869 }
1870 #endif