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configure: switch to CONFIG_SOFTFLOAT for PPC
[qemu/qemu-JZ.git] / target-ppc / op_helper.c
blob7cd589a1edda67841dd2a5eb7d60ab6a7f1cc0c4
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22 #include "helper.h"
23
24 #include "helper_regs.h"
25
26 //#define DEBUG_OP
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
29
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
32
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
34 {
35 #if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37 #endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
41 }
42
43 void helper_raise_exception (uint32_t exception)
44 {
45 helper_raise_exception_err(exception, 0);
46 }
47
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
51 {
52 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
60 }
61
62 void helper_store_cr (target_ulong val, uint32_t mask)
63 {
64 int i, sh;
65
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
67 if (mask & (1 << sh))
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
69 }
70 }
71
72 /*****************************************************************************/
73 /* SPR accesses */
74 void helper_load_dump_spr (uint32_t sprn)
75 {
76 if (loglevel != 0) {
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
80 }
81
82 void helper_store_dump_spr (uint32_t sprn)
83 {
84 if (loglevel != 0) {
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
87 }
88 }
89
90 target_ulong helper_load_tbl (void)
91 {
92 return cpu_ppc_load_tbl(env);
93 }
94
95 target_ulong helper_load_tbu (void)
96 {
97 return cpu_ppc_load_tbu(env);
98 }
99
100 target_ulong helper_load_atbl (void)
101 {
102 return cpu_ppc_load_atbl(env);
103 }
104
105 target_ulong helper_load_atbu (void)
106 {
107 return cpu_ppc_load_atbu(env);
108 }
109
110 target_ulong helper_load_601_rtcl (void)
111 {
112 return cpu_ppc601_load_rtcl(env);
113 }
114
115 target_ulong helper_load_601_rtcu (void)
116 {
117 return cpu_ppc601_load_rtcu(env);
118 }
119
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
123 {
124 ppc_store_asr(env, val);
125 }
126 #endif
127
128 void helper_store_sdr1 (target_ulong val)
129 {
130 ppc_store_sdr1(env, val);
131 }
132
133 void helper_store_tbl (target_ulong val)
134 {
135 cpu_ppc_store_tbl(env, val);
136 }
137
138 void helper_store_tbu (target_ulong val)
139 {
140 cpu_ppc_store_tbu(env, val);
141 }
142
143 void helper_store_atbl (target_ulong val)
144 {
145 cpu_ppc_store_atbl(env, val);
146 }
147
148 void helper_store_atbu (target_ulong val)
149 {
150 cpu_ppc_store_atbu(env, val);
151 }
152
153 void helper_store_601_rtcl (target_ulong val)
154 {
155 cpu_ppc601_store_rtcl(env, val);
156 }
157
158 void helper_store_601_rtcu (target_ulong val)
159 {
160 cpu_ppc601_store_rtcu(env, val);
161 }
162
163 target_ulong helper_load_decr (void)
164 {
165 return cpu_ppc_load_decr(env);
166 }
167
168 void helper_store_decr (target_ulong val)
169 {
170 cpu_ppc_store_decr(env, val);
171 }
172
173 void helper_store_hid0_601 (target_ulong val)
174 {
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
188 }
189 env->spr[SPR_HID0] = (uint32_t)val;
190 }
191
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
193 {
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199 }
200
201 target_ulong helper_load_40x_pit (void)
202 {
203 return load_40x_pit(env);
204 }
205
206 void helper_store_40x_pit (target_ulong val)
207 {
208 store_40x_pit(env, val);
209 }
210
211 void helper_store_40x_dbcr0 (target_ulong val)
212 {
213 store_40x_dbcr0(env, val);
214 }
215
216 void helper_store_40x_sler (target_ulong val)
217 {
218 store_40x_sler(env, val);
219 }
220
221 void helper_store_booke_tcr (target_ulong val)
222 {
223 store_booke_tcr(env, val);
224 }
225
226 void helper_store_booke_tsr (target_ulong val)
227 {
228 store_booke_tsr(env, val);
229 }
230
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
232 {
233 ppc_store_ibatu(env, nr, val);
234 }
235
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
237 {
238 ppc_store_ibatl(env, nr, val);
239 }
240
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
242 {
243 ppc_store_dbatu(env, nr, val);
244 }
245
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
247 {
248 ppc_store_dbatl(env, nr, val);
249 }
250
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
252 {
253 ppc_store_ibatl_601(env, nr, val);
254 }
255
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
257 {
258 ppc_store_ibatu_601(env, nr, val);
259 }
260 #endif
261
262 /*****************************************************************************/
263 /* Memory load and stores */
264
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
266 {
267 #if defined(TARGET_PPC64)
268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
270 else
271 #endif
272 return addr + arg;
273 }
274
275 void helper_lmw (target_ulong addr, uint32_t reg)
276 {
277 for (; reg < 32; reg++) {
278 if (msr_le)
279 env->gpr[reg] = bswap32(ldl(addr));
280 else
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
283 }
284 }
285
286 void helper_stmw (target_ulong addr, uint32_t reg)
287 {
288 for (; reg < 32; reg++) {
289 if (msr_le)
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
291 else
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
294 }
295 }
296
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298 {
299 int sh;
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
310 }
311 }
312 }
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319 {
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330 }
331
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333 {
334 int sh;
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
339 }
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
344 }
345 }
346
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
348 {
349 addr &= ~(dcache_line_size - 1);
350 int i;
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
352 stl(addr + i , 0);
353 }
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
356 }
357
358 void helper_dcbz(target_ulong addr)
359 {
360 do_dcbz(addr, env->dcache_line_size);
361 }
362
363 void helper_dcbz_970(target_ulong addr)
364 {
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
366 do_dcbz(addr, 32);
367 else
368 do_dcbz(addr, env->dcache_line_size);
369 }
370
371 void helper_icbi(target_ulong addr)
372 {
373 uint32_t tmp;
374
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
380 */
381 tmp = ldl(addr);
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
383 }
384
385 // XXX: to be tested
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
387 {
388 int i, c, d;
389 d = 24;
390 for (i = 0; i < xer_bc; i++) {
391 c = ldub(addr);
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
396 }
397 if (unlikely(c == xer_cmp))
398 break;
399 if (likely(d != 0)) {
400 d -= 8;
401 } else {
402 d = 24;
403 reg++;
404 reg = reg & 0x1F;
405 }
406 }
407 return i;
408 }
409
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
413
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
416 {
417 uint64_t tl, th;
418
419 muls64(&tl, &th, arg1, arg2);
420 return th;
421 }
422
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
425 {
426 uint64_t tl, th;
427
428 mulu64(&tl, &th, arg1, arg2);
429 return th;
430 }
431
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
433 {
434 int64_t th;
435 uint64_t tl;
436
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
441 } else {
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
443 }
444 return (int64_t)tl;
445 }
446 #endif
447
448 target_ulong helper_cntlzw (target_ulong t)
449 {
450 return clz32(t);
451 }
452
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
455 {
456 return clz64(t);
457 }
458 #endif
459
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
462 {
463 int32_t ret;
464
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
467 shift &= 0x1f;
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
471 } else {
472 env->xer |= (1 << XER_CA);
473 }
474 } else {
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
477 }
478 } else {
479 ret = (int32_t)value >> 31;
480 if (ret) {
481 env->xer |= (1 << XER_CA);
482 } else {
483 env->xer &= ~(1 << XER_CA);
484 }
485 }
486 return (target_long)ret;
487 }
488
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
491 {
492 int64_t ret;
493
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
496 shift &= 0x3f;
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
500 } else {
501 env->xer |= (1 << XER_CA);
502 }
503 } else {
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
506 }
507 } else {
508 ret = (int64_t)value >> 63;
509 if (ret) {
510 env->xer |= (1 << XER_CA);
511 } else {
512 env->xer &= ~(1 << XER_CA);
513 }
514 }
515 return ret;
516 }
517 #endif
518
519 target_ulong helper_popcntb (target_ulong val)
520 {
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
524 return val;
525 }
526
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
529 {
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
533 return val;
534 }
535 #endif
536
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
540 {
541 CPU_FloatU f;
542 CPU_DoubleU d;
543 f.l = arg;
544 d.d = float32_to_float64(f.f, &env->fp_status);
545 return d.ll;
546 }
547
548 uint32_t helper_float64_to_float32(uint64_t arg)
549 {
550 CPU_FloatU f;
551 CPU_DoubleU d;
552 d.ll = arg;
553 f.f = float64_to_float32(d.d, &env->fp_status);
554 return f.l;
555 }
556
557 static always_inline int fpisneg (float64 d)
558 {
559 CPU_DoubleU u;
560
561 u.d = d;
562
563 return u.ll >> 63 != 0;
564 }
565
566 static always_inline int isden (float64 d)
567 {
568 CPU_DoubleU u;
569
570 u.d = d;
571
572 return ((u.ll >> 52) & 0x7FF) == 0;
573 }
574
575 static always_inline int iszero (float64 d)
576 {
577 CPU_DoubleU u;
578
579 u.d = d;
580
581 return (u.ll & ~0x8000000000000000ULL) == 0;
582 }
583
584 static always_inline int isinfinity (float64 d)
585 {
586 CPU_DoubleU u;
587
588 u.d = d;
589
590 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
591 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
592 }
593
594 #ifdef CONFIG_SOFTFLOAT
595 static always_inline int isfinite (float64 d)
596 {
597 CPU_DoubleU u;
598
599 u.d = d;
600
601 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
602 }
603
604 static always_inline int isnormal (float64 d)
605 {
606 CPU_DoubleU u;
607
608 u.d = d;
609
610 uint32_t exp = (u.ll >> 52) & 0x7FF;
611 return ((0 < exp) && (exp < 0x7FF));
612 }
613 #endif
614
615 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
616 {
617 CPU_DoubleU farg;
618 int isneg;
619 int ret;
620 farg.ll = arg;
621 isneg = fpisneg(farg.d);
622 if (unlikely(float64_is_nan(farg.d))) {
623 if (float64_is_signaling_nan(farg.d)) {
624 /* Signaling NaN: flags are undefined */
625 ret = 0x00;
626 } else {
627 /* Quiet NaN */
628 ret = 0x11;
629 }
630 } else if (unlikely(isinfinity(farg.d))) {
631 /* +/- infinity */
632 if (isneg)
633 ret = 0x09;
634 else
635 ret = 0x05;
636 } else {
637 if (iszero(farg.d)) {
638 /* +/- zero */
639 if (isneg)
640 ret = 0x12;
641 else
642 ret = 0x02;
643 } else {
644 if (isden(farg.d)) {
645 /* Denormalized numbers */
646 ret = 0x10;
647 } else {
648 /* Normalized numbers */
649 ret = 0x00;
650 }
651 if (isneg) {
652 ret |= 0x08;
653 } else {
654 ret |= 0x04;
655 }
656 }
657 }
658 if (set_fprf) {
659 /* We update FPSCR_FPRF */
660 env->fpscr &= ~(0x1F << FPSCR_FPRF);
661 env->fpscr |= ret << FPSCR_FPRF;
662 }
663 /* We just need fpcc to update Rc1 */
664 return ret & 0xF;
665 }
666
667 /* Floating-point invalid operations exception */
668 static always_inline uint64_t fload_invalid_op_excp (int op)
669 {
670 uint64_t ret = 0;
671 int ve;
672
673 ve = fpscr_ve;
674 if (op & POWERPC_EXCP_FP_VXSNAN) {
675 /* Operation on signaling NaN */
676 env->fpscr |= 1 << FPSCR_VXSNAN;
677 }
678 if (op & POWERPC_EXCP_FP_VXSOFT) {
679 /* Software-defined condition */
680 env->fpscr |= 1 << FPSCR_VXSOFT;
681 }
682 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
683 case POWERPC_EXCP_FP_VXISI:
684 /* Magnitude subtraction of infinities */
685 env->fpscr |= 1 << FPSCR_VXISI;
686 goto update_arith;
687 case POWERPC_EXCP_FP_VXIDI:
688 /* Division of infinity by infinity */
689 env->fpscr |= 1 << FPSCR_VXIDI;
690 goto update_arith;
691 case POWERPC_EXCP_FP_VXZDZ:
692 /* Division of zero by zero */
693 env->fpscr |= 1 << FPSCR_VXZDZ;
694 goto update_arith;
695 case POWERPC_EXCP_FP_VXIMZ:
696 /* Multiplication of zero by infinity */
697 env->fpscr |= 1 << FPSCR_VXIMZ;
698 goto update_arith;
699 case POWERPC_EXCP_FP_VXVC:
700 /* Ordered comparison of NaN */
701 env->fpscr |= 1 << FPSCR_VXVC;
702 env->fpscr &= ~(0xF << FPSCR_FPCC);
703 env->fpscr |= 0x11 << FPSCR_FPCC;
704 /* We must update the target FPR before raising the exception */
705 if (ve != 0) {
706 env->exception_index = POWERPC_EXCP_PROGRAM;
707 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 /* Exception is differed */
711 ve = 0;
712 }
713 break;
714 case POWERPC_EXCP_FP_VXSQRT:
715 /* Square root of a negative number */
716 env->fpscr |= 1 << FPSCR_VXSQRT;
717 update_arith:
718 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
719 if (ve == 0) {
720 /* Set the result to quiet NaN */
721 ret = UINT64_MAX;
722 env->fpscr &= ~(0xF << FPSCR_FPCC);
723 env->fpscr |= 0x11 << FPSCR_FPCC;
724 }
725 break;
726 case POWERPC_EXCP_FP_VXCVI:
727 /* Invalid conversion */
728 env->fpscr |= 1 << FPSCR_VXCVI;
729 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
730 if (ve == 0) {
731 /* Set the result to quiet NaN */
732 ret = UINT64_MAX;
733 env->fpscr &= ~(0xF << FPSCR_FPCC);
734 env->fpscr |= 0x11 << FPSCR_FPCC;
735 }
736 break;
737 }
738 /* Update the floating-point invalid operation summary */
739 env->fpscr |= 1 << FPSCR_VX;
740 /* Update the floating-point exception summary */
741 env->fpscr |= 1 << FPSCR_FX;
742 if (ve != 0) {
743 /* Update the floating-point enabled exception summary */
744 env->fpscr |= 1 << FPSCR_FEX;
745 if (msr_fe0 != 0 || msr_fe1 != 0)
746 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
747 }
748 return ret;
749 }
750
751 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
752 {
753 env->fpscr |= 1 << FPSCR_ZX;
754 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
755 /* Update the floating-point exception summary */
756 env->fpscr |= 1 << FPSCR_FX;
757 if (fpscr_ze != 0) {
758 /* Update the floating-point enabled exception summary */
759 env->fpscr |= 1 << FPSCR_FEX;
760 if (msr_fe0 != 0 || msr_fe1 != 0) {
761 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
762 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
763 }
764 } else {
765 /* Set the result to infinity */
766 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
767 arg1 |= 0x7FFULL << 52;
768 }
769 return arg1;
770 }
771
772 static always_inline void float_overflow_excp (void)
773 {
774 env->fpscr |= 1 << FPSCR_OX;
775 /* Update the floating-point exception summary */
776 env->fpscr |= 1 << FPSCR_FX;
777 if (fpscr_oe != 0) {
778 /* XXX: should adjust the result */
779 /* Update the floating-point enabled exception summary */
780 env->fpscr |= 1 << FPSCR_FEX;
781 /* We must update the target FPR before raising the exception */
782 env->exception_index = POWERPC_EXCP_PROGRAM;
783 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
784 } else {
785 env->fpscr |= 1 << FPSCR_XX;
786 env->fpscr |= 1 << FPSCR_FI;
787 }
788 }
789
790 static always_inline void float_underflow_excp (void)
791 {
792 env->fpscr |= 1 << FPSCR_UX;
793 /* Update the floating-point exception summary */
794 env->fpscr |= 1 << FPSCR_FX;
795 if (fpscr_ue != 0) {
796 /* XXX: should adjust the result */
797 /* Update the floating-point enabled exception summary */
798 env->fpscr |= 1 << FPSCR_FEX;
799 /* We must update the target FPR before raising the exception */
800 env->exception_index = POWERPC_EXCP_PROGRAM;
801 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
802 }
803 }
804
805 static always_inline void float_inexact_excp (void)
806 {
807 env->fpscr |= 1 << FPSCR_XX;
808 /* Update the floating-point exception summary */
809 env->fpscr |= 1 << FPSCR_FX;
810 if (fpscr_xe != 0) {
811 /* Update the floating-point enabled exception summary */
812 env->fpscr |= 1 << FPSCR_FEX;
813 /* We must update the target FPR before raising the exception */
814 env->exception_index = POWERPC_EXCP_PROGRAM;
815 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
816 }
817 }
818
819 static always_inline void fpscr_set_rounding_mode (void)
820 {
821 int rnd_type;
822
823 /* Set rounding mode */
824 switch (fpscr_rn) {
825 case 0:
826 /* Best approximation (round to nearest) */
827 rnd_type = float_round_nearest_even;
828 break;
829 case 1:
830 /* Smaller magnitude (round toward zero) */
831 rnd_type = float_round_to_zero;
832 break;
833 case 2:
834 /* Round toward +infinite */
835 rnd_type = float_round_up;
836 break;
837 default:
838 case 3:
839 /* Round toward -infinite */
840 rnd_type = float_round_down;
841 break;
842 }
843 set_float_rounding_mode(rnd_type, &env->fp_status);
844 }
845
846 void helper_fpscr_clrbit (uint32_t bit)
847 {
848 int prev;
849
850 prev = (env->fpscr >> bit) & 1;
851 env->fpscr &= ~(1 << bit);
852 if (prev == 1) {
853 switch (bit) {
854 case FPSCR_RN1:
855 case FPSCR_RN:
856 fpscr_set_rounding_mode();
857 break;
858 default:
859 break;
860 }
861 }
862 }
863
864 void helper_fpscr_setbit (uint32_t bit)
865 {
866 int prev;
867
868 prev = (env->fpscr >> bit) & 1;
869 env->fpscr |= 1 << bit;
870 if (prev == 0) {
871 switch (bit) {
872 case FPSCR_VX:
873 env->fpscr |= 1 << FPSCR_FX;
874 if (fpscr_ve)
875 goto raise_ve;
876 case FPSCR_OX:
877 env->fpscr |= 1 << FPSCR_FX;
878 if (fpscr_oe)
879 goto raise_oe;
880 break;
881 case FPSCR_UX:
882 env->fpscr |= 1 << FPSCR_FX;
883 if (fpscr_ue)
884 goto raise_ue;
885 break;
886 case FPSCR_ZX:
887 env->fpscr |= 1 << FPSCR_FX;
888 if (fpscr_ze)
889 goto raise_ze;
890 break;
891 case FPSCR_XX:
892 env->fpscr |= 1 << FPSCR_FX;
893 if (fpscr_xe)
894 goto raise_xe;
895 break;
896 case FPSCR_VXSNAN:
897 case FPSCR_VXISI:
898 case FPSCR_VXIDI:
899 case FPSCR_VXZDZ:
900 case FPSCR_VXIMZ:
901 case FPSCR_VXVC:
902 case FPSCR_VXSOFT:
903 case FPSCR_VXSQRT:
904 case FPSCR_VXCVI:
905 env->fpscr |= 1 << FPSCR_VX;
906 env->fpscr |= 1 << FPSCR_FX;
907 if (fpscr_ve != 0)
908 goto raise_ve;
909 break;
910 case FPSCR_VE:
911 if (fpscr_vx != 0) {
912 raise_ve:
913 env->error_code = POWERPC_EXCP_FP;
914 if (fpscr_vxsnan)
915 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
916 if (fpscr_vxisi)
917 env->error_code |= POWERPC_EXCP_FP_VXISI;
918 if (fpscr_vxidi)
919 env->error_code |= POWERPC_EXCP_FP_VXIDI;
920 if (fpscr_vxzdz)
921 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
922 if (fpscr_vximz)
923 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
924 if (fpscr_vxvc)
925 env->error_code |= POWERPC_EXCP_FP_VXVC;
926 if (fpscr_vxsoft)
927 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
928 if (fpscr_vxsqrt)
929 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
930 if (fpscr_vxcvi)
931 env->error_code |= POWERPC_EXCP_FP_VXCVI;
932 goto raise_excp;
933 }
934 break;
935 case FPSCR_OE:
936 if (fpscr_ox != 0) {
937 raise_oe:
938 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
939 goto raise_excp;
940 }
941 break;
942 case FPSCR_UE:
943 if (fpscr_ux != 0) {
944 raise_ue:
945 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
946 goto raise_excp;
947 }
948 break;
949 case FPSCR_ZE:
950 if (fpscr_zx != 0) {
951 raise_ze:
952 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
953 goto raise_excp;
954 }
955 break;
956 case FPSCR_XE:
957 if (fpscr_xx != 0) {
958 raise_xe:
959 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
960 goto raise_excp;
961 }
962 break;
963 case FPSCR_RN1:
964 case FPSCR_RN:
965 fpscr_set_rounding_mode();
966 break;
967 default:
968 break;
969 raise_excp:
970 /* Update the floating-point enabled exception summary */
971 env->fpscr |= 1 << FPSCR_FEX;
972 /* We have to update Rc1 before raising the exception */
973 env->exception_index = POWERPC_EXCP_PROGRAM;
974 break;
975 }
976 }
977 }
978
979 void helper_store_fpscr (uint64_t arg, uint32_t mask)
980 {
981 /*
982 * We use only the 32 LSB of the incoming fpr
983 */
984 uint32_t prev, new;
985 int i;
986
987 prev = env->fpscr;
988 new = (uint32_t)arg;
989 new &= ~0x60000000;
990 new |= prev & 0x60000000;
991 for (i = 0; i < 8; i++) {
992 if (mask & (1 << i)) {
993 env->fpscr &= ~(0xF << (4 * i));
994 env->fpscr |= new & (0xF << (4 * i));
995 }
996 }
997 /* Update VX and FEX */
998 if (fpscr_ix != 0)
999 env->fpscr |= 1 << FPSCR_VX;
1000 else
1001 env->fpscr &= ~(1 << FPSCR_VX);
1002 if ((fpscr_ex & fpscr_eex) != 0) {
1003 env->fpscr |= 1 << FPSCR_FEX;
1004 env->exception_index = POWERPC_EXCP_PROGRAM;
1005 /* XXX: we should compute it properly */
1006 env->error_code = POWERPC_EXCP_FP;
1007 }
1008 else
1009 env->fpscr &= ~(1 << FPSCR_FEX);
1010 fpscr_set_rounding_mode();
1011 }
1012
1013 void helper_float_check_status (void)
1014 {
1015 #ifdef CONFIG_SOFTFLOAT
1016 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1017 (env->error_code & POWERPC_EXCP_FP)) {
1018 /* Differred floating-point exception after target FPR update */
1019 if (msr_fe0 != 0 || msr_fe1 != 0)
1020 helper_raise_exception_err(env->exception_index, env->error_code);
1021 } else {
1022 int status = get_float_exception_flags(&env->fp_status);
1023 if (status & float_flag_overflow) {
1024 float_overflow_excp();
1025 } else if (status & float_flag_underflow) {
1026 float_underflow_excp();
1027 } else if (status & float_flag_inexact) {
1028 float_inexact_excp();
1029 }
1030 }
1031 #else
1032 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1033 (env->error_code & POWERPC_EXCP_FP)) {
1034 /* Differred floating-point exception after target FPR update */
1035 if (msr_fe0 != 0 || msr_fe1 != 0)
1036 helper_raise_exception_err(env->exception_index, env->error_code);
1037 }
1038 #endif
1039 }
1040
1041 #ifdef CONFIG_SOFTFLOAT
1042 void helper_reset_fpstatus (void)
1043 {
1044 set_float_exception_flags(0, &env->fp_status);
1045 }
1046 #endif
1047
1048 /* fadd - fadd. */
1049 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1050 {
1051 CPU_DoubleU farg1, farg2;
1052
1053 farg1.ll = arg1;
1054 farg2.ll = arg2;
1055 #if USE_PRECISE_EMULATION
1056 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1057 float64_is_signaling_nan(farg2.d))) {
1058 /* sNaN addition */
1059 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1060 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1061 fpisneg(farg1.d) == fpisneg(farg2.d))) {
1062 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1063 } else {
1064 /* Magnitude subtraction of infinities */
1065 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1066 }
1067 #else
1068 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1069 #endif
1070 return farg1.ll;
1071 }
1072
1073 /* fsub - fsub. */
1074 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1075 {
1076 CPU_DoubleU farg1, farg2;
1077
1078 farg1.ll = arg1;
1079 farg2.ll = arg2;
1080 #if USE_PRECISE_EMULATION
1081 {
1082 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1083 float64_is_signaling_nan(farg2.d))) {
1084 /* sNaN subtraction */
1085 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1086 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1087 fpisneg(farg1.d) != fpisneg(farg2.d))) {
1088 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1089 } else {
1090 /* Magnitude subtraction of infinities */
1091 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1092 }
1093 }
1094 #else
1095 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1096 #endif
1097 return farg1.ll;
1098 }
1099
1100 /* fmul - fmul. */
1101 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1102 {
1103 CPU_DoubleU farg1, farg2;
1104
1105 farg1.ll = arg1;
1106 farg2.ll = arg2;
1107 #if USE_PRECISE_EMULATION
1108 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1109 float64_is_signaling_nan(farg2.d))) {
1110 /* sNaN multiplication */
1111 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1112 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
1113 (iszero(farg1.d) && isinfinity(farg2.d)))) {
1114 /* Multiplication of zero by infinity */
1115 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1116 } else {
1117 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1118 }
1119 #else
1120 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1121 #endif
1122 return farg1.ll;
1123 }
1124
1125 /* fdiv - fdiv. */
1126 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1127 {
1128 CPU_DoubleU farg1, farg2;
1129
1130 farg1.ll = arg1;
1131 farg2.ll = arg2;
1132 #if USE_PRECISE_EMULATION
1133 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1134 float64_is_signaling_nan(farg2.d))) {
1135 /* sNaN division */
1136 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1137 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
1138 /* Division of infinity by infinity */
1139 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1140 } else if (unlikely(iszero(farg2.d))) {
1141 if (iszero(farg1.d)) {
1142 /* Division of zero by zero */
1143 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1144 } else {
1145 /* Division by zero */
1146 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1147 }
1148 } else {
1149 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1150 }
1151 #else
1152 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1153 #endif
1154 return farg1.ll;
1155 }
1156
1157 /* fabs */
1158 uint64_t helper_fabs (uint64_t arg)
1159 {
1160 CPU_DoubleU farg;
1161
1162 farg.ll = arg;
1163 farg.d = float64_abs(farg.d);
1164 return farg.ll;
1165 }
1166
1167 /* fnabs */
1168 uint64_t helper_fnabs (uint64_t arg)
1169 {
1170 CPU_DoubleU farg;
1171
1172 farg.ll = arg;
1173 farg.d = float64_abs(farg.d);
1174 farg.d = float64_chs(farg.d);
1175 return farg.ll;
1176 }
1177
1178 /* fneg */
1179 uint64_t helper_fneg (uint64_t arg)
1180 {
1181 CPU_DoubleU farg;
1182
1183 farg.ll = arg;
1184 farg.d = float64_chs(farg.d);
1185 return farg.ll;
1186 }
1187
1188 /* fctiw - fctiw. */
1189 uint64_t helper_fctiw (uint64_t arg)
1190 {
1191 CPU_DoubleU farg;
1192 farg.ll = arg;
1193
1194 if (unlikely(float64_is_signaling_nan(farg.d))) {
1195 /* sNaN conversion */
1196 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1197 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1198 /* qNan / infinity conversion */
1199 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1200 } else {
1201 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1202 #if USE_PRECISE_EMULATION
1203 /* XXX: higher bits are not supposed to be significant.
1204 * to make tests easier, return the same as a real PowerPC 750
1205 */
1206 farg.ll |= 0xFFF80000ULL << 32;
1207 #endif
1208 }
1209 return farg.ll;
1210 }
1211
1212 /* fctiwz - fctiwz. */
1213 uint64_t helper_fctiwz (uint64_t arg)
1214 {
1215 CPU_DoubleU farg;
1216 farg.ll = arg;
1217
1218 if (unlikely(float64_is_signaling_nan(farg.d))) {
1219 /* sNaN conversion */
1220 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1221 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1222 /* qNan / infinity conversion */
1223 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1224 } else {
1225 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1226 #if USE_PRECISE_EMULATION
1227 /* XXX: higher bits are not supposed to be significant.
1228 * to make tests easier, return the same as a real PowerPC 750
1229 */
1230 farg.ll |= 0xFFF80000ULL << 32;
1231 #endif
1232 }
1233 return farg.ll;
1234 }
1235
1236 #if defined(TARGET_PPC64)
1237 /* fcfid - fcfid. */
1238 uint64_t helper_fcfid (uint64_t arg)
1239 {
1240 CPU_DoubleU farg;
1241 farg.d = int64_to_float64(arg, &env->fp_status);
1242 return farg.ll;
1243 }
1244
1245 /* fctid - fctid. */
1246 uint64_t helper_fctid (uint64_t arg)
1247 {
1248 CPU_DoubleU farg;
1249 farg.ll = arg;
1250
1251 if (unlikely(float64_is_signaling_nan(farg.d))) {
1252 /* sNaN conversion */
1253 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1254 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1255 /* qNan / infinity conversion */
1256 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1257 } else {
1258 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1259 }
1260 return farg.ll;
1261 }
1262
1263 /* fctidz - fctidz. */
1264 uint64_t helper_fctidz (uint64_t arg)
1265 {
1266 CPU_DoubleU farg;
1267 farg.ll = arg;
1268
1269 if (unlikely(float64_is_signaling_nan(farg.d))) {
1270 /* sNaN conversion */
1271 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1272 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1273 /* qNan / infinity conversion */
1274 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1275 } else {
1276 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1277 }
1278 return farg.ll;
1279 }
1280
1281 #endif
1282
1283 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1284 {
1285 CPU_DoubleU farg;
1286 farg.ll = arg;
1287
1288 if (unlikely(float64_is_signaling_nan(farg.d))) {
1289 /* sNaN round */
1290 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1291 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1292 /* qNan / infinity round */
1293 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1294 } else {
1295 set_float_rounding_mode(rounding_mode, &env->fp_status);
1296 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1297 /* Restore rounding mode from FPSCR */
1298 fpscr_set_rounding_mode();
1299 }
1300 return farg.ll;
1301 }
1302
1303 uint64_t helper_frin (uint64_t arg)
1304 {
1305 return do_fri(arg, float_round_nearest_even);
1306 }
1307
1308 uint64_t helper_friz (uint64_t arg)
1309 {
1310 return do_fri(arg, float_round_to_zero);
1311 }
1312
1313 uint64_t helper_frip (uint64_t arg)
1314 {
1315 return do_fri(arg, float_round_up);
1316 }
1317
1318 uint64_t helper_frim (uint64_t arg)
1319 {
1320 return do_fri(arg, float_round_down);
1321 }
1322
1323 /* fmadd - fmadd. */
1324 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1325 {
1326 CPU_DoubleU farg1, farg2, farg3;
1327
1328 farg1.ll = arg1;
1329 farg2.ll = arg2;
1330 farg3.ll = arg3;
1331 #if USE_PRECISE_EMULATION
1332 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1333 float64_is_signaling_nan(farg2.d) ||
1334 float64_is_signaling_nan(farg3.d))) {
1335 /* sNaN operation */
1336 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1337 } else {
1338 #ifdef FLOAT128
1339 /* This is the way the PowerPC specification defines it */
1340 float128 ft0_128, ft1_128;
1341
1342 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1343 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1344 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1345 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1346 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1347 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1348 #else
1349 /* This is OK on x86 hosts */
1350 farg1.d = (farg1.d * farg2.d) + farg3.d;
1351 #endif
1352 }
1353 #else
1354 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1355 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1356 #endif
1357 return farg1.ll;
1358 }
1359
1360 /* fmsub - fmsub. */
1361 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1362 {
1363 CPU_DoubleU farg1, farg2, farg3;
1364
1365 farg1.ll = arg1;
1366 farg2.ll = arg2;
1367 farg3.ll = arg3;
1368 #if USE_PRECISE_EMULATION
1369 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1370 float64_is_signaling_nan(farg2.d) ||
1371 float64_is_signaling_nan(farg3.d))) {
1372 /* sNaN operation */
1373 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1374 } else {
1375 #ifdef FLOAT128
1376 /* This is the way the PowerPC specification defines it */
1377 float128 ft0_128, ft1_128;
1378
1379 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1380 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1381 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1382 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1383 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1384 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1385 #else
1386 /* This is OK on x86 hosts */
1387 farg1.d = (farg1.d * farg2.d) - farg3.d;
1388 #endif
1389 }
1390 #else
1391 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1392 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1393 #endif
1394 return farg1.ll;
1395 }
1396
1397 /* fnmadd - fnmadd. */
1398 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1399 {
1400 CPU_DoubleU farg1, farg2, farg3;
1401
1402 farg1.ll = arg1;
1403 farg2.ll = arg2;
1404 farg3.ll = arg3;
1405
1406 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1407 float64_is_signaling_nan(farg2.d) ||
1408 float64_is_signaling_nan(farg3.d))) {
1409 /* sNaN operation */
1410 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1411 } else {
1412 #if USE_PRECISE_EMULATION
1413 #ifdef FLOAT128
1414 /* This is the way the PowerPC specification defines it */
1415 float128 ft0_128, ft1_128;
1416
1417 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1418 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1419 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1420 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1421 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1422 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1423 #else
1424 /* This is OK on x86 hosts */
1425 farg1.d = (farg1.d * farg2.d) + farg3.d;
1426 #endif
1427 #else
1428 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1429 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1430 #endif
1431 if (likely(!float64_is_nan(farg1.d)))
1432 farg1.d = float64_chs(farg1.d);
1433 }
1434 return farg1.ll;
1435 }
1436
1437 /* fnmsub - fnmsub. */
1438 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1439 {
1440 CPU_DoubleU farg1, farg2, farg3;
1441
1442 farg1.ll = arg1;
1443 farg2.ll = arg2;
1444 farg3.ll = arg3;
1445
1446 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1447 float64_is_signaling_nan(farg2.d) ||
1448 float64_is_signaling_nan(farg3.d))) {
1449 /* sNaN operation */
1450 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1451 } else {
1452 #if USE_PRECISE_EMULATION
1453 #ifdef FLOAT128
1454 /* This is the way the PowerPC specification defines it */
1455 float128 ft0_128, ft1_128;
1456
1457 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1458 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1459 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1460 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1461 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1462 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1463 #else
1464 /* This is OK on x86 hosts */
1465 farg1.d = (farg1.d * farg2.d) - farg3.d;
1466 #endif
1467 #else
1468 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1469 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1470 #endif
1471 if (likely(!float64_is_nan(farg1.d)))
1472 farg1.d = float64_chs(farg1.d);
1473 }
1474 return farg1.ll;
1475 }
1476
1477 /* frsp - frsp. */
1478 uint64_t helper_frsp (uint64_t arg)
1479 {
1480 CPU_DoubleU farg;
1481 float32 f32;
1482 farg.ll = arg;
1483
1484 #if USE_PRECISE_EMULATION
1485 if (unlikely(float64_is_signaling_nan(farg.d))) {
1486 /* sNaN square root */
1487 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1488 } else {
1489 f32 = float64_to_float32(farg.d, &env->fp_status);
1490 farg.d = float32_to_float64(f32, &env->fp_status);
1491 }
1492 #else
1493 f32 = float64_to_float32(farg.d, &env->fp_status);
1494 farg.d = float32_to_float64(f32, &env->fp_status);
1495 #endif
1496 return farg.ll;
1497 }
1498
1499 /* fsqrt - fsqrt. */
1500 uint64_t helper_fsqrt (uint64_t arg)
1501 {
1502 CPU_DoubleU farg;
1503 farg.ll = arg;
1504
1505 if (unlikely(float64_is_signaling_nan(farg.d))) {
1506 /* sNaN square root */
1507 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1508 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1509 /* Square root of a negative nonzero number */
1510 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1511 } else {
1512 farg.d = float64_sqrt(farg.d, &env->fp_status);
1513 }
1514 return farg.ll;
1515 }
1516
1517 /* fre - fre. */
1518 uint64_t helper_fre (uint64_t arg)
1519 {
1520 CPU_DoubleU farg;
1521 farg.ll = arg;
1522
1523 if (unlikely(float64_is_signaling_nan(farg.d))) {
1524 /* sNaN reciprocal */
1525 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1526 } else if (unlikely(iszero(farg.d))) {
1527 /* Zero reciprocal */
1528 farg.ll = float_zero_divide_excp(1.0, farg.d);
1529 } else if (likely(isnormal(farg.d))) {
1530 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1531 } else {
1532 if (farg.ll == 0x8000000000000000ULL) {
1533 farg.ll = 0xFFF0000000000000ULL;
1534 } else if (farg.ll == 0x0000000000000000ULL) {
1535 farg.ll = 0x7FF0000000000000ULL;
1536 } else if (float64_is_nan(farg.d)) {
1537 farg.ll = 0x7FF8000000000000ULL;
1538 } else if (fpisneg(farg.d)) {
1539 farg.ll = 0x8000000000000000ULL;
1540 } else {
1541 farg.ll = 0x0000000000000000ULL;
1542 }
1543 }
1544 return farg.d;
1545 }
1546
1547 /* fres - fres. */
1548 uint64_t helper_fres (uint64_t arg)
1549 {
1550 CPU_DoubleU farg;
1551 farg.ll = arg;
1552
1553 if (unlikely(float64_is_signaling_nan(farg.d))) {
1554 /* sNaN reciprocal */
1555 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1556 } else if (unlikely(iszero(farg.d))) {
1557 /* Zero reciprocal */
1558 farg.ll = float_zero_divide_excp(1.0, farg.d);
1559 } else if (likely(isnormal(farg.d))) {
1560 #if USE_PRECISE_EMULATION
1561 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1562 farg.d = float64_to_float32(farg.d, &env->fp_status);
1563 #else
1564 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1565 #endif
1566 } else {
1567 if (farg.ll == 0x8000000000000000ULL) {
1568 farg.ll = 0xFFF0000000000000ULL;
1569 } else if (farg.ll == 0x0000000000000000ULL) {
1570 farg.ll = 0x7FF0000000000000ULL;
1571 } else if (float64_is_nan(farg.d)) {
1572 farg.ll = 0x7FF8000000000000ULL;
1573 } else if (fpisneg(farg.d)) {
1574 farg.ll = 0x8000000000000000ULL;
1575 } else {
1576 farg.ll = 0x0000000000000000ULL;
1577 }
1578 }
1579 return farg.ll;
1580 }
1581
1582 /* frsqrte - frsqrte. */
1583 uint64_t helper_frsqrte (uint64_t arg)
1584 {
1585 CPU_DoubleU farg;
1586 farg.ll = arg;
1587
1588 if (unlikely(float64_is_signaling_nan(farg.d))) {
1589 /* sNaN reciprocal square root */
1590 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1591 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1592 /* Reciprocal square root of a negative nonzero number */
1593 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1594 } else if (likely(isnormal(farg.d))) {
1595 farg.d = float64_sqrt(farg.d, &env->fp_status);
1596 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1597 } else {
1598 if (farg.ll == 0x8000000000000000ULL) {
1599 farg.ll = 0xFFF0000000000000ULL;
1600 } else if (farg.ll == 0x0000000000000000ULL) {
1601 farg.ll = 0x7FF0000000000000ULL;
1602 } else if (float64_is_nan(farg.d)) {
1603 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1604 } else if (fpisneg(farg.d)) {
1605 farg.ll = 0x7FF8000000000000ULL;
1606 } else {
1607 farg.ll = 0x0000000000000000ULL;
1608 }
1609 }
1610 return farg.ll;
1611 }
1612
1613 /* fsel - fsel. */
1614 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1615 {
1616 CPU_DoubleU farg1;
1617
1618 farg1.ll = arg1;
1619
1620 if (!fpisneg(farg1.d) || iszero(farg1.d))
1621 return arg2;
1622 else
1623 return arg3;
1624 }
1625
1626 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1627 {
1628 CPU_DoubleU farg1, farg2;
1629 uint32_t ret = 0;
1630 farg1.ll = arg1;
1631 farg2.ll = arg2;
1632
1633 if (unlikely(float64_is_nan(farg1.d) ||
1634 float64_is_nan(farg2.d))) {
1635 ret = 0x01UL;
1636 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1637 ret = 0x08UL;
1638 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1639 ret = 0x04UL;
1640 } else {
1641 ret = 0x02UL;
1642 }
1643
1644 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1645 env->fpscr |= ret << FPSCR_FPRF;
1646 env->crf[crfD] = ret;
1647 if (unlikely(ret == 0x01UL
1648 && (float64_is_signaling_nan(farg1.d) ||
1649 float64_is_signaling_nan(farg2.d)))) {
1650 /* sNaN comparison */
1651 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1652 }
1653 }
1654
1655 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1656 {
1657 CPU_DoubleU farg1, farg2;
1658 uint32_t ret = 0;
1659 farg1.ll = arg1;
1660 farg2.ll = arg2;
1661
1662 if (unlikely(float64_is_nan(farg1.d) ||
1663 float64_is_nan(farg2.d))) {
1664 ret = 0x01UL;
1665 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1666 ret = 0x08UL;
1667 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1668 ret = 0x04UL;
1669 } else {
1670 ret = 0x02UL;
1671 }
1672
1673 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1674 env->fpscr |= ret << FPSCR_FPRF;
1675 env->crf[crfD] = ret;
1676 if (unlikely (ret == 0x01UL)) {
1677 if (float64_is_signaling_nan(farg1.d) ||
1678 float64_is_signaling_nan(farg2.d)) {
1679 /* sNaN comparison */
1680 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1681 POWERPC_EXCP_FP_VXVC);
1682 } else {
1683 /* qNaN comparison */
1684 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1685 }
1686 }
1687 }
1688
1689 #if !defined (CONFIG_USER_ONLY)
1690 void helper_store_msr (target_ulong val)
1691 {
1692 val = hreg_store_msr(env, val, 0);
1693 if (val != 0) {
1694 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1695 helper_raise_exception(val);
1696 }
1697 }
1698
1699 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1700 target_ulong msrm, int keep_msrh)
1701 {
1702 #if defined(TARGET_PPC64)
1703 if (msr & (1ULL << MSR_SF)) {
1704 nip = (uint64_t)nip;
1705 msr &= (uint64_t)msrm;
1706 } else {
1707 nip = (uint32_t)nip;
1708 msr = (uint32_t)(msr & msrm);
1709 if (keep_msrh)
1710 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1711 }
1712 #else
1713 nip = (uint32_t)nip;
1714 msr &= (uint32_t)msrm;
1715 #endif
1716 /* XXX: beware: this is false if VLE is supported */
1717 env->nip = nip & ~((target_ulong)0x00000003);
1718 hreg_store_msr(env, msr, 1);
1719 #if defined (DEBUG_OP)
1720 cpu_dump_rfi(env->nip, env->msr);
1721 #endif
1722 /* No need to raise an exception here,
1723 * as rfi is always the last insn of a TB
1724 */
1725 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1726 }
1727
1728 void helper_rfi (void)
1729 {
1730 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1731 ~((target_ulong)0xFFFF0000), 1);
1732 }
1733
1734 #if defined(TARGET_PPC64)
1735 void helper_rfid (void)
1736 {
1737 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1738 ~((target_ulong)0xFFFF0000), 0);
1739 }
1740
1741 void helper_hrfid (void)
1742 {
1743 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1744 ~((target_ulong)0xFFFF0000), 0);
1745 }
1746 #endif
1747 #endif
1748
1749 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1750 {
1751 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1752 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1753 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1754 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1755 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1756 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1757 }
1758 }
1759
1760 #if defined(TARGET_PPC64)
1761 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1762 {
1763 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1764 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1765 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1766 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1767 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1768 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1769 }
1770 #endif
1771
1772 /*****************************************************************************/
1773 /* PowerPC 601 specific instructions (POWER bridge) */
1774
1775 target_ulong helper_clcs (uint32_t arg)
1776 {
1777 switch (arg) {
1778 case 0x0CUL:
1779 /* Instruction cache line size */
1780 return env->icache_line_size;
1781 break;
1782 case 0x0DUL:
1783 /* Data cache line size */
1784 return env->dcache_line_size;
1785 break;
1786 case 0x0EUL:
1787 /* Minimum cache line size */
1788 return (env->icache_line_size < env->dcache_line_size) ?
1789 env->icache_line_size : env->dcache_line_size;
1790 break;
1791 case 0x0FUL:
1792 /* Maximum cache line size */
1793 return (env->icache_line_size > env->dcache_line_size) ?
1794 env->icache_line_size : env->dcache_line_size;
1795 break;
1796 default:
1797 /* Undefined */
1798 return 0;
1799 break;
1800 }
1801 }
1802
1803 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1804 {
1805 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1806
1807 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1808 (int32_t)arg2 == 0) {
1809 env->spr[SPR_MQ] = 0;
1810 return INT32_MIN;
1811 } else {
1812 env->spr[SPR_MQ] = tmp % arg2;
1813 return tmp / (int32_t)arg2;
1814 }
1815 }
1816
1817 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1818 {
1819 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1820
1821 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1822 (int32_t)arg2 == 0) {
1823 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1824 env->spr[SPR_MQ] = 0;
1825 return INT32_MIN;
1826 } else {
1827 env->spr[SPR_MQ] = tmp % arg2;
1828 tmp /= (int32_t)arg2;
1829 if ((int32_t)tmp != tmp) {
1830 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1831 } else {
1832 env->xer &= ~(1 << XER_OV);
1833 }
1834 return tmp;
1835 }
1836 }
1837
1838 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1839 {
1840 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1841 (int32_t)arg2 == 0) {
1842 env->spr[SPR_MQ] = 0;
1843 return INT32_MIN;
1844 } else {
1845 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1846 return (int32_t)arg1 / (int32_t)arg2;
1847 }
1848 }
1849
1850 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1851 {
1852 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1853 (int32_t)arg2 == 0) {
1854 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1855 env->spr[SPR_MQ] = 0;
1856 return INT32_MIN;
1857 } else {
1858 env->xer &= ~(1 << XER_OV);
1859 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1860 return (int32_t)arg1 / (int32_t)arg2;
1861 }
1862 }
1863
1864 #if !defined (CONFIG_USER_ONLY)
1865 target_ulong helper_rac (target_ulong addr)
1866 {
1867 mmu_ctx_t ctx;
1868 int nb_BATs;
1869 target_ulong ret = 0;
1870
1871 /* We don't have to generate many instances of this instruction,
1872 * as rac is supervisor only.
1873 */
1874 /* XXX: FIX THIS: Pretend we have no BAT */
1875 nb_BATs = env->nb_BATs;
1876 env->nb_BATs = 0;
1877 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1878 ret = ctx.raddr;
1879 env->nb_BATs = nb_BATs;
1880 return ret;
1881 }
1882
1883 void helper_rfsvc (void)
1884 {
1885 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1886 }
1887 #endif
1888
1889 /*****************************************************************************/
1890 /* 602 specific instructions */
1891 /* mfrom is the most crazy instruction ever seen, imho ! */
1892 /* Real implementation uses a ROM table. Do the same */
1893 /* Extremly decomposed:
1894 * -arg / 256
1895 * return 256 * log10(10 + 1.0) + 0.5
1896 */
1897 #if !defined (CONFIG_USER_ONLY)
1898 target_ulong helper_602_mfrom (target_ulong arg)
1899 {
1900 if (likely(arg < 602)) {
1901 #include "mfrom_table.c"
1902 return mfrom_ROM_table[arg];
1903 } else {
1904 return 0;
1905 }
1906 }
1907 #endif
1908
1909 /*****************************************************************************/
1910 /* Embedded PowerPC specific helpers */
1911
1912 /* XXX: to be improved to check access rights when in user-mode */
1913 target_ulong helper_load_dcr (target_ulong dcrn)
1914 {
1915 target_ulong val = 0;
1916
1917 if (unlikely(env->dcr_env == NULL)) {
1918 if (loglevel != 0) {
1919 fprintf(logfile, "No DCR environment\n");
1920 }
1921 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1922 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1923 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1924 if (loglevel != 0) {
1925 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1926 }
1927 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1928 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1929 }
1930 return val;
1931 }
1932
1933 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1934 {
1935 if (unlikely(env->dcr_env == NULL)) {
1936 if (loglevel != 0) {
1937 fprintf(logfile, "No DCR environment\n");
1938 }
1939 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1940 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1941 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1942 if (loglevel != 0) {
1943 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1944 }
1945 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1946 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1947 }
1948 }
1949
1950 #if !defined(CONFIG_USER_ONLY)
1951 void helper_40x_rfci (void)
1952 {
1953 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1954 ~((target_ulong)0xFFFF0000), 0);
1955 }
1956
1957 void helper_rfci (void)
1958 {
1959 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1960 ~((target_ulong)0x3FFF0000), 0);
1961 }
1962
1963 void helper_rfdi (void)
1964 {
1965 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1966 ~((target_ulong)0x3FFF0000), 0);
1967 }
1968
1969 void helper_rfmci (void)
1970 {
1971 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1972 ~((target_ulong)0x3FFF0000), 0);
1973 }
1974 #endif
1975
1976 /* 440 specific */
1977 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1978 {
1979 target_ulong mask;
1980 int i;
1981
1982 i = 1;
1983 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1984 if ((high & mask) == 0) {
1985 if (update_Rc) {
1986 env->crf[0] = 0x4;
1987 }
1988 goto done;
1989 }
1990 i++;
1991 }
1992 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1993 if ((low & mask) == 0) {
1994 if (update_Rc) {
1995 env->crf[0] = 0x8;
1996 }
1997 goto done;
1998 }
1999 i++;
2000 }
2001 if (update_Rc) {
2002 env->crf[0] = 0x2;
2003 }
2004 done:
2005 env->xer = (env->xer & ~0x7F) | i;
2006 if (update_Rc) {
2007 env->crf[0] |= xer_so;
2008 }
2009 return i;
2010 }
2011
2012 /*****************************************************************************/
2013 /* SPE extension helpers */
2014 /* Use a table to make this quicker */
2015 static uint8_t hbrev[16] = {
2016 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2017 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2018 };
2019
2020 static always_inline uint8_t byte_reverse (uint8_t val)
2021 {
2022 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2023 }
2024
2025 static always_inline uint32_t word_reverse (uint32_t val)
2026 {
2027 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2028 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2029 }
2030
2031 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2032 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2033 {
2034 uint32_t a, b, d, mask;
2035
2036 mask = UINT32_MAX >> (32 - MASKBITS);
2037 a = arg1 & mask;
2038 b = arg2 & mask;
2039 d = word_reverse(1 + word_reverse(a | ~b));
2040 return (arg1 & ~mask) | (d & b);
2041 }
2042
2043 uint32_t helper_cntlsw32 (uint32_t val)
2044 {
2045 if (val & 0x80000000)
2046 return clz32(~val);
2047 else
2048 return clz32(val);
2049 }
2050
2051 uint32_t helper_cntlzw32 (uint32_t val)
2052 {
2053 return clz32(val);
2054 }
2055
2056 /* Single-precision floating-point conversions */
2057 static always_inline uint32_t efscfsi (uint32_t val)
2058 {
2059 CPU_FloatU u;
2060
2061 u.f = int32_to_float32(val, &env->spe_status);
2062
2063 return u.l;
2064 }
2065
2066 static always_inline uint32_t efscfui (uint32_t val)
2067 {
2068 CPU_FloatU u;
2069
2070 u.f = uint32_to_float32(val, &env->spe_status);
2071
2072 return u.l;
2073 }
2074
2075 static always_inline int32_t efsctsi (uint32_t val)
2076 {
2077 CPU_FloatU u;
2078
2079 u.l = val;
2080 /* NaN are not treated the same way IEEE 754 does */
2081 if (unlikely(float32_is_nan(u.f)))
2082 return 0;
2083
2084 return float32_to_int32(u.f, &env->spe_status);
2085 }
2086
2087 static always_inline uint32_t efsctui (uint32_t val)
2088 {
2089 CPU_FloatU u;
2090
2091 u.l = val;
2092 /* NaN are not treated the same way IEEE 754 does */
2093 if (unlikely(float32_is_nan(u.f)))
2094 return 0;
2095
2096 return float32_to_uint32(u.f, &env->spe_status);
2097 }
2098
2099 static always_inline uint32_t efsctsiz (uint32_t val)
2100 {
2101 CPU_FloatU u;
2102
2103 u.l = val;
2104 /* NaN are not treated the same way IEEE 754 does */
2105 if (unlikely(float32_is_nan(u.f)))
2106 return 0;
2107
2108 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2109 }
2110
2111 static always_inline uint32_t efsctuiz (uint32_t val)
2112 {
2113 CPU_FloatU u;
2114
2115 u.l = val;
2116 /* NaN are not treated the same way IEEE 754 does */
2117 if (unlikely(float32_is_nan(u.f)))
2118 return 0;
2119
2120 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2121 }
2122
2123 static always_inline uint32_t efscfsf (uint32_t val)
2124 {
2125 CPU_FloatU u;
2126 float32 tmp;
2127
2128 u.f = int32_to_float32(val, &env->spe_status);
2129 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2130 u.f = float32_div(u.f, tmp, &env->spe_status);
2131
2132 return u.l;
2133 }
2134
2135 static always_inline uint32_t efscfuf (uint32_t val)
2136 {
2137 CPU_FloatU u;
2138 float32 tmp;
2139
2140 u.f = uint32_to_float32(val, &env->spe_status);
2141 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2142 u.f = float32_div(u.f, tmp, &env->spe_status);
2143
2144 return u.l;
2145 }
2146
2147 static always_inline uint32_t efsctsf (uint32_t val)
2148 {
2149 CPU_FloatU u;
2150 float32 tmp;
2151
2152 u.l = val;
2153 /* NaN are not treated the same way IEEE 754 does */
2154 if (unlikely(float32_is_nan(u.f)))
2155 return 0;
2156 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2157 u.f = float32_mul(u.f, tmp, &env->spe_status);
2158
2159 return float32_to_int32(u.f, &env->spe_status);
2160 }
2161
2162 static always_inline uint32_t efsctuf (uint32_t val)
2163 {
2164 CPU_FloatU u;
2165 float32 tmp;
2166
2167 u.l = val;
2168 /* NaN are not treated the same way IEEE 754 does */
2169 if (unlikely(float32_is_nan(u.f)))
2170 return 0;
2171 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2172 u.f = float32_mul(u.f, tmp, &env->spe_status);
2173
2174 return float32_to_uint32(u.f, &env->spe_status);
2175 }
2176
2177 #define HELPER_SPE_SINGLE_CONV(name) \
2178 uint32_t helper_e##name (uint32_t val) \
2179 { \
2180 return e##name(val); \
2181 }
2182 /* efscfsi */
2183 HELPER_SPE_SINGLE_CONV(fscfsi);
2184 /* efscfui */
2185 HELPER_SPE_SINGLE_CONV(fscfui);
2186 /* efscfuf */
2187 HELPER_SPE_SINGLE_CONV(fscfuf);
2188 /* efscfsf */
2189 HELPER_SPE_SINGLE_CONV(fscfsf);
2190 /* efsctsi */
2191 HELPER_SPE_SINGLE_CONV(fsctsi);
2192 /* efsctui */
2193 HELPER_SPE_SINGLE_CONV(fsctui);
2194 /* efsctsiz */
2195 HELPER_SPE_SINGLE_CONV(fsctsiz);
2196 /* efsctuiz */
2197 HELPER_SPE_SINGLE_CONV(fsctuiz);
2198 /* efsctsf */
2199 HELPER_SPE_SINGLE_CONV(fsctsf);
2200 /* efsctuf */
2201 HELPER_SPE_SINGLE_CONV(fsctuf);
2202
2203 #define HELPER_SPE_VECTOR_CONV(name) \
2204 uint64_t helper_ev##name (uint64_t val) \
2205 { \
2206 return ((uint64_t)e##name(val >> 32) << 32) | \
2207 (uint64_t)e##name(val); \
2208 }
2209 /* evfscfsi */
2210 HELPER_SPE_VECTOR_CONV(fscfsi);
2211 /* evfscfui */
2212 HELPER_SPE_VECTOR_CONV(fscfui);
2213 /* evfscfuf */
2214 HELPER_SPE_VECTOR_CONV(fscfuf);
2215 /* evfscfsf */
2216 HELPER_SPE_VECTOR_CONV(fscfsf);
2217 /* evfsctsi */
2218 HELPER_SPE_VECTOR_CONV(fsctsi);
2219 /* evfsctui */
2220 HELPER_SPE_VECTOR_CONV(fsctui);
2221 /* evfsctsiz */
2222 HELPER_SPE_VECTOR_CONV(fsctsiz);
2223 /* evfsctuiz */
2224 HELPER_SPE_VECTOR_CONV(fsctuiz);
2225 /* evfsctsf */
2226 HELPER_SPE_VECTOR_CONV(fsctsf);
2227 /* evfsctuf */
2228 HELPER_SPE_VECTOR_CONV(fsctuf);
2229
2230 /* Single-precision floating-point arithmetic */
2231 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2232 {
2233 CPU_FloatU u1, u2;
2234 u1.l = op1;
2235 u2.l = op2;
2236 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2237 return u1.l;
2238 }
2239
2240 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2241 {
2242 CPU_FloatU u1, u2;
2243 u1.l = op1;
2244 u2.l = op2;
2245 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2246 return u1.l;
2247 }
2248
2249 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2250 {
2251 CPU_FloatU u1, u2;
2252 u1.l = op1;
2253 u2.l = op2;
2254 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2255 return u1.l;
2256 }
2257
2258 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2259 {
2260 CPU_FloatU u1, u2;
2261 u1.l = op1;
2262 u2.l = op2;
2263 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2264 return u1.l;
2265 }
2266
2267 #define HELPER_SPE_SINGLE_ARITH(name) \
2268 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2269 { \
2270 return e##name(op1, op2); \
2271 }
2272 /* efsadd */
2273 HELPER_SPE_SINGLE_ARITH(fsadd);
2274 /* efssub */
2275 HELPER_SPE_SINGLE_ARITH(fssub);
2276 /* efsmul */
2277 HELPER_SPE_SINGLE_ARITH(fsmul);
2278 /* efsdiv */
2279 HELPER_SPE_SINGLE_ARITH(fsdiv);
2280
2281 #define HELPER_SPE_VECTOR_ARITH(name) \
2282 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2283 { \
2284 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2285 (uint64_t)e##name(op1, op2); \
2286 }
2287 /* evfsadd */
2288 HELPER_SPE_VECTOR_ARITH(fsadd);
2289 /* evfssub */
2290 HELPER_SPE_VECTOR_ARITH(fssub);
2291 /* evfsmul */
2292 HELPER_SPE_VECTOR_ARITH(fsmul);
2293 /* evfsdiv */
2294 HELPER_SPE_VECTOR_ARITH(fsdiv);
2295
2296 /* Single-precision floating-point comparisons */
2297 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2298 {
2299 CPU_FloatU u1, u2;
2300 u1.l = op1;
2301 u2.l = op2;
2302 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2303 }
2304
2305 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2306 {
2307 CPU_FloatU u1, u2;
2308 u1.l = op1;
2309 u2.l = op2;
2310 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2311 }
2312
2313 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2314 {
2315 CPU_FloatU u1, u2;
2316 u1.l = op1;
2317 u2.l = op2;
2318 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2319 }
2320
2321 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2322 {
2323 /* XXX: TODO: test special values (NaN, infinites, ...) */
2324 return efststlt(op1, op2);
2325 }
2326
2327 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2328 {
2329 /* XXX: TODO: test special values (NaN, infinites, ...) */
2330 return efststgt(op1, op2);
2331 }
2332
2333 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2334 {
2335 /* XXX: TODO: test special values (NaN, infinites, ...) */
2336 return efststeq(op1, op2);
2337 }
2338
2339 #define HELPER_SINGLE_SPE_CMP(name) \
2340 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2341 { \
2342 return e##name(op1, op2) << 2; \
2343 }
2344 /* efststlt */
2345 HELPER_SINGLE_SPE_CMP(fststlt);
2346 /* efststgt */
2347 HELPER_SINGLE_SPE_CMP(fststgt);
2348 /* efststeq */
2349 HELPER_SINGLE_SPE_CMP(fststeq);
2350 /* efscmplt */
2351 HELPER_SINGLE_SPE_CMP(fscmplt);
2352 /* efscmpgt */
2353 HELPER_SINGLE_SPE_CMP(fscmpgt);
2354 /* efscmpeq */
2355 HELPER_SINGLE_SPE_CMP(fscmpeq);
2356
2357 static always_inline uint32_t evcmp_merge (int t0, int t1)
2358 {
2359 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2360 }
2361
2362 #define HELPER_VECTOR_SPE_CMP(name) \
2363 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2364 { \
2365 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2366 }
2367 /* evfststlt */
2368 HELPER_VECTOR_SPE_CMP(fststlt);
2369 /* evfststgt */
2370 HELPER_VECTOR_SPE_CMP(fststgt);
2371 /* evfststeq */
2372 HELPER_VECTOR_SPE_CMP(fststeq);
2373 /* evfscmplt */
2374 HELPER_VECTOR_SPE_CMP(fscmplt);
2375 /* evfscmpgt */
2376 HELPER_VECTOR_SPE_CMP(fscmpgt);
2377 /* evfscmpeq */
2378 HELPER_VECTOR_SPE_CMP(fscmpeq);
2379
2380 /* Double-precision floating-point conversion */
2381 uint64_t helper_efdcfsi (uint32_t val)
2382 {
2383 CPU_DoubleU u;
2384
2385 u.d = int32_to_float64(val, &env->spe_status);
2386
2387 return u.ll;
2388 }
2389
2390 uint64_t helper_efdcfsid (uint64_t val)
2391 {
2392 CPU_DoubleU u;
2393
2394 u.d = int64_to_float64(val, &env->spe_status);
2395
2396 return u.ll;
2397 }
2398
2399 uint64_t helper_efdcfui (uint32_t val)
2400 {
2401 CPU_DoubleU u;
2402
2403 u.d = uint32_to_float64(val, &env->spe_status);
2404
2405 return u.ll;
2406 }
2407
2408 uint64_t helper_efdcfuid (uint64_t val)
2409 {
2410 CPU_DoubleU u;
2411
2412 u.d = uint64_to_float64(val, &env->spe_status);
2413
2414 return u.ll;
2415 }
2416
2417 uint32_t helper_efdctsi (uint64_t val)
2418 {
2419 CPU_DoubleU u;
2420
2421 u.ll = val;
2422 /* NaN are not treated the same way IEEE 754 does */
2423 if (unlikely(float64_is_nan(u.d)))
2424 return 0;
2425
2426 return float64_to_int32(u.d, &env->spe_status);
2427 }
2428
2429 uint32_t helper_efdctui (uint64_t val)
2430 {
2431 CPU_DoubleU u;
2432
2433 u.ll = val;
2434 /* NaN are not treated the same way IEEE 754 does */
2435 if (unlikely(float64_is_nan(u.d)))
2436 return 0;
2437
2438 return float64_to_uint32(u.d, &env->spe_status);
2439 }
2440
2441 uint32_t helper_efdctsiz (uint64_t val)
2442 {
2443 CPU_DoubleU u;
2444
2445 u.ll = val;
2446 /* NaN are not treated the same way IEEE 754 does */
2447 if (unlikely(float64_is_nan(u.d)))
2448 return 0;
2449
2450 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2451 }
2452
2453 uint64_t helper_efdctsidz (uint64_t val)
2454 {
2455 CPU_DoubleU u;
2456
2457 u.ll = val;
2458 /* NaN are not treated the same way IEEE 754 does */
2459 if (unlikely(float64_is_nan(u.d)))
2460 return 0;
2461
2462 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2463 }
2464
2465 uint32_t helper_efdctuiz (uint64_t val)
2466 {
2467 CPU_DoubleU u;
2468
2469 u.ll = val;
2470 /* NaN are not treated the same way IEEE 754 does */
2471 if (unlikely(float64_is_nan(u.d)))
2472 return 0;
2473
2474 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2475 }
2476
2477 uint64_t helper_efdctuidz (uint64_t val)
2478 {
2479 CPU_DoubleU u;
2480
2481 u.ll = val;
2482 /* NaN are not treated the same way IEEE 754 does */
2483 if (unlikely(float64_is_nan(u.d)))
2484 return 0;
2485
2486 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2487 }
2488
2489 uint64_t helper_efdcfsf (uint32_t val)
2490 {
2491 CPU_DoubleU u;
2492 float64 tmp;
2493
2494 u.d = int32_to_float64(val, &env->spe_status);
2495 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2496 u.d = float64_div(u.d, tmp, &env->spe_status);
2497
2498 return u.ll;
2499 }
2500
2501 uint64_t helper_efdcfuf (uint32_t val)
2502 {
2503 CPU_DoubleU u;
2504 float64 tmp;
2505
2506 u.d = uint32_to_float64(val, &env->spe_status);
2507 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2508 u.d = float64_div(u.d, tmp, &env->spe_status);
2509
2510 return u.ll;
2511 }
2512
2513 uint32_t helper_efdctsf (uint64_t val)
2514 {
2515 CPU_DoubleU u;
2516 float64 tmp;
2517
2518 u.ll = val;
2519 /* NaN are not treated the same way IEEE 754 does */
2520 if (unlikely(float64_is_nan(u.d)))
2521 return 0;
2522 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2523 u.d = float64_mul(u.d, tmp, &env->spe_status);
2524
2525 return float64_to_int32(u.d, &env->spe_status);
2526 }
2527
2528 uint32_t helper_efdctuf (uint64_t val)
2529 {
2530 CPU_DoubleU u;
2531 float64 tmp;
2532
2533 u.ll = val;
2534 /* NaN are not treated the same way IEEE 754 does */
2535 if (unlikely(float64_is_nan(u.d)))
2536 return 0;
2537 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2538 u.d = float64_mul(u.d, tmp, &env->spe_status);
2539
2540 return float64_to_uint32(u.d, &env->spe_status);
2541 }
2542
2543 uint32_t helper_efscfd (uint64_t val)
2544 {
2545 CPU_DoubleU u1;
2546 CPU_FloatU u2;
2547
2548 u1.ll = val;
2549 u2.f = float64_to_float32(u1.d, &env->spe_status);
2550
2551 return u2.l;
2552 }
2553
2554 uint64_t helper_efdcfs (uint32_t val)
2555 {
2556 CPU_DoubleU u2;
2557 CPU_FloatU u1;
2558
2559 u1.l = val;
2560 u2.d = float32_to_float64(u1.f, &env->spe_status);
2561
2562 return u2.ll;
2563 }
2564
2565 /* Double precision fixed-point arithmetic */
2566 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2567 {
2568 CPU_DoubleU u1, u2;
2569 u1.ll = op1;
2570 u2.ll = op2;
2571 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2572 return u1.ll;
2573 }
2574
2575 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2576 {
2577 CPU_DoubleU u1, u2;
2578 u1.ll = op1;
2579 u2.ll = op2;
2580 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2581 return u1.ll;
2582 }
2583
2584 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2585 {
2586 CPU_DoubleU u1, u2;
2587 u1.ll = op1;
2588 u2.ll = op2;
2589 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2590 return u1.ll;
2591 }
2592
2593 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2594 {
2595 CPU_DoubleU u1, u2;
2596 u1.ll = op1;
2597 u2.ll = op2;
2598 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2599 return u1.ll;
2600 }
2601
2602 /* Double precision floating point helpers */
2603 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2604 {
2605 CPU_DoubleU u1, u2;
2606 u1.ll = op1;
2607 u2.ll = op2;
2608 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2609 }
2610
2611 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2612 {
2613 CPU_DoubleU u1, u2;
2614 u1.ll = op1;
2615 u2.ll = op2;
2616 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2617 }
2618
2619 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2620 {
2621 CPU_DoubleU u1, u2;
2622 u1.ll = op1;
2623 u2.ll = op2;
2624 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2625 }
2626
2627 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2628 {
2629 /* XXX: TODO: test special values (NaN, infinites, ...) */
2630 return helper_efdtstlt(op1, op2);
2631 }
2632
2633 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2634 {
2635 /* XXX: TODO: test special values (NaN, infinites, ...) */
2636 return helper_efdtstgt(op1, op2);
2637 }
2638
2639 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2640 {
2641 /* XXX: TODO: test special values (NaN, infinites, ...) */
2642 return helper_efdtsteq(op1, op2);
2643 }
2644
2645 /*****************************************************************************/
2646 /* Softmmu support */
2647 #if !defined (CONFIG_USER_ONLY)
2648
2649 #define MMUSUFFIX _mmu
2650
2651 #define SHIFT 0
2652 #include "softmmu_template.h"
2653
2654 #define SHIFT 1
2655 #include "softmmu_template.h"
2656
2657 #define SHIFT 2
2658 #include "softmmu_template.h"
2659
2660 #define SHIFT 3
2661 #include "softmmu_template.h"
2662
2663 /* try to fill the TLB and return an exception if error. If retaddr is
2664 NULL, it means that the function was called in C code (i.e. not
2665 from generated code or from helper.c) */
2666 /* XXX: fix it to restore all registers */
2667 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2668 {
2669 TranslationBlock *tb;
2670 CPUState *saved_env;
2671 unsigned long pc;
2672 int ret;
2673
2674 /* XXX: hack to restore env in all cases, even if not called from
2675 generated code */
2676 saved_env = env;
2677 env = cpu_single_env;
2678 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2679 if (unlikely(ret != 0)) {
2680 if (likely(retaddr)) {
2681 /* now we have a real cpu fault */
2682 pc = (unsigned long)retaddr;
2683 tb = tb_find_pc(pc);
2684 if (likely(tb)) {
2685 /* the PC is inside the translated code. It means that we have
2686 a virtual CPU fault */
2687 cpu_restore_state(tb, env, pc, NULL);
2688 }
2689 }
2690 helper_raise_exception_err(env->exception_index, env->error_code);
2691 }
2692 env = saved_env;
2693 }
2694
2695 /* Segment registers load and store */
2696 target_ulong helper_load_sr (target_ulong sr_num)
2697 {
2698 return env->sr[sr_num];
2699 }
2700
2701 void helper_store_sr (target_ulong sr_num, target_ulong val)
2702 {
2703 ppc_store_sr(env, sr_num, val);
2704 }
2705
2706 /* SLB management */
2707 #if defined(TARGET_PPC64)
2708 target_ulong helper_load_slb (target_ulong slb_nr)
2709 {
2710 return ppc_load_slb(env, slb_nr);
2711 }
2712
2713 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2714 {
2715 ppc_store_slb(env, slb_nr, rs);
2716 }
2717
2718 void helper_slbia (void)
2719 {
2720 ppc_slb_invalidate_all(env);
2721 }
2722
2723 void helper_slbie (target_ulong addr)
2724 {
2725 ppc_slb_invalidate_one(env, addr);
2726 }
2727
2728 #endif /* defined(TARGET_PPC64) */
2729
2730 /* TLB management */
2731 void helper_tlbia (void)
2732 {
2733 ppc_tlb_invalidate_all(env);
2734 }
2735
2736 void helper_tlbie (target_ulong addr)
2737 {
2738 ppc_tlb_invalidate_one(env, addr);
2739 }
2740
2741 /* Software driven TLBs management */
2742 /* PowerPC 602/603 software TLB load instructions helpers */
2743 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2744 {
2745 target_ulong RPN, CMP, EPN;
2746 int way;
2747
2748 RPN = env->spr[SPR_RPA];
2749 if (is_code) {
2750 CMP = env->spr[SPR_ICMP];
2751 EPN = env->spr[SPR_IMISS];
2752 } else {
2753 CMP = env->spr[SPR_DCMP];
2754 EPN = env->spr[SPR_DMISS];
2755 }
2756 way = (env->spr[SPR_SRR1] >> 17) & 1;
2757 #if defined (DEBUG_SOFTWARE_TLB)
2758 if (loglevel != 0) {
2759 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2760 " PTE1 " ADDRX " way %d\n",
2761 __func__, new_EPN, EPN, CMP, RPN, way);
2762 }
2763 #endif
2764 /* Store this TLB */
2765 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2766 way, is_code, CMP, RPN);
2767 }
2768
2769 void helper_6xx_tlbd (target_ulong EPN)
2770 {
2771 do_6xx_tlb(EPN, 0);
2772 }
2773
2774 void helper_6xx_tlbi (target_ulong EPN)
2775 {
2776 do_6xx_tlb(EPN, 1);
2777 }
2778
2779 /* PowerPC 74xx software TLB load instructions helpers */
2780 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2781 {
2782 target_ulong RPN, CMP, EPN;
2783 int way;
2784
2785 RPN = env->spr[SPR_PTELO];
2786 CMP = env->spr[SPR_PTEHI];
2787 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2788 way = env->spr[SPR_TLBMISS] & 0x3;
2789 #if defined (DEBUG_SOFTWARE_TLB)
2790 if (loglevel != 0) {
2791 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2792 " PTE1 " ADDRX " way %d\n",
2793 __func__, new_EPN, EPN, CMP, RPN, way);
2794 }
2795 #endif
2796 /* Store this TLB */
2797 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2798 way, is_code, CMP, RPN);
2799 }
2800
2801 void helper_74xx_tlbd (target_ulong EPN)
2802 {
2803 do_74xx_tlb(EPN, 0);
2804 }
2805
2806 void helper_74xx_tlbi (target_ulong EPN)
2807 {
2808 do_74xx_tlb(EPN, 1);
2809 }
2810
2811 static always_inline target_ulong booke_tlb_to_page_size (int size)
2812 {
2813 return 1024 << (2 * size);
2814 }
2815
2816 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2817 {
2818 int size;
2819
2820 switch (page_size) {
2821 case 0x00000400UL:
2822 size = 0x0;
2823 break;
2824 case 0x00001000UL:
2825 size = 0x1;
2826 break;
2827 case 0x00004000UL:
2828 size = 0x2;
2829 break;
2830 case 0x00010000UL:
2831 size = 0x3;
2832 break;
2833 case 0x00040000UL:
2834 size = 0x4;
2835 break;
2836 case 0x00100000UL:
2837 size = 0x5;
2838 break;
2839 case 0x00400000UL:
2840 size = 0x6;
2841 break;
2842 case 0x01000000UL:
2843 size = 0x7;
2844 break;
2845 case 0x04000000UL:
2846 size = 0x8;
2847 break;
2848 case 0x10000000UL:
2849 size = 0x9;
2850 break;
2851 case 0x40000000UL:
2852 size = 0xA;
2853 break;
2854 #if defined (TARGET_PPC64)
2855 case 0x000100000000ULL:
2856 size = 0xB;
2857 break;
2858 case 0x000400000000ULL:
2859 size = 0xC;
2860 break;
2861 case 0x001000000000ULL:
2862 size = 0xD;
2863 break;
2864 case 0x004000000000ULL:
2865 size = 0xE;
2866 break;
2867 case 0x010000000000ULL:
2868 size = 0xF;
2869 break;
2870 #endif
2871 default:
2872 size = -1;
2873 break;
2874 }
2875
2876 return size;
2877 }
2878
2879 /* Helpers for 4xx TLB management */
2880 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2881 {
2882 ppcemb_tlb_t *tlb;
2883 target_ulong ret;
2884 int size;
2885
2886 entry &= 0x3F;
2887 tlb = &env->tlb[entry].tlbe;
2888 ret = tlb->EPN;
2889 if (tlb->prot & PAGE_VALID)
2890 ret |= 0x400;
2891 size = booke_page_size_to_tlb(tlb->size);
2892 if (size < 0 || size > 0x7)
2893 size = 1;
2894 ret |= size << 7;
2895 env->spr[SPR_40x_PID] = tlb->PID;
2896 return ret;
2897 }
2898
2899 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2900 {
2901 ppcemb_tlb_t *tlb;
2902 target_ulong ret;
2903
2904 entry &= 0x3F;
2905 tlb = &env->tlb[entry].tlbe;
2906 ret = tlb->RPN;
2907 if (tlb->prot & PAGE_EXEC)
2908 ret |= 0x200;
2909 if (tlb->prot & PAGE_WRITE)
2910 ret |= 0x100;
2911 return ret;
2912 }
2913
2914 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2915 {
2916 ppcemb_tlb_t *tlb;
2917 target_ulong page, end;
2918
2919 #if defined (DEBUG_SOFTWARE_TLB)
2920 if (loglevel != 0) {
2921 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2922 }
2923 #endif
2924 entry &= 0x3F;
2925 tlb = &env->tlb[entry].tlbe;
2926 /* Invalidate previous TLB (if it's valid) */
2927 if (tlb->prot & PAGE_VALID) {
2928 end = tlb->EPN + tlb->size;
2929 #if defined (DEBUG_SOFTWARE_TLB)
2930 if (loglevel != 0) {
2931 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2932 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2933 }
2934 #endif
2935 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2936 tlb_flush_page(env, page);
2937 }
2938 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2939 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2940 * If this ever occurs, one should use the ppcemb target instead
2941 * of the ppc or ppc64 one
2942 */
2943 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2944 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2945 "are not supported (%d)\n",
2946 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2947 }
2948 tlb->EPN = val & ~(tlb->size - 1);
2949 if (val & 0x40)
2950 tlb->prot |= PAGE_VALID;
2951 else
2952 tlb->prot &= ~PAGE_VALID;
2953 if (val & 0x20) {
2954 /* XXX: TO BE FIXED */
2955 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2956 }
2957 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2958 tlb->attr = val & 0xFF;
2959 #if defined (DEBUG_SOFTWARE_TLB)
2960 if (loglevel != 0) {
2961 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2962 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2963 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2964 tlb->prot & PAGE_READ ? 'r' : '-',
2965 tlb->prot & PAGE_WRITE ? 'w' : '-',
2966 tlb->prot & PAGE_EXEC ? 'x' : '-',
2967 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2968 }
2969 #endif
2970 /* Invalidate new TLB (if valid) */
2971 if (tlb->prot & PAGE_VALID) {
2972 end = tlb->EPN + tlb->size;
2973 #if defined (DEBUG_SOFTWARE_TLB)
2974 if (loglevel != 0) {
2975 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2976 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2977 }
2978 #endif
2979 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2980 tlb_flush_page(env, page);
2981 }
2982 }
2983
2984 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2985 {
2986 ppcemb_tlb_t *tlb;
2987
2988 #if defined (DEBUG_SOFTWARE_TLB)
2989 if (loglevel != 0) {
2990 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2991 }
2992 #endif
2993 entry &= 0x3F;
2994 tlb = &env->tlb[entry].tlbe;
2995 tlb->RPN = val & 0xFFFFFC00;
2996 tlb->prot = PAGE_READ;
2997 if (val & 0x200)
2998 tlb->prot |= PAGE_EXEC;
2999 if (val & 0x100)
3000 tlb->prot |= PAGE_WRITE;
3001 #if defined (DEBUG_SOFTWARE_TLB)
3002 if (loglevel != 0) {
3003 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3004 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3005 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3006 tlb->prot & PAGE_READ ? 'r' : '-',
3007 tlb->prot & PAGE_WRITE ? 'w' : '-',
3008 tlb->prot & PAGE_EXEC ? 'x' : '-',
3009 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3010 }
3011 #endif
3012 }
3013
3014 target_ulong helper_4xx_tlbsx (target_ulong address)
3015 {
3016 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3017 }
3018
3019 /* PowerPC 440 TLB management */
3020 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3021 {
3022 ppcemb_tlb_t *tlb;
3023 target_ulong EPN, RPN, size;
3024 int do_flush_tlbs;
3025
3026 #if defined (DEBUG_SOFTWARE_TLB)
3027 if (loglevel != 0) {
3028 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3029 __func__, word, (int)entry, value);
3030 }
3031 #endif
3032 do_flush_tlbs = 0;
3033 entry &= 0x3F;
3034 tlb = &env->tlb[entry].tlbe;
3035 switch (word) {
3036 default:
3037 /* Just here to please gcc */
3038 case 0:
3039 EPN = value & 0xFFFFFC00;
3040 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3041 do_flush_tlbs = 1;
3042 tlb->EPN = EPN;
3043 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3044 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3045 do_flush_tlbs = 1;
3046 tlb->size = size;
3047 tlb->attr &= ~0x1;
3048 tlb->attr |= (value >> 8) & 1;
3049 if (value & 0x200) {
3050 tlb->prot |= PAGE_VALID;
3051 } else {
3052 if (tlb->prot & PAGE_VALID) {
3053 tlb->prot &= ~PAGE_VALID;
3054 do_flush_tlbs = 1;
3055 }
3056 }
3057 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3058 if (do_flush_tlbs)
3059 tlb_flush(env, 1);
3060 break;
3061 case 1:
3062 RPN = value & 0xFFFFFC0F;
3063 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3064 tlb_flush(env, 1);
3065 tlb->RPN = RPN;
3066 break;
3067 case 2:
3068 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3069 tlb->prot = tlb->prot & PAGE_VALID;
3070 if (value & 0x1)
3071 tlb->prot |= PAGE_READ << 4;
3072 if (value & 0x2)
3073 tlb->prot |= PAGE_WRITE << 4;
3074 if (value & 0x4)
3075 tlb->prot |= PAGE_EXEC << 4;
3076 if (value & 0x8)
3077 tlb->prot |= PAGE_READ;
3078 if (value & 0x10)
3079 tlb->prot |= PAGE_WRITE;
3080 if (value & 0x20)
3081 tlb->prot |= PAGE_EXEC;
3082 break;
3083 }
3084 }
3085
3086 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3087 {
3088 ppcemb_tlb_t *tlb;
3089 target_ulong ret;
3090 int size;
3091
3092 entry &= 0x3F;
3093 tlb = &env->tlb[entry].tlbe;
3094 switch (word) {
3095 default:
3096 /* Just here to please gcc */
3097 case 0:
3098 ret = tlb->EPN;
3099 size = booke_page_size_to_tlb(tlb->size);
3100 if (size < 0 || size > 0xF)
3101 size = 1;
3102 ret |= size << 4;
3103 if (tlb->attr & 0x1)
3104 ret |= 0x100;
3105 if (tlb->prot & PAGE_VALID)
3106 ret |= 0x200;
3107 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3108 env->spr[SPR_440_MMUCR] |= tlb->PID;
3109 break;
3110 case 1:
3111 ret = tlb->RPN;
3112 break;
3113 case 2:
3114 ret = tlb->attr & ~0x1;
3115 if (tlb->prot & (PAGE_READ << 4))
3116 ret |= 0x1;
3117 if (tlb->prot & (PAGE_WRITE << 4))
3118 ret |= 0x2;
3119 if (tlb->prot & (PAGE_EXEC << 4))
3120 ret |= 0x4;
3121 if (tlb->prot & PAGE_READ)
3122 ret |= 0x8;
3123 if (tlb->prot & PAGE_WRITE)
3124 ret |= 0x10;
3125 if (tlb->prot & PAGE_EXEC)
3126 ret |= 0x20;
3127 break;
3128 }
3129 return ret;
3130 }
3131
3132 target_ulong helper_440_tlbsx (target_ulong address)
3133 {
3134 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3135 }
3136
3137 #endif /* !CONFIG_USER_ONLY */
jz4740 based target emulation