4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #define SH4_DEBUG_DISAS
29 //#define SH4_SINGLE_STEP
35 #include "qemu-common.h"
41 typedef struct DisasContext
{
42 struct TranslationBlock
*tb
;
51 int singlestep_enabled
;
55 #if defined(CONFIG_USER_ONLY)
56 #define IS_USER(ctx) 1
58 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
62 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
65 BS_STOP
= 1, /* We want to stop translation for any reason */
66 BS_BRANCH
= 2, /* We reached a branch condition */
67 BS_EXCP
= 3, /* We reached an exception condition */
70 /* global register indexes */
71 static TCGv_ptr cpu_env
;
72 static TCGv cpu_gregs
[24];
73 static TCGv cpu_pc
, cpu_sr
, cpu_ssr
, cpu_spc
, cpu_gbr
;
74 static TCGv cpu_vbr
, cpu_sgr
, cpu_dbr
, cpu_mach
, cpu_macl
;
75 static TCGv cpu_pr
, cpu_fpscr
, cpu_fpul
;
76 static TCGv cpu_fregs
[32];
78 /* internal register indexes */
79 static TCGv cpu_flags
, cpu_delayed_pc
;
81 #include "gen-icount.h"
83 static void sh4_translate_init(void)
86 static int done_init
= 0;
87 static const char * const gregnames
[24] = {
88 "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
89 "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
90 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
91 "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
92 "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
94 static const char * const fregnames
[32] = {
95 "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
96 "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
97 "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
98 "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
99 "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
100 "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
101 "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
102 "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
108 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
110 for (i
= 0; i
< 24; i
++)
111 cpu_gregs
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
112 offsetof(CPUState
, gregs
[i
]),
115 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
116 offsetof(CPUState
, pc
), "PC");
117 cpu_sr
= tcg_global_mem_new_i32(TCG_AREG0
,
118 offsetof(CPUState
, sr
), "SR");
119 cpu_ssr
= tcg_global_mem_new_i32(TCG_AREG0
,
120 offsetof(CPUState
, ssr
), "SSR");
121 cpu_spc
= tcg_global_mem_new_i32(TCG_AREG0
,
122 offsetof(CPUState
, spc
), "SPC");
123 cpu_gbr
= tcg_global_mem_new_i32(TCG_AREG0
,
124 offsetof(CPUState
, gbr
), "GBR");
125 cpu_vbr
= tcg_global_mem_new_i32(TCG_AREG0
,
126 offsetof(CPUState
, vbr
), "VBR");
127 cpu_sgr
= tcg_global_mem_new_i32(TCG_AREG0
,
128 offsetof(CPUState
, sgr
), "SGR");
129 cpu_dbr
= tcg_global_mem_new_i32(TCG_AREG0
,
130 offsetof(CPUState
, dbr
), "DBR");
131 cpu_mach
= tcg_global_mem_new_i32(TCG_AREG0
,
132 offsetof(CPUState
, mach
), "MACH");
133 cpu_macl
= tcg_global_mem_new_i32(TCG_AREG0
,
134 offsetof(CPUState
, macl
), "MACL");
135 cpu_pr
= tcg_global_mem_new_i32(TCG_AREG0
,
136 offsetof(CPUState
, pr
), "PR");
137 cpu_fpscr
= tcg_global_mem_new_i32(TCG_AREG0
,
138 offsetof(CPUState
, fpscr
), "FPSCR");
139 cpu_fpul
= tcg_global_mem_new_i32(TCG_AREG0
,
140 offsetof(CPUState
, fpul
), "FPUL");
142 cpu_flags
= tcg_global_mem_new_i32(TCG_AREG0
,
143 offsetof(CPUState
, flags
), "_flags_");
144 cpu_delayed_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
145 offsetof(CPUState
, delayed_pc
),
148 for (i
= 0; i
< 32; i
++)
149 cpu_fregs
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
150 offsetof(CPUState
, fregs
[i
]),
153 /* register helpers */
160 void cpu_dump_state(CPUState
* env
, FILE * f
,
161 int (*cpu_fprintf
) (FILE * f
, const char *fmt
, ...),
165 cpu_fprintf(f
, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
166 env
->pc
, env
->sr
, env
->pr
, env
->fpscr
);
167 cpu_fprintf(f
, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
168 env
->spc
, env
->ssr
, env
->gbr
, env
->vbr
);
169 cpu_fprintf(f
, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
170 env
->sgr
, env
->dbr
, env
->delayed_pc
, env
->fpul
);
171 for (i
= 0; i
< 24; i
+= 4) {
172 cpu_fprintf(f
, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
173 i
, env
->gregs
[i
], i
+ 1, env
->gregs
[i
+ 1],
174 i
+ 2, env
->gregs
[i
+ 2], i
+ 3, env
->gregs
[i
+ 3]);
176 if (env
->flags
& DELAY_SLOT
) {
177 cpu_fprintf(f
, "in delay slot (delayed_pc=0x%08x)\n",
179 } else if (env
->flags
& DELAY_SLOT_CONDITIONAL
) {
180 cpu_fprintf(f
, "in conditional delay slot (delayed_pc=0x%08x)\n",
185 static void cpu_sh4_reset(CPUSH4State
* env
)
187 #if defined(CONFIG_USER_ONLY)
190 env
->sr
= SR_MD
| SR_RB
| SR_BL
| SR_I3
| SR_I2
| SR_I1
| SR_I0
;
193 env
->pc
= 0xA0000000;
194 #if defined(CONFIG_USER_ONLY)
195 env
->fpscr
= FPSCR_PR
; /* value for userspace according to the kernel */
196 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
); /* ?! */
198 env
->fpscr
= 0x00040001; /* CPU reset value according to SH4 manual */
199 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
213 static sh4_def_t sh4_defs
[] = {
216 .id
= SH_CPU_SH7750R
,
222 .id
= SH_CPU_SH7751R
,
225 .cvr
= 0x00110000, /* Neutered caches, should be 0x20480000 */
232 .features
= SH_FEATURE_SH4A
,
236 static const sh4_def_t
*cpu_sh4_find_by_name(const char *name
)
240 if (strcasecmp(name
, "any") == 0)
243 for (i
= 0; i
< sizeof(sh4_defs
) / sizeof(*sh4_defs
); i
++)
244 if (strcasecmp(name
, sh4_defs
[i
].name
) == 0)
250 void sh4_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
254 for (i
= 0; i
< sizeof(sh4_defs
) / sizeof(*sh4_defs
); i
++)
255 (*cpu_fprintf
)(f
, "%s\n", sh4_defs
[i
].name
);
258 static void cpu_sh4_register(CPUSH4State
*env
, const sh4_def_t
*def
)
266 CPUSH4State
*cpu_sh4_init(const char *cpu_model
)
269 const sh4_def_t
*def
;
271 def
= cpu_sh4_find_by_name(cpu_model
);
274 env
= qemu_mallocz(sizeof(CPUSH4State
));
277 env
->features
= def
->features
;
279 sh4_translate_init();
280 env
->cpu_model_str
= cpu_model
;
282 cpu_sh4_register(env
, def
);
287 static void gen_goto_tb(DisasContext
* ctx
, int n
, target_ulong dest
)
289 TranslationBlock
*tb
;
292 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
293 !ctx
->singlestep_enabled
) {
294 /* Use a direct jump if in same page and singlestep not enabled */
296 tcg_gen_movi_i32(cpu_pc
, dest
);
297 tcg_gen_exit_tb((long) tb
+ n
);
299 tcg_gen_movi_i32(cpu_pc
, dest
);
300 if (ctx
->singlestep_enabled
)
306 static void gen_jump(DisasContext
* ctx
)
308 if (ctx
->delayed_pc
== (uint32_t) - 1) {
309 /* Target is not statically known, it comes necessarily from a
310 delayed jump as immediate jump are conditinal jumps */
311 tcg_gen_mov_i32(cpu_pc
, cpu_delayed_pc
);
312 if (ctx
->singlestep_enabled
)
316 gen_goto_tb(ctx
, 0, ctx
->delayed_pc
);
320 static inline void gen_branch_slot(uint32_t delayed_pc
, int t
)
323 int label
= gen_new_label();
324 tcg_gen_movi_i32(cpu_delayed_pc
, delayed_pc
);
326 tcg_gen_andi_i32(sr
, cpu_sr
, SR_T
);
327 tcg_gen_brcondi_i32(TCG_COND_NE
, sr
, t
? SR_T
: 0, label
);
328 tcg_gen_ori_i32(cpu_flags
, cpu_flags
, DELAY_SLOT_TRUE
);
329 gen_set_label(label
);
332 /* Immediate conditional jump (bt or bf) */
333 static void gen_conditional_jump(DisasContext
* ctx
,
334 target_ulong ift
, target_ulong ifnott
)
339 l1
= gen_new_label();
341 tcg_gen_andi_i32(sr
, cpu_sr
, SR_T
);
342 tcg_gen_brcondi_i32(TCG_COND_EQ
, sr
, SR_T
, l1
);
343 gen_goto_tb(ctx
, 0, ifnott
);
345 gen_goto_tb(ctx
, 1, ift
);
348 /* Delayed conditional jump (bt or bf) */
349 static void gen_delayed_conditional_jump(DisasContext
* ctx
)
354 l1
= gen_new_label();
356 tcg_gen_andi_i32(ds
, cpu_flags
, DELAY_SLOT_TRUE
);
357 tcg_gen_brcondi_i32(TCG_COND_EQ
, ds
, DELAY_SLOT_TRUE
, l1
);
358 gen_goto_tb(ctx
, 1, ctx
->pc
+ 2);
360 tcg_gen_andi_i32(cpu_flags
, cpu_flags
, ~DELAY_SLOT_TRUE
);
364 static inline void gen_set_t(void)
366 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, SR_T
);
369 static inline void gen_clr_t(void)
371 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~SR_T
);
374 static inline void gen_cmp(int cond
, TCGv t0
, TCGv t1
)
376 int label1
= gen_new_label();
377 int label2
= gen_new_label();
378 tcg_gen_brcond_i32(cond
, t1
, t0
, label1
);
381 gen_set_label(label1
);
383 gen_set_label(label2
);
386 static inline void gen_cmp_imm(int cond
, TCGv t0
, int32_t imm
)
388 int label1
= gen_new_label();
389 int label2
= gen_new_label();
390 tcg_gen_brcondi_i32(cond
, t0
, imm
, label1
);
393 gen_set_label(label1
);
395 gen_set_label(label2
);
398 static inline void gen_store_flags(uint32_t flags
)
400 tcg_gen_andi_i32(cpu_flags
, cpu_flags
, DELAY_SLOT_TRUE
);
401 tcg_gen_ori_i32(cpu_flags
, cpu_flags
, flags
);
404 static inline void gen_copy_bit_i32(TCGv t0
, int p0
, TCGv t1
, int p1
)
406 TCGv tmp
= tcg_temp_new();
411 tcg_gen_andi_i32(tmp
, t1
, (1 << p1
));
412 tcg_gen_andi_i32(t0
, t0
, ~(1 << p0
));
414 tcg_gen_shri_i32(tmp
, tmp
, p1
- p0
);
416 tcg_gen_shli_i32(tmp
, tmp
, p0
- p1
);
417 tcg_gen_or_i32(t0
, t0
, tmp
);
422 static inline void gen_load_fpr64(TCGv_i64 t
, int reg
)
424 tcg_gen_concat_i32_i64(t
, cpu_fregs
[reg
+ 1], cpu_fregs
[reg
]);
427 static inline void gen_store_fpr64 (TCGv_i64 t
, int reg
)
429 TCGv_i32 tmp
= tcg_temp_new_i32();
430 tcg_gen_trunc_i64_i32(tmp
, t
);
431 tcg_gen_mov_i32(cpu_fregs
[reg
+ 1], tmp
);
432 tcg_gen_shri_i64(t
, t
, 32);
433 tcg_gen_trunc_i64_i32(tmp
, t
);
434 tcg_gen_mov_i32(cpu_fregs
[reg
], tmp
);
435 tcg_temp_free_i32(tmp
);
438 #define B3_0 (ctx->opcode & 0xf)
439 #define B6_4 ((ctx->opcode >> 4) & 0x7)
440 #define B7_4 ((ctx->opcode >> 4) & 0xf)
441 #define B7_0 (ctx->opcode & 0xff)
442 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
443 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
444 (ctx->opcode & 0xfff))
445 #define B11_8 ((ctx->opcode >> 8) & 0xf)
446 #define B15_12 ((ctx->opcode >> 12) & 0xf)
448 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
449 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
451 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
452 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
454 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
455 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
456 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
457 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
459 #define CHECK_NOT_DELAY_SLOT \
460 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
462 tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
463 gen_helper_raise_slot_illegal_instruction(); \
464 ctx->bstate = BS_EXCP; \
468 #define CHECK_PRIVILEGED \
469 if (IS_USER(ctx)) { \
470 tcg_gen_movi_i32(cpu_pc, ctx->pc); \
471 gen_helper_raise_illegal_instruction(); \
472 ctx->bstate = BS_EXCP; \
476 #define CHECK_FPU_ENABLED \
477 if (ctx->flags & SR_FD) { \
478 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
479 tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
480 gen_helper_raise_slot_fpu_disable(); \
482 tcg_gen_movi_i32(cpu_pc, ctx->pc); \
483 gen_helper_raise_fpu_disable(); \
485 ctx->bstate = BS_EXCP; \
489 static void _decode_opc(DisasContext
* ctx
)
492 fprintf(stderr
, "Translating opcode 0x%04x\n", ctx
->opcode
);
495 switch (ctx
->opcode
) {
496 case 0x0019: /* div0u */
497 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~(SR_M
| SR_Q
| SR_T
));
499 case 0x000b: /* rts */
501 tcg_gen_mov_i32(cpu_delayed_pc
, cpu_pr
);
502 ctx
->flags
|= DELAY_SLOT
;
503 ctx
->delayed_pc
= (uint32_t) - 1;
505 case 0x0028: /* clrmac */
506 tcg_gen_movi_i32(cpu_mach
, 0);
507 tcg_gen_movi_i32(cpu_macl
, 0);
509 case 0x0048: /* clrs */
510 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~SR_S
);
512 case 0x0008: /* clrt */
515 case 0x0038: /* ldtlb */
519 case 0x002b: /* rte */
522 tcg_gen_mov_i32(cpu_sr
, cpu_ssr
);
523 tcg_gen_mov_i32(cpu_delayed_pc
, cpu_spc
);
524 ctx
->flags
|= DELAY_SLOT
;
525 ctx
->delayed_pc
= (uint32_t) - 1;
527 case 0x0058: /* sets */
528 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, SR_S
);
530 case 0x0018: /* sett */
533 case 0xfbfd: /* frchg */
534 tcg_gen_xori_i32(cpu_fpscr
, cpu_fpscr
, FPSCR_FR
);
535 ctx
->bstate
= BS_STOP
;
537 case 0xf3fd: /* fschg */
538 tcg_gen_xori_i32(cpu_fpscr
, cpu_fpscr
, FPSCR_SZ
);
539 ctx
->bstate
= BS_STOP
;
541 case 0x0009: /* nop */
543 case 0x001b: /* sleep */
545 gen_helper_sleep(tcg_const_i32(ctx
->pc
+ 2));
549 switch (ctx
->opcode
& 0xf000) {
550 case 0x1000: /* mov.l Rm,@(disp,Rn) */
552 TCGv addr
= tcg_temp_new();
553 tcg_gen_addi_i32(addr
, REG(B11_8
), B3_0
* 4);
554 tcg_gen_qemu_st32(REG(B7_4
), addr
, ctx
->memidx
);
558 case 0x5000: /* mov.l @(disp,Rm),Rn */
560 TCGv addr
= tcg_temp_new();
561 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
* 4);
562 tcg_gen_qemu_ld32s(REG(B11_8
), addr
, ctx
->memidx
);
566 case 0xe000: /* mov #imm,Rn */
567 tcg_gen_movi_i32(REG(B11_8
), B7_0s
);
569 case 0x9000: /* mov.w @(disp,PC),Rn */
571 TCGv addr
= tcg_const_i32(ctx
->pc
+ 4 + B7_0
* 2);
572 tcg_gen_qemu_ld16s(REG(B11_8
), addr
, ctx
->memidx
);
576 case 0xd000: /* mov.l @(disp,PC),Rn */
578 TCGv addr
= tcg_const_i32((ctx
->pc
+ 4 + B7_0
* 4) & ~3);
579 tcg_gen_qemu_ld32s(REG(B11_8
), addr
, ctx
->memidx
);
583 case 0x7000: /* add #imm,Rn */
584 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), B7_0s
);
586 case 0xa000: /* bra disp */
588 ctx
->delayed_pc
= ctx
->pc
+ 4 + B11_0s
* 2;
589 tcg_gen_movi_i32(cpu_delayed_pc
, ctx
->delayed_pc
);
590 ctx
->flags
|= DELAY_SLOT
;
592 case 0xb000: /* bsr disp */
594 tcg_gen_movi_i32(cpu_pr
, ctx
->pc
+ 4);
595 ctx
->delayed_pc
= ctx
->pc
+ 4 + B11_0s
* 2;
596 tcg_gen_movi_i32(cpu_delayed_pc
, ctx
->delayed_pc
);
597 ctx
->flags
|= DELAY_SLOT
;
601 switch (ctx
->opcode
& 0xf00f) {
602 case 0x6003: /* mov Rm,Rn */
603 tcg_gen_mov_i32(REG(B11_8
), REG(B7_4
));
605 case 0x2000: /* mov.b Rm,@Rn */
606 tcg_gen_qemu_st8(REG(B7_4
), REG(B11_8
), ctx
->memidx
);
608 case 0x2001: /* mov.w Rm,@Rn */
609 tcg_gen_qemu_st16(REG(B7_4
), REG(B11_8
), ctx
->memidx
);
611 case 0x2002: /* mov.l Rm,@Rn */
612 tcg_gen_qemu_st32(REG(B7_4
), REG(B11_8
), ctx
->memidx
);
614 case 0x6000: /* mov.b @Rm,Rn */
615 tcg_gen_qemu_ld8s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
617 case 0x6001: /* mov.w @Rm,Rn */
618 tcg_gen_qemu_ld16s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
620 case 0x6002: /* mov.l @Rm,Rn */
621 tcg_gen_qemu_ld32s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
623 case 0x2004: /* mov.b Rm,@-Rn */
625 TCGv addr
= tcg_temp_new();
626 tcg_gen_subi_i32(addr
, REG(B11_8
), 1);
627 tcg_gen_qemu_st8(REG(B7_4
), addr
, ctx
->memidx
); /* might cause re-execution */
628 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 1); /* modify register status */
632 case 0x2005: /* mov.w Rm,@-Rn */
634 TCGv addr
= tcg_temp_new();
635 tcg_gen_subi_i32(addr
, REG(B11_8
), 2);
636 tcg_gen_qemu_st16(REG(B7_4
), addr
, ctx
->memidx
);
637 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 2);
641 case 0x2006: /* mov.l Rm,@-Rn */
643 TCGv addr
= tcg_temp_new();
644 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
645 tcg_gen_qemu_st32(REG(B7_4
), addr
, ctx
->memidx
);
646 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
649 case 0x6004: /* mov.b @Rm+,Rn */
650 tcg_gen_qemu_ld8s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
652 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 1);
654 case 0x6005: /* mov.w @Rm+,Rn */
655 tcg_gen_qemu_ld16s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
657 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 2);
659 case 0x6006: /* mov.l @Rm+,Rn */
660 tcg_gen_qemu_ld32s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
662 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 4);
664 case 0x0004: /* mov.b Rm,@(R0,Rn) */
666 TCGv addr
= tcg_temp_new();
667 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
668 tcg_gen_qemu_st8(REG(B7_4
), addr
, ctx
->memidx
);
672 case 0x0005: /* mov.w Rm,@(R0,Rn) */
674 TCGv addr
= tcg_temp_new();
675 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
676 tcg_gen_qemu_st16(REG(B7_4
), addr
, ctx
->memidx
);
680 case 0x0006: /* mov.l Rm,@(R0,Rn) */
682 TCGv addr
= tcg_temp_new();
683 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
684 tcg_gen_qemu_st32(REG(B7_4
), addr
, ctx
->memidx
);
688 case 0x000c: /* mov.b @(R0,Rm),Rn */
690 TCGv addr
= tcg_temp_new();
691 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
692 tcg_gen_qemu_ld8s(REG(B11_8
), addr
, ctx
->memidx
);
696 case 0x000d: /* mov.w @(R0,Rm),Rn */
698 TCGv addr
= tcg_temp_new();
699 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
700 tcg_gen_qemu_ld16s(REG(B11_8
), addr
, ctx
->memidx
);
704 case 0x000e: /* mov.l @(R0,Rm),Rn */
706 TCGv addr
= tcg_temp_new();
707 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
708 tcg_gen_qemu_ld32s(REG(B11_8
), addr
, ctx
->memidx
);
712 case 0x6008: /* swap.b Rm,Rn */
714 TCGv highw
, high
, low
;
715 highw
= tcg_temp_new();
716 tcg_gen_andi_i32(highw
, REG(B7_4
), 0xffff0000);
717 high
= tcg_temp_new();
718 tcg_gen_ext8u_i32(high
, REG(B7_4
));
719 tcg_gen_shli_i32(high
, high
, 8);
720 low
= tcg_temp_new();
721 tcg_gen_shri_i32(low
, REG(B7_4
), 8);
722 tcg_gen_ext8u_i32(low
, low
);
723 tcg_gen_or_i32(REG(B11_8
), high
, low
);
724 tcg_gen_or_i32(REG(B11_8
), REG(B11_8
), highw
);
729 case 0x6009: /* swap.w Rm,Rn */
732 high
= tcg_temp_new();
733 tcg_gen_ext16u_i32(high
, REG(B7_4
));
734 tcg_gen_shli_i32(high
, high
, 16);
735 low
= tcg_temp_new();
736 tcg_gen_shri_i32(low
, REG(B7_4
), 16);
737 tcg_gen_ext16u_i32(low
, low
);
738 tcg_gen_or_i32(REG(B11_8
), high
, low
);
743 case 0x200d: /* xtrct Rm,Rn */
746 high
= tcg_temp_new();
747 tcg_gen_ext16u_i32(high
, REG(B7_4
));
748 tcg_gen_shli_i32(high
, high
, 16);
749 low
= tcg_temp_new();
750 tcg_gen_shri_i32(low
, REG(B11_8
), 16);
751 tcg_gen_ext16u_i32(low
, low
);
752 tcg_gen_or_i32(REG(B11_8
), high
, low
);
757 case 0x300c: /* add Rm,Rn */
758 tcg_gen_add_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
760 case 0x300e: /* addc Rm,Rn */
761 gen_helper_addc(REG(B11_8
), REG(B7_4
), REG(B11_8
));
763 case 0x300f: /* addv Rm,Rn */
764 gen_helper_addv(REG(B11_8
), REG(B7_4
), REG(B11_8
));
766 case 0x2009: /* and Rm,Rn */
767 tcg_gen_and_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
769 case 0x3000: /* cmp/eq Rm,Rn */
770 gen_cmp(TCG_COND_EQ
, REG(B7_4
), REG(B11_8
));
772 case 0x3003: /* cmp/ge Rm,Rn */
773 gen_cmp(TCG_COND_GE
, REG(B7_4
), REG(B11_8
));
775 case 0x3007: /* cmp/gt Rm,Rn */
776 gen_cmp(TCG_COND_GT
, REG(B7_4
), REG(B11_8
));
778 case 0x3006: /* cmp/hi Rm,Rn */
779 gen_cmp(TCG_COND_GTU
, REG(B7_4
), REG(B11_8
));
781 case 0x3002: /* cmp/hs Rm,Rn */
782 gen_cmp(TCG_COND_GEU
, REG(B7_4
), REG(B11_8
));
784 case 0x200c: /* cmp/str Rm,Rn */
786 int label1
= gen_new_label();
787 int label2
= gen_new_label();
788 TCGv cmp1
= tcg_temp_local_new(TCG_TYPE_I32
);
789 TCGv cmp2
= tcg_temp_local_new(TCG_TYPE_I32
);
790 tcg_gen_xor_i32(cmp1
, REG(B7_4
), REG(B11_8
));
791 tcg_gen_andi_i32(cmp2
, cmp1
, 0xff000000);
792 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
793 tcg_gen_andi_i32(cmp2
, cmp1
, 0x00ff0000);
794 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
795 tcg_gen_andi_i32(cmp2
, cmp1
, 0x0000ff00);
796 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
797 tcg_gen_andi_i32(cmp2
, cmp1
, 0x000000ff);
798 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
799 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~SR_T
);
801 gen_set_label(label1
);
802 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, SR_T
);
803 gen_set_label(label2
);
808 case 0x2007: /* div0s Rm,Rn */
810 gen_copy_bit_i32(cpu_sr
, 8, REG(B11_8
), 31); /* SR_Q */
811 gen_copy_bit_i32(cpu_sr
, 9, REG(B7_4
), 31); /* SR_M */
812 TCGv val
= tcg_temp_new();
813 tcg_gen_xor_i32(val
, REG(B7_4
), REG(B11_8
));
814 gen_copy_bit_i32(cpu_sr
, 0, val
, 31); /* SR_T */
818 case 0x3004: /* div1 Rm,Rn */
819 gen_helper_div1(REG(B11_8
), REG(B7_4
), REG(B11_8
));
821 case 0x300d: /* dmuls.l Rm,Rn */
823 TCGv_i64 tmp1
= tcg_temp_new_i64();
824 TCGv_i64 tmp2
= tcg_temp_new_i64();
826 tcg_gen_ext_i32_i64(tmp1
, REG(B7_4
));
827 tcg_gen_ext_i32_i64(tmp2
, REG(B11_8
));
828 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
829 tcg_gen_trunc_i64_i32(cpu_macl
, tmp1
);
830 tcg_gen_shri_i64(tmp1
, tmp1
, 32);
831 tcg_gen_trunc_i64_i32(cpu_mach
, tmp1
);
833 tcg_temp_free_i64(tmp2
);
834 tcg_temp_free_i64(tmp1
);
837 case 0x3005: /* dmulu.l Rm,Rn */
839 TCGv_i64 tmp1
= tcg_temp_new_i64();
840 TCGv_i64 tmp2
= tcg_temp_new_i64();
842 tcg_gen_extu_i32_i64(tmp1
, REG(B7_4
));
843 tcg_gen_extu_i32_i64(tmp2
, REG(B11_8
));
844 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
845 tcg_gen_trunc_i64_i32(cpu_macl
, tmp1
);
846 tcg_gen_shri_i64(tmp1
, tmp1
, 32);
847 tcg_gen_trunc_i64_i32(cpu_mach
, tmp1
);
849 tcg_temp_free_i64(tmp2
);
850 tcg_temp_free_i64(tmp1
);
853 case 0x600e: /* exts.b Rm,Rn */
854 tcg_gen_ext8s_i32(REG(B11_8
), REG(B7_4
));
856 case 0x600f: /* exts.w Rm,Rn */
857 tcg_gen_ext16s_i32(REG(B11_8
), REG(B7_4
));
859 case 0x600c: /* extu.b Rm,Rn */
860 tcg_gen_ext8u_i32(REG(B11_8
), REG(B7_4
));
862 case 0x600d: /* extu.w Rm,Rn */
863 tcg_gen_ext16u_i32(REG(B11_8
), REG(B7_4
));
865 case 0x000f: /* mac.l @Rm+,@Rn+ */
868 arg0
= tcg_temp_new();
869 tcg_gen_qemu_ld32s(arg0
, REG(B7_4
), ctx
->memidx
);
870 arg1
= tcg_temp_new();
871 tcg_gen_qemu_ld32s(arg1
, REG(B11_8
), ctx
->memidx
);
872 gen_helper_macl(arg0
, arg1
);
875 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 4);
876 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
879 case 0x400f: /* mac.w @Rm+,@Rn+ */
882 arg0
= tcg_temp_new();
883 tcg_gen_qemu_ld32s(arg0
, REG(B7_4
), ctx
->memidx
);
884 arg1
= tcg_temp_new();
885 tcg_gen_qemu_ld32s(arg1
, REG(B11_8
), ctx
->memidx
);
886 gen_helper_macw(arg0
, arg1
);
889 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 2);
890 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 2);
893 case 0x0007: /* mul.l Rm,Rn */
894 tcg_gen_mul_i32(cpu_macl
, REG(B7_4
), REG(B11_8
));
896 case 0x200f: /* muls.w Rm,Rn */
899 arg0
= tcg_temp_new();
900 tcg_gen_ext16s_i32(arg0
, REG(B7_4
));
901 arg1
= tcg_temp_new();
902 tcg_gen_ext16s_i32(arg1
, REG(B11_8
));
903 tcg_gen_mul_i32(cpu_macl
, arg0
, arg1
);
908 case 0x200e: /* mulu.w Rm,Rn */
911 arg0
= tcg_temp_new();
912 tcg_gen_ext16u_i32(arg0
, REG(B7_4
));
913 arg1
= tcg_temp_new();
914 tcg_gen_ext16u_i32(arg1
, REG(B11_8
));
915 tcg_gen_mul_i32(cpu_macl
, arg0
, arg1
);
920 case 0x600b: /* neg Rm,Rn */
921 tcg_gen_neg_i32(REG(B11_8
), REG(B7_4
));
923 case 0x600a: /* negc Rm,Rn */
924 gen_helper_negc(REG(B11_8
), REG(B7_4
));
926 case 0x6007: /* not Rm,Rn */
927 tcg_gen_not_i32(REG(B11_8
), REG(B7_4
));
929 case 0x200b: /* or Rm,Rn */
930 tcg_gen_or_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
932 case 0x400c: /* shad Rm,Rn */
934 int label1
= gen_new_label();
935 int label2
= gen_new_label();
936 int label3
= gen_new_label();
937 int label4
= gen_new_label();
938 TCGv shift
= tcg_temp_local_new(TCG_TYPE_I32
);
939 tcg_gen_brcondi_i32(TCG_COND_LT
, REG(B7_4
), 0, label1
);
940 /* Rm positive, shift to the left */
941 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
942 tcg_gen_shl_i32(REG(B11_8
), REG(B11_8
), shift
);
944 /* Rm negative, shift to the right */
945 gen_set_label(label1
);
946 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
947 tcg_gen_brcondi_i32(TCG_COND_EQ
, shift
, 0, label2
);
948 tcg_gen_not_i32(shift
, REG(B7_4
));
949 tcg_gen_andi_i32(shift
, shift
, 0x1f);
950 tcg_gen_addi_i32(shift
, shift
, 1);
951 tcg_gen_sar_i32(REG(B11_8
), REG(B11_8
), shift
);
954 gen_set_label(label2
);
955 tcg_gen_brcondi_i32(TCG_COND_LT
, REG(B11_8
), 0, label3
);
956 tcg_gen_movi_i32(REG(B11_8
), 0);
958 gen_set_label(label3
);
959 tcg_gen_movi_i32(REG(B11_8
), 0xffffffff);
960 gen_set_label(label4
);
961 tcg_temp_free(shift
);
964 case 0x400d: /* shld Rm,Rn */
966 int label1
= gen_new_label();
967 int label2
= gen_new_label();
968 int label3
= gen_new_label();
969 TCGv shift
= tcg_temp_local_new(TCG_TYPE_I32
);
970 tcg_gen_brcondi_i32(TCG_COND_LT
, REG(B7_4
), 0, label1
);
971 /* Rm positive, shift to the left */
972 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
973 tcg_gen_shl_i32(REG(B11_8
), REG(B11_8
), shift
);
975 /* Rm negative, shift to the right */
976 gen_set_label(label1
);
977 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
978 tcg_gen_brcondi_i32(TCG_COND_EQ
, shift
, 0, label2
);
979 tcg_gen_not_i32(shift
, REG(B7_4
));
980 tcg_gen_andi_i32(shift
, shift
, 0x1f);
981 tcg_gen_addi_i32(shift
, shift
, 1);
982 tcg_gen_shr_i32(REG(B11_8
), REG(B11_8
), shift
);
985 gen_set_label(label2
);
986 tcg_gen_movi_i32(REG(B11_8
), 0);
987 gen_set_label(label3
);
988 tcg_temp_free(shift
);
991 case 0x3008: /* sub Rm,Rn */
992 tcg_gen_sub_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
994 case 0x300a: /* subc Rm,Rn */
995 gen_helper_subc(REG(B11_8
), REG(B7_4
), REG(B11_8
));
997 case 0x300b: /* subv Rm,Rn */
998 gen_helper_subv(REG(B11_8
), REG(B7_4
), REG(B11_8
));
1000 case 0x2008: /* tst Rm,Rn */
1002 TCGv val
= tcg_temp_new();
1003 tcg_gen_and_i32(val
, REG(B7_4
), REG(B11_8
));
1004 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1008 case 0x200a: /* xor Rm,Rn */
1009 tcg_gen_xor_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
1011 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
1013 if (ctx
->fpscr
& FPSCR_SZ
) {
1014 TCGv_i64 fp
= tcg_temp_new_i64();
1015 gen_load_fpr64(fp
, XREG(B7_4
));
1016 gen_store_fpr64(fp
, XREG(B11_8
));
1017 tcg_temp_free_i64(fp
);
1019 tcg_gen_mov_i32(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1022 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
1024 if (ctx
->fpscr
& FPSCR_SZ
) {
1025 TCGv addr_hi
= tcg_temp_new();
1026 int fr
= XREG(B7_4
);
1027 tcg_gen_addi_i32(addr_hi
, REG(B11_8
), 4);
1028 tcg_gen_qemu_st32(cpu_fregs
[fr
], REG(B11_8
), ctx
->memidx
);
1029 tcg_gen_qemu_st32(cpu_fregs
[fr
+1], addr_hi
, ctx
->memidx
);
1030 tcg_temp_free(addr_hi
);
1032 tcg_gen_qemu_st32(cpu_fregs
[FREG(B7_4
)], REG(B11_8
), ctx
->memidx
);
1035 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1037 if (ctx
->fpscr
& FPSCR_SZ
) {
1038 TCGv addr_hi
= tcg_temp_new();
1039 int fr
= XREG(B11_8
);
1040 tcg_gen_addi_i32(addr_hi
, REG(B7_4
), 4);
1041 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], REG(B7_4
), ctx
->memidx
);
1042 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr_hi
, ctx
->memidx
);
1043 tcg_temp_free(addr_hi
);
1045 tcg_gen_qemu_ld32u(cpu_fregs
[FREG(B11_8
)], REG(B7_4
), ctx
->memidx
);
1048 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1050 if (ctx
->fpscr
& FPSCR_SZ
) {
1051 TCGv addr_hi
= tcg_temp_new();
1052 int fr
= XREG(B11_8
);
1053 tcg_gen_addi_i32(addr_hi
, REG(B7_4
), 4);
1054 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], REG(B7_4
), ctx
->memidx
);
1055 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr_hi
, ctx
->memidx
);
1056 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 8);
1057 tcg_temp_free(addr_hi
);
1059 tcg_gen_qemu_ld32u(cpu_fregs
[FREG(B11_8
)], REG(B7_4
), ctx
->memidx
);
1060 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 4);
1063 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1065 if (ctx
->fpscr
& FPSCR_SZ
) {
1066 TCGv addr
= tcg_temp_new_i32();
1067 int fr
= XREG(B7_4
);
1068 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1069 tcg_gen_qemu_st32(cpu_fregs
[fr
+1], addr
, ctx
->memidx
);
1070 tcg_gen_subi_i32(addr
, REG(B11_8
), 8);
1071 tcg_gen_qemu_st32(cpu_fregs
[fr
], addr
, ctx
->memidx
);
1072 tcg_gen_mov_i32(REG(B11_8
), addr
);
1073 tcg_temp_free(addr
);
1076 addr
= tcg_temp_new_i32();
1077 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1078 tcg_gen_qemu_st32(cpu_fregs
[FREG(B7_4
)], addr
, ctx
->memidx
);
1079 tcg_temp_free(addr
);
1080 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1083 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1086 TCGv addr
= tcg_temp_new_i32();
1087 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
1088 if (ctx
->fpscr
& FPSCR_SZ
) {
1089 int fr
= XREG(B11_8
);
1090 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], addr
, ctx
->memidx
);
1091 tcg_gen_addi_i32(addr
, addr
, 4);
1092 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr
, ctx
->memidx
);
1094 tcg_gen_qemu_ld32u(cpu_fregs
[FREG(B11_8
)], addr
, ctx
->memidx
);
1096 tcg_temp_free(addr
);
1099 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1102 TCGv addr
= tcg_temp_new();
1103 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
1104 if (ctx
->fpscr
& FPSCR_SZ
) {
1105 int fr
= XREG(B7_4
);
1106 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], addr
, ctx
->memidx
);
1107 tcg_gen_addi_i32(addr
, addr
, 4);
1108 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr
, ctx
->memidx
);
1110 tcg_gen_qemu_st32(cpu_fregs
[FREG(B7_4
)], addr
, ctx
->memidx
);
1112 tcg_temp_free(addr
);
1115 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1116 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1117 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1118 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1119 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1120 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1123 if (ctx
->fpscr
& FPSCR_PR
) {
1126 if (ctx
->opcode
& 0x0110)
1127 break; /* illegal instruction */
1128 fp0
= tcg_temp_new_i64();
1129 fp1
= tcg_temp_new_i64();
1130 gen_load_fpr64(fp0
, DREG(B11_8
));
1131 gen_load_fpr64(fp1
, DREG(B7_4
));
1132 switch (ctx
->opcode
& 0xf00f) {
1133 case 0xf000: /* fadd Rm,Rn */
1134 gen_helper_fadd_DT(fp0
, fp0
, fp1
);
1136 case 0xf001: /* fsub Rm,Rn */
1137 gen_helper_fsub_DT(fp0
, fp0
, fp1
);
1139 case 0xf002: /* fmul Rm,Rn */
1140 gen_helper_fmul_DT(fp0
, fp0
, fp1
);
1142 case 0xf003: /* fdiv Rm,Rn */
1143 gen_helper_fdiv_DT(fp0
, fp0
, fp1
);
1145 case 0xf004: /* fcmp/eq Rm,Rn */
1146 gen_helper_fcmp_eq_DT(fp0
, fp1
);
1148 case 0xf005: /* fcmp/gt Rm,Rn */
1149 gen_helper_fcmp_gt_DT(fp0
, fp1
);
1152 gen_store_fpr64(fp0
, DREG(B11_8
));
1153 tcg_temp_free_i64(fp0
);
1154 tcg_temp_free_i64(fp1
);
1156 switch (ctx
->opcode
& 0xf00f) {
1157 case 0xf000: /* fadd Rm,Rn */
1158 gen_helper_fadd_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1160 case 0xf001: /* fsub Rm,Rn */
1161 gen_helper_fsub_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1163 case 0xf002: /* fmul Rm,Rn */
1164 gen_helper_fmul_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1166 case 0xf003: /* fdiv Rm,Rn */
1167 gen_helper_fdiv_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1169 case 0xf004: /* fcmp/eq Rm,Rn */
1170 gen_helper_fcmp_eq_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1172 case 0xf005: /* fcmp/gt Rm,Rn */
1173 gen_helper_fcmp_gt_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1181 switch (ctx
->opcode
& 0xff00) {
1182 case 0xc900: /* and #imm,R0 */
1183 tcg_gen_andi_i32(REG(0), REG(0), B7_0
);
1185 case 0xcd00: /* and.b #imm,@(R0,GBR) */
1188 addr
= tcg_temp_new();
1189 tcg_gen_add_i32(addr
, REG(0), cpu_gbr
);
1190 val
= tcg_temp_new();
1191 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1192 tcg_gen_andi_i32(val
, val
, B7_0
);
1193 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1195 tcg_temp_free(addr
);
1198 case 0x8b00: /* bf label */
1199 CHECK_NOT_DELAY_SLOT
1200 gen_conditional_jump(ctx
, ctx
->pc
+ 2,
1201 ctx
->pc
+ 4 + B7_0s
* 2);
1202 ctx
->bstate
= BS_BRANCH
;
1204 case 0x8f00: /* bf/s label */
1205 CHECK_NOT_DELAY_SLOT
1206 gen_branch_slot(ctx
->delayed_pc
= ctx
->pc
+ 4 + B7_0s
* 2, 0);
1207 ctx
->flags
|= DELAY_SLOT_CONDITIONAL
;
1209 case 0x8900: /* bt label */
1210 CHECK_NOT_DELAY_SLOT
1211 gen_conditional_jump(ctx
, ctx
->pc
+ 4 + B7_0s
* 2,
1213 ctx
->bstate
= BS_BRANCH
;
1215 case 0x8d00: /* bt/s label */
1216 CHECK_NOT_DELAY_SLOT
1217 gen_branch_slot(ctx
->delayed_pc
= ctx
->pc
+ 4 + B7_0s
* 2, 1);
1218 ctx
->flags
|= DELAY_SLOT_CONDITIONAL
;
1220 case 0x8800: /* cmp/eq #imm,R0 */
1221 gen_cmp_imm(TCG_COND_EQ
, REG(0), B7_0s
);
1223 case 0xc400: /* mov.b @(disp,GBR),R0 */
1225 TCGv addr
= tcg_temp_new();
1226 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
);
1227 tcg_gen_qemu_ld8s(REG(0), addr
, ctx
->memidx
);
1228 tcg_temp_free(addr
);
1231 case 0xc500: /* mov.w @(disp,GBR),R0 */
1233 TCGv addr
= tcg_temp_new();
1234 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 2);
1235 tcg_gen_qemu_ld16s(REG(0), addr
, ctx
->memidx
);
1236 tcg_temp_free(addr
);
1239 case 0xc600: /* mov.l @(disp,GBR),R0 */
1241 TCGv addr
= tcg_temp_new();
1242 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 4);
1243 tcg_gen_qemu_ld32s(REG(0), addr
, ctx
->memidx
);
1244 tcg_temp_free(addr
);
1247 case 0xc000: /* mov.b R0,@(disp,GBR) */
1249 TCGv addr
= tcg_temp_new();
1250 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
);
1251 tcg_gen_qemu_st8(REG(0), addr
, ctx
->memidx
);
1252 tcg_temp_free(addr
);
1255 case 0xc100: /* mov.w R0,@(disp,GBR) */
1257 TCGv addr
= tcg_temp_new();
1258 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 2);
1259 tcg_gen_qemu_st16(REG(0), addr
, ctx
->memidx
);
1260 tcg_temp_free(addr
);
1263 case 0xc200: /* mov.l R0,@(disp,GBR) */
1265 TCGv addr
= tcg_temp_new();
1266 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 4);
1267 tcg_gen_qemu_st32(REG(0), addr
, ctx
->memidx
);
1268 tcg_temp_free(addr
);
1271 case 0x8000: /* mov.b R0,@(disp,Rn) */
1273 TCGv addr
= tcg_temp_new();
1274 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
);
1275 tcg_gen_qemu_st8(REG(0), addr
, ctx
->memidx
);
1276 tcg_temp_free(addr
);
1279 case 0x8100: /* mov.w R0,@(disp,Rn) */
1281 TCGv addr
= tcg_temp_new();
1282 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
* 2);
1283 tcg_gen_qemu_st16(REG(0), addr
, ctx
->memidx
);
1284 tcg_temp_free(addr
);
1287 case 0x8400: /* mov.b @(disp,Rn),R0 */
1289 TCGv addr
= tcg_temp_new();
1290 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
);
1291 tcg_gen_qemu_ld8s(REG(0), addr
, ctx
->memidx
);
1292 tcg_temp_free(addr
);
1295 case 0x8500: /* mov.w @(disp,Rn),R0 */
1297 TCGv addr
= tcg_temp_new();
1298 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
* 2);
1299 tcg_gen_qemu_ld16s(REG(0), addr
, ctx
->memidx
);
1300 tcg_temp_free(addr
);
1303 case 0xc700: /* mova @(disp,PC),R0 */
1304 tcg_gen_movi_i32(REG(0), ((ctx
->pc
& 0xfffffffc) + 4 + B7_0
* 4) & ~3);
1306 case 0xcb00: /* or #imm,R0 */
1307 tcg_gen_ori_i32(REG(0), REG(0), B7_0
);
1309 case 0xcf00: /* or.b #imm,@(R0,GBR) */
1312 addr
= tcg_temp_new();
1313 tcg_gen_add_i32(addr
, REG(0), cpu_gbr
);
1314 val
= tcg_temp_new();
1315 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1316 tcg_gen_ori_i32(val
, val
, B7_0
);
1317 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1319 tcg_temp_free(addr
);
1322 case 0xc300: /* trapa #imm */
1325 CHECK_NOT_DELAY_SLOT
1326 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
1327 imm
= tcg_const_i32(B7_0
);
1328 gen_helper_trapa(imm
);
1330 ctx
->bstate
= BS_BRANCH
;
1333 case 0xc800: /* tst #imm,R0 */
1335 TCGv val
= tcg_temp_new();
1336 tcg_gen_andi_i32(val
, REG(0), B7_0
);
1337 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1341 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
1343 TCGv val
= tcg_temp_new();
1344 tcg_gen_add_i32(val
, REG(0), cpu_gbr
);
1345 tcg_gen_qemu_ld8u(val
, val
, ctx
->memidx
);
1346 tcg_gen_andi_i32(val
, val
, B7_0
);
1347 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1351 case 0xca00: /* xor #imm,R0 */
1352 tcg_gen_xori_i32(REG(0), REG(0), B7_0
);
1354 case 0xce00: /* xor.b #imm,@(R0,GBR) */
1357 addr
= tcg_temp_new();
1358 tcg_gen_add_i32(addr
, REG(0), cpu_gbr
);
1359 val
= tcg_temp_new();
1360 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1361 tcg_gen_xori_i32(val
, val
, B7_0
);
1362 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1364 tcg_temp_free(addr
);
1369 switch (ctx
->opcode
& 0xf08f) {
1370 case 0x408e: /* ldc Rm,Rn_BANK */
1372 tcg_gen_mov_i32(ALTREG(B6_4
), REG(B11_8
));
1374 case 0x4087: /* ldc.l @Rm+,Rn_BANK */
1376 tcg_gen_qemu_ld32s(ALTREG(B6_4
), REG(B11_8
), ctx
->memidx
);
1377 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1379 case 0x0082: /* stc Rm_BANK,Rn */
1381 tcg_gen_mov_i32(REG(B11_8
), ALTREG(B6_4
));
1383 case 0x4083: /* stc.l Rm_BANK,@-Rn */
1386 TCGv addr
= tcg_temp_new();
1387 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1388 tcg_gen_qemu_st32(ALTREG(B6_4
), addr
, ctx
->memidx
);
1389 tcg_temp_free(addr
);
1390 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1395 switch (ctx
->opcode
& 0xf0ff) {
1396 case 0x0023: /* braf Rn */
1397 CHECK_NOT_DELAY_SLOT
1398 tcg_gen_addi_i32(cpu_delayed_pc
, REG(B11_8
), ctx
->pc
+ 4);
1399 ctx
->flags
|= DELAY_SLOT
;
1400 ctx
->delayed_pc
= (uint32_t) - 1;
1402 case 0x0003: /* bsrf Rn */
1403 CHECK_NOT_DELAY_SLOT
1404 tcg_gen_movi_i32(cpu_pr
, ctx
->pc
+ 4);
1405 tcg_gen_add_i32(cpu_delayed_pc
, REG(B11_8
), cpu_pr
);
1406 ctx
->flags
|= DELAY_SLOT
;
1407 ctx
->delayed_pc
= (uint32_t) - 1;
1409 case 0x4015: /* cmp/pl Rn */
1410 gen_cmp_imm(TCG_COND_GT
, REG(B11_8
), 0);
1412 case 0x4011: /* cmp/pz Rn */
1413 gen_cmp_imm(TCG_COND_GE
, REG(B11_8
), 0);
1415 case 0x4010: /* dt Rn */
1416 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 1);
1417 gen_cmp_imm(TCG_COND_EQ
, REG(B11_8
), 0);
1419 case 0x402b: /* jmp @Rn */
1420 CHECK_NOT_DELAY_SLOT
1421 tcg_gen_mov_i32(cpu_delayed_pc
, REG(B11_8
));
1422 ctx
->flags
|= DELAY_SLOT
;
1423 ctx
->delayed_pc
= (uint32_t) - 1;
1425 case 0x400b: /* jsr @Rn */
1426 CHECK_NOT_DELAY_SLOT
1427 tcg_gen_movi_i32(cpu_pr
, ctx
->pc
+ 4);
1428 tcg_gen_mov_i32(cpu_delayed_pc
, REG(B11_8
));
1429 ctx
->flags
|= DELAY_SLOT
;
1430 ctx
->delayed_pc
= (uint32_t) - 1;
1432 case 0x400e: /* ldc Rm,SR */
1434 tcg_gen_andi_i32(cpu_sr
, REG(B11_8
), 0x700083f3);
1435 ctx
->bstate
= BS_STOP
;
1437 case 0x4007: /* ldc.l @Rm+,SR */
1440 TCGv val
= tcg_temp_new();
1441 tcg_gen_qemu_ld32s(val
, REG(B11_8
), ctx
->memidx
);
1442 tcg_gen_andi_i32(cpu_sr
, val
, 0x700083f3);
1444 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1445 ctx
->bstate
= BS_STOP
;
1448 case 0x0002: /* stc SR,Rn */
1450 tcg_gen_mov_i32(REG(B11_8
), cpu_sr
);
1452 case 0x4003: /* stc SR,@-Rn */
1455 TCGv addr
= tcg_temp_new();
1456 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1457 tcg_gen_qemu_st32(cpu_sr
, addr
, ctx
->memidx
);
1458 tcg_temp_free(addr
);
1459 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1462 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
1465 tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \
1469 tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
1470 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
1474 tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \
1479 TCGv addr = tcg_temp_new(); \
1480 tcg_gen_subi_i32(addr, REG(B11_8), 4); \
1481 tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
1482 tcg_temp_free(addr); \
1483 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
1486 LDST(gbr
, 0x401e, 0x4017, 0x0012, 0x4013, {})
1487 LDST(vbr
, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED
)
1488 LDST(ssr
, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED
)
1489 LDST(spc
, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED
)
1490 LDST(dbr
, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED
)
1491 LDST(mach
, 0x400a, 0x4006, 0x000a, 0x4002, {})
1492 LDST(macl
, 0x401a, 0x4016, 0x001a, 0x4012, {})
1493 LDST(pr
, 0x402a, 0x4026, 0x002a, 0x4022, {})
1494 LDST(fpul
, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED
})
1495 case 0x406a: /* lds Rm,FPSCR */
1497 gen_helper_ld_fpscr(REG(B11_8
));
1498 ctx
->bstate
= BS_STOP
;
1500 case 0x4066: /* lds.l @Rm+,FPSCR */
1503 TCGv addr
= tcg_temp_new();
1504 tcg_gen_qemu_ld32s(addr
, REG(B11_8
), ctx
->memidx
);
1505 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1506 gen_helper_ld_fpscr(addr
);
1507 tcg_temp_free(addr
);
1508 ctx
->bstate
= BS_STOP
;
1511 case 0x006a: /* sts FPSCR,Rn */
1513 tcg_gen_andi_i32(REG(B11_8
), cpu_fpscr
, 0x003fffff);
1515 case 0x4062: /* sts FPSCR,@-Rn */
1519 val
= tcg_temp_new();
1520 tcg_gen_andi_i32(val
, cpu_fpscr
, 0x003fffff);
1521 addr
= tcg_temp_new();
1522 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1523 tcg_gen_qemu_st32(val
, addr
, ctx
->memidx
);
1524 tcg_temp_free(addr
);
1526 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1529 case 0x00c3: /* movca.l R0,@Rm */
1530 tcg_gen_qemu_st32(REG(0), REG(B11_8
), ctx
->memidx
);
1533 /* MOVUA.L @Rm,R0 (Rm) -> R0
1534 Load non-boundary-aligned data */
1535 tcg_gen_qemu_ld32u(REG(0), REG(B11_8
), ctx
->memidx
);
1538 /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
1539 Load non-boundary-aligned data */
1540 tcg_gen_qemu_ld32u(REG(0), REG(B11_8
), ctx
->memidx
);
1541 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1543 case 0x0029: /* movt Rn */
1544 tcg_gen_andi_i32(REG(B11_8
), cpu_sr
, SR_T
);
1546 case 0x0093: /* ocbi @Rn */
1548 TCGv dummy
= tcg_temp_new();
1549 tcg_gen_qemu_ld32s(dummy
, REG(B11_8
), ctx
->memidx
);
1550 tcg_temp_free(dummy
);
1553 case 0x00a3: /* ocbp @Rn */
1555 TCGv dummy
= tcg_temp_new();
1556 tcg_gen_qemu_ld32s(dummy
, REG(B11_8
), ctx
->memidx
);
1557 tcg_temp_free(dummy
);
1560 case 0x00b3: /* ocbwb @Rn */
1562 TCGv dummy
= tcg_temp_new();
1563 tcg_gen_qemu_ld32s(dummy
, REG(B11_8
), ctx
->memidx
);
1564 tcg_temp_free(dummy
);
1567 case 0x0083: /* pref @Rn */
1569 case 0x00d3: /* prefi @Rn */
1570 if (ctx
->features
& SH_FEATURE_SH4A
)
1574 case 0x00e3: /* icbi @Rn */
1575 if (ctx
->features
& SH_FEATURE_SH4A
)
1579 case 0x00ab: /* synco */
1580 if (ctx
->features
& SH_FEATURE_SH4A
)
1584 case 0x4024: /* rotcl Rn */
1586 TCGv tmp
= tcg_temp_new();
1587 tcg_gen_mov_i32(tmp
, cpu_sr
);
1588 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 31);
1589 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 1);
1590 gen_copy_bit_i32(REG(B11_8
), 0, tmp
, 0);
1594 case 0x4025: /* rotcr Rn */
1596 TCGv tmp
= tcg_temp_new();
1597 tcg_gen_mov_i32(tmp
, cpu_sr
);
1598 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1599 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 1);
1600 gen_copy_bit_i32(REG(B11_8
), 31, tmp
, 0);
1604 case 0x4004: /* rotl Rn */
1605 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 31);
1606 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 1);
1607 gen_copy_bit_i32(REG(B11_8
), 0, cpu_sr
, 0);
1609 case 0x4005: /* rotr Rn */
1610 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1611 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 1);
1612 gen_copy_bit_i32(REG(B11_8
), 31, cpu_sr
, 0);
1614 case 0x4000: /* shll Rn */
1615 case 0x4020: /* shal Rn */
1616 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 31);
1617 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 1);
1619 case 0x4021: /* shar Rn */
1620 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1621 tcg_gen_sari_i32(REG(B11_8
), REG(B11_8
), 1);
1623 case 0x4001: /* shlr Rn */
1624 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1625 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 1);
1627 case 0x4008: /* shll2 Rn */
1628 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 2);
1630 case 0x4018: /* shll8 Rn */
1631 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 8);
1633 case 0x4028: /* shll16 Rn */
1634 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 16);
1636 case 0x4009: /* shlr2 Rn */
1637 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 2);
1639 case 0x4019: /* shlr8 Rn */
1640 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 8);
1642 case 0x4029: /* shlr16 Rn */
1643 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 16);
1645 case 0x401b: /* tas.b @Rn */
1648 addr
= tcg_temp_local_new(TCG_TYPE_I32
);
1649 tcg_gen_mov_i32(addr
, REG(B11_8
));
1650 val
= tcg_temp_local_new(TCG_TYPE_I32
);
1651 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1652 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1653 tcg_gen_ori_i32(val
, val
, 0x80);
1654 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1656 tcg_temp_free(addr
);
1659 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1661 tcg_gen_mov_i32(cpu_fregs
[FREG(B11_8
)], cpu_fpul
);
1663 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1665 tcg_gen_mov_i32(cpu_fpul
, cpu_fregs
[FREG(B11_8
)]);
1667 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1669 if (ctx
->fpscr
& FPSCR_PR
) {
1671 if (ctx
->opcode
& 0x0100)
1672 break; /* illegal instruction */
1673 fp
= tcg_temp_new_i64();
1674 gen_helper_float_DT(fp
, cpu_fpul
);
1675 gen_store_fpr64(fp
, DREG(B11_8
));
1676 tcg_temp_free_i64(fp
);
1679 gen_helper_float_FT(cpu_fregs
[FREG(B11_8
)], cpu_fpul
);
1682 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1684 if (ctx
->fpscr
& FPSCR_PR
) {
1686 if (ctx
->opcode
& 0x0100)
1687 break; /* illegal instruction */
1688 fp
= tcg_temp_new_i64();
1689 gen_load_fpr64(fp
, DREG(B11_8
));
1690 gen_helper_ftrc_DT(cpu_fpul
, fp
);
1691 tcg_temp_free_i64(fp
);
1694 gen_helper_ftrc_FT(cpu_fpul
, cpu_fregs
[FREG(B11_8
)]);
1697 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1700 gen_helper_fneg_T(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)]);
1703 case 0xf05d: /* fabs FRn/DRn */
1705 if (ctx
->fpscr
& FPSCR_PR
) {
1706 if (ctx
->opcode
& 0x0100)
1707 break; /* illegal instruction */
1708 TCGv_i64 fp
= tcg_temp_new_i64();
1709 gen_load_fpr64(fp
, DREG(B11_8
));
1710 gen_helper_fabs_DT(fp
, fp
);
1711 gen_store_fpr64(fp
, DREG(B11_8
));
1712 tcg_temp_free_i64(fp
);
1714 gen_helper_fabs_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)]);
1717 case 0xf06d: /* fsqrt FRn */
1719 if (ctx
->fpscr
& FPSCR_PR
) {
1720 if (ctx
->opcode
& 0x0100)
1721 break; /* illegal instruction */
1722 TCGv_i64 fp
= tcg_temp_new_i64();
1723 gen_load_fpr64(fp
, DREG(B11_8
));
1724 gen_helper_fsqrt_DT(fp
, fp
);
1725 gen_store_fpr64(fp
, DREG(B11_8
));
1726 tcg_temp_free_i64(fp
);
1728 gen_helper_fsqrt_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)]);
1731 case 0xf07d: /* fsrra FRn */
1734 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1736 if (!(ctx
->fpscr
& FPSCR_PR
)) {
1737 tcg_gen_movi_i32(cpu_fregs
[FREG(B11_8
)], 0);
1740 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1742 if (!(ctx
->fpscr
& FPSCR_PR
)) {
1743 tcg_gen_movi_i32(cpu_fregs
[FREG(B11_8
)], 0x3f800000);
1746 case 0xf0ad: /* fcnvsd FPUL,DRn */
1749 TCGv_i64 fp
= tcg_temp_new_i64();
1750 gen_helper_fcnvsd_FT_DT(fp
, cpu_fpul
);
1751 gen_store_fpr64(fp
, DREG(B11_8
));
1752 tcg_temp_free_i64(fp
);
1755 case 0xf0bd: /* fcnvds DRn,FPUL */
1758 TCGv_i64 fp
= tcg_temp_new_i64();
1759 gen_load_fpr64(fp
, DREG(B11_8
));
1760 gen_helper_fcnvds_DT_FT(cpu_fpul
, fp
);
1761 tcg_temp_free_i64(fp
);
1766 fprintf(stderr
, "unknown instruction 0x%04x at pc 0x%08x\n",
1767 ctx
->opcode
, ctx
->pc
);
1770 gen_helper_raise_illegal_instruction();
1771 ctx
->bstate
= BS_EXCP
;
1774 static void decode_opc(DisasContext
* ctx
)
1776 uint32_t old_flags
= ctx
->flags
;
1780 if (old_flags
& (DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
)) {
1781 if (ctx
->flags
& DELAY_SLOT_CLEARME
) {
1784 /* go out of the delay slot */
1785 uint32_t new_flags
= ctx
->flags
;
1786 new_flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
);
1787 gen_store_flags(new_flags
);
1790 ctx
->bstate
= BS_BRANCH
;
1791 if (old_flags
& DELAY_SLOT_CONDITIONAL
) {
1792 gen_delayed_conditional_jump(ctx
);
1793 } else if (old_flags
& DELAY_SLOT
) {
1799 /* go into a delay slot */
1800 if (ctx
->flags
& (DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
))
1801 gen_store_flags(ctx
->flags
);
1805 gen_intermediate_code_internal(CPUState
* env
, TranslationBlock
* tb
,
1809 target_ulong pc_start
;
1810 static uint16_t *gen_opc_end
;
1817 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1819 ctx
.flags
= (uint32_t)tb
->flags
;
1820 ctx
.bstate
= BS_NONE
;
1822 ctx
.fpscr
= env
->fpscr
;
1823 ctx
.memidx
= (env
->sr
& SR_MD
) ? 1 : 0;
1824 /* We don't know if the delayed pc came from a dynamic or static branch,
1825 so assume it is a dynamic branch. */
1826 ctx
.delayed_pc
= -1; /* use delayed pc from env pointer */
1828 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
1829 ctx
.features
= env
->features
;
1832 if (loglevel
& CPU_LOG_TB_CPU
) {
1834 "------------------------------------------------\n");
1835 cpu_dump_state(env
, logfile
, fprintf
, 0);
1841 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1843 max_insns
= CF_COUNT_MASK
;
1845 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
1846 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
1847 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1848 if (ctx
.pc
== bp
->pc
) {
1849 /* We have hit a breakpoint - make sure PC is up-to-date */
1850 tcg_gen_movi_i32(cpu_pc
, ctx
.pc
);
1852 ctx
.bstate
= BS_EXCP
;
1858 i
= gen_opc_ptr
- gen_opc_buf
;
1862 gen_opc_instr_start
[ii
++] = 0;
1864 gen_opc_pc
[ii
] = ctx
.pc
;
1865 gen_opc_hflags
[ii
] = ctx
.flags
;
1866 gen_opc_instr_start
[ii
] = 1;
1867 gen_opc_icount
[ii
] = num_insns
;
1869 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
1872 fprintf(stderr
, "Loading opcode at address 0x%08x\n", ctx
.pc
);
1875 ctx
.opcode
= lduw_code(ctx
.pc
);
1879 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
1881 if (env
->singlestep_enabled
)
1883 if (num_insns
>= max_insns
)
1885 #ifdef SH4_SINGLE_STEP
1889 if (tb
->cflags
& CF_LAST_IO
)
1891 if (env
->singlestep_enabled
) {
1892 tcg_gen_movi_i32(cpu_pc
, ctx
.pc
);
1895 switch (ctx
.bstate
) {
1897 /* gen_op_interrupt_restart(); */
1901 gen_store_flags(ctx
.flags
| DELAY_SLOT_CLEARME
);
1903 gen_goto_tb(&ctx
, 0, ctx
.pc
);
1906 /* gen_op_interrupt_restart(); */
1915 gen_icount_end(tb
, num_insns
);
1916 *gen_opc_ptr
= INDEX_op_end
;
1918 i
= gen_opc_ptr
- gen_opc_buf
;
1921 gen_opc_instr_start
[ii
++] = 0;
1923 tb
->size
= ctx
.pc
- pc_start
;
1924 tb
->icount
= num_insns
;
1928 #ifdef SH4_DEBUG_DISAS
1929 if (loglevel
& CPU_LOG_TB_IN_ASM
)
1930 fprintf(logfile
, "\n");
1932 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1933 fprintf(logfile
, "IN:\n"); /* , lookup_symbol(pc_start)); */
1934 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
1935 fprintf(logfile
, "\n");
1940 void gen_intermediate_code(CPUState
* env
, struct TranslationBlock
*tb
)
1942 gen_intermediate_code_internal(env
, tb
, 0);
1945 void gen_intermediate_code_pc(CPUState
* env
, struct TranslationBlock
*tb
)
1947 gen_intermediate_code_internal(env
, tb
, 1);
1950 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
1951 unsigned long searched_pc
, int pc_pos
, void *puc
)
1953 env
->pc
= gen_opc_pc
[pc_pos
];
1954 env
->flags
= gen_opc_hflags
[pc_pos
];