target-cris/cpu.h

   1 /*
   2  *  CRIS virtual CPU header
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #ifndef CPU_CRIS_H
  22 #define CPU_CRIS_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #include "cpu-defs.h"
  27
  28 #define TARGET_HAS_ICE 1
  29
  30 #define ELF_MACHINE     EM_CRIS
  31
  32 #define EXCP_MMU_EXEC    0
  33 #define EXCP_MMU_READ    1
  34 #define EXCP_MMU_WRITE   2
  35 #define EXCP_MMU_FLUSH   3
  36 #define EXCP_MMU_FAULT   4
  37 #define EXCP_BREAK      16 /* trap.  */
  38
  39 /* Register aliases. R0 - R15 */
  40 #define R_FP  8
  41 #define R_SP  14
  42 #define R_ACR 15
  43
  44 /* Support regs, P0 - P15  */
  45 #define PR_BZ  0
  46 #define PR_VR  1
  47 #define PR_PID 2
  48 #define PR_SRS 3
  49 #define PR_WZ  4
  50 #define PR_EXS 5
  51 #define PR_EDA 6
  52 #define PR_MOF 7
  53 #define PR_DZ  8
  54 #define PR_EBP 9
  55 #define PR_ERP 10
  56 #define PR_SRP 11
  57 #define PR_CCS 13
  58 #define PR_USP 14
  59 #define PR_SPC 15
  60
  61 /* CPU flags.  */
  62 #define S_FLAG 0x200
  63 #define R_FLAG 0x100
  64 #define P_FLAG 0x80
  65 #define U_FLAG 0x40
  66 #define P_FLAG 0x80
  67 #define U_FLAG 0x40
  68 #define I_FLAG 0x20
  69 #define X_FLAG 0x10
  70 #define N_FLAG 0x08
  71 #define Z_FLAG 0x04
  72 #define V_FLAG 0x02
  73 #define C_FLAG 0x01
  74 #define ALU_FLAGS 0x1F
  75
  76 /* Condition codes.  */
  77 #define CC_CC   0
  78 #define CC_CS   1
  79 #define CC_NE   2
  80 #define CC_EQ   3
  81 #define CC_VC   4
  82 #define CC_VS   5
  83 #define CC_PL   6
  84 #define CC_MI   7
  85 #define CC_LS   8
  86 #define CC_HI   9
  87 #define CC_GE  10
  88 #define CC_LT  11
  89 #define CC_GT  12
  90 #define CC_LE  13
  91 #define CC_A   14
  92 #define CC_P   15
  93
  94 /* Internal flags for the implementation.  */
  95 #define F_DELAYSLOT 1
  96
  97 #define NB_MMU_MODES 2
  98
  99 typedef struct CPUCRISState {
 100         uint32_t regs[16];
 101         /* P0 - P15 are referred to as special registers in the docs.  */
 102         uint32_t pregs[16];
 103
 104         /* Pseudo register for the PC. Not directly accessable on CRIS.  */
 105         uint32_t pc;
 106
 107         /* Pseudo register for the kernel stack.  */
 108         uint32_t ksp;
 109
 110         /* Branch.  */
 111         int dslot;
 112         int btaken;
 113         uint32_t btarget;
 114
 115         /* Condition flag tracking.  */
 116         uint32_t cc_op;
 117         uint32_t cc_mask;
 118         uint32_t cc_dest;
 119         uint32_t cc_src;
 120         uint32_t cc_result;
 121         /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 122         int cc_size;
 123         /* X flag at the time of cc snapshot.  */
 124         int cc_x;
 125
 126         int exception_index;
 127         int interrupt_request;
 128         int interrupt_vector;
 129         int fault_vector;
 130         int trap_vector;
 131
 132         /* FIXME: add a check in the translator to avoid writing to support
 133            register sets beyond the 4th. The ISA allows up to 256! but in
 134            practice there is no core that implements more than 4.
 135
 136            Support function registers are used to control units close to the
 137            core. Accesses do not pass down the normal hierarchy.
 138         */
 139         uint32_t sregs[4][16];
 140
 141         /* Linear feedback shift reg in the mmu. Used to provide pseudo
 142            randomness for the 'hint' the mmu gives to sw for chosing valid
 143            sets on TLB refills.  */
 144         uint32_t mmu_rand_lfsr;
 145
 146         /*
 147          * We just store the stores to the tlbset here for later evaluation
 148          * when the hw needs access to them.
 149          *
 150          * One for I and another for D.
 151          */
 152         struct
 153         {
 154                 uint32_t hi;
 155                 uint32_t lo;
 156         } tlbsets[2][4][16];
 157
 158         int features;
 159         int user_mode_only;
 160         int halted;
 161
 162         jmp_buf jmp_env;
 163         CPU_COMMON
 164 } CPUCRISState;
 165
 166 CPUCRISState *cpu_cris_init(const char *cpu_model);
 167 int cpu_cris_exec(CPUCRISState *s);
 168 void cpu_cris_close(CPUCRISState *s);
 169 void do_interrupt(CPUCRISState *env);
 170 /* you can call this signal handler from your SIGBUS and SIGSEGV
 171    signal handlers to inform the virtual CPU of exceptions. non zero
 172    is returned if the signal was handled by the virtual CPU.  */
 173 int cpu_cris_signal_handler(int host_signum, void *pinfo,
 174                            void *puc);
 175 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 176                           int is_asi);
 177
 178 enum {
 179     CC_OP_DYNAMIC, /* Use env->cc_op  */
 180     CC_OP_FLAGS,
 181     CC_OP_CMP,
 182     CC_OP_MOVE,
 183     CC_OP_ADD,
 184     CC_OP_ADDC,
 185     CC_OP_MCP,
 186     CC_OP_ADDU,
 187     CC_OP_SUB,
 188     CC_OP_SUBU,
 189     CC_OP_NEG,
 190     CC_OP_BTST,
 191     CC_OP_MULS,
 192     CC_OP_MULU,
 193     CC_OP_DSTEP,
 194     CC_OP_BOUND,
 195
 196     CC_OP_OR,
 197     CC_OP_AND,
 198     CC_OP_XOR,
 199     CC_OP_LSL,
 200     CC_OP_LSR,
 201     CC_OP_ASR,
 202     CC_OP_LZ
 203 };
 204
 205 /* CRIS uses 8k pages.  */
 206 #define TARGET_PAGE_BITS 13
 207 #define MMAP_SHIFT TARGET_PAGE_BITS
 208
 209 #define CPUState CPUCRISState
 210 #define cpu_init cpu_cris_init
 211 #define cpu_exec cpu_cris_exec
 212 #define cpu_gen_code cpu_cris_gen_code
 213 #define cpu_signal_handler cpu_cris_signal_handler
 214
 215 /* MMU modes definitions */
 216 #define MMU_MODE0_SUFFIX _kernel
 217 #define MMU_MODE1_SUFFIX _user
 218 #define MMU_USER_IDX 1
 219 static inline int cpu_mmu_index (CPUState *env)
 220 {
 221         return !!(env->pregs[PR_CCS] & U_FLAG);
 222 }
 223
 224 /* Support function regs.  */
 225 #define SFR_RW_GC_CFG      0][0
 226 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 227 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 228 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 229 #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 230 #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 231 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 232 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 233
 234 #include "cpu-all.h"
 235 #endif