4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #define TARGET_LONG_BITS 32
26 #define TARGET_HAS_ICE 1
28 #define ELF_MACHINE EM_SH
31 #define SH_CPU_SH7750 (1 << 0)
32 #define SH_CPU_SH7750S (1 << 1)
33 #define SH_CPU_SH7750R (1 << 2)
34 #define SH_CPU_SH7751 (1 << 3)
35 #define SH_CPU_SH7751R (1 << 4)
36 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
37 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
41 #include "softfloat.h"
43 #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
45 #define SR_MD (1 << 30)
46 #define SR_RB (1 << 29)
47 #define SR_BL (1 << 28)
48 #define SR_FD (1 << 15)
54 #define FPSCR_FR (1 << 21)
55 #define FPSCR_SZ (1 << 20)
56 #define FPSCR_PR (1 << 19)
57 #define FPSCR_DN (1 << 18)
58 #define DELAY_SLOT (1 << 0)
59 #define DELAY_SLOT_CONDITIONAL (1 << 1)
60 #define DELAY_SLOT_TRUE (1 << 2)
61 #define DELAY_SLOT_CLEARME (1 << 3)
62 /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
63 * after the delay slot should be taken or not. It is calculated from SR_T.
65 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
66 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
69 /* XXXXX The structure could be made more compact */
70 typedef struct tlb_t
{
71 uint8_t asid
; /* address space identifier */
72 uint32_t vpn
; /* virtual page number */
73 uint8_t v
; /* validity */
74 uint32_t ppn
; /* physical page number */
75 uint8_t sz
; /* page size */
76 uint32_t size
; /* cached page size in bytes */
77 uint8_t sh
; /* share status */
78 uint8_t c
; /* cacheability */
79 uint8_t pr
; /* protection key */
80 uint8_t d
; /* dirty */
81 uint8_t wt
; /* write through */
82 uint8_t sa
; /* space attribute (PCMCIA) */
83 uint8_t tc
; /* timing control */
89 #define NB_MMU_MODES 2
91 typedef struct CPUSH4State
{
92 int id
; /* CPU model */
94 uint32_t flags
; /* general execution flags */
95 uint32_t gregs
[24]; /* general registers */
96 float32 fregs
[32]; /* floating point registers */
97 uint32_t sr
; /* status register */
98 uint32_t ssr
; /* saved status register */
99 uint32_t spc
; /* saved program counter */
100 uint32_t gbr
; /* global base register */
101 uint32_t vbr
; /* vector base register */
102 uint32_t sgr
; /* saved global register 15 */
103 uint32_t dbr
; /* debug base register */
104 uint32_t pc
; /* program counter */
105 uint32_t delayed_pc
; /* target of delayed jump */
106 uint32_t mach
; /* multiply and accumulate high */
107 uint32_t macl
; /* multiply and accumulate low */
108 uint32_t pr
; /* procedure register */
109 uint32_t fpscr
; /* floating point status/control register */
110 uint32_t fpul
; /* floating point communication register */
112 /* float point status register */
113 float_status fp_status
;
115 /* Those belong to the specific unit (SH7750) but are handled here */
116 uint32_t mmucr
; /* MMU control register */
117 uint32_t pteh
; /* page table entry high register */
118 uint32_t ptel
; /* page table entry low register */
119 uint32_t ptea
; /* page table entry assistance register */
120 uint32_t ttb
; /* tranlation table base register */
121 uint32_t tea
; /* TLB exception address register */
122 uint32_t tra
; /* TRAPA exception register */
123 uint32_t expevt
; /* exception event register */
124 uint32_t intevt
; /* interrupt event register */
126 uint32_t pvr
; /* Processor Version Register */
127 uint32_t prr
; /* Processor Revision Register */
128 uint32_t cvr
; /* Cache Version Register */
130 CPU_COMMON tlb_t utlb
[UTLB_SIZE
]; /* unified translation table */
131 tlb_t itlb
[ITLB_SIZE
]; /* instruction translation table */
133 int intr_at_halt
; /* SR_BL ignored during sleep */
136 CPUSH4State
*cpu_sh4_init(const char *cpu_model
);
137 int cpu_sh4_exec(CPUSH4State
* s
);
138 int cpu_sh4_signal_handler(int host_signum
, void *pinfo
,
140 void sh4_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
141 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State
*s
, target_phys_addr_t addr
,
144 static inline void cpu_set_tls(CPUSH4State
*env
, target_ulong newtls
)
149 #include "softfloat.h"
151 #define CPUState CPUSH4State
152 #define cpu_init cpu_sh4_init
153 #define cpu_exec cpu_sh4_exec
154 #define cpu_gen_code cpu_sh4_gen_code
155 #define cpu_signal_handler cpu_sh4_signal_handler
156 #define cpu_list sh4_cpu_list
158 /* MMU modes definitions */
159 #define MMU_MODE0_SUFFIX _kernel
160 #define MMU_MODE1_SUFFIX _user
161 #define MMU_USER_IDX 1
162 static inline int cpu_mmu_index (CPUState
*env
)
164 return (env
->sr
& SR_MD
) == 0 ? 1 : 0;
167 #if defined(CONFIG_USER_ONLY)
168 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
171 env
->gregs
[15] = newsp
;
176 #define CPU_PC_FROM_TB(env, tb) do { \
178 env->flags = tb->flags; \
183 /* Memory access type */
189 /* Type of instruction */
194 /* MMU control register */
195 #define MMUCR 0x1F000010
196 #define MMUCR_AT (1<<0)
197 #define MMUCR_SV (1<<8)
198 #define MMUCR_URC_BITS (6)
199 #define MMUCR_URC_OFFSET (10)
200 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
201 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
202 static inline int cpu_mmucr_urc (uint32_t mmucr
)
204 return ((mmucr
& MMUCR_URC_MASK
) >> MMUCR_URC_OFFSET
);
207 /* PTEH : Page Translation Entry High register */
208 #define PTEH_ASID_BITS (8)
209 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
210 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
211 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
212 #define PTEH_VPN_BITS (22)
213 #define PTEH_VPN_OFFSET (10)
214 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
215 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
216 static inline int cpu_pteh_vpn (uint32_t pteh
)
218 return ((pteh
& PTEH_VPN_MASK
) >> PTEH_VPN_OFFSET
);
221 /* PTEL : Page Translation Entry Low register */
222 #define PTEL_V (1 << 8)
223 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
224 #define PTEL_C (1 << 3)
225 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
226 #define PTEL_D (1 << 2)
227 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
228 #define PTEL_SH (1 << 1)
229 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
230 #define PTEL_WT (1 << 0)
231 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
233 #define PTEL_SZ_HIGH_OFFSET (7)
234 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
235 #define PTEL_SZ_LOW_OFFSET (4)
236 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
237 static inline int cpu_ptel_sz (uint32_t ptel
)
240 sz
= (ptel
& PTEL_SZ_HIGH
) >> PTEL_SZ_HIGH_OFFSET
;
242 sz
|= (ptel
& PTEL_SZ_LOW
) >> PTEL_SZ_LOW_OFFSET
;
246 #define PTEL_PPN_BITS (19)
247 #define PTEL_PPN_OFFSET (10)
248 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
249 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
250 static inline int cpu_ptel_ppn (uint32_t ptel
)
252 return ((ptel
& PTEL_PPN_MASK
) >> PTEL_PPN_OFFSET
);
255 #define PTEL_PR_BITS (2)
256 #define PTEL_PR_OFFSET (5)
257 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
258 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
259 static inline int cpu_ptel_pr (uint32_t ptel
)
261 return ((ptel
& PTEL_PR_MASK
) >> PTEL_PR_OFFSET
);
264 /* PTEA : Page Translation Entry Assistance register */
265 #define PTEA_SA_BITS (3)
266 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
267 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
268 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
269 #define PTEA_TC (1 << 3)
270 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
272 #endif /* _CPU_SH4_H */