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softfloat-native: fix *nan()
[qemu/qemu-JZ.git] / target-ppc / op_helper.c
blob20b124a63b6cb9d635bd06d67ec8cd1ac06e9567
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22 #include "helper.h"
23
24 #include "helper_regs.h"
25
26 //#define DEBUG_OP
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
29
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
32
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
34 {
35 #if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37 #endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
41 }
42
43 void helper_raise_exception (uint32_t exception)
44 {
45 helper_raise_exception_err(exception, 0);
46 }
47
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
51 {
52 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
60 }
61
62 void helper_store_cr (target_ulong val, uint32_t mask)
63 {
64 int i, sh;
65
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
67 if (mask & (1 << sh))
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
69 }
70 }
71
72 /*****************************************************************************/
73 /* SPR accesses */
74 void helper_load_dump_spr (uint32_t sprn)
75 {
76 if (loglevel != 0) {
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
80 }
81
82 void helper_store_dump_spr (uint32_t sprn)
83 {
84 if (loglevel != 0) {
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
87 }
88 }
89
90 target_ulong helper_load_tbl (void)
91 {
92 return cpu_ppc_load_tbl(env);
93 }
94
95 target_ulong helper_load_tbu (void)
96 {
97 return cpu_ppc_load_tbu(env);
98 }
99
100 target_ulong helper_load_atbl (void)
101 {
102 return cpu_ppc_load_atbl(env);
103 }
104
105 target_ulong helper_load_atbu (void)
106 {
107 return cpu_ppc_load_atbu(env);
108 }
109
110 target_ulong helper_load_601_rtcl (void)
111 {
112 return cpu_ppc601_load_rtcl(env);
113 }
114
115 target_ulong helper_load_601_rtcu (void)
116 {
117 return cpu_ppc601_load_rtcu(env);
118 }
119
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
123 {
124 ppc_store_asr(env, val);
125 }
126 #endif
127
128 void helper_store_sdr1 (target_ulong val)
129 {
130 ppc_store_sdr1(env, val);
131 }
132
133 void helper_store_tbl (target_ulong val)
134 {
135 cpu_ppc_store_tbl(env, val);
136 }
137
138 void helper_store_tbu (target_ulong val)
139 {
140 cpu_ppc_store_tbu(env, val);
141 }
142
143 void helper_store_atbl (target_ulong val)
144 {
145 cpu_ppc_store_atbl(env, val);
146 }
147
148 void helper_store_atbu (target_ulong val)
149 {
150 cpu_ppc_store_atbu(env, val);
151 }
152
153 void helper_store_601_rtcl (target_ulong val)
154 {
155 cpu_ppc601_store_rtcl(env, val);
156 }
157
158 void helper_store_601_rtcu (target_ulong val)
159 {
160 cpu_ppc601_store_rtcu(env, val);
161 }
162
163 target_ulong helper_load_decr (void)
164 {
165 return cpu_ppc_load_decr(env);
166 }
167
168 void helper_store_decr (target_ulong val)
169 {
170 cpu_ppc_store_decr(env, val);
171 }
172
173 void helper_store_hid0_601 (target_ulong val)
174 {
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
188 }
189 env->spr[SPR_HID0] = (uint32_t)val;
190 }
191
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
193 {
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199 }
200
201 target_ulong helper_load_40x_pit (void)
202 {
203 return load_40x_pit(env);
204 }
205
206 void helper_store_40x_pit (target_ulong val)
207 {
208 store_40x_pit(env, val);
209 }
210
211 void helper_store_40x_dbcr0 (target_ulong val)
212 {
213 store_40x_dbcr0(env, val);
214 }
215
216 void helper_store_40x_sler (target_ulong val)
217 {
218 store_40x_sler(env, val);
219 }
220
221 void helper_store_booke_tcr (target_ulong val)
222 {
223 store_booke_tcr(env, val);
224 }
225
226 void helper_store_booke_tsr (target_ulong val)
227 {
228 store_booke_tsr(env, val);
229 }
230
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
232 {
233 ppc_store_ibatu(env, nr, val);
234 }
235
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
237 {
238 ppc_store_ibatl(env, nr, val);
239 }
240
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
242 {
243 ppc_store_dbatu(env, nr, val);
244 }
245
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
247 {
248 ppc_store_dbatl(env, nr, val);
249 }
250
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
252 {
253 ppc_store_ibatl_601(env, nr, val);
254 }
255
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
257 {
258 ppc_store_ibatu_601(env, nr, val);
259 }
260 #endif
261
262 /*****************************************************************************/
263 /* Memory load and stores */
264
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
266 {
267 #if defined(TARGET_PPC64)
268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
270 else
271 #endif
272 return addr + arg;
273 }
274
275 void helper_lmw (target_ulong addr, uint32_t reg)
276 {
277 for (; reg < 32; reg++) {
278 if (msr_le)
279 env->gpr[reg] = bswap32(ldl(addr));
280 else
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
283 }
284 }
285
286 void helper_stmw (target_ulong addr, uint32_t reg)
287 {
288 for (; reg < 32; reg++) {
289 if (msr_le)
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
291 else
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
294 }
295 }
296
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298 {
299 int sh;
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
310 }
311 }
312 }
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319 {
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330 }
331
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333 {
334 int sh;
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
339 }
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
344 }
345 }
346
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
348 {
349 addr &= ~(dcache_line_size - 1);
350 int i;
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
352 stl(addr + i , 0);
353 }
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
356 }
357
358 void helper_dcbz(target_ulong addr)
359 {
360 do_dcbz(addr, env->dcache_line_size);
361 }
362
363 void helper_dcbz_970(target_ulong addr)
364 {
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
366 do_dcbz(addr, 32);
367 else
368 do_dcbz(addr, env->dcache_line_size);
369 }
370
371 void helper_icbi(target_ulong addr)
372 {
373 uint32_t tmp;
374
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
380 */
381 tmp = ldl(addr);
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
383 }
384
385 // XXX: to be tested
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
387 {
388 int i, c, d;
389 d = 24;
390 for (i = 0; i < xer_bc; i++) {
391 c = ldub(addr);
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
396 }
397 if (unlikely(c == xer_cmp))
398 break;
399 if (likely(d != 0)) {
400 d -= 8;
401 } else {
402 d = 24;
403 reg++;
404 reg = reg & 0x1F;
405 }
406 }
407 return i;
408 }
409
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
413
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
416 {
417 uint64_t tl, th;
418
419 muls64(&tl, &th, arg1, arg2);
420 return th;
421 }
422
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
425 {
426 uint64_t tl, th;
427
428 mulu64(&tl, &th, arg1, arg2);
429 return th;
430 }
431
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
433 {
434 int64_t th;
435 uint64_t tl;
436
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
441 } else {
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
443 }
444 return (int64_t)tl;
445 }
446 #endif
447
448 target_ulong helper_cntlzw (target_ulong t)
449 {
450 return clz32(t);
451 }
452
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
455 {
456 return clz64(t);
457 }
458 #endif
459
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
462 {
463 int32_t ret;
464
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
467 shift &= 0x1f;
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
471 } else {
472 env->xer |= (1 << XER_CA);
473 }
474 } else {
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
477 }
478 } else {
479 ret = (int32_t)value >> 31;
480 if (ret) {
481 env->xer |= (1 << XER_CA);
482 } else {
483 env->xer &= ~(1 << XER_CA);
484 }
485 }
486 return (target_long)ret;
487 }
488
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
491 {
492 int64_t ret;
493
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
496 shift &= 0x3f;
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
500 } else {
501 env->xer |= (1 << XER_CA);
502 }
503 } else {
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
506 }
507 } else {
508 ret = (int64_t)value >> 63;
509 if (ret) {
510 env->xer |= (1 << XER_CA);
511 } else {
512 env->xer &= ~(1 << XER_CA);
513 }
514 }
515 return ret;
516 }
517 #endif
518
519 target_ulong helper_popcntb (target_ulong val)
520 {
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
524 return val;
525 }
526
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
529 {
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
533 return val;
534 }
535 #endif
536
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
540 {
541 CPU_FloatU f;
542 CPU_DoubleU d;
543 f.l = arg;
544 d.d = float32_to_float64(f.f, &env->fp_status);
545 return d.ll;
546 }
547
548 uint32_t helper_float64_to_float32(uint64_t arg)
549 {
550 CPU_FloatU f;
551 CPU_DoubleU d;
552 d.ll = arg;
553 f.f = float64_to_float32(d.d, &env->fp_status);
554 return f.l;
555 }
556
557 static always_inline int fpisneg (float64 d)
558 {
559 CPU_DoubleU u;
560
561 u.d = d;
562
563 return u.ll >> 63 != 0;
564 }
565
566 static always_inline int isden (float64 d)
567 {
568 CPU_DoubleU u;
569
570 u.d = d;
571
572 return ((u.ll >> 52) & 0x7FF) == 0;
573 }
574
575 static always_inline int iszero (float64 d)
576 {
577 CPU_DoubleU u;
578
579 u.d = d;
580
581 return (u.ll & ~0x8000000000000000ULL) == 0;
582 }
583
584 static always_inline int isinfinity (float64 d)
585 {
586 CPU_DoubleU u;
587
588 u.d = d;
589
590 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
591 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
592 }
593
594 #ifdef CONFIG_SOFTFLOAT
595 static always_inline int isfinite (float64 d)
596 {
597 CPU_DoubleU u;
598
599 u.d = d;
600
601 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
602 }
603
604 static always_inline int isnormal (float64 d)
605 {
606 CPU_DoubleU u;
607
608 u.d = d;
609
610 uint32_t exp = (u.ll >> 52) & 0x7FF;
611 return ((0 < exp) && (exp < 0x7FF));
612 }
613 #endif
614
615 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
616 {
617 CPU_DoubleU farg;
618 int isneg;
619 int ret;
620 farg.ll = arg;
621 isneg = fpisneg(farg.d);
622 if (unlikely(float64_is_nan(farg.d))) {
623 if (float64_is_signaling_nan(farg.d)) {
624 /* Signaling NaN: flags are undefined */
625 ret = 0x00;
626 } else {
627 /* Quiet NaN */
628 ret = 0x11;
629 }
630 } else if (unlikely(isinfinity(farg.d))) {
631 /* +/- infinity */
632 if (isneg)
633 ret = 0x09;
634 else
635 ret = 0x05;
636 } else {
637 if (iszero(farg.d)) {
638 /* +/- zero */
639 if (isneg)
640 ret = 0x12;
641 else
642 ret = 0x02;
643 } else {
644 if (isden(farg.d)) {
645 /* Denormalized numbers */
646 ret = 0x10;
647 } else {
648 /* Normalized numbers */
649 ret = 0x00;
650 }
651 if (isneg) {
652 ret |= 0x08;
653 } else {
654 ret |= 0x04;
655 }
656 }
657 }
658 if (set_fprf) {
659 /* We update FPSCR_FPRF */
660 env->fpscr &= ~(0x1F << FPSCR_FPRF);
661 env->fpscr |= ret << FPSCR_FPRF;
662 }
663 /* We just need fpcc to update Rc1 */
664 return ret & 0xF;
665 }
666
667 /* Floating-point invalid operations exception */
668 static always_inline uint64_t fload_invalid_op_excp (int op)
669 {
670 uint64_t ret = 0;
671 int ve;
672
673 ve = fpscr_ve;
674 switch (op) {
675 case POWERPC_EXCP_FP_VXSNAN:
676 env->fpscr |= 1 << FPSCR_VXSNAN;
677 break;
678 case POWERPC_EXCP_FP_VXSOFT:
679 env->fpscr |= 1 << FPSCR_VXSOFT;
680 break;
681 case POWERPC_EXCP_FP_VXISI:
682 /* Magnitude subtraction of infinities */
683 env->fpscr |= 1 << FPSCR_VXISI;
684 goto update_arith;
685 case POWERPC_EXCP_FP_VXIDI:
686 /* Division of infinity by infinity */
687 env->fpscr |= 1 << FPSCR_VXIDI;
688 goto update_arith;
689 case POWERPC_EXCP_FP_VXZDZ:
690 /* Division of zero by zero */
691 env->fpscr |= 1 << FPSCR_VXZDZ;
692 goto update_arith;
693 case POWERPC_EXCP_FP_VXIMZ:
694 /* Multiplication of zero by infinity */
695 env->fpscr |= 1 << FPSCR_VXIMZ;
696 goto update_arith;
697 case POWERPC_EXCP_FP_VXVC:
698 /* Ordered comparison of NaN */
699 env->fpscr |= 1 << FPSCR_VXVC;
700 env->fpscr &= ~(0xF << FPSCR_FPCC);
701 env->fpscr |= 0x11 << FPSCR_FPCC;
702 /* We must update the target FPR before raising the exception */
703 if (ve != 0) {
704 env->exception_index = POWERPC_EXCP_PROGRAM;
705 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
706 /* Update the floating-point enabled exception summary */
707 env->fpscr |= 1 << FPSCR_FEX;
708 /* Exception is differed */
709 ve = 0;
710 }
711 break;
712 case POWERPC_EXCP_FP_VXSQRT:
713 /* Square root of a negative number */
714 env->fpscr |= 1 << FPSCR_VXSQRT;
715 update_arith:
716 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
717 if (ve == 0) {
718 /* Set the result to quiet NaN */
719 ret = 0xFFF8000000000000ULL;
720 env->fpscr &= ~(0xF << FPSCR_FPCC);
721 env->fpscr |= 0x11 << FPSCR_FPCC;
722 }
723 break;
724 case POWERPC_EXCP_FP_VXCVI:
725 /* Invalid conversion */
726 env->fpscr |= 1 << FPSCR_VXCVI;
727 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
728 if (ve == 0) {
729 /* Set the result to quiet NaN */
730 ret = 0xFFF8000000000000ULL;
731 env->fpscr &= ~(0xF << FPSCR_FPCC);
732 env->fpscr |= 0x11 << FPSCR_FPCC;
733 }
734 break;
735 }
736 /* Update the floating-point invalid operation summary */
737 env->fpscr |= 1 << FPSCR_VX;
738 /* Update the floating-point exception summary */
739 env->fpscr |= 1 << FPSCR_FX;
740 if (ve != 0) {
741 /* Update the floating-point enabled exception summary */
742 env->fpscr |= 1 << FPSCR_FEX;
743 if (msr_fe0 != 0 || msr_fe1 != 0)
744 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
745 }
746 return ret;
747 }
748
749 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
750 {
751 env->fpscr |= 1 << FPSCR_ZX;
752 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
753 /* Update the floating-point exception summary */
754 env->fpscr |= 1 << FPSCR_FX;
755 if (fpscr_ze != 0) {
756 /* Update the floating-point enabled exception summary */
757 env->fpscr |= 1 << FPSCR_FEX;
758 if (msr_fe0 != 0 || msr_fe1 != 0) {
759 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
760 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
761 }
762 } else {
763 /* Set the result to infinity */
764 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
765 arg1 |= 0x7FFULL << 52;
766 }
767 return arg1;
768 }
769
770 static always_inline void float_overflow_excp (void)
771 {
772 env->fpscr |= 1 << FPSCR_OX;
773 /* Update the floating-point exception summary */
774 env->fpscr |= 1 << FPSCR_FX;
775 if (fpscr_oe != 0) {
776 /* XXX: should adjust the result */
777 /* Update the floating-point enabled exception summary */
778 env->fpscr |= 1 << FPSCR_FEX;
779 /* We must update the target FPR before raising the exception */
780 env->exception_index = POWERPC_EXCP_PROGRAM;
781 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
782 } else {
783 env->fpscr |= 1 << FPSCR_XX;
784 env->fpscr |= 1 << FPSCR_FI;
785 }
786 }
787
788 static always_inline void float_underflow_excp (void)
789 {
790 env->fpscr |= 1 << FPSCR_UX;
791 /* Update the floating-point exception summary */
792 env->fpscr |= 1 << FPSCR_FX;
793 if (fpscr_ue != 0) {
794 /* XXX: should adjust the result */
795 /* Update the floating-point enabled exception summary */
796 env->fpscr |= 1 << FPSCR_FEX;
797 /* We must update the target FPR before raising the exception */
798 env->exception_index = POWERPC_EXCP_PROGRAM;
799 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
800 }
801 }
802
803 static always_inline void float_inexact_excp (void)
804 {
805 env->fpscr |= 1 << FPSCR_XX;
806 /* Update the floating-point exception summary */
807 env->fpscr |= 1 << FPSCR_FX;
808 if (fpscr_xe != 0) {
809 /* Update the floating-point enabled exception summary */
810 env->fpscr |= 1 << FPSCR_FEX;
811 /* We must update the target FPR before raising the exception */
812 env->exception_index = POWERPC_EXCP_PROGRAM;
813 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
814 }
815 }
816
817 static always_inline void fpscr_set_rounding_mode (void)
818 {
819 int rnd_type;
820
821 /* Set rounding mode */
822 switch (fpscr_rn) {
823 case 0:
824 /* Best approximation (round to nearest) */
825 rnd_type = float_round_nearest_even;
826 break;
827 case 1:
828 /* Smaller magnitude (round toward zero) */
829 rnd_type = float_round_to_zero;
830 break;
831 case 2:
832 /* Round toward +infinite */
833 rnd_type = float_round_up;
834 break;
835 default:
836 case 3:
837 /* Round toward -infinite */
838 rnd_type = float_round_down;
839 break;
840 }
841 set_float_rounding_mode(rnd_type, &env->fp_status);
842 }
843
844 void helper_fpscr_clrbit (uint32_t bit)
845 {
846 int prev;
847
848 prev = (env->fpscr >> bit) & 1;
849 env->fpscr &= ~(1 << bit);
850 if (prev == 1) {
851 switch (bit) {
852 case FPSCR_RN1:
853 case FPSCR_RN:
854 fpscr_set_rounding_mode();
855 break;
856 default:
857 break;
858 }
859 }
860 }
861
862 void helper_fpscr_setbit (uint32_t bit)
863 {
864 int prev;
865
866 prev = (env->fpscr >> bit) & 1;
867 env->fpscr |= 1 << bit;
868 if (prev == 0) {
869 switch (bit) {
870 case FPSCR_VX:
871 env->fpscr |= 1 << FPSCR_FX;
872 if (fpscr_ve)
873 goto raise_ve;
874 case FPSCR_OX:
875 env->fpscr |= 1 << FPSCR_FX;
876 if (fpscr_oe)
877 goto raise_oe;
878 break;
879 case FPSCR_UX:
880 env->fpscr |= 1 << FPSCR_FX;
881 if (fpscr_ue)
882 goto raise_ue;
883 break;
884 case FPSCR_ZX:
885 env->fpscr |= 1 << FPSCR_FX;
886 if (fpscr_ze)
887 goto raise_ze;
888 break;
889 case FPSCR_XX:
890 env->fpscr |= 1 << FPSCR_FX;
891 if (fpscr_xe)
892 goto raise_xe;
893 break;
894 case FPSCR_VXSNAN:
895 case FPSCR_VXISI:
896 case FPSCR_VXIDI:
897 case FPSCR_VXZDZ:
898 case FPSCR_VXIMZ:
899 case FPSCR_VXVC:
900 case FPSCR_VXSOFT:
901 case FPSCR_VXSQRT:
902 case FPSCR_VXCVI:
903 env->fpscr |= 1 << FPSCR_VX;
904 env->fpscr |= 1 << FPSCR_FX;
905 if (fpscr_ve != 0)
906 goto raise_ve;
907 break;
908 case FPSCR_VE:
909 if (fpscr_vx != 0) {
910 raise_ve:
911 env->error_code = POWERPC_EXCP_FP;
912 if (fpscr_vxsnan)
913 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
914 if (fpscr_vxisi)
915 env->error_code |= POWERPC_EXCP_FP_VXISI;
916 if (fpscr_vxidi)
917 env->error_code |= POWERPC_EXCP_FP_VXIDI;
918 if (fpscr_vxzdz)
919 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
920 if (fpscr_vximz)
921 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
922 if (fpscr_vxvc)
923 env->error_code |= POWERPC_EXCP_FP_VXVC;
924 if (fpscr_vxsoft)
925 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
926 if (fpscr_vxsqrt)
927 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
928 if (fpscr_vxcvi)
929 env->error_code |= POWERPC_EXCP_FP_VXCVI;
930 goto raise_excp;
931 }
932 break;
933 case FPSCR_OE:
934 if (fpscr_ox != 0) {
935 raise_oe:
936 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
937 goto raise_excp;
938 }
939 break;
940 case FPSCR_UE:
941 if (fpscr_ux != 0) {
942 raise_ue:
943 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
944 goto raise_excp;
945 }
946 break;
947 case FPSCR_ZE:
948 if (fpscr_zx != 0) {
949 raise_ze:
950 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
951 goto raise_excp;
952 }
953 break;
954 case FPSCR_XE:
955 if (fpscr_xx != 0) {
956 raise_xe:
957 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
958 goto raise_excp;
959 }
960 break;
961 case FPSCR_RN1:
962 case FPSCR_RN:
963 fpscr_set_rounding_mode();
964 break;
965 default:
966 break;
967 raise_excp:
968 /* Update the floating-point enabled exception summary */
969 env->fpscr |= 1 << FPSCR_FEX;
970 /* We have to update Rc1 before raising the exception */
971 env->exception_index = POWERPC_EXCP_PROGRAM;
972 break;
973 }
974 }
975 }
976
977 void helper_store_fpscr (uint64_t arg, uint32_t mask)
978 {
979 /*
980 * We use only the 32 LSB of the incoming fpr
981 */
982 uint32_t prev, new;
983 int i;
984
985 prev = env->fpscr;
986 new = (uint32_t)arg;
987 new &= ~0x60000000;
988 new |= prev & 0x60000000;
989 for (i = 0; i < 8; i++) {
990 if (mask & (1 << i)) {
991 env->fpscr &= ~(0xF << (4 * i));
992 env->fpscr |= new & (0xF << (4 * i));
993 }
994 }
995 /* Update VX and FEX */
996 if (fpscr_ix != 0)
997 env->fpscr |= 1 << FPSCR_VX;
998 else
999 env->fpscr &= ~(1 << FPSCR_VX);
1000 if ((fpscr_ex & fpscr_eex) != 0) {
1001 env->fpscr |= 1 << FPSCR_FEX;
1002 env->exception_index = POWERPC_EXCP_PROGRAM;
1003 /* XXX: we should compute it properly */
1004 env->error_code = POWERPC_EXCP_FP;
1005 }
1006 else
1007 env->fpscr &= ~(1 << FPSCR_FEX);
1008 fpscr_set_rounding_mode();
1009 }
1010
1011 void helper_float_check_status (void)
1012 {
1013 #ifdef CONFIG_SOFTFLOAT
1014 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1015 (env->error_code & POWERPC_EXCP_FP)) {
1016 /* Differred floating-point exception after target FPR update */
1017 if (msr_fe0 != 0 || msr_fe1 != 0)
1018 helper_raise_exception_err(env->exception_index, env->error_code);
1019 } else {
1020 int status = get_float_exception_flags(&env->fp_status);
1021 if (status & float_flag_overflow) {
1022 float_overflow_excp();
1023 } else if (status & float_flag_underflow) {
1024 float_underflow_excp();
1025 } else if (status & float_flag_inexact) {
1026 float_inexact_excp();
1027 }
1028 }
1029 #else
1030 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1031 (env->error_code & POWERPC_EXCP_FP)) {
1032 /* Differred floating-point exception after target FPR update */
1033 if (msr_fe0 != 0 || msr_fe1 != 0)
1034 helper_raise_exception_err(env->exception_index, env->error_code);
1035 }
1036 #endif
1037 }
1038
1039 #ifdef CONFIG_SOFTFLOAT
1040 void helper_reset_fpstatus (void)
1041 {
1042 set_float_exception_flags(0, &env->fp_status);
1043 }
1044 #endif
1045
1046 /* fadd - fadd. */
1047 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1048 {
1049 CPU_DoubleU farg1, farg2;
1050
1051 farg1.ll = arg1;
1052 farg2.ll = arg2;
1053 #if USE_PRECISE_EMULATION
1054 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1055 float64_is_signaling_nan(farg2.d))) {
1056 /* sNaN addition */
1057 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1058 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1059 fpisneg(farg1.d) == fpisneg(farg2.d))) {
1060 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1061 } else {
1062 /* Magnitude subtraction of infinities */
1063 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1064 }
1065 #else
1066 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1067 #endif
1068 return farg1.ll;
1069 }
1070
1071 /* fsub - fsub. */
1072 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1073 {
1074 CPU_DoubleU farg1, farg2;
1075
1076 farg1.ll = arg1;
1077 farg2.ll = arg2;
1078 #if USE_PRECISE_EMULATION
1079 {
1080 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1081 float64_is_signaling_nan(farg2.d))) {
1082 /* sNaN subtraction */
1083 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1084 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1085 fpisneg(farg1.d) != fpisneg(farg2.d))) {
1086 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1087 } else {
1088 /* Magnitude subtraction of infinities */
1089 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1090 }
1091 }
1092 #else
1093 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1094 #endif
1095 return farg1.ll;
1096 }
1097
1098 /* fmul - fmul. */
1099 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1100 {
1101 CPU_DoubleU farg1, farg2;
1102
1103 farg1.ll = arg1;
1104 farg2.ll = arg2;
1105 #if USE_PRECISE_EMULATION
1106 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1107 float64_is_signaling_nan(farg2.d))) {
1108 /* sNaN multiplication */
1109 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1110 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
1111 (iszero(farg1.d) && isinfinity(farg2.d)))) {
1112 /* Multiplication of zero by infinity */
1113 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1114 } else {
1115 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1116 }
1117 #else
1118 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1119 #endif
1120 return farg1.ll;
1121 }
1122
1123 /* fdiv - fdiv. */
1124 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1125 {
1126 CPU_DoubleU farg1, farg2;
1127
1128 farg1.ll = arg1;
1129 farg2.ll = arg2;
1130 #if USE_PRECISE_EMULATION
1131 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1132 float64_is_signaling_nan(farg2.d))) {
1133 /* sNaN division */
1134 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1135 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
1136 /* Division of infinity by infinity */
1137 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1138 } else if (unlikely(!float64_is_nan(farg1.d) && iszero(farg2.d))) {
1139 if (iszero(farg1.d)) {
1140 /* Division of zero by zero */
1141 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1142 } else {
1143 /* Division by zero */
1144 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1145 }
1146 } else {
1147 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1148 }
1149 #else
1150 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1151 #endif
1152 return farg1.ll;
1153 }
1154
1155 /* fabs */
1156 uint64_t helper_fabs (uint64_t arg)
1157 {
1158 CPU_DoubleU farg;
1159
1160 farg.ll = arg;
1161 farg.d = float64_abs(farg.d);
1162 return farg.ll;
1163 }
1164
1165 /* fnabs */
1166 uint64_t helper_fnabs (uint64_t arg)
1167 {
1168 CPU_DoubleU farg;
1169
1170 farg.ll = arg;
1171 farg.d = float64_abs(farg.d);
1172 farg.d = float64_chs(farg.d);
1173 return farg.ll;
1174 }
1175
1176 /* fneg */
1177 uint64_t helper_fneg (uint64_t arg)
1178 {
1179 CPU_DoubleU farg;
1180
1181 farg.ll = arg;
1182 farg.d = float64_chs(farg.d);
1183 return farg.ll;
1184 }
1185
1186 /* fctiw - fctiw. */
1187 uint64_t helper_fctiw (uint64_t arg)
1188 {
1189 CPU_DoubleU farg;
1190 farg.ll = arg;
1191
1192 if (unlikely(float64_is_signaling_nan(farg.d))) {
1193 /* sNaN conversion */
1194 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1195 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1196 /* qNan / infinity conversion */
1197 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1198 } else {
1199 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1200 #if USE_PRECISE_EMULATION
1201 /* XXX: higher bits are not supposed to be significant.
1202 * to make tests easier, return the same as a real PowerPC 750
1203 */
1204 farg.ll |= 0xFFF80000ULL << 32;
1205 #endif
1206 }
1207 return farg.ll;
1208 }
1209
1210 /* fctiwz - fctiwz. */
1211 uint64_t helper_fctiwz (uint64_t arg)
1212 {
1213 CPU_DoubleU farg;
1214 farg.ll = arg;
1215
1216 if (unlikely(float64_is_signaling_nan(farg.d))) {
1217 /* sNaN conversion */
1218 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1219 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1220 /* qNan / infinity conversion */
1221 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1222 } else {
1223 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1224 #if USE_PRECISE_EMULATION
1225 /* XXX: higher bits are not supposed to be significant.
1226 * to make tests easier, return the same as a real PowerPC 750
1227 */
1228 farg.ll |= 0xFFF80000ULL << 32;
1229 #endif
1230 }
1231 return farg.ll;
1232 }
1233
1234 #if defined(TARGET_PPC64)
1235 /* fcfid - fcfid. */
1236 uint64_t helper_fcfid (uint64_t arg)
1237 {
1238 CPU_DoubleU farg;
1239 farg.d = int64_to_float64(arg, &env->fp_status);
1240 return farg.ll;
1241 }
1242
1243 /* fctid - fctid. */
1244 uint64_t helper_fctid (uint64_t arg)
1245 {
1246 CPU_DoubleU farg;
1247 farg.ll = arg;
1248
1249 if (unlikely(float64_is_signaling_nan(farg.d))) {
1250 /* sNaN conversion */
1251 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1252 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1253 /* qNan / infinity conversion */
1254 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1255 } else {
1256 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1257 }
1258 return farg.ll;
1259 }
1260
1261 /* fctidz - fctidz. */
1262 uint64_t helper_fctidz (uint64_t arg)
1263 {
1264 CPU_DoubleU farg;
1265 farg.ll = arg;
1266
1267 if (unlikely(float64_is_signaling_nan(farg.d))) {
1268 /* sNaN conversion */
1269 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1270 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1271 /* qNan / infinity conversion */
1272 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1273 } else {
1274 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1275 }
1276 return farg.ll;
1277 }
1278
1279 #endif
1280
1281 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1282 {
1283 CPU_DoubleU farg;
1284 farg.ll = arg;
1285
1286 if (unlikely(float64_is_signaling_nan(farg.d))) {
1287 /* sNaN round */
1288 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1289 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1290 /* qNan / infinity round */
1291 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1292 } else {
1293 set_float_rounding_mode(rounding_mode, &env->fp_status);
1294 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1295 /* Restore rounding mode from FPSCR */
1296 fpscr_set_rounding_mode();
1297 }
1298 return farg.ll;
1299 }
1300
1301 uint64_t helper_frin (uint64_t arg)
1302 {
1303 return do_fri(arg, float_round_nearest_even);
1304 }
1305
1306 uint64_t helper_friz (uint64_t arg)
1307 {
1308 return do_fri(arg, float_round_to_zero);
1309 }
1310
1311 uint64_t helper_frip (uint64_t arg)
1312 {
1313 return do_fri(arg, float_round_up);
1314 }
1315
1316 uint64_t helper_frim (uint64_t arg)
1317 {
1318 return do_fri(arg, float_round_down);
1319 }
1320
1321 /* fmadd - fmadd. */
1322 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1323 {
1324 CPU_DoubleU farg1, farg2, farg3;
1325
1326 farg1.ll = arg1;
1327 farg2.ll = arg2;
1328 farg3.ll = arg3;
1329 #if USE_PRECISE_EMULATION
1330 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1331 float64_is_signaling_nan(farg2.d) ||
1332 float64_is_signaling_nan(farg3.d))) {
1333 /* sNaN operation */
1334 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1335 } else {
1336 #ifdef FLOAT128
1337 /* This is the way the PowerPC specification defines it */
1338 float128 ft0_128, ft1_128;
1339
1340 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1341 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1342 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1343 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1344 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1345 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1346 #else
1347 /* This is OK on x86 hosts */
1348 farg1.d = (farg1.d * farg2.d) + farg3.d;
1349 #endif
1350 }
1351 #else
1352 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1353 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1354 #endif
1355 return farg1.ll;
1356 }
1357
1358 /* fmsub - fmsub. */
1359 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1360 {
1361 CPU_DoubleU farg1, farg2, farg3;
1362
1363 farg1.ll = arg1;
1364 farg2.ll = arg2;
1365 farg3.ll = arg3;
1366 #if USE_PRECISE_EMULATION
1367 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1368 float64_is_signaling_nan(farg2.d) ||
1369 float64_is_signaling_nan(farg3.d))) {
1370 /* sNaN operation */
1371 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1372 } else {
1373 #ifdef FLOAT128
1374 /* This is the way the PowerPC specification defines it */
1375 float128 ft0_128, ft1_128;
1376
1377 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1378 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1379 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1380 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1381 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1382 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1383 #else
1384 /* This is OK on x86 hosts */
1385 farg1.d = (farg1.d * farg2.d) - farg3.d;
1386 #endif
1387 }
1388 #else
1389 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1390 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1391 #endif
1392 return farg1.ll;
1393 }
1394
1395 /* fnmadd - fnmadd. */
1396 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1397 {
1398 CPU_DoubleU farg1, farg2, farg3;
1399
1400 farg1.ll = arg1;
1401 farg2.ll = arg2;
1402 farg3.ll = arg3;
1403
1404 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1405 float64_is_signaling_nan(farg2.d) ||
1406 float64_is_signaling_nan(farg3.d))) {
1407 /* sNaN operation */
1408 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1409 } else {
1410 #if USE_PRECISE_EMULATION
1411 #ifdef FLOAT128
1412 /* This is the way the PowerPC specification defines it */
1413 float128 ft0_128, ft1_128;
1414
1415 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1416 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1417 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1418 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1419 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1420 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1421 #else
1422 /* This is OK on x86 hosts */
1423 farg1.d = (farg1.d * farg2.d) + farg3.d;
1424 #endif
1425 #else
1426 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1427 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1428 #endif
1429 if (likely(!float64_is_nan(farg1.d)))
1430 farg1.d = float64_chs(farg1.d);
1431 }
1432 return farg1.ll;
1433 }
1434
1435 /* fnmsub - fnmsub. */
1436 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1437 {
1438 CPU_DoubleU farg1, farg2, farg3;
1439
1440 farg1.ll = arg1;
1441 farg2.ll = arg2;
1442 farg3.ll = arg3;
1443
1444 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1445 float64_is_signaling_nan(farg2.d) ||
1446 float64_is_signaling_nan(farg3.d))) {
1447 /* sNaN operation */
1448 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1449 } else {
1450 #if USE_PRECISE_EMULATION
1451 #ifdef FLOAT128
1452 /* This is the way the PowerPC specification defines it */
1453 float128 ft0_128, ft1_128;
1454
1455 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1456 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1457 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1458 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1459 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1460 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1461 #else
1462 /* This is OK on x86 hosts */
1463 farg1.d = (farg1.d * farg2.d) - farg3.d;
1464 #endif
1465 #else
1466 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1467 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1468 #endif
1469 if (likely(!float64_is_nan(farg1.d)))
1470 farg1.d = float64_chs(farg1.d);
1471 }
1472 return farg1.ll;
1473 }
1474
1475 /* frsp - frsp. */
1476 uint64_t helper_frsp (uint64_t arg)
1477 {
1478 CPU_DoubleU farg;
1479 float32 f32;
1480 farg.ll = arg;
1481
1482 #if USE_PRECISE_EMULATION
1483 if (unlikely(float64_is_signaling_nan(farg.d))) {
1484 /* sNaN square root */
1485 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1486 } else {
1487 f32 = float64_to_float32(farg.d, &env->fp_status);
1488 farg.d = float32_to_float64(f32, &env->fp_status);
1489 }
1490 #else
1491 f32 = float64_to_float32(farg.d, &env->fp_status);
1492 farg.d = float32_to_float64(f32, &env->fp_status);
1493 #endif
1494 return farg.ll;
1495 }
1496
1497 /* fsqrt - fsqrt. */
1498 uint64_t helper_fsqrt (uint64_t arg)
1499 {
1500 CPU_DoubleU farg;
1501 farg.ll = arg;
1502
1503 if (unlikely(float64_is_signaling_nan(farg.d))) {
1504 /* sNaN square root */
1505 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1506 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1507 /* Square root of a negative nonzero number */
1508 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1509 } else {
1510 farg.d = float64_sqrt(farg.d, &env->fp_status);
1511 }
1512 return farg.ll;
1513 }
1514
1515 /* fre - fre. */
1516 uint64_t helper_fre (uint64_t arg)
1517 {
1518 CPU_DoubleU fone, farg;
1519 fone.ll = 0x3FF0000000000000ULL;
1520 farg.ll = arg;
1521
1522 if (unlikely(float64_is_signaling_nan(farg.d))) {
1523 /* sNaN reciprocal */
1524 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1525 } else if (unlikely(iszero(farg.d))) {
1526 /* Zero reciprocal */
1527 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1528 } else if (likely(isnormal(farg.d))) {
1529 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1530 } else {
1531 if (farg.ll == 0x8000000000000000ULL) {
1532 farg.ll = 0xFFF0000000000000ULL;
1533 } else if (farg.ll == 0x0000000000000000ULL) {
1534 farg.ll = 0x7FF0000000000000ULL;
1535 } else if (float64_is_nan(farg.d)) {
1536 farg.ll = 0x7FF8000000000000ULL;
1537 } else if (fpisneg(farg.d)) {
1538 farg.ll = 0x8000000000000000ULL;
1539 } else {
1540 farg.ll = 0x0000000000000000ULL;
1541 }
1542 }
1543 return farg.d;
1544 }
1545
1546 /* fres - fres. */
1547 uint64_t helper_fres (uint64_t arg)
1548 {
1549 CPU_DoubleU fone, farg;
1550 fone.ll = 0x3FF0000000000000ULL;
1551 farg.ll = arg;
1552
1553 if (unlikely(float64_is_signaling_nan(farg.d))) {
1554 /* sNaN reciprocal */
1555 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1556 } else if (unlikely(iszero(farg.d))) {
1557 /* Zero reciprocal */
1558 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1559 } else if (likely(isnormal(farg.d))) {
1560 #if USE_PRECISE_EMULATION
1561 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1562 farg.d = float64_to_float32(farg.d, &env->fp_status);
1563 #else
1564 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1565 #endif
1566 } else {
1567 if (farg.ll == 0x8000000000000000ULL) {
1568 farg.ll = 0xFFF0000000000000ULL;
1569 } else if (farg.ll == 0x0000000000000000ULL) {
1570 farg.ll = 0x7FF0000000000000ULL;
1571 } else if (float64_is_nan(farg.d)) {
1572 farg.ll = 0x7FF8000000000000ULL;
1573 } else if (fpisneg(farg.d)) {
1574 farg.ll = 0x8000000000000000ULL;
1575 } else {
1576 farg.ll = 0x0000000000000000ULL;
1577 }
1578 }
1579 return farg.ll;
1580 }
1581
1582 /* frsqrte - frsqrte. */
1583 uint64_t helper_frsqrte (uint64_t arg)
1584 {
1585 CPU_DoubleU fone, farg;
1586 fone.ll = 0x3FF0000000000000ULL;
1587 farg.ll = arg;
1588
1589 if (unlikely(float64_is_signaling_nan(farg.d))) {
1590 /* sNaN reciprocal square root */
1591 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1592 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1593 /* Reciprocal square root of a negative nonzero number */
1594 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1595 } else if (likely(isnormal(farg.d))) {
1596 farg.d = float64_sqrt(farg.d, &env->fp_status);
1597 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1598 } else {
1599 if (farg.ll == 0x8000000000000000ULL) {
1600 farg.ll = 0xFFF0000000000000ULL;
1601 } else if (farg.ll == 0x0000000000000000ULL) {
1602 farg.ll = 0x7FF0000000000000ULL;
1603 } else if (float64_is_nan(farg.d)) {
1604 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1605 } else if (fpisneg(farg.d)) {
1606 farg.ll = 0x7FF8000000000000ULL;
1607 } else {
1608 farg.ll = 0x0000000000000000ULL;
1609 }
1610 }
1611 return farg.ll;
1612 }
1613
1614 /* fsel - fsel. */
1615 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1616 {
1617 CPU_DoubleU farg1;
1618
1619 farg1.ll = arg1;
1620
1621 if (!fpisneg(farg1.d) || iszero(farg1.d))
1622 return arg2;
1623 else
1624 return arg3;
1625 }
1626
1627 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1628 {
1629 CPU_DoubleU farg1, farg2;
1630 uint32_t ret = 0;
1631 farg1.ll = arg1;
1632 farg2.ll = arg2;
1633
1634 if (unlikely(float64_is_nan(farg1.d) ||
1635 float64_is_nan(farg2.d))) {
1636 ret = 0x01UL;
1637 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1638 ret = 0x08UL;
1639 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1640 ret = 0x04UL;
1641 } else {
1642 ret = 0x02UL;
1643 }
1644
1645 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1646 env->fpscr |= ret << FPSCR_FPRF;
1647 env->crf[crfD] = ret;
1648 if (unlikely(ret == 0x01UL
1649 && (float64_is_signaling_nan(farg1.d) ||
1650 float64_is_signaling_nan(farg2.d)))) {
1651 /* sNaN comparison */
1652 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1653 }
1654 }
1655
1656 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1657 {
1658 CPU_DoubleU farg1, farg2;
1659 uint32_t ret = 0;
1660 farg1.ll = arg1;
1661 farg2.ll = arg2;
1662
1663 if (unlikely(float64_is_nan(farg1.d) ||
1664 float64_is_nan(farg2.d))) {
1665 ret = 0x01UL;
1666 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1667 ret = 0x08UL;
1668 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1669 ret = 0x04UL;
1670 } else {
1671 ret = 0x02UL;
1672 }
1673
1674 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1675 env->fpscr |= ret << FPSCR_FPRF;
1676 env->crf[crfD] = ret;
1677 if (unlikely (ret == 0x01UL)) {
1678 if (float64_is_signaling_nan(farg1.d) ||
1679 float64_is_signaling_nan(farg2.d)) {
1680 /* sNaN comparison */
1681 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1682 POWERPC_EXCP_FP_VXVC);
1683 } else {
1684 /* qNaN comparison */
1685 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1686 }
1687 }
1688 }
1689
1690 #if !defined (CONFIG_USER_ONLY)
1691 void helper_store_msr (target_ulong val)
1692 {
1693 val = hreg_store_msr(env, val, 0);
1694 if (val != 0) {
1695 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1696 helper_raise_exception(val);
1697 }
1698 }
1699
1700 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1701 target_ulong msrm, int keep_msrh)
1702 {
1703 #if defined(TARGET_PPC64)
1704 if (msr & (1ULL << MSR_SF)) {
1705 nip = (uint64_t)nip;
1706 msr &= (uint64_t)msrm;
1707 } else {
1708 nip = (uint32_t)nip;
1709 msr = (uint32_t)(msr & msrm);
1710 if (keep_msrh)
1711 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1712 }
1713 #else
1714 nip = (uint32_t)nip;
1715 msr &= (uint32_t)msrm;
1716 #endif
1717 /* XXX: beware: this is false if VLE is supported */
1718 env->nip = nip & ~((target_ulong)0x00000003);
1719 hreg_store_msr(env, msr, 1);
1720 #if defined (DEBUG_OP)
1721 cpu_dump_rfi(env->nip, env->msr);
1722 #endif
1723 /* No need to raise an exception here,
1724 * as rfi is always the last insn of a TB
1725 */
1726 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1727 }
1728
1729 void helper_rfi (void)
1730 {
1731 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1732 ~((target_ulong)0xFFFF0000), 1);
1733 }
1734
1735 #if defined(TARGET_PPC64)
1736 void helper_rfid (void)
1737 {
1738 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1739 ~((target_ulong)0xFFFF0000), 0);
1740 }
1741
1742 void helper_hrfid (void)
1743 {
1744 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1745 ~((target_ulong)0xFFFF0000), 0);
1746 }
1747 #endif
1748 #endif
1749
1750 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1751 {
1752 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1753 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1754 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1755 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1756 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1757 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1758 }
1759 }
1760
1761 #if defined(TARGET_PPC64)
1762 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1763 {
1764 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1765 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1766 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1767 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1768 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1769 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1770 }
1771 #endif
1772
1773 /*****************************************************************************/
1774 /* PowerPC 601 specific instructions (POWER bridge) */
1775
1776 target_ulong helper_clcs (uint32_t arg)
1777 {
1778 switch (arg) {
1779 case 0x0CUL:
1780 /* Instruction cache line size */
1781 return env->icache_line_size;
1782 break;
1783 case 0x0DUL:
1784 /* Data cache line size */
1785 return env->dcache_line_size;
1786 break;
1787 case 0x0EUL:
1788 /* Minimum cache line size */
1789 return (env->icache_line_size < env->dcache_line_size) ?
1790 env->icache_line_size : env->dcache_line_size;
1791 break;
1792 case 0x0FUL:
1793 /* Maximum cache line size */
1794 return (env->icache_line_size > env->dcache_line_size) ?
1795 env->icache_line_size : env->dcache_line_size;
1796 break;
1797 default:
1798 /* Undefined */
1799 return 0;
1800 break;
1801 }
1802 }
1803
1804 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1805 {
1806 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1807
1808 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1809 (int32_t)arg2 == 0) {
1810 env->spr[SPR_MQ] = 0;
1811 return INT32_MIN;
1812 } else {
1813 env->spr[SPR_MQ] = tmp % arg2;
1814 return tmp / (int32_t)arg2;
1815 }
1816 }
1817
1818 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1819 {
1820 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1821
1822 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1823 (int32_t)arg2 == 0) {
1824 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1825 env->spr[SPR_MQ] = 0;
1826 return INT32_MIN;
1827 } else {
1828 env->spr[SPR_MQ] = tmp % arg2;
1829 tmp /= (int32_t)arg2;
1830 if ((int32_t)tmp != tmp) {
1831 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1832 } else {
1833 env->xer &= ~(1 << XER_OV);
1834 }
1835 return tmp;
1836 }
1837 }
1838
1839 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1840 {
1841 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1842 (int32_t)arg2 == 0) {
1843 env->spr[SPR_MQ] = 0;
1844 return INT32_MIN;
1845 } else {
1846 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1847 return (int32_t)arg1 / (int32_t)arg2;
1848 }
1849 }
1850
1851 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1852 {
1853 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1854 (int32_t)arg2 == 0) {
1855 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1856 env->spr[SPR_MQ] = 0;
1857 return INT32_MIN;
1858 } else {
1859 env->xer &= ~(1 << XER_OV);
1860 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1861 return (int32_t)arg1 / (int32_t)arg2;
1862 }
1863 }
1864
1865 #if !defined (CONFIG_USER_ONLY)
1866 target_ulong helper_rac (target_ulong addr)
1867 {
1868 mmu_ctx_t ctx;
1869 int nb_BATs;
1870 target_ulong ret = 0;
1871
1872 /* We don't have to generate many instances of this instruction,
1873 * as rac is supervisor only.
1874 */
1875 /* XXX: FIX THIS: Pretend we have no BAT */
1876 nb_BATs = env->nb_BATs;
1877 env->nb_BATs = 0;
1878 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1879 ret = ctx.raddr;
1880 env->nb_BATs = nb_BATs;
1881 return ret;
1882 }
1883
1884 void helper_rfsvc (void)
1885 {
1886 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1887 }
1888 #endif
1889
1890 /*****************************************************************************/
1891 /* 602 specific instructions */
1892 /* mfrom is the most crazy instruction ever seen, imho ! */
1893 /* Real implementation uses a ROM table. Do the same */
1894 /* Extremly decomposed:
1895 * -arg / 256
1896 * return 256 * log10(10 + 1.0) + 0.5
1897 */
1898 #if !defined (CONFIG_USER_ONLY)
1899 target_ulong helper_602_mfrom (target_ulong arg)
1900 {
1901 if (likely(arg < 602)) {
1902 #include "mfrom_table.c"
1903 return mfrom_ROM_table[arg];
1904 } else {
1905 return 0;
1906 }
1907 }
1908 #endif
1909
1910 /*****************************************************************************/
1911 /* Embedded PowerPC specific helpers */
1912
1913 /* XXX: to be improved to check access rights when in user-mode */
1914 target_ulong helper_load_dcr (target_ulong dcrn)
1915 {
1916 target_ulong val = 0;
1917
1918 if (unlikely(env->dcr_env == NULL)) {
1919 if (loglevel != 0) {
1920 fprintf(logfile, "No DCR environment\n");
1921 }
1922 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1923 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1924 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1925 if (loglevel != 0) {
1926 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1927 }
1928 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1929 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1930 }
1931 return val;
1932 }
1933
1934 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1935 {
1936 if (unlikely(env->dcr_env == NULL)) {
1937 if (loglevel != 0) {
1938 fprintf(logfile, "No DCR environment\n");
1939 }
1940 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1941 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1942 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1943 if (loglevel != 0) {
1944 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1945 }
1946 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1947 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1948 }
1949 }
1950
1951 #if !defined(CONFIG_USER_ONLY)
1952 void helper_40x_rfci (void)
1953 {
1954 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1955 ~((target_ulong)0xFFFF0000), 0);
1956 }
1957
1958 void helper_rfci (void)
1959 {
1960 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1961 ~((target_ulong)0x3FFF0000), 0);
1962 }
1963
1964 void helper_rfdi (void)
1965 {
1966 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1967 ~((target_ulong)0x3FFF0000), 0);
1968 }
1969
1970 void helper_rfmci (void)
1971 {
1972 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1973 ~((target_ulong)0x3FFF0000), 0);
1974 }
1975 #endif
1976
1977 /* 440 specific */
1978 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1979 {
1980 target_ulong mask;
1981 int i;
1982
1983 i = 1;
1984 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1985 if ((high & mask) == 0) {
1986 if (update_Rc) {
1987 env->crf[0] = 0x4;
1988 }
1989 goto done;
1990 }
1991 i++;
1992 }
1993 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1994 if ((low & mask) == 0) {
1995 if (update_Rc) {
1996 env->crf[0] = 0x8;
1997 }
1998 goto done;
1999 }
2000 i++;
2001 }
2002 if (update_Rc) {
2003 env->crf[0] = 0x2;
2004 }
2005 done:
2006 env->xer = (env->xer & ~0x7F) | i;
2007 if (update_Rc) {
2008 env->crf[0] |= xer_so;
2009 }
2010 return i;
2011 }
2012
2013 /*****************************************************************************/
2014 /* SPE extension helpers */
2015 /* Use a table to make this quicker */
2016 static uint8_t hbrev[16] = {
2017 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2018 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2019 };
2020
2021 static always_inline uint8_t byte_reverse (uint8_t val)
2022 {
2023 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2024 }
2025
2026 static always_inline uint32_t word_reverse (uint32_t val)
2027 {
2028 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2029 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2030 }
2031
2032 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2033 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2034 {
2035 uint32_t a, b, d, mask;
2036
2037 mask = UINT32_MAX >> (32 - MASKBITS);
2038 a = arg1 & mask;
2039 b = arg2 & mask;
2040 d = word_reverse(1 + word_reverse(a | ~b));
2041 return (arg1 & ~mask) | (d & b);
2042 }
2043
2044 uint32_t helper_cntlsw32 (uint32_t val)
2045 {
2046 if (val & 0x80000000)
2047 return clz32(~val);
2048 else
2049 return clz32(val);
2050 }
2051
2052 uint32_t helper_cntlzw32 (uint32_t val)
2053 {
2054 return clz32(val);
2055 }
2056
2057 /* Single-precision floating-point conversions */
2058 static always_inline uint32_t efscfsi (uint32_t val)
2059 {
2060 CPU_FloatU u;
2061
2062 u.f = int32_to_float32(val, &env->spe_status);
2063
2064 return u.l;
2065 }
2066
2067 static always_inline uint32_t efscfui (uint32_t val)
2068 {
2069 CPU_FloatU u;
2070
2071 u.f = uint32_to_float32(val, &env->spe_status);
2072
2073 return u.l;
2074 }
2075
2076 static always_inline int32_t efsctsi (uint32_t val)
2077 {
2078 CPU_FloatU u;
2079
2080 u.l = val;
2081 /* NaN are not treated the same way IEEE 754 does */
2082 if (unlikely(float32_is_nan(u.f)))
2083 return 0;
2084
2085 return float32_to_int32(u.f, &env->spe_status);
2086 }
2087
2088 static always_inline uint32_t efsctui (uint32_t val)
2089 {
2090 CPU_FloatU u;
2091
2092 u.l = val;
2093 /* NaN are not treated the same way IEEE 754 does */
2094 if (unlikely(float32_is_nan(u.f)))
2095 return 0;
2096
2097 return float32_to_uint32(u.f, &env->spe_status);
2098 }
2099
2100 static always_inline uint32_t efsctsiz (uint32_t val)
2101 {
2102 CPU_FloatU u;
2103
2104 u.l = val;
2105 /* NaN are not treated the same way IEEE 754 does */
2106 if (unlikely(float32_is_nan(u.f)))
2107 return 0;
2108
2109 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2110 }
2111
2112 static always_inline uint32_t efsctuiz (uint32_t val)
2113 {
2114 CPU_FloatU u;
2115
2116 u.l = val;
2117 /* NaN are not treated the same way IEEE 754 does */
2118 if (unlikely(float32_is_nan(u.f)))
2119 return 0;
2120
2121 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2122 }
2123
2124 static always_inline uint32_t efscfsf (uint32_t val)
2125 {
2126 CPU_FloatU u;
2127 float32 tmp;
2128
2129 u.f = int32_to_float32(val, &env->spe_status);
2130 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2131 u.f = float32_div(u.f, tmp, &env->spe_status);
2132
2133 return u.l;
2134 }
2135
2136 static always_inline uint32_t efscfuf (uint32_t val)
2137 {
2138 CPU_FloatU u;
2139 float32 tmp;
2140
2141 u.f = uint32_to_float32(val, &env->spe_status);
2142 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2143 u.f = float32_div(u.f, tmp, &env->spe_status);
2144
2145 return u.l;
2146 }
2147
2148 static always_inline uint32_t efsctsf (uint32_t val)
2149 {
2150 CPU_FloatU u;
2151 float32 tmp;
2152
2153 u.l = val;
2154 /* NaN are not treated the same way IEEE 754 does */
2155 if (unlikely(float32_is_nan(u.f)))
2156 return 0;
2157 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2158 u.f = float32_mul(u.f, tmp, &env->spe_status);
2159
2160 return float32_to_int32(u.f, &env->spe_status);
2161 }
2162
2163 static always_inline uint32_t efsctuf (uint32_t val)
2164 {
2165 CPU_FloatU u;
2166 float32 tmp;
2167
2168 u.l = val;
2169 /* NaN are not treated the same way IEEE 754 does */
2170 if (unlikely(float32_is_nan(u.f)))
2171 return 0;
2172 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2173 u.f = float32_mul(u.f, tmp, &env->spe_status);
2174
2175 return float32_to_uint32(u.f, &env->spe_status);
2176 }
2177
2178 #define HELPER_SPE_SINGLE_CONV(name) \
2179 uint32_t helper_e##name (uint32_t val) \
2180 { \
2181 return e##name(val); \
2182 }
2183 /* efscfsi */
2184 HELPER_SPE_SINGLE_CONV(fscfsi);
2185 /* efscfui */
2186 HELPER_SPE_SINGLE_CONV(fscfui);
2187 /* efscfuf */
2188 HELPER_SPE_SINGLE_CONV(fscfuf);
2189 /* efscfsf */
2190 HELPER_SPE_SINGLE_CONV(fscfsf);
2191 /* efsctsi */
2192 HELPER_SPE_SINGLE_CONV(fsctsi);
2193 /* efsctui */
2194 HELPER_SPE_SINGLE_CONV(fsctui);
2195 /* efsctsiz */
2196 HELPER_SPE_SINGLE_CONV(fsctsiz);
2197 /* efsctuiz */
2198 HELPER_SPE_SINGLE_CONV(fsctuiz);
2199 /* efsctsf */
2200 HELPER_SPE_SINGLE_CONV(fsctsf);
2201 /* efsctuf */
2202 HELPER_SPE_SINGLE_CONV(fsctuf);
2203
2204 #define HELPER_SPE_VECTOR_CONV(name) \
2205 uint64_t helper_ev##name (uint64_t val) \
2206 { \
2207 return ((uint64_t)e##name(val >> 32) << 32) | \
2208 (uint64_t)e##name(val); \
2209 }
2210 /* evfscfsi */
2211 HELPER_SPE_VECTOR_CONV(fscfsi);
2212 /* evfscfui */
2213 HELPER_SPE_VECTOR_CONV(fscfui);
2214 /* evfscfuf */
2215 HELPER_SPE_VECTOR_CONV(fscfuf);
2216 /* evfscfsf */
2217 HELPER_SPE_VECTOR_CONV(fscfsf);
2218 /* evfsctsi */
2219 HELPER_SPE_VECTOR_CONV(fsctsi);
2220 /* evfsctui */
2221 HELPER_SPE_VECTOR_CONV(fsctui);
2222 /* evfsctsiz */
2223 HELPER_SPE_VECTOR_CONV(fsctsiz);
2224 /* evfsctuiz */
2225 HELPER_SPE_VECTOR_CONV(fsctuiz);
2226 /* evfsctsf */
2227 HELPER_SPE_VECTOR_CONV(fsctsf);
2228 /* evfsctuf */
2229 HELPER_SPE_VECTOR_CONV(fsctuf);
2230
2231 /* Single-precision floating-point arithmetic */
2232 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2233 {
2234 CPU_FloatU u1, u2;
2235 u1.l = op1;
2236 u2.l = op2;
2237 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2238 return u1.l;
2239 }
2240
2241 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2242 {
2243 CPU_FloatU u1, u2;
2244 u1.l = op1;
2245 u2.l = op2;
2246 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2247 return u1.l;
2248 }
2249
2250 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2251 {
2252 CPU_FloatU u1, u2;
2253 u1.l = op1;
2254 u2.l = op2;
2255 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2256 return u1.l;
2257 }
2258
2259 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2260 {
2261 CPU_FloatU u1, u2;
2262 u1.l = op1;
2263 u2.l = op2;
2264 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2265 return u1.l;
2266 }
2267
2268 #define HELPER_SPE_SINGLE_ARITH(name) \
2269 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2270 { \
2271 return e##name(op1, op2); \
2272 }
2273 /* efsadd */
2274 HELPER_SPE_SINGLE_ARITH(fsadd);
2275 /* efssub */
2276 HELPER_SPE_SINGLE_ARITH(fssub);
2277 /* efsmul */
2278 HELPER_SPE_SINGLE_ARITH(fsmul);
2279 /* efsdiv */
2280 HELPER_SPE_SINGLE_ARITH(fsdiv);
2281
2282 #define HELPER_SPE_VECTOR_ARITH(name) \
2283 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2284 { \
2285 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2286 (uint64_t)e##name(op1, op2); \
2287 }
2288 /* evfsadd */
2289 HELPER_SPE_VECTOR_ARITH(fsadd);
2290 /* evfssub */
2291 HELPER_SPE_VECTOR_ARITH(fssub);
2292 /* evfsmul */
2293 HELPER_SPE_VECTOR_ARITH(fsmul);
2294 /* evfsdiv */
2295 HELPER_SPE_VECTOR_ARITH(fsdiv);
2296
2297 /* Single-precision floating-point comparisons */
2298 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2299 {
2300 CPU_FloatU u1, u2;
2301 u1.l = op1;
2302 u2.l = op2;
2303 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2304 }
2305
2306 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2307 {
2308 CPU_FloatU u1, u2;
2309 u1.l = op1;
2310 u2.l = op2;
2311 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2312 }
2313
2314 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2315 {
2316 CPU_FloatU u1, u2;
2317 u1.l = op1;
2318 u2.l = op2;
2319 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2320 }
2321
2322 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2323 {
2324 /* XXX: TODO: test special values (NaN, infinites, ...) */
2325 return efststlt(op1, op2);
2326 }
2327
2328 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2329 {
2330 /* XXX: TODO: test special values (NaN, infinites, ...) */
2331 return efststgt(op1, op2);
2332 }
2333
2334 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2335 {
2336 /* XXX: TODO: test special values (NaN, infinites, ...) */
2337 return efststeq(op1, op2);
2338 }
2339
2340 #define HELPER_SINGLE_SPE_CMP(name) \
2341 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2342 { \
2343 return e##name(op1, op2) << 2; \
2344 }
2345 /* efststlt */
2346 HELPER_SINGLE_SPE_CMP(fststlt);
2347 /* efststgt */
2348 HELPER_SINGLE_SPE_CMP(fststgt);
2349 /* efststeq */
2350 HELPER_SINGLE_SPE_CMP(fststeq);
2351 /* efscmplt */
2352 HELPER_SINGLE_SPE_CMP(fscmplt);
2353 /* efscmpgt */
2354 HELPER_SINGLE_SPE_CMP(fscmpgt);
2355 /* efscmpeq */
2356 HELPER_SINGLE_SPE_CMP(fscmpeq);
2357
2358 static always_inline uint32_t evcmp_merge (int t0, int t1)
2359 {
2360 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2361 }
2362
2363 #define HELPER_VECTOR_SPE_CMP(name) \
2364 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2365 { \
2366 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2367 }
2368 /* evfststlt */
2369 HELPER_VECTOR_SPE_CMP(fststlt);
2370 /* evfststgt */
2371 HELPER_VECTOR_SPE_CMP(fststgt);
2372 /* evfststeq */
2373 HELPER_VECTOR_SPE_CMP(fststeq);
2374 /* evfscmplt */
2375 HELPER_VECTOR_SPE_CMP(fscmplt);
2376 /* evfscmpgt */
2377 HELPER_VECTOR_SPE_CMP(fscmpgt);
2378 /* evfscmpeq */
2379 HELPER_VECTOR_SPE_CMP(fscmpeq);
2380
2381 /* Double-precision floating-point conversion */
2382 uint64_t helper_efdcfsi (uint32_t val)
2383 {
2384 CPU_DoubleU u;
2385
2386 u.d = int32_to_float64(val, &env->spe_status);
2387
2388 return u.ll;
2389 }
2390
2391 uint64_t helper_efdcfsid (uint64_t val)
2392 {
2393 CPU_DoubleU u;
2394
2395 u.d = int64_to_float64(val, &env->spe_status);
2396
2397 return u.ll;
2398 }
2399
2400 uint64_t helper_efdcfui (uint32_t val)
2401 {
2402 CPU_DoubleU u;
2403
2404 u.d = uint32_to_float64(val, &env->spe_status);
2405
2406 return u.ll;
2407 }
2408
2409 uint64_t helper_efdcfuid (uint64_t val)
2410 {
2411 CPU_DoubleU u;
2412
2413 u.d = uint64_to_float64(val, &env->spe_status);
2414
2415 return u.ll;
2416 }
2417
2418 uint32_t helper_efdctsi (uint64_t val)
2419 {
2420 CPU_DoubleU u;
2421
2422 u.ll = val;
2423 /* NaN are not treated the same way IEEE 754 does */
2424 if (unlikely(float64_is_nan(u.d)))
2425 return 0;
2426
2427 return float64_to_int32(u.d, &env->spe_status);
2428 }
2429
2430 uint32_t helper_efdctui (uint64_t val)
2431 {
2432 CPU_DoubleU u;
2433
2434 u.ll = val;
2435 /* NaN are not treated the same way IEEE 754 does */
2436 if (unlikely(float64_is_nan(u.d)))
2437 return 0;
2438
2439 return float64_to_uint32(u.d, &env->spe_status);
2440 }
2441
2442 uint32_t helper_efdctsiz (uint64_t val)
2443 {
2444 CPU_DoubleU u;
2445
2446 u.ll = val;
2447 /* NaN are not treated the same way IEEE 754 does */
2448 if (unlikely(float64_is_nan(u.d)))
2449 return 0;
2450
2451 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2452 }
2453
2454 uint64_t helper_efdctsidz (uint64_t val)
2455 {
2456 CPU_DoubleU u;
2457
2458 u.ll = val;
2459 /* NaN are not treated the same way IEEE 754 does */
2460 if (unlikely(float64_is_nan(u.d)))
2461 return 0;
2462
2463 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2464 }
2465
2466 uint32_t helper_efdctuiz (uint64_t val)
2467 {
2468 CPU_DoubleU u;
2469
2470 u.ll = val;
2471 /* NaN are not treated the same way IEEE 754 does */
2472 if (unlikely(float64_is_nan(u.d)))
2473 return 0;
2474
2475 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2476 }
2477
2478 uint64_t helper_efdctuidz (uint64_t val)
2479 {
2480 CPU_DoubleU u;
2481
2482 u.ll = val;
2483 /* NaN are not treated the same way IEEE 754 does */
2484 if (unlikely(float64_is_nan(u.d)))
2485 return 0;
2486
2487 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2488 }
2489
2490 uint64_t helper_efdcfsf (uint32_t val)
2491 {
2492 CPU_DoubleU u;
2493 float64 tmp;
2494
2495 u.d = int32_to_float64(val, &env->spe_status);
2496 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2497 u.d = float64_div(u.d, tmp, &env->spe_status);
2498
2499 return u.ll;
2500 }
2501
2502 uint64_t helper_efdcfuf (uint32_t val)
2503 {
2504 CPU_DoubleU u;
2505 float64 tmp;
2506
2507 u.d = uint32_to_float64(val, &env->spe_status);
2508 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2509 u.d = float64_div(u.d, tmp, &env->spe_status);
2510
2511 return u.ll;
2512 }
2513
2514 uint32_t helper_efdctsf (uint64_t val)
2515 {
2516 CPU_DoubleU u;
2517 float64 tmp;
2518
2519 u.ll = val;
2520 /* NaN are not treated the same way IEEE 754 does */
2521 if (unlikely(float64_is_nan(u.d)))
2522 return 0;
2523 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2524 u.d = float64_mul(u.d, tmp, &env->spe_status);
2525
2526 return float64_to_int32(u.d, &env->spe_status);
2527 }
2528
2529 uint32_t helper_efdctuf (uint64_t val)
2530 {
2531 CPU_DoubleU u;
2532 float64 tmp;
2533
2534 u.ll = val;
2535 /* NaN are not treated the same way IEEE 754 does */
2536 if (unlikely(float64_is_nan(u.d)))
2537 return 0;
2538 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2539 u.d = float64_mul(u.d, tmp, &env->spe_status);
2540
2541 return float64_to_uint32(u.d, &env->spe_status);
2542 }
2543
2544 uint32_t helper_efscfd (uint64_t val)
2545 {
2546 CPU_DoubleU u1;
2547 CPU_FloatU u2;
2548
2549 u1.ll = val;
2550 u2.f = float64_to_float32(u1.d, &env->spe_status);
2551
2552 return u2.l;
2553 }
2554
2555 uint64_t helper_efdcfs (uint32_t val)
2556 {
2557 CPU_DoubleU u2;
2558 CPU_FloatU u1;
2559
2560 u1.l = val;
2561 u2.d = float32_to_float64(u1.f, &env->spe_status);
2562
2563 return u2.ll;
2564 }
2565
2566 /* Double precision fixed-point arithmetic */
2567 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2568 {
2569 CPU_DoubleU u1, u2;
2570 u1.ll = op1;
2571 u2.ll = op2;
2572 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2573 return u1.ll;
2574 }
2575
2576 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2577 {
2578 CPU_DoubleU u1, u2;
2579 u1.ll = op1;
2580 u2.ll = op2;
2581 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2582 return u1.ll;
2583 }
2584
2585 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2586 {
2587 CPU_DoubleU u1, u2;
2588 u1.ll = op1;
2589 u2.ll = op2;
2590 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2591 return u1.ll;
2592 }
2593
2594 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2595 {
2596 CPU_DoubleU u1, u2;
2597 u1.ll = op1;
2598 u2.ll = op2;
2599 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2600 return u1.ll;
2601 }
2602
2603 /* Double precision floating point helpers */
2604 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2605 {
2606 CPU_DoubleU u1, u2;
2607 u1.ll = op1;
2608 u2.ll = op2;
2609 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2610 }
2611
2612 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2613 {
2614 CPU_DoubleU u1, u2;
2615 u1.ll = op1;
2616 u2.ll = op2;
2617 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2618 }
2619
2620 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2621 {
2622 CPU_DoubleU u1, u2;
2623 u1.ll = op1;
2624 u2.ll = op2;
2625 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2626 }
2627
2628 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2629 {
2630 /* XXX: TODO: test special values (NaN, infinites, ...) */
2631 return helper_efdtstlt(op1, op2);
2632 }
2633
2634 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2635 {
2636 /* XXX: TODO: test special values (NaN, infinites, ...) */
2637 return helper_efdtstgt(op1, op2);
2638 }
2639
2640 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2641 {
2642 /* XXX: TODO: test special values (NaN, infinites, ...) */
2643 return helper_efdtsteq(op1, op2);
2644 }
2645
2646 /*****************************************************************************/
2647 /* Softmmu support */
2648 #if !defined (CONFIG_USER_ONLY)
2649
2650 #define MMUSUFFIX _mmu
2651
2652 #define SHIFT 0
2653 #include "softmmu_template.h"
2654
2655 #define SHIFT 1
2656 #include "softmmu_template.h"
2657
2658 #define SHIFT 2
2659 #include "softmmu_template.h"
2660
2661 #define SHIFT 3
2662 #include "softmmu_template.h"
2663
2664 /* try to fill the TLB and return an exception if error. If retaddr is
2665 NULL, it means that the function was called in C code (i.e. not
2666 from generated code or from helper.c) */
2667 /* XXX: fix it to restore all registers */
2668 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2669 {
2670 TranslationBlock *tb;
2671 CPUState *saved_env;
2672 unsigned long pc;
2673 int ret;
2674
2675 /* XXX: hack to restore env in all cases, even if not called from
2676 generated code */
2677 saved_env = env;
2678 env = cpu_single_env;
2679 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2680 if (unlikely(ret != 0)) {
2681 if (likely(retaddr)) {
2682 /* now we have a real cpu fault */
2683 pc = (unsigned long)retaddr;
2684 tb = tb_find_pc(pc);
2685 if (likely(tb)) {
2686 /* the PC is inside the translated code. It means that we have
2687 a virtual CPU fault */
2688 cpu_restore_state(tb, env, pc, NULL);
2689 }
2690 }
2691 helper_raise_exception_err(env->exception_index, env->error_code);
2692 }
2693 env = saved_env;
2694 }
2695
2696 /* Segment registers load and store */
2697 target_ulong helper_load_sr (target_ulong sr_num)
2698 {
2699 return env->sr[sr_num];
2700 }
2701
2702 void helper_store_sr (target_ulong sr_num, target_ulong val)
2703 {
2704 ppc_store_sr(env, sr_num, val);
2705 }
2706
2707 /* SLB management */
2708 #if defined(TARGET_PPC64)
2709 target_ulong helper_load_slb (target_ulong slb_nr)
2710 {
2711 return ppc_load_slb(env, slb_nr);
2712 }
2713
2714 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2715 {
2716 ppc_store_slb(env, slb_nr, rs);
2717 }
2718
2719 void helper_slbia (void)
2720 {
2721 ppc_slb_invalidate_all(env);
2722 }
2723
2724 void helper_slbie (target_ulong addr)
2725 {
2726 ppc_slb_invalidate_one(env, addr);
2727 }
2728
2729 #endif /* defined(TARGET_PPC64) */
2730
2731 /* TLB management */
2732 void helper_tlbia (void)
2733 {
2734 ppc_tlb_invalidate_all(env);
2735 }
2736
2737 void helper_tlbie (target_ulong addr)
2738 {
2739 ppc_tlb_invalidate_one(env, addr);
2740 }
2741
2742 /* Software driven TLBs management */
2743 /* PowerPC 602/603 software TLB load instructions helpers */
2744 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2745 {
2746 target_ulong RPN, CMP, EPN;
2747 int way;
2748
2749 RPN = env->spr[SPR_RPA];
2750 if (is_code) {
2751 CMP = env->spr[SPR_ICMP];
2752 EPN = env->spr[SPR_IMISS];
2753 } else {
2754 CMP = env->spr[SPR_DCMP];
2755 EPN = env->spr[SPR_DMISS];
2756 }
2757 way = (env->spr[SPR_SRR1] >> 17) & 1;
2758 #if defined (DEBUG_SOFTWARE_TLB)
2759 if (loglevel != 0) {
2760 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2761 " PTE1 " ADDRX " way %d\n",
2762 __func__, new_EPN, EPN, CMP, RPN, way);
2763 }
2764 #endif
2765 /* Store this TLB */
2766 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2767 way, is_code, CMP, RPN);
2768 }
2769
2770 void helper_6xx_tlbd (target_ulong EPN)
2771 {
2772 do_6xx_tlb(EPN, 0);
2773 }
2774
2775 void helper_6xx_tlbi (target_ulong EPN)
2776 {
2777 do_6xx_tlb(EPN, 1);
2778 }
2779
2780 /* PowerPC 74xx software TLB load instructions helpers */
2781 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2782 {
2783 target_ulong RPN, CMP, EPN;
2784 int way;
2785
2786 RPN = env->spr[SPR_PTELO];
2787 CMP = env->spr[SPR_PTEHI];
2788 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2789 way = env->spr[SPR_TLBMISS] & 0x3;
2790 #if defined (DEBUG_SOFTWARE_TLB)
2791 if (loglevel != 0) {
2792 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2793 " PTE1 " ADDRX " way %d\n",
2794 __func__, new_EPN, EPN, CMP, RPN, way);
2795 }
2796 #endif
2797 /* Store this TLB */
2798 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2799 way, is_code, CMP, RPN);
2800 }
2801
2802 void helper_74xx_tlbd (target_ulong EPN)
2803 {
2804 do_74xx_tlb(EPN, 0);
2805 }
2806
2807 void helper_74xx_tlbi (target_ulong EPN)
2808 {
2809 do_74xx_tlb(EPN, 1);
2810 }
2811
2812 static always_inline target_ulong booke_tlb_to_page_size (int size)
2813 {
2814 return 1024 << (2 * size);
2815 }
2816
2817 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2818 {
2819 int size;
2820
2821 switch (page_size) {
2822 case 0x00000400UL:
2823 size = 0x0;
2824 break;
2825 case 0x00001000UL:
2826 size = 0x1;
2827 break;
2828 case 0x00004000UL:
2829 size = 0x2;
2830 break;
2831 case 0x00010000UL:
2832 size = 0x3;
2833 break;
2834 case 0x00040000UL:
2835 size = 0x4;
2836 break;
2837 case 0x00100000UL:
2838 size = 0x5;
2839 break;
2840 case 0x00400000UL:
2841 size = 0x6;
2842 break;
2843 case 0x01000000UL:
2844 size = 0x7;
2845 break;
2846 case 0x04000000UL:
2847 size = 0x8;
2848 break;
2849 case 0x10000000UL:
2850 size = 0x9;
2851 break;
2852 case 0x40000000UL:
2853 size = 0xA;
2854 break;
2855 #if defined (TARGET_PPC64)
2856 case 0x000100000000ULL:
2857 size = 0xB;
2858 break;
2859 case 0x000400000000ULL:
2860 size = 0xC;
2861 break;
2862 case 0x001000000000ULL:
2863 size = 0xD;
2864 break;
2865 case 0x004000000000ULL:
2866 size = 0xE;
2867 break;
2868 case 0x010000000000ULL:
2869 size = 0xF;
2870 break;
2871 #endif
2872 default:
2873 size = -1;
2874 break;
2875 }
2876
2877 return size;
2878 }
2879
2880 /* Helpers for 4xx TLB management */
2881 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2882 {
2883 ppcemb_tlb_t *tlb;
2884 target_ulong ret;
2885 int size;
2886
2887 entry &= 0x3F;
2888 tlb = &env->tlb[entry].tlbe;
2889 ret = tlb->EPN;
2890 if (tlb->prot & PAGE_VALID)
2891 ret |= 0x400;
2892 size = booke_page_size_to_tlb(tlb->size);
2893 if (size < 0 || size > 0x7)
2894 size = 1;
2895 ret |= size << 7;
2896 env->spr[SPR_40x_PID] = tlb->PID;
2897 return ret;
2898 }
2899
2900 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2901 {
2902 ppcemb_tlb_t *tlb;
2903 target_ulong ret;
2904
2905 entry &= 0x3F;
2906 tlb = &env->tlb[entry].tlbe;
2907 ret = tlb->RPN;
2908 if (tlb->prot & PAGE_EXEC)
2909 ret |= 0x200;
2910 if (tlb->prot & PAGE_WRITE)
2911 ret |= 0x100;
2912 return ret;
2913 }
2914
2915 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2916 {
2917 ppcemb_tlb_t *tlb;
2918 target_ulong page, end;
2919
2920 #if defined (DEBUG_SOFTWARE_TLB)
2921 if (loglevel != 0) {
2922 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2923 }
2924 #endif
2925 entry &= 0x3F;
2926 tlb = &env->tlb[entry].tlbe;
2927 /* Invalidate previous TLB (if it's valid) */
2928 if (tlb->prot & PAGE_VALID) {
2929 end = tlb->EPN + tlb->size;
2930 #if defined (DEBUG_SOFTWARE_TLB)
2931 if (loglevel != 0) {
2932 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2933 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2934 }
2935 #endif
2936 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2937 tlb_flush_page(env, page);
2938 }
2939 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2940 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2941 * If this ever occurs, one should use the ppcemb target instead
2942 * of the ppc or ppc64 one
2943 */
2944 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2945 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2946 "are not supported (%d)\n",
2947 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2948 }
2949 tlb->EPN = val & ~(tlb->size - 1);
2950 if (val & 0x40)
2951 tlb->prot |= PAGE_VALID;
2952 else
2953 tlb->prot &= ~PAGE_VALID;
2954 if (val & 0x20) {
2955 /* XXX: TO BE FIXED */
2956 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2957 }
2958 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2959 tlb->attr = val & 0xFF;
2960 #if defined (DEBUG_SOFTWARE_TLB)
2961 if (loglevel != 0) {
2962 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2963 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2964 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2965 tlb->prot & PAGE_READ ? 'r' : '-',
2966 tlb->prot & PAGE_WRITE ? 'w' : '-',
2967 tlb->prot & PAGE_EXEC ? 'x' : '-',
2968 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2969 }
2970 #endif
2971 /* Invalidate new TLB (if valid) */
2972 if (tlb->prot & PAGE_VALID) {
2973 end = tlb->EPN + tlb->size;
2974 #if defined (DEBUG_SOFTWARE_TLB)
2975 if (loglevel != 0) {
2976 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2977 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2978 }
2979 #endif
2980 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2981 tlb_flush_page(env, page);
2982 }
2983 }
2984
2985 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2986 {
2987 ppcemb_tlb_t *tlb;
2988
2989 #if defined (DEBUG_SOFTWARE_TLB)
2990 if (loglevel != 0) {
2991 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2992 }
2993 #endif
2994 entry &= 0x3F;
2995 tlb = &env->tlb[entry].tlbe;
2996 tlb->RPN = val & 0xFFFFFC00;
2997 tlb->prot = PAGE_READ;
2998 if (val & 0x200)
2999 tlb->prot |= PAGE_EXEC;
3000 if (val & 0x100)
3001 tlb->prot |= PAGE_WRITE;
3002 #if defined (DEBUG_SOFTWARE_TLB)
3003 if (loglevel != 0) {
3004 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3005 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3006 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3007 tlb->prot & PAGE_READ ? 'r' : '-',
3008 tlb->prot & PAGE_WRITE ? 'w' : '-',
3009 tlb->prot & PAGE_EXEC ? 'x' : '-',
3010 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3011 }
3012 #endif
3013 }
3014
3015 target_ulong helper_4xx_tlbsx (target_ulong address)
3016 {
3017 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3018 }
3019
3020 /* PowerPC 440 TLB management */
3021 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3022 {
3023 ppcemb_tlb_t *tlb;
3024 target_ulong EPN, RPN, size;
3025 int do_flush_tlbs;
3026
3027 #if defined (DEBUG_SOFTWARE_TLB)
3028 if (loglevel != 0) {
3029 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3030 __func__, word, (int)entry, value);
3031 }
3032 #endif
3033 do_flush_tlbs = 0;
3034 entry &= 0x3F;
3035 tlb = &env->tlb[entry].tlbe;
3036 switch (word) {
3037 default:
3038 /* Just here to please gcc */
3039 case 0:
3040 EPN = value & 0xFFFFFC00;
3041 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3042 do_flush_tlbs = 1;
3043 tlb->EPN = EPN;
3044 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3045 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3046 do_flush_tlbs = 1;
3047 tlb->size = size;
3048 tlb->attr &= ~0x1;
3049 tlb->attr |= (value >> 8) & 1;
3050 if (value & 0x200) {
3051 tlb->prot |= PAGE_VALID;
3052 } else {
3053 if (tlb->prot & PAGE_VALID) {
3054 tlb->prot &= ~PAGE_VALID;
3055 do_flush_tlbs = 1;
3056 }
3057 }
3058 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3059 if (do_flush_tlbs)
3060 tlb_flush(env, 1);
3061 break;
3062 case 1:
3063 RPN = value & 0xFFFFFC0F;
3064 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3065 tlb_flush(env, 1);
3066 tlb->RPN = RPN;
3067 break;
3068 case 2:
3069 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3070 tlb->prot = tlb->prot & PAGE_VALID;
3071 if (value & 0x1)
3072 tlb->prot |= PAGE_READ << 4;
3073 if (value & 0x2)
3074 tlb->prot |= PAGE_WRITE << 4;
3075 if (value & 0x4)
3076 tlb->prot |= PAGE_EXEC << 4;
3077 if (value & 0x8)
3078 tlb->prot |= PAGE_READ;
3079 if (value & 0x10)
3080 tlb->prot |= PAGE_WRITE;
3081 if (value & 0x20)
3082 tlb->prot |= PAGE_EXEC;
3083 break;
3084 }
3085 }
3086
3087 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3088 {
3089 ppcemb_tlb_t *tlb;
3090 target_ulong ret;
3091 int size;
3092
3093 entry &= 0x3F;
3094 tlb = &env->tlb[entry].tlbe;
3095 switch (word) {
3096 default:
3097 /* Just here to please gcc */
3098 case 0:
3099 ret = tlb->EPN;
3100 size = booke_page_size_to_tlb(tlb->size);
3101 if (size < 0 || size > 0xF)
3102 size = 1;
3103 ret |= size << 4;
3104 if (tlb->attr & 0x1)
3105 ret |= 0x100;
3106 if (tlb->prot & PAGE_VALID)
3107 ret |= 0x200;
3108 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3109 env->spr[SPR_440_MMUCR] |= tlb->PID;
3110 break;
3111 case 1:
3112 ret = tlb->RPN;
3113 break;
3114 case 2:
3115 ret = tlb->attr & ~0x1;
3116 if (tlb->prot & (PAGE_READ << 4))
3117 ret |= 0x1;
3118 if (tlb->prot & (PAGE_WRITE << 4))
3119 ret |= 0x2;
3120 if (tlb->prot & (PAGE_EXEC << 4))
3121 ret |= 0x4;
3122 if (tlb->prot & PAGE_READ)
3123 ret |= 0x8;
3124 if (tlb->prot & PAGE_WRITE)
3125 ret |= 0x10;
3126 if (tlb->prot & PAGE_EXEC)
3127 ret |= 0x20;
3128 break;
3129 }
3130 return ret;
3131 }
3132
3133 target_ulong helper_440_tlbsx (target_ulong address)
3134 {
3135 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3136 }
3137
3138 #endif /* !CONFIG_USER_ONLY */
jz4740 based target emulation