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softfloat-native: fix *nan()
[qemu/qemu-JZ.git] / target-ppc / helper.c
blob538d9f34c41a4281ea0524d9972bdec9635f441e
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "helper_regs.h"
31 #include "qemu-common.h"
32
33 //#define DEBUG_MMU
34 //#define DEBUG_BATS
35 //#define DEBUG_SLB
36 //#define DEBUG_SOFTWARE_TLB
37 //#define DUMP_PAGE_TABLES
38 //#define DEBUG_EXCEPTIONS
39 //#define FLUSH_ALL_TLBS
40
41 /*****************************************************************************/
42 /* PowerPC MMU emulation */
43
44 #if defined(CONFIG_USER_ONLY)
45 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
46 int mmu_idx, int is_softmmu)
47 {
48 int exception, error_code;
49
50 if (rw == 2) {
51 exception = POWERPC_EXCP_ISI;
52 error_code = 0x40000000;
53 } else {
54 exception = POWERPC_EXCP_DSI;
55 error_code = 0x40000000;
56 if (rw)
57 error_code |= 0x02000000;
58 env->spr[SPR_DAR] = address;
59 env->spr[SPR_DSISR] = error_code;
60 }
61 env->exception_index = exception;
62 env->error_code = error_code;
63
64 return 1;
65 }
66
67 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
68 {
69 return addr;
70 }
71
72 #else
73 /* Common routines used by software and hardware TLBs emulation */
74 static always_inline int pte_is_valid (target_ulong pte0)
75 {
76 return pte0 & 0x80000000 ? 1 : 0;
77 }
78
79 static always_inline void pte_invalidate (target_ulong *pte0)
80 {
81 *pte0 &= ~0x80000000;
82 }
83
84 #if defined(TARGET_PPC64)
85 static always_inline int pte64_is_valid (target_ulong pte0)
86 {
87 return pte0 & 0x0000000000000001ULL ? 1 : 0;
88 }
89
90 static always_inline void pte64_invalidate (target_ulong *pte0)
91 {
92 *pte0 &= ~0x0000000000000001ULL;
93 }
94 #endif
95
96 #define PTE_PTEM_MASK 0x7FFFFFBF
97 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
98 #if defined(TARGET_PPC64)
99 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
100 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
101 #endif
102
103 static always_inline int pp_check (int key, int pp, int nx)
104 {
105 int access;
106
107 /* Compute access rights */
108 /* When pp is 3/7, the result is undefined. Set it to noaccess */
109 access = 0;
110 if (key == 0) {
111 switch (pp) {
112 case 0x0:
113 case 0x1:
114 case 0x2:
115 access |= PAGE_WRITE;
116 /* No break here */
117 case 0x3:
118 case 0x6:
119 access |= PAGE_READ;
120 break;
121 }
122 } else {
123 switch (pp) {
124 case 0x0:
125 case 0x6:
126 access = 0;
127 break;
128 case 0x1:
129 case 0x3:
130 access = PAGE_READ;
131 break;
132 case 0x2:
133 access = PAGE_READ | PAGE_WRITE;
134 break;
135 }
136 }
137 if (nx == 0)
138 access |= PAGE_EXEC;
139
140 return access;
141 }
142
143 static always_inline int check_prot (int prot, int rw, int access_type)
144 {
145 int ret;
146
147 if (access_type == ACCESS_CODE) {
148 if (prot & PAGE_EXEC)
149 ret = 0;
150 else
151 ret = -2;
152 } else if (rw) {
153 if (prot & PAGE_WRITE)
154 ret = 0;
155 else
156 ret = -2;
157 } else {
158 if (prot & PAGE_READ)
159 ret = 0;
160 else
161 ret = -2;
162 }
163
164 return ret;
165 }
166
167 static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
168 target_ulong pte0, target_ulong pte1,
169 int h, int rw, int type)
170 {
171 target_ulong ptem, mmask;
172 int access, ret, pteh, ptev, pp;
173
174 access = 0;
175 ret = -1;
176 /* Check validity and table match */
177 #if defined(TARGET_PPC64)
178 if (is_64b) {
179 ptev = pte64_is_valid(pte0);
180 pteh = (pte0 >> 1) & 1;
181 } else
182 #endif
183 {
184 ptev = pte_is_valid(pte0);
185 pteh = (pte0 >> 6) & 1;
186 }
187 if (ptev && h == pteh) {
188 /* Check vsid & api */
189 #if defined(TARGET_PPC64)
190 if (is_64b) {
191 ptem = pte0 & PTE64_PTEM_MASK;
192 mmask = PTE64_CHECK_MASK;
193 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
194 ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */
195 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
196 } else
197 #endif
198 {
199 ptem = pte0 & PTE_PTEM_MASK;
200 mmask = PTE_CHECK_MASK;
201 pp = pte1 & 0x00000003;
202 }
203 if (ptem == ctx->ptem) {
204 if (ctx->raddr != (target_phys_addr_t)-1ULL) {
205 /* all matches should have equal RPN, WIMG & PP */
206 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
207 if (loglevel != 0)
208 fprintf(logfile, "Bad RPN/WIMG/PP\n");
209 return -3;
210 }
211 }
212 /* Compute access rights */
213 access = pp_check(ctx->key, pp, ctx->nx);
214 /* Keep the matching PTE informations */
215 ctx->raddr = pte1;
216 ctx->prot = access;
217 ret = check_prot(ctx->prot, rw, type);
218 if (ret == 0) {
219 /* Access granted */
220 #if defined (DEBUG_MMU)
221 if (loglevel != 0)
222 fprintf(logfile, "PTE access granted !\n");
223 #endif
224 } else {
225 /* Access right violation */
226 #if defined (DEBUG_MMU)
227 if (loglevel != 0)
228 fprintf(logfile, "PTE access rejected\n");
229 #endif
230 }
231 }
232 }
233
234 return ret;
235 }
236
237 static always_inline int pte32_check (mmu_ctx_t *ctx,
238 target_ulong pte0, target_ulong pte1,
239 int h, int rw, int type)
240 {
241 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
242 }
243
244 #if defined(TARGET_PPC64)
245 static always_inline int pte64_check (mmu_ctx_t *ctx,
246 target_ulong pte0, target_ulong pte1,
247 int h, int rw, int type)
248 {
249 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
250 }
251 #endif
252
253 static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
254 int ret, int rw)
255 {
256 int store = 0;
257
258 /* Update page flags */
259 if (!(*pte1p & 0x00000100)) {
260 /* Update accessed flag */
261 *pte1p |= 0x00000100;
262 store = 1;
263 }
264 if (!(*pte1p & 0x00000080)) {
265 if (rw == 1 && ret == 0) {
266 /* Update changed flag */
267 *pte1p |= 0x00000080;
268 store = 1;
269 } else {
270 /* Force page fault for first write access */
271 ctx->prot &= ~PAGE_WRITE;
272 }
273 }
274
275 return store;
276 }
277
278 /* Software driven TLB helpers */
279 static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
280 int way, int is_code)
281 {
282 int nr;
283
284 /* Select TLB num in a way from address */
285 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
286 /* Select TLB way */
287 nr += env->tlb_per_way * way;
288 /* 6xx have separate TLBs for instructions and data */
289 if (is_code && env->id_tlbs == 1)
290 nr += env->nb_tlb;
291
292 return nr;
293 }
294
295 static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
296 {
297 ppc6xx_tlb_t *tlb;
298 int nr, max;
299
300 #if defined (DEBUG_SOFTWARE_TLB) && 0
301 if (loglevel != 0) {
302 fprintf(logfile, "Invalidate all TLBs\n");
303 }
304 #endif
305 /* Invalidate all defined software TLB */
306 max = env->nb_tlb;
307 if (env->id_tlbs == 1)
308 max *= 2;
309 for (nr = 0; nr < max; nr++) {
310 tlb = &env->tlb[nr].tlb6;
311 pte_invalidate(&tlb->pte0);
312 }
313 tlb_flush(env, 1);
314 }
315
316 static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
317 target_ulong eaddr,
318 int is_code,
319 int match_epn)
320 {
321 #if !defined(FLUSH_ALL_TLBS)
322 ppc6xx_tlb_t *tlb;
323 int way, nr;
324
325 /* Invalidate ITLB + DTLB, all ways */
326 for (way = 0; way < env->nb_ways; way++) {
327 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
328 tlb = &env->tlb[nr].tlb6;
329 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
330 #if defined (DEBUG_SOFTWARE_TLB)
331 if (loglevel != 0) {
332 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
333 nr, env->nb_tlb, eaddr);
334 }
335 #endif
336 pte_invalidate(&tlb->pte0);
337 tlb_flush_page(env, tlb->EPN);
338 }
339 }
340 #else
341 /* XXX: PowerPC specification say this is valid as well */
342 ppc6xx_tlb_invalidate_all(env);
343 #endif
344 }
345
346 static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
347 target_ulong eaddr,
348 int is_code)
349 {
350 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
351 }
352
353 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
354 target_ulong pte0, target_ulong pte1)
355 {
356 ppc6xx_tlb_t *tlb;
357 int nr;
358
359 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
360 tlb = &env->tlb[nr].tlb6;
361 #if defined (DEBUG_SOFTWARE_TLB)
362 if (loglevel != 0) {
363 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
364 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
365 }
366 #endif
367 /* Invalidate any pending reference in Qemu for this virtual address */
368 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
369 tlb->pte0 = pte0;
370 tlb->pte1 = pte1;
371 tlb->EPN = EPN;
372 /* Store last way for LRU mechanism */
373 env->last_way = way;
374 }
375
376 static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
377 target_ulong eaddr, int rw,
378 int access_type)
379 {
380 ppc6xx_tlb_t *tlb;
381 int nr, best, way;
382 int ret;
383
384 best = -1;
385 ret = -1; /* No TLB found */
386 for (way = 0; way < env->nb_ways; way++) {
387 nr = ppc6xx_tlb_getnum(env, eaddr, way,
388 access_type == ACCESS_CODE ? 1 : 0);
389 tlb = &env->tlb[nr].tlb6;
390 /* This test "emulates" the PTE index match for hardware TLBs */
391 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
392 #if defined (DEBUG_SOFTWARE_TLB)
393 if (loglevel != 0) {
394 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
395 "] <> " ADDRX "\n",
396 nr, env->nb_tlb,
397 pte_is_valid(tlb->pte0) ? "valid" : "inval",
398 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
399 }
400 #endif
401 continue;
402 }
403 #if defined (DEBUG_SOFTWARE_TLB)
404 if (loglevel != 0) {
405 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
406 " %c %c\n",
407 nr, env->nb_tlb,
408 pte_is_valid(tlb->pte0) ? "valid" : "inval",
409 tlb->EPN, eaddr, tlb->pte1,
410 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
411 }
412 #endif
413 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
414 case -3:
415 /* TLB inconsistency */
416 return -1;
417 case -2:
418 /* Access violation */
419 ret = -2;
420 best = nr;
421 break;
422 case -1:
423 default:
424 /* No match */
425 break;
426 case 0:
427 /* access granted */
428 /* XXX: we should go on looping to check all TLBs consistency
429 * but we can speed-up the whole thing as the
430 * result would be undefined if TLBs are not consistent.
431 */
432 ret = 0;
433 best = nr;
434 goto done;
435 }
436 }
437 if (best != -1) {
438 done:
439 #if defined (DEBUG_SOFTWARE_TLB)
440 if (loglevel != 0) {
441 fprintf(logfile, "found TLB at addr " PADDRX " prot=%01x ret=%d\n",
442 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
443 }
444 #endif
445 /* Update page flags */
446 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
447 }
448
449 return ret;
450 }
451
452 /* Perform BAT hit & translation */
453 static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
454 int *validp, int *protp,
455 target_ulong *BATu, target_ulong *BATl)
456 {
457 target_ulong bl;
458 int pp, valid, prot;
459
460 bl = (*BATu & 0x00001FFC) << 15;
461 valid = 0;
462 prot = 0;
463 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
464 ((msr_pr != 0) && (*BATu & 0x00000001))) {
465 valid = 1;
466 pp = *BATl & 0x00000003;
467 if (pp != 0) {
468 prot = PAGE_READ | PAGE_EXEC;
469 if (pp == 0x2)
470 prot |= PAGE_WRITE;
471 }
472 }
473 *blp = bl;
474 *validp = valid;
475 *protp = prot;
476 }
477
478 static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
479 int *validp, int *protp,
480 target_ulong *BATu,
481 target_ulong *BATl)
482 {
483 target_ulong bl;
484 int key, pp, valid, prot;
485
486 bl = (*BATl & 0x0000003F) << 17;
487 #if defined (DEBUG_BATS)
488 if (loglevel != 0) {
489 fprintf(logfile, "b %02x ==> bl " ADDRX " msk " ADDRX "\n",
490 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
491 }
492 #endif
493 prot = 0;
494 valid = (*BATl >> 6) & 1;
495 if (valid) {
496 pp = *BATu & 0x00000003;
497 if (msr_pr == 0)
498 key = (*BATu >> 3) & 1;
499 else
500 key = (*BATu >> 2) & 1;
501 prot = pp_check(key, pp, 0);
502 }
503 *blp = bl;
504 *validp = valid;
505 *protp = prot;
506 }
507
508 static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
509 target_ulong virtual, int rw, int type)
510 {
511 target_ulong *BATlt, *BATut, *BATu, *BATl;
512 target_ulong base, BEPIl, BEPIu, bl;
513 int i, valid, prot;
514 int ret = -1;
515
516 #if defined (DEBUG_BATS)
517 if (loglevel != 0) {
518 fprintf(logfile, "%s: %cBAT v " ADDRX "\n", __func__,
519 type == ACCESS_CODE ? 'I' : 'D', virtual);
520 }
521 #endif
522 switch (type) {
523 case ACCESS_CODE:
524 BATlt = env->IBAT[1];
525 BATut = env->IBAT[0];
526 break;
527 default:
528 BATlt = env->DBAT[1];
529 BATut = env->DBAT[0];
530 break;
531 }
532 base = virtual & 0xFFFC0000;
533 for (i = 0; i < env->nb_BATs; i++) {
534 BATu = &BATut[i];
535 BATl = &BATlt[i];
536 BEPIu = *BATu & 0xF0000000;
537 BEPIl = *BATu & 0x0FFE0000;
538 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
539 bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
540 } else {
541 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
542 }
543 #if defined (DEBUG_BATS)
544 if (loglevel != 0) {
545 fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX
546 " BATl " ADDRX "\n", __func__,
547 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
548 }
549 #endif
550 if ((virtual & 0xF0000000) == BEPIu &&
551 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
552 /* BAT matches */
553 if (valid != 0) {
554 /* Get physical address */
555 ctx->raddr = (*BATl & 0xF0000000) |
556 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
557 (virtual & 0x0001F000);
558 /* Compute access rights */
559 ctx->prot = prot;
560 ret = check_prot(ctx->prot, rw, type);
561 #if defined (DEBUG_BATS)
562 if (ret == 0 && loglevel != 0) {
563 fprintf(logfile, "BAT %d match: r " PADDRX " prot=%c%c\n",
564 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
565 ctx->prot & PAGE_WRITE ? 'W' : '-');
566 }
567 #endif
568 break;
569 }
570 }
571 }
572 if (ret < 0) {
573 #if defined (DEBUG_BATS)
574 if (loglevel != 0) {
575 fprintf(logfile, "no BAT match for " ADDRX ":\n", virtual);
576 for (i = 0; i < 4; i++) {
577 BATu = &BATut[i];
578 BATl = &BATlt[i];
579 BEPIu = *BATu & 0xF0000000;
580 BEPIl = *BATu & 0x0FFE0000;
581 bl = (*BATu & 0x00001FFC) << 15;
582 fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX
583 " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
584 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
585 *BATu, *BATl, BEPIu, BEPIl, bl);
586 }
587 }
588 #endif
589 }
590
591 /* No hit */
592 return ret;
593 }
594
595 /* PTE table lookup */
596 static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
597 int rw, int type)
598 {
599 target_ulong base, pte0, pte1;
600 int i, good = -1;
601 int ret, r;
602
603 ret = -1; /* No entry found */
604 base = ctx->pg_addr[h];
605 for (i = 0; i < 8; i++) {
606 #if defined(TARGET_PPC64)
607 if (is_64b) {
608 pte0 = ldq_phys(base + (i * 16));
609 pte1 = ldq_phys(base + (i * 16) + 8);
610 r = pte64_check(ctx, pte0, pte1, h, rw, type);
611 #if defined (DEBUG_MMU)
612 if (loglevel != 0) {
613 fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX
614 " %d %d %d " ADDRX "\n",
615 base + (i * 16), pte0, pte1,
616 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
617 ctx->ptem);
618 }
619 #endif
620 } else
621 #endif
622 {
623 pte0 = ldl_phys(base + (i * 8));
624 pte1 = ldl_phys(base + (i * 8) + 4);
625 r = pte32_check(ctx, pte0, pte1, h, rw, type);
626 #if defined (DEBUG_MMU)
627 if (loglevel != 0) {
628 fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX
629 " %d %d %d " ADDRX "\n",
630 base + (i * 8), pte0, pte1,
631 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
632 ctx->ptem);
633 }
634 #endif
635 }
636 switch (r) {
637 case -3:
638 /* PTE inconsistency */
639 return -1;
640 case -2:
641 /* Access violation */
642 ret = -2;
643 good = i;
644 break;
645 case -1:
646 default:
647 /* No PTE match */
648 break;
649 case 0:
650 /* access granted */
651 /* XXX: we should go on looping to check all PTEs consistency
652 * but if we can speed-up the whole thing as the
653 * result would be undefined if PTEs are not consistent.
654 */
655 ret = 0;
656 good = i;
657 goto done;
658 }
659 }
660 if (good != -1) {
661 done:
662 #if defined (DEBUG_MMU)
663 if (loglevel != 0) {
664 fprintf(logfile, "found PTE at addr " PADDRX " prot=%01x ret=%d\n",
665 ctx->raddr, ctx->prot, ret);
666 }
667 #endif
668 /* Update page flags */
669 pte1 = ctx->raddr;
670 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
671 #if defined(TARGET_PPC64)
672 if (is_64b) {
673 stq_phys_notdirty(base + (good * 16) + 8, pte1);
674 } else
675 #endif
676 {
677 stl_phys_notdirty(base + (good * 8) + 4, pte1);
678 }
679 }
680 }
681
682 return ret;
683 }
684
685 static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
686 {
687 return _find_pte(ctx, 0, h, rw, type);
688 }
689
690 #if defined(TARGET_PPC64)
691 static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
692 {
693 return _find_pte(ctx, 1, h, rw, type);
694 }
695 #endif
696
697 static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
698 int h, int rw, int type)
699 {
700 #if defined(TARGET_PPC64)
701 if (env->mmu_model & POWERPC_MMU_64)
702 return find_pte64(ctx, h, rw, type);
703 #endif
704
705 return find_pte32(ctx, h, rw, type);
706 }
707
708 #if defined(TARGET_PPC64)
709 static always_inline int slb_is_valid (uint64_t slb64)
710 {
711 return slb64 & 0x0000000008000000ULL ? 1 : 0;
712 }
713
714 static always_inline void slb_invalidate (uint64_t *slb64)
715 {
716 *slb64 &= ~0x0000000008000000ULL;
717 }
718
719 static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
720 target_ulong *vsid,
721 target_ulong *page_mask, int *attr)
722 {
723 target_phys_addr_t sr_base;
724 target_ulong mask;
725 uint64_t tmp64;
726 uint32_t tmp;
727 int n, ret;
728
729 ret = -5;
730 sr_base = env->spr[SPR_ASR];
731 #if defined(DEBUG_SLB)
732 if (loglevel != 0) {
733 fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
734 __func__, eaddr, sr_base);
735 }
736 #endif
737 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
738 for (n = 0; n < env->slb_nr; n++) {
739 tmp64 = ldq_phys(sr_base);
740 tmp = ldl_phys(sr_base + 8);
741 #if defined(DEBUG_SLB)
742 if (loglevel != 0) {
743 fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"
744 PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
745 }
746 #endif
747 if (slb_is_valid(tmp64)) {
748 /* SLB entry is valid */
749 switch (tmp64 & 0x0000000006000000ULL) {
750 case 0x0000000000000000ULL:
751 /* 256 MB segment */
752 mask = 0xFFFFFFFFF0000000ULL;
753 break;
754 case 0x0000000002000000ULL:
755 /* 1 TB segment */
756 mask = 0xFFFF000000000000ULL;
757 break;
758 case 0x0000000004000000ULL:
759 case 0x0000000006000000ULL:
760 /* Reserved => segment is invalid */
761 continue;
762 }
763 if ((eaddr & mask) == (tmp64 & mask)) {
764 /* SLB match */
765 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
766 *page_mask = ~mask;
767 *attr = tmp & 0xFF;
768 ret = n;
769 break;
770 }
771 }
772 sr_base += 12;
773 }
774
775 return ret;
776 }
777
778 void ppc_slb_invalidate_all (CPUPPCState *env)
779 {
780 target_phys_addr_t sr_base;
781 uint64_t tmp64;
782 int n, do_invalidate;
783
784 do_invalidate = 0;
785 sr_base = env->spr[SPR_ASR];
786 /* XXX: Warning: slbia never invalidates the first segment */
787 for (n = 1; n < env->slb_nr; n++) {
788 tmp64 = ldq_phys(sr_base);
789 if (slb_is_valid(tmp64)) {
790 slb_invalidate(&tmp64);
791 stq_phys(sr_base, tmp64);
792 /* XXX: given the fact that segment size is 256 MB or 1TB,
793 * and we still don't have a tlb_flush_mask(env, n, mask)
794 * in Qemu, we just invalidate all TLBs
795 */
796 do_invalidate = 1;
797 }
798 sr_base += 12;
799 }
800 if (do_invalidate)
801 tlb_flush(env, 1);
802 }
803
804 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
805 {
806 target_phys_addr_t sr_base;
807 target_ulong vsid, page_mask;
808 uint64_t tmp64;
809 int attr;
810 int n;
811
812 n = slb_lookup(env, T0, &vsid, &page_mask, &attr);
813 if (n >= 0) {
814 sr_base = env->spr[SPR_ASR];
815 sr_base += 12 * n;
816 tmp64 = ldq_phys(sr_base);
817 if (slb_is_valid(tmp64)) {
818 slb_invalidate(&tmp64);
819 stq_phys(sr_base, tmp64);
820 /* XXX: given the fact that segment size is 256 MB or 1TB,
821 * and we still don't have a tlb_flush_mask(env, n, mask)
822 * in Qemu, we just invalidate all TLBs
823 */
824 tlb_flush(env, 1);
825 }
826 }
827 }
828
829 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
830 {
831 target_phys_addr_t sr_base;
832 target_ulong rt;
833 uint64_t tmp64;
834 uint32_t tmp;
835
836 sr_base = env->spr[SPR_ASR];
837 sr_base += 12 * slb_nr;
838 tmp64 = ldq_phys(sr_base);
839 tmp = ldl_phys(sr_base + 8);
840 if (tmp64 & 0x0000000008000000ULL) {
841 /* SLB entry is valid */
842 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
843 rt = tmp >> 8; /* 65:88 => 40:63 */
844 rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
845 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
846 rt |= ((tmp >> 4) & 0xF) << 27;
847 } else {
848 rt = 0;
849 }
850 #if defined(DEBUG_SLB)
851 if (loglevel != 0) {
852 fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
853 ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
854 }
855 #endif
856
857 return rt;
858 }
859
860 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
861 {
862 target_phys_addr_t sr_base;
863 uint64_t tmp64;
864 uint32_t tmp;
865
866 sr_base = env->spr[SPR_ASR];
867 sr_base += 12 * slb_nr;
868 /* Copy Rs bits 37:63 to SLB 62:88 */
869 tmp = rs << 8;
870 tmp64 = (rs >> 24) & 0x7;
871 /* Copy Rs bits 33:36 to SLB 89:92 */
872 tmp |= ((rs >> 27) & 0xF) << 4;
873 /* Set the valid bit */
874 tmp64 |= 1 << 27;
875 /* Set ESID */
876 tmp64 |= (uint32_t)slb_nr << 28;
877 #if defined(DEBUG_SLB)
878 if (loglevel != 0) {
879 fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64
880 " %08" PRIx32 "\n", __func__,
881 slb_nr, rs, sr_base, tmp64, tmp);
882 }
883 #endif
884 /* Write SLB entry to memory */
885 stq_phys(sr_base, tmp64);
886 stl_phys(sr_base + 8, tmp);
887 }
888 #endif /* defined(TARGET_PPC64) */
889
890 /* Perform segment based translation */
891 static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
892 int sdr_sh,
893 target_phys_addr_t hash,
894 target_phys_addr_t mask)
895 {
896 return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
897 }
898
899 static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
900 target_ulong eaddr, int rw, int type)
901 {
902 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
903 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
904 #if defined(TARGET_PPC64)
905 int attr;
906 #endif
907 int ds, vsid_sh, sdr_sh, pr;
908 int ret, ret2;
909
910 pr = msr_pr;
911 #if defined(TARGET_PPC64)
912 if (env->mmu_model & POWERPC_MMU_64) {
913 #if defined (DEBUG_MMU)
914 if (loglevel != 0) {
915 fprintf(logfile, "Check SLBs\n");
916 }
917 #endif
918 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
919 if (ret < 0)
920 return ret;
921 ctx->key = ((attr & 0x40) && (pr != 0)) ||
922 ((attr & 0x80) && (pr == 0)) ? 1 : 0;
923 ds = 0;
924 ctx->nx = attr & 0x20 ? 1 : 0;
925 vsid_mask = 0x00003FFFFFFFFF80ULL;
926 vsid_sh = 7;
927 sdr_sh = 18;
928 sdr_mask = 0x3FF80;
929 } else
930 #endif /* defined(TARGET_PPC64) */
931 {
932 sr = env->sr[eaddr >> 28];
933 page_mask = 0x0FFFFFFF;
934 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
935 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
936 ds = sr & 0x80000000 ? 1 : 0;
937 ctx->nx = sr & 0x10000000 ? 1 : 0;
938 vsid = sr & 0x00FFFFFF;
939 vsid_mask = 0x01FFFFC0;
940 vsid_sh = 6;
941 sdr_sh = 16;
942 sdr_mask = 0xFFC0;
943 #if defined (DEBUG_MMU)
944 if (loglevel != 0) {
945 fprintf(logfile, "Check segment v=" ADDRX " %d " ADDRX
946 " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
947 eaddr, (int)(eaddr >> 28), sr, env->nip,
948 env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
949 rw, type);
950 }
951 #endif
952 }
953 #if defined (DEBUG_MMU)
954 if (loglevel != 0) {
955 fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
956 ctx->key, ds, ctx->nx, vsid);
957 }
958 #endif
959 ret = -1;
960 if (!ds) {
961 /* Check if instruction fetch is allowed, if needed */
962 if (type != ACCESS_CODE || ctx->nx == 0) {
963 /* Page address translation */
964 /* Primary table address */
965 sdr = env->sdr1;
966 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
967 #if defined(TARGET_PPC64)
968 if (env->mmu_model & POWERPC_MMU_64) {
969 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
970 /* XXX: this is false for 1 TB segments */
971 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
972 } else
973 #endif
974 {
975 htab_mask = sdr & 0x000001FF;
976 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
977 }
978 mask = (htab_mask << sdr_sh) | sdr_mask;
979 #if defined (DEBUG_MMU)
980 if (loglevel != 0) {
981 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX
982 " mask " PADDRX " " ADDRX "\n",
983 sdr, sdr_sh, hash, mask, page_mask);
984 }
985 #endif
986 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
987 /* Secondary table address */
988 hash = (~hash) & vsid_mask;
989 #if defined (DEBUG_MMU)
990 if (loglevel != 0) {
991 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX
992 " mask " PADDRX "\n",
993 sdr, sdr_sh, hash, mask);
994 }
995 #endif
996 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
997 #if defined(TARGET_PPC64)
998 if (env->mmu_model & POWERPC_MMU_64) {
999 /* Only 5 bits of the page index are used in the AVPN */
1000 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
1001 } else
1002 #endif
1003 {
1004 ctx->ptem = (vsid << 7) | (pgidx >> 10);
1005 }
1006 /* Initialize real address with an invalid value */
1007 ctx->raddr = (target_phys_addr_t)-1ULL;
1008 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
1009 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
1010 /* Software TLB search */
1011 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
1012 } else {
1013 #if defined (DEBUG_MMU)
1014 if (loglevel != 0) {
1015 fprintf(logfile, "0 sdr1=" PADDRX " vsid=" ADDRX " "
1016 "api=" ADDRX " hash=" PADDRX
1017 " pg_addr=" PADDRX "\n",
1018 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
1019 }
1020 #endif
1021 /* Primary table lookup */
1022 ret = find_pte(env, ctx, 0, rw, type);
1023 if (ret < 0) {
1024 /* Secondary table lookup */
1025 #if defined (DEBUG_MMU)
1026 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
1027 fprintf(logfile, "1 sdr1=" PADDRX " vsid=" ADDRX " "
1028 "api=" ADDRX " hash=" PADDRX
1029 " pg_addr=" PADDRX "\n",
1030 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
1031 }
1032 #endif
1033 ret2 = find_pte(env, ctx, 1, rw, type);
1034 if (ret2 != -1)
1035 ret = ret2;
1036 }
1037 }
1038 #if defined (DUMP_PAGE_TABLES)
1039 if (loglevel != 0) {
1040 target_phys_addr_t curaddr;
1041 uint32_t a0, a1, a2, a3;
1042 fprintf(logfile, "Page table: " PADDRX " len " PADDRX "\n",
1043 sdr, mask + 0x80);
1044 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
1045 curaddr += 16) {
1046 a0 = ldl_phys(curaddr);
1047 a1 = ldl_phys(curaddr + 4);
1048 a2 = ldl_phys(curaddr + 8);
1049 a3 = ldl_phys(curaddr + 12);
1050 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
1051 fprintf(logfile, PADDRX ": %08x %08x %08x %08x\n",
1052 curaddr, a0, a1, a2, a3);
1053 }
1054 }
1055 }
1056 #endif
1057 } else {
1058 #if defined (DEBUG_MMU)
1059 if (loglevel != 0)
1060 fprintf(logfile, "No access allowed\n");
1061 #endif
1062 ret = -3;
1063 }
1064 } else {
1065 #if defined (DEBUG_MMU)
1066 if (loglevel != 0)
1067 fprintf(logfile, "direct store...\n");
1068 #endif
1069 /* Direct-store segment : absolutely *BUGGY* for now */
1070 switch (type) {
1071 case ACCESS_INT:
1072 /* Integer load/store : only access allowed */
1073 break;
1074 case ACCESS_CODE:
1075 /* No code fetch is allowed in direct-store areas */
1076 return -4;
1077 case ACCESS_FLOAT:
1078 /* Floating point load/store */
1079 return -4;
1080 case ACCESS_RES:
1081 /* lwarx, ldarx or srwcx. */
1082 return -4;
1083 case ACCESS_CACHE:
1084 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1085 /* Should make the instruction do no-op.
1086 * As it already do no-op, it's quite easy :-)
1087 */
1088 ctx->raddr = eaddr;
1089 return 0;
1090 case ACCESS_EXT:
1091 /* eciwx or ecowx */
1092 return -4;
1093 default:
1094 if (logfile) {
1095 fprintf(logfile, "ERROR: instruction should not need "
1096 "address translation\n");
1097 }
1098 return -4;
1099 }
1100 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1101 ctx->raddr = eaddr;
1102 ret = 2;
1103 } else {
1104 ret = -2;
1105 }
1106 }
1107
1108 return ret;
1109 }
1110
1111 /* Generic TLB check function for embedded PowerPC implementations */
1112 static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
1113 target_phys_addr_t *raddrp,
1114 target_ulong address,
1115 uint32_t pid, int ext, int i)
1116 {
1117 target_ulong mask;
1118
1119 /* Check valid flag */
1120 if (!(tlb->prot & PAGE_VALID)) {
1121 if (loglevel != 0)
1122 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
1123 return -1;
1124 }
1125 mask = ~(tlb->size - 1);
1126 #if defined (DEBUG_SOFTWARE_TLB)
1127 if (loglevel != 0) {
1128 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
1129 " " ADDRX " %u\n",
1130 __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
1131 }
1132 #endif
1133 /* Check PID */
1134 if (tlb->PID != 0 && tlb->PID != pid)
1135 return -1;
1136 /* Check effective address */
1137 if ((address & mask) != tlb->EPN)
1138 return -1;
1139 *raddrp = (tlb->RPN & mask) | (address & ~mask);
1140 #if (TARGET_PHYS_ADDR_BITS >= 36)
1141 if (ext) {
1142 /* Extend the physical address to 36 bits */
1143 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1144 }
1145 #endif
1146
1147 return 0;
1148 }
1149
1150 /* Generic TLB search function for PowerPC embedded implementations */
1151 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
1152 {
1153 ppcemb_tlb_t *tlb;
1154 target_phys_addr_t raddr;
1155 int i, ret;
1156
1157 /* Default return value is no match */
1158 ret = -1;
1159 for (i = 0; i < env->nb_tlb; i++) {
1160 tlb = &env->tlb[i].tlbe;
1161 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
1162 ret = i;
1163 break;
1164 }
1165 }
1166
1167 return ret;
1168 }
1169
1170 /* Helpers specific to PowerPC 40x implementations */
1171 static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
1172 {
1173 ppcemb_tlb_t *tlb;
1174 int i;
1175
1176 for (i = 0; i < env->nb_tlb; i++) {
1177 tlb = &env->tlb[i].tlbe;
1178 tlb->prot &= ~PAGE_VALID;
1179 }
1180 tlb_flush(env, 1);
1181 }
1182
1183 static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
1184 target_ulong eaddr,
1185 uint32_t pid)
1186 {
1187 #if !defined(FLUSH_ALL_TLBS)
1188 ppcemb_tlb_t *tlb;
1189 target_phys_addr_t raddr;
1190 target_ulong page, end;
1191 int i;
1192
1193 for (i = 0; i < env->nb_tlb; i++) {
1194 tlb = &env->tlb[i].tlbe;
1195 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1196 end = tlb->EPN + tlb->size;
1197 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1198 tlb_flush_page(env, page);
1199 tlb->prot &= ~PAGE_VALID;
1200 break;
1201 }
1202 }
1203 #else
1204 ppc4xx_tlb_invalidate_all(env);
1205 #endif
1206 }
1207
1208 static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1209 target_ulong address, int rw, int access_type)
1210 {
1211 ppcemb_tlb_t *tlb;
1212 target_phys_addr_t raddr;
1213 int i, ret, zsel, zpr, pr;
1214
1215 ret = -1;
1216 raddr = (target_phys_addr_t)-1ULL;
1217 pr = msr_pr;
1218 for (i = 0; i < env->nb_tlb; i++) {
1219 tlb = &env->tlb[i].tlbe;
1220 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1221 env->spr[SPR_40x_PID], 0, i) < 0)
1222 continue;
1223 zsel = (tlb->attr >> 4) & 0xF;
1224 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
1225 #if defined (DEBUG_SOFTWARE_TLB)
1226 if (loglevel != 0) {
1227 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1228 __func__, i, zsel, zpr, rw, tlb->attr);
1229 }
1230 #endif
1231 /* Check execute enable bit */
1232 switch (zpr) {
1233 case 0x2:
1234 if (pr != 0)
1235 goto check_perms;
1236 /* No break here */
1237 case 0x3:
1238 /* All accesses granted */
1239 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1240 ret = 0;
1241 break;
1242 case 0x0:
1243 if (pr != 0) {
1244 ctx->prot = 0;
1245 ret = -2;
1246 break;
1247 }
1248 /* No break here */
1249 case 0x1:
1250 check_perms:
1251 /* Check from TLB entry */
1252 /* XXX: there is a problem here or in the TLB fill code... */
1253 ctx->prot = tlb->prot;
1254 ctx->prot |= PAGE_EXEC;
1255 ret = check_prot(ctx->prot, rw, access_type);
1256 break;
1257 }
1258 if (ret >= 0) {
1259 ctx->raddr = raddr;
1260 #if defined (DEBUG_SOFTWARE_TLB)
1261 if (loglevel != 0) {
1262 fprintf(logfile, "%s: access granted " ADDRX " => " PADDRX
1263 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1264 ret);
1265 }
1266 #endif
1267 return 0;
1268 }
1269 }
1270 #if defined (DEBUG_SOFTWARE_TLB)
1271 if (loglevel != 0) {
1272 fprintf(logfile, "%s: access refused " ADDRX " => " PADDRX
1273 " %d %d\n", __func__, address, raddr, ctx->prot,
1274 ret);
1275 }
1276 #endif
1277
1278 return ret;
1279 }
1280
1281 void store_40x_sler (CPUPPCState *env, uint32_t val)
1282 {
1283 /* XXX: TO BE FIXED */
1284 if (val != 0x00000000) {
1285 cpu_abort(env, "Little-endian regions are not supported by now\n");
1286 }
1287 env->spr[SPR_405_SLER] = val;
1288 }
1289
1290 static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1291 target_ulong address, int rw,
1292 int access_type)
1293 {
1294 ppcemb_tlb_t *tlb;
1295 target_phys_addr_t raddr;
1296 int i, prot, ret;
1297
1298 ret = -1;
1299 raddr = (target_phys_addr_t)-1ULL;
1300 for (i = 0; i < env->nb_tlb; i++) {
1301 tlb = &env->tlb[i].tlbe;
1302 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1303 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1304 continue;
1305 if (msr_pr != 0)
1306 prot = tlb->prot & 0xF;
1307 else
1308 prot = (tlb->prot >> 4) & 0xF;
1309 /* Check the address space */
1310 if (access_type == ACCESS_CODE) {
1311 if (msr_ir != (tlb->attr & 1))
1312 continue;
1313 ctx->prot = prot;
1314 if (prot & PAGE_EXEC) {
1315 ret = 0;
1316 break;
1317 }
1318 ret = -3;
1319 } else {
1320 if (msr_dr != (tlb->attr & 1))
1321 continue;
1322 ctx->prot = prot;
1323 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1324 ret = 0;
1325 break;
1326 }
1327 ret = -2;
1328 }
1329 }
1330 if (ret >= 0)
1331 ctx->raddr = raddr;
1332
1333 return ret;
1334 }
1335
1336 static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
1337 target_ulong eaddr, int rw)
1338 {
1339 int in_plb, ret;
1340
1341 ctx->raddr = eaddr;
1342 ctx->prot = PAGE_READ | PAGE_EXEC;
1343 ret = 0;
1344 switch (env->mmu_model) {
1345 case POWERPC_MMU_32B:
1346 case POWERPC_MMU_601:
1347 case POWERPC_MMU_SOFT_6xx:
1348 case POWERPC_MMU_SOFT_74xx:
1349 case POWERPC_MMU_SOFT_4xx:
1350 case POWERPC_MMU_REAL:
1351 case POWERPC_MMU_BOOKE:
1352 ctx->prot |= PAGE_WRITE;
1353 break;
1354 #if defined(TARGET_PPC64)
1355 case POWERPC_MMU_620:
1356 case POWERPC_MMU_64B:
1357 /* Real address are 60 bits long */
1358 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1359 ctx->prot |= PAGE_WRITE;
1360 break;
1361 #endif
1362 case POWERPC_MMU_SOFT_4xx_Z:
1363 if (unlikely(msr_pe != 0)) {
1364 /* 403 family add some particular protections,
1365 * using PBL/PBU registers for accesses with no translation.
1366 */
1367 in_plb =
1368 /* Check PLB validity */
1369 (env->pb[0] < env->pb[1] &&
1370 /* and address in plb area */
1371 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1372 (env->pb[2] < env->pb[3] &&
1373 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1374 if (in_plb ^ msr_px) {
1375 /* Access in protected area */
1376 if (rw == 1) {
1377 /* Access is not allowed */
1378 ret = -2;
1379 }
1380 } else {
1381 /* Read-write access is allowed */
1382 ctx->prot |= PAGE_WRITE;
1383 }
1384 }
1385 break;
1386 case POWERPC_MMU_MPC8xx:
1387 /* XXX: TODO */
1388 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1389 break;
1390 case POWERPC_MMU_BOOKE_FSL:
1391 /* XXX: TODO */
1392 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1393 break;
1394 default:
1395 cpu_abort(env, "Unknown or invalid MMU model\n");
1396 return -1;
1397 }
1398
1399 return ret;
1400 }
1401
1402 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1403 int rw, int access_type)
1404 {
1405 int ret;
1406
1407 #if 0
1408 if (loglevel != 0) {
1409 fprintf(logfile, "%s\n", __func__);
1410 }
1411 #endif
1412 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1413 (access_type != ACCESS_CODE && msr_dr == 0)) {
1414 /* No address translation */
1415 ret = check_physical(env, ctx, eaddr, rw);
1416 } else {
1417 ret = -1;
1418 switch (env->mmu_model) {
1419 case POWERPC_MMU_32B:
1420 case POWERPC_MMU_601:
1421 case POWERPC_MMU_SOFT_6xx:
1422 case POWERPC_MMU_SOFT_74xx:
1423 #if defined(TARGET_PPC64)
1424 case POWERPC_MMU_620:
1425 case POWERPC_MMU_64B:
1426 #endif
1427 /* Try to find a BAT */
1428 if (env->nb_BATs != 0)
1429 ret = get_bat(env, ctx, eaddr, rw, access_type);
1430 if (ret < 0) {
1431 /* We didn't match any BAT entry or don't have BATs */
1432 ret = get_segment(env, ctx, eaddr, rw, access_type);
1433 }
1434 break;
1435 case POWERPC_MMU_SOFT_4xx:
1436 case POWERPC_MMU_SOFT_4xx_Z:
1437 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1438 rw, access_type);
1439 break;
1440 case POWERPC_MMU_BOOKE:
1441 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1442 rw, access_type);
1443 break;
1444 case POWERPC_MMU_MPC8xx:
1445 /* XXX: TODO */
1446 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1447 break;
1448 case POWERPC_MMU_BOOKE_FSL:
1449 /* XXX: TODO */
1450 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1451 return -1;
1452 case POWERPC_MMU_REAL:
1453 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1454 return -1;
1455 default:
1456 cpu_abort(env, "Unknown or invalid MMU model\n");
1457 return -1;
1458 }
1459 }
1460 #if 0
1461 if (loglevel != 0) {
1462 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
1463 __func__, eaddr, ret, ctx->raddr);
1464 }
1465 #endif
1466
1467 return ret;
1468 }
1469
1470 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1471 {
1472 mmu_ctx_t ctx;
1473
1474 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
1475 return -1;
1476
1477 return ctx.raddr & TARGET_PAGE_MASK;
1478 }
1479
1480 /* Perform address translation */
1481 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1482 int mmu_idx, int is_softmmu)
1483 {
1484 mmu_ctx_t ctx;
1485 int access_type;
1486 int ret = 0;
1487
1488 if (rw == 2) {
1489 /* code access */
1490 rw = 0;
1491 access_type = ACCESS_CODE;
1492 } else {
1493 /* data access */
1494 access_type = env->access_type;
1495 }
1496 ret = get_physical_address(env, &ctx, address, rw, access_type);
1497 if (ret == 0) {
1498 ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
1499 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1500 mmu_idx, is_softmmu);
1501 } else if (ret < 0) {
1502 #if defined (DEBUG_MMU)
1503 if (loglevel != 0)
1504 cpu_dump_state(env, logfile, fprintf, 0);
1505 #endif
1506 if (access_type == ACCESS_CODE) {
1507 switch (ret) {
1508 case -1:
1509 /* No matches in page tables or TLB */
1510 switch (env->mmu_model) {
1511 case POWERPC_MMU_SOFT_6xx:
1512 env->exception_index = POWERPC_EXCP_IFTLB;
1513 env->error_code = 1 << 18;
1514 env->spr[SPR_IMISS] = address;
1515 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1516 goto tlb_miss;
1517 case POWERPC_MMU_SOFT_74xx:
1518 env->exception_index = POWERPC_EXCP_IFTLB;
1519 goto tlb_miss_74xx;
1520 case POWERPC_MMU_SOFT_4xx:
1521 case POWERPC_MMU_SOFT_4xx_Z:
1522 env->exception_index = POWERPC_EXCP_ITLB;
1523 env->error_code = 0;
1524 env->spr[SPR_40x_DEAR] = address;
1525 env->spr[SPR_40x_ESR] = 0x00000000;
1526 break;
1527 case POWERPC_MMU_32B:
1528 case POWERPC_MMU_601:
1529 #if defined(TARGET_PPC64)
1530 case POWERPC_MMU_620:
1531 case POWERPC_MMU_64B:
1532 #endif
1533 env->exception_index = POWERPC_EXCP_ISI;
1534 env->error_code = 0x40000000;
1535 break;
1536 case POWERPC_MMU_BOOKE:
1537 /* XXX: TODO */
1538 cpu_abort(env, "BookE MMU model is not implemented\n");
1539 return -1;
1540 case POWERPC_MMU_BOOKE_FSL:
1541 /* XXX: TODO */
1542 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1543 return -1;
1544 case POWERPC_MMU_MPC8xx:
1545 /* XXX: TODO */
1546 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1547 break;
1548 case POWERPC_MMU_REAL:
1549 cpu_abort(env, "PowerPC in real mode should never raise "
1550 "any MMU exceptions\n");
1551 return -1;
1552 default:
1553 cpu_abort(env, "Unknown or invalid MMU model\n");
1554 return -1;
1555 }
1556 break;
1557 case -2:
1558 /* Access rights violation */
1559 env->exception_index = POWERPC_EXCP_ISI;
1560 env->error_code = 0x08000000;
1561 break;
1562 case -3:
1563 /* No execute protection violation */
1564 env->exception_index = POWERPC_EXCP_ISI;
1565 env->error_code = 0x10000000;
1566 break;
1567 case -4:
1568 /* Direct store exception */
1569 /* No code fetch is allowed in direct-store areas */
1570 env->exception_index = POWERPC_EXCP_ISI;
1571 env->error_code = 0x10000000;
1572 break;
1573 #if defined(TARGET_PPC64)
1574 case -5:
1575 /* No match in segment table */
1576 if (env->mmu_model == POWERPC_MMU_620) {
1577 env->exception_index = POWERPC_EXCP_ISI;
1578 /* XXX: this might be incorrect */
1579 env->error_code = 0x40000000;
1580 } else {
1581 env->exception_index = POWERPC_EXCP_ISEG;
1582 env->error_code = 0;
1583 }
1584 break;
1585 #endif
1586 }
1587 } else {
1588 switch (ret) {
1589 case -1:
1590 /* No matches in page tables or TLB */
1591 switch (env->mmu_model) {
1592 case POWERPC_MMU_SOFT_6xx:
1593 if (rw == 1) {
1594 env->exception_index = POWERPC_EXCP_DSTLB;
1595 env->error_code = 1 << 16;
1596 } else {
1597 env->exception_index = POWERPC_EXCP_DLTLB;
1598 env->error_code = 0;
1599 }
1600 env->spr[SPR_DMISS] = address;
1601 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1602 tlb_miss:
1603 env->error_code |= ctx.key << 19;
1604 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1605 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1606 break;
1607 case POWERPC_MMU_SOFT_74xx:
1608 if (rw == 1) {
1609 env->exception_index = POWERPC_EXCP_DSTLB;
1610 } else {
1611 env->exception_index = POWERPC_EXCP_DLTLB;
1612 }
1613 tlb_miss_74xx:
1614 /* Implement LRU algorithm */
1615 env->error_code = ctx.key << 19;
1616 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1617 ((env->last_way + 1) & (env->nb_ways - 1));
1618 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1619 break;
1620 case POWERPC_MMU_SOFT_4xx:
1621 case POWERPC_MMU_SOFT_4xx_Z:
1622 env->exception_index = POWERPC_EXCP_DTLB;
1623 env->error_code = 0;
1624 env->spr[SPR_40x_DEAR] = address;
1625 if (rw)
1626 env->spr[SPR_40x_ESR] = 0x00800000;
1627 else
1628 env->spr[SPR_40x_ESR] = 0x00000000;
1629 break;
1630 case POWERPC_MMU_32B:
1631 case POWERPC_MMU_601:
1632 #if defined(TARGET_PPC64)
1633 case POWERPC_MMU_620:
1634 case POWERPC_MMU_64B:
1635 #endif
1636 env->exception_index = POWERPC_EXCP_DSI;
1637 env->error_code = 0;
1638 env->spr[SPR_DAR] = address;
1639 if (rw == 1)
1640 env->spr[SPR_DSISR] = 0x42000000;
1641 else
1642 env->spr[SPR_DSISR] = 0x40000000;
1643 break;
1644 case POWERPC_MMU_MPC8xx:
1645 /* XXX: TODO */
1646 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1647 break;
1648 case POWERPC_MMU_BOOKE:
1649 /* XXX: TODO */
1650 cpu_abort(env, "BookE MMU model is not implemented\n");
1651 return -1;
1652 case POWERPC_MMU_BOOKE_FSL:
1653 /* XXX: TODO */
1654 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1655 return -1;
1656 case POWERPC_MMU_REAL:
1657 cpu_abort(env, "PowerPC in real mode should never raise "
1658 "any MMU exceptions\n");
1659 return -1;
1660 default:
1661 cpu_abort(env, "Unknown or invalid MMU model\n");
1662 return -1;
1663 }
1664 break;
1665 case -2:
1666 /* Access rights violation */
1667 env->exception_index = POWERPC_EXCP_DSI;
1668 env->error_code = 0;
1669 env->spr[SPR_DAR] = address;
1670 if (rw == 1)
1671 env->spr[SPR_DSISR] = 0x0A000000;
1672 else
1673 env->spr[SPR_DSISR] = 0x08000000;
1674 break;
1675 case -4:
1676 /* Direct store exception */
1677 switch (access_type) {
1678 case ACCESS_FLOAT:
1679 /* Floating point load/store */
1680 env->exception_index = POWERPC_EXCP_ALIGN;
1681 env->error_code = POWERPC_EXCP_ALIGN_FP;
1682 env->spr[SPR_DAR] = address;
1683 break;
1684 case ACCESS_RES:
1685 /* lwarx, ldarx or stwcx. */
1686 env->exception_index = POWERPC_EXCP_DSI;
1687 env->error_code = 0;
1688 env->spr[SPR_DAR] = address;
1689 if (rw == 1)
1690 env->spr[SPR_DSISR] = 0x06000000;
1691 else
1692 env->spr[SPR_DSISR] = 0x04000000;
1693 break;
1694 case ACCESS_EXT:
1695 /* eciwx or ecowx */
1696 env->exception_index = POWERPC_EXCP_DSI;
1697 env->error_code = 0;
1698 env->spr[SPR_DAR] = address;
1699 if (rw == 1)
1700 env->spr[SPR_DSISR] = 0x06100000;
1701 else
1702 env->spr[SPR_DSISR] = 0x04100000;
1703 break;
1704 default:
1705 printf("DSI: invalid exception (%d)\n", ret);
1706 env->exception_index = POWERPC_EXCP_PROGRAM;
1707 env->error_code =
1708 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1709 env->spr[SPR_DAR] = address;
1710 break;
1711 }
1712 break;
1713 #if defined(TARGET_PPC64)
1714 case -5:
1715 /* No match in segment table */
1716 if (env->mmu_model == POWERPC_MMU_620) {
1717 env->exception_index = POWERPC_EXCP_DSI;
1718 env->error_code = 0;
1719 env->spr[SPR_DAR] = address;
1720 /* XXX: this might be incorrect */
1721 if (rw == 1)
1722 env->spr[SPR_DSISR] = 0x42000000;
1723 else
1724 env->spr[SPR_DSISR] = 0x40000000;
1725 } else {
1726 env->exception_index = POWERPC_EXCP_DSEG;
1727 env->error_code = 0;
1728 env->spr[SPR_DAR] = address;
1729 }
1730 break;
1731 #endif
1732 }
1733 }
1734 #if 0
1735 printf("%s: set exception to %d %02x\n", __func__,
1736 env->exception, env->error_code);
1737 #endif
1738 ret = 1;
1739 }
1740
1741 return ret;
1742 }
1743
1744 /*****************************************************************************/
1745 /* BATs management */
1746 #if !defined(FLUSH_ALL_TLBS)
1747 static always_inline void do_invalidate_BAT (CPUPPCState *env,
1748 target_ulong BATu,
1749 target_ulong mask)
1750 {
1751 target_ulong base, end, page;
1752
1753 base = BATu & ~0x0001FFFF;
1754 end = base + mask + 0x00020000;
1755 #if defined (DEBUG_BATS)
1756 if (loglevel != 0) {
1757 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1758 base, end, mask);
1759 }
1760 #endif
1761 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1762 tlb_flush_page(env, page);
1763 #if defined (DEBUG_BATS)
1764 if (loglevel != 0)
1765 fprintf(logfile, "Flush done\n");
1766 #endif
1767 }
1768 #endif
1769
1770 static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1771 int ul, int nr, target_ulong value)
1772 {
1773 #if defined (DEBUG_BATS)
1774 if (loglevel != 0) {
1775 fprintf(logfile, "Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
1776 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1777 }
1778 #endif
1779 }
1780
1781 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1782 {
1783 target_ulong mask;
1784
1785 dump_store_bat(env, 'I', 0, nr, value);
1786 if (env->IBAT[0][nr] != value) {
1787 mask = (value << 15) & 0x0FFE0000UL;
1788 #if !defined(FLUSH_ALL_TLBS)
1789 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1790 #endif
1791 /* When storing valid upper BAT, mask BEPI and BRPN
1792 * and invalidate all TLBs covered by this BAT
1793 */
1794 mask = (value << 15) & 0x0FFE0000UL;
1795 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1796 (value & ~0x0001FFFFUL & ~mask);
1797 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1798 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1799 #if !defined(FLUSH_ALL_TLBS)
1800 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1801 #else
1802 tlb_flush(env, 1);
1803 #endif
1804 }
1805 }
1806
1807 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1808 {
1809 dump_store_bat(env, 'I', 1, nr, value);
1810 env->IBAT[1][nr] = value;
1811 }
1812
1813 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1814 {
1815 target_ulong mask;
1816
1817 dump_store_bat(env, 'D', 0, nr, value);
1818 if (env->DBAT[0][nr] != value) {
1819 /* When storing valid upper BAT, mask BEPI and BRPN
1820 * and invalidate all TLBs covered by this BAT
1821 */
1822 mask = (value << 15) & 0x0FFE0000UL;
1823 #if !defined(FLUSH_ALL_TLBS)
1824 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1825 #endif
1826 mask = (value << 15) & 0x0FFE0000UL;
1827 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1828 (value & ~0x0001FFFFUL & ~mask);
1829 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1830 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1831 #if !defined(FLUSH_ALL_TLBS)
1832 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1833 #else
1834 tlb_flush(env, 1);
1835 #endif
1836 }
1837 }
1838
1839 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1840 {
1841 dump_store_bat(env, 'D', 1, nr, value);
1842 env->DBAT[1][nr] = value;
1843 }
1844
1845 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
1846 {
1847 target_ulong mask;
1848 int do_inval;
1849
1850 dump_store_bat(env, 'I', 0, nr, value);
1851 if (env->IBAT[0][nr] != value) {
1852 do_inval = 0;
1853 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1854 if (env->IBAT[1][nr] & 0x40) {
1855 /* Invalidate BAT only if it is valid */
1856 #if !defined(FLUSH_ALL_TLBS)
1857 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1858 #else
1859 do_inval = 1;
1860 #endif
1861 }
1862 /* When storing valid upper BAT, mask BEPI and BRPN
1863 * and invalidate all TLBs covered by this BAT
1864 */
1865 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1866 (value & ~0x0001FFFFUL & ~mask);
1867 env->DBAT[0][nr] = env->IBAT[0][nr];
1868 if (env->IBAT[1][nr] & 0x40) {
1869 #if !defined(FLUSH_ALL_TLBS)
1870 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1871 #else
1872 do_inval = 1;
1873 #endif
1874 }
1875 #if defined(FLUSH_ALL_TLBS)
1876 if (do_inval)
1877 tlb_flush(env, 1);
1878 #endif
1879 }
1880 }
1881
1882 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
1883 {
1884 target_ulong mask;
1885 int do_inval;
1886
1887 dump_store_bat(env, 'I', 1, nr, value);
1888 if (env->IBAT[1][nr] != value) {
1889 do_inval = 0;
1890 if (env->IBAT[1][nr] & 0x40) {
1891 #if !defined(FLUSH_ALL_TLBS)
1892 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1893 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1894 #else
1895 do_inval = 1;
1896 #endif
1897 }
1898 if (value & 0x40) {
1899 #if !defined(FLUSH_ALL_TLBS)
1900 mask = (value << 17) & 0x0FFE0000UL;
1901 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1902 #else
1903 do_inval = 1;
1904 #endif
1905 }
1906 env->IBAT[1][nr] = value;
1907 env->DBAT[1][nr] = value;
1908 #if defined(FLUSH_ALL_TLBS)
1909 if (do_inval)
1910 tlb_flush(env, 1);
1911 #endif
1912 }
1913 }
1914
1915 /*****************************************************************************/
1916 /* TLB management */
1917 void ppc_tlb_invalidate_all (CPUPPCState *env)
1918 {
1919 switch (env->mmu_model) {
1920 case POWERPC_MMU_SOFT_6xx:
1921 case POWERPC_MMU_SOFT_74xx:
1922 ppc6xx_tlb_invalidate_all(env);
1923 break;
1924 case POWERPC_MMU_SOFT_4xx:
1925 case POWERPC_MMU_SOFT_4xx_Z:
1926 ppc4xx_tlb_invalidate_all(env);
1927 break;
1928 case POWERPC_MMU_REAL:
1929 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1930 break;
1931 case POWERPC_MMU_MPC8xx:
1932 /* XXX: TODO */
1933 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1934 break;
1935 case POWERPC_MMU_BOOKE:
1936 /* XXX: TODO */
1937 cpu_abort(env, "BookE MMU model is not implemented\n");
1938 break;
1939 case POWERPC_MMU_BOOKE_FSL:
1940 /* XXX: TODO */
1941 cpu_abort(env, "BookE MMU model is not implemented\n");
1942 break;
1943 case POWERPC_MMU_32B:
1944 case POWERPC_MMU_601:
1945 #if defined(TARGET_PPC64)
1946 case POWERPC_MMU_620:
1947 case POWERPC_MMU_64B:
1948 #endif /* defined(TARGET_PPC64) */
1949 tlb_flush(env, 1);
1950 break;
1951 default:
1952 /* XXX: TODO */
1953 cpu_abort(env, "Unknown MMU model\n");
1954 break;
1955 }
1956 }
1957
1958 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1959 {
1960 #if !defined(FLUSH_ALL_TLBS)
1961 addr &= TARGET_PAGE_MASK;
1962 switch (env->mmu_model) {
1963 case POWERPC_MMU_SOFT_6xx:
1964 case POWERPC_MMU_SOFT_74xx:
1965 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1966 if (env->id_tlbs == 1)
1967 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1968 break;
1969 case POWERPC_MMU_SOFT_4xx:
1970 case POWERPC_MMU_SOFT_4xx_Z:
1971 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1972 break;
1973 case POWERPC_MMU_REAL:
1974 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1975 break;
1976 case POWERPC_MMU_MPC8xx:
1977 /* XXX: TODO */
1978 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1979 break;
1980 case POWERPC_MMU_BOOKE:
1981 /* XXX: TODO */
1982 cpu_abort(env, "BookE MMU model is not implemented\n");
1983 break;
1984 case POWERPC_MMU_BOOKE_FSL:
1985 /* XXX: TODO */
1986 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1987 break;
1988 case POWERPC_MMU_32B:
1989 case POWERPC_MMU_601:
1990 /* tlbie invalidate TLBs for all segments */
1991 addr &= ~((target_ulong)-1ULL << 28);
1992 /* XXX: this case should be optimized,
1993 * giving a mask to tlb_flush_page
1994 */
1995 tlb_flush_page(env, addr | (0x0 << 28));
1996 tlb_flush_page(env, addr | (0x1 << 28));
1997 tlb_flush_page(env, addr | (0x2 << 28));
1998 tlb_flush_page(env, addr | (0x3 << 28));
1999 tlb_flush_page(env, addr | (0x4 << 28));
2000 tlb_flush_page(env, addr | (0x5 << 28));
2001 tlb_flush_page(env, addr | (0x6 << 28));
2002 tlb_flush_page(env, addr | (0x7 << 28));
2003 tlb_flush_page(env, addr | (0x8 << 28));
2004 tlb_flush_page(env, addr | (0x9 << 28));
2005 tlb_flush_page(env, addr | (0xA << 28));
2006 tlb_flush_page(env, addr | (0xB << 28));
2007 tlb_flush_page(env, addr | (0xC << 28));
2008 tlb_flush_page(env, addr | (0xD << 28));
2009 tlb_flush_page(env, addr | (0xE << 28));
2010 tlb_flush_page(env, addr | (0xF << 28));
2011 break;
2012 #if defined(TARGET_PPC64)
2013 case POWERPC_MMU_620:
2014 case POWERPC_MMU_64B:
2015 /* tlbie invalidate TLBs for all segments */
2016 /* XXX: given the fact that there are too many segments to invalidate,
2017 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
2018 * we just invalidate all TLBs
2019 */
2020 tlb_flush(env, 1);
2021 break;
2022 #endif /* defined(TARGET_PPC64) */
2023 default:
2024 /* XXX: TODO */
2025 cpu_abort(env, "Unknown MMU model\n");
2026 break;
2027 }
2028 #else
2029 ppc_tlb_invalidate_all(env);
2030 #endif
2031 }
2032
2033 /*****************************************************************************/
2034 /* Special registers manipulation */
2035 #if defined(TARGET_PPC64)
2036 void ppc_store_asr (CPUPPCState *env, target_ulong value)
2037 {
2038 if (env->asr != value) {
2039 env->asr = value;
2040 tlb_flush(env, 1);
2041 }
2042 }
2043 #endif
2044
2045 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
2046 {
2047 #if defined (DEBUG_MMU)
2048 if (loglevel != 0) {
2049 fprintf(logfile, "%s: " ADDRX "\n", __func__, value);
2050 }
2051 #endif
2052 if (env->sdr1 != value) {
2053 /* XXX: for PowerPC 64, should check that the HTABSIZE value
2054 * is <= 28
2055 */
2056 env->sdr1 = value;
2057 tlb_flush(env, 1);
2058 }
2059 }
2060
2061 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
2062 {
2063 #if defined (DEBUG_MMU)
2064 if (loglevel != 0) {
2065 fprintf(logfile, "%s: reg=%d " ADDRX " " ADDRX "\n",
2066 __func__, srnum, value, env->sr[srnum]);
2067 }
2068 #endif
2069 if (env->sr[srnum] != value) {
2070 env->sr[srnum] = value;
2071 #if !defined(FLUSH_ALL_TLBS) && 0
2072 {
2073 target_ulong page, end;
2074 /* Invalidate 256 MB of virtual memory */
2075 page = (16 << 20) * srnum;
2076 end = page + (16 << 20);
2077 for (; page != end; page += TARGET_PAGE_SIZE)
2078 tlb_flush_page(env, page);
2079 }
2080 #else
2081 tlb_flush(env, 1);
2082 #endif
2083 }
2084 }
2085 #endif /* !defined (CONFIG_USER_ONLY) */
2086
2087 /* GDBstub can read and write MSR... */
2088 void ppc_store_msr (CPUPPCState *env, target_ulong value)
2089 {
2090 hreg_store_msr(env, value, 0);
2091 }
2092
2093 /*****************************************************************************/
2094 /* Exception processing */
2095 #if defined (CONFIG_USER_ONLY)
2096 void do_interrupt (CPUState *env)
2097 {
2098 env->exception_index = POWERPC_EXCP_NONE;
2099 env->error_code = 0;
2100 }
2101
2102 void ppc_hw_interrupt (CPUState *env)
2103 {
2104 env->exception_index = POWERPC_EXCP_NONE;
2105 env->error_code = 0;
2106 }
2107 #else /* defined (CONFIG_USER_ONLY) */
2108 static always_inline void dump_syscall (CPUState *env)
2109 {
2110 fprintf(logfile, "syscall r0=" REGX " r3=" REGX " r4=" REGX
2111 " r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
2112 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
2113 ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip);
2114 }
2115
2116 /* Note that this function should be greatly optimized
2117 * when called with a constant excp, from ppc_hw_interrupt
2118 */
2119 static always_inline void powerpc_excp (CPUState *env,
2120 int excp_model, int excp)
2121 {
2122 target_ulong msr, new_msr, vector;
2123 int srr0, srr1, asrr0, asrr1;
2124 int lpes0, lpes1, lev;
2125
2126 if (0) {
2127 /* XXX: find a suitable condition to enable the hypervisor mode */
2128 lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
2129 lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
2130 } else {
2131 /* Those values ensure we won't enter the hypervisor mode */
2132 lpes0 = 0;
2133 lpes1 = 1;
2134 }
2135
2136 if (loglevel & CPU_LOG_INT) {
2137 fprintf(logfile, "Raise exception at " ADDRX " => %08x (%02x)\n",
2138 env->nip, excp, env->error_code);
2139 }
2140 msr = env->msr;
2141 new_msr = msr;
2142 srr0 = SPR_SRR0;
2143 srr1 = SPR_SRR1;
2144 asrr0 = -1;
2145 asrr1 = -1;
2146 msr &= ~((target_ulong)0x783F0000);
2147 switch (excp) {
2148 case POWERPC_EXCP_NONE:
2149 /* Should never happen */
2150 return;
2151 case POWERPC_EXCP_CRITICAL: /* Critical input */
2152 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2153 switch (excp_model) {
2154 case POWERPC_EXCP_40x:
2155 srr0 = SPR_40x_SRR2;
2156 srr1 = SPR_40x_SRR3;
2157 break;
2158 case POWERPC_EXCP_BOOKE:
2159 srr0 = SPR_BOOKE_CSRR0;
2160 srr1 = SPR_BOOKE_CSRR1;
2161 break;
2162 case POWERPC_EXCP_G2:
2163 break;
2164 default:
2165 goto excp_invalid;
2166 }
2167 goto store_next;
2168 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2169 if (msr_me == 0) {
2170 /* Machine check exception is not enabled.
2171 * Enter checkstop state.
2172 */
2173 if (loglevel != 0) {
2174 fprintf(logfile, "Machine check while not allowed. "
2175 "Entering checkstop state\n");
2176 } else {
2177 fprintf(stderr, "Machine check while not allowed. "
2178 "Entering checkstop state\n");
2179 }
2180 env->halted = 1;
2181 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2182 }
2183 new_msr &= ~((target_ulong)1 << MSR_RI);
2184 new_msr &= ~((target_ulong)1 << MSR_ME);
2185 if (0) {
2186 /* XXX: find a suitable condition to enable the hypervisor mode */
2187 new_msr |= (target_ulong)MSR_HVB;
2188 }
2189 /* XXX: should also have something loaded in DAR / DSISR */
2190 switch (excp_model) {
2191 case POWERPC_EXCP_40x:
2192 srr0 = SPR_40x_SRR2;
2193 srr1 = SPR_40x_SRR3;
2194 break;
2195 case POWERPC_EXCP_BOOKE:
2196 srr0 = SPR_BOOKE_MCSRR0;
2197 srr1 = SPR_BOOKE_MCSRR1;
2198 asrr0 = SPR_BOOKE_CSRR0;
2199 asrr1 = SPR_BOOKE_CSRR1;
2200 break;
2201 default:
2202 break;
2203 }
2204 goto store_next;
2205 case POWERPC_EXCP_DSI: /* Data storage exception */
2206 #if defined (DEBUG_EXCEPTIONS)
2207 if (loglevel != 0) {
2208 fprintf(logfile, "DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
2209 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2210 }
2211 #endif
2212 new_msr &= ~((target_ulong)1 << MSR_RI);
2213 if (lpes1 == 0)
2214 new_msr |= (target_ulong)MSR_HVB;
2215 goto store_next;
2216 case POWERPC_EXCP_ISI: /* Instruction storage exception */
2217 #if defined (DEBUG_EXCEPTIONS)
2218 if (loglevel != 0) {
2219 fprintf(logfile, "ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
2220 msr, env->nip);
2221 }
2222 #endif
2223 new_msr &= ~((target_ulong)1 << MSR_RI);
2224 if (lpes1 == 0)
2225 new_msr |= (target_ulong)MSR_HVB;
2226 msr |= env->error_code;
2227 goto store_next;
2228 case POWERPC_EXCP_EXTERNAL: /* External input */
2229 new_msr &= ~((target_ulong)1 << MSR_RI);
2230 if (lpes0 == 1)
2231 new_msr |= (target_ulong)MSR_HVB;
2232 goto store_next;
2233 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2234 new_msr &= ~((target_ulong)1 << MSR_RI);
2235 if (lpes1 == 0)
2236 new_msr |= (target_ulong)MSR_HVB;
2237 /* XXX: this is false */
2238 /* Get rS/rD and rA from faulting opcode */
2239 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2240 goto store_current;
2241 case POWERPC_EXCP_PROGRAM: /* Program exception */
2242 switch (env->error_code & ~0xF) {
2243 case POWERPC_EXCP_FP:
2244 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2245 #if defined (DEBUG_EXCEPTIONS)
2246 if (loglevel != 0) {
2247 fprintf(logfile, "Ignore floating point exception\n");
2248 }
2249 #endif
2250 env->exception_index = POWERPC_EXCP_NONE;
2251 env->error_code = 0;
2252 return;
2253 }
2254 new_msr &= ~((target_ulong)1 << MSR_RI);
2255 if (lpes1 == 0)
2256 new_msr |= (target_ulong)MSR_HVB;
2257 msr |= 0x00100000;
2258 if (msr_fe0 == msr_fe1)
2259 goto store_next;
2260 msr |= 0x00010000;
2261 break;
2262 case POWERPC_EXCP_INVAL:
2263 #if defined (DEBUG_EXCEPTIONS)
2264 if (loglevel != 0) {
2265 fprintf(logfile, "Invalid instruction at " ADDRX "\n",
2266 env->nip);
2267 }
2268 #endif
2269 new_msr &= ~((target_ulong)1 << MSR_RI);
2270 if (lpes1 == 0)
2271 new_msr |= (target_ulong)MSR_HVB;
2272 msr |= 0x00080000;
2273 break;
2274 case POWERPC_EXCP_PRIV:
2275 new_msr &= ~((target_ulong)1 << MSR_RI);
2276 if (lpes1 == 0)
2277 new_msr |= (target_ulong)MSR_HVB;
2278 msr |= 0x00040000;
2279 break;
2280 case POWERPC_EXCP_TRAP:
2281 new_msr &= ~((target_ulong)1 << MSR_RI);
2282 if (lpes1 == 0)
2283 new_msr |= (target_ulong)MSR_HVB;
2284 msr |= 0x00020000;
2285 break;
2286 default:
2287 /* Should never occur */
2288 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2289 env->error_code);
2290 break;
2291 }
2292 goto store_current;
2293 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2294 new_msr &= ~((target_ulong)1 << MSR_RI);
2295 if (lpes1 == 0)
2296 new_msr |= (target_ulong)MSR_HVB;
2297 goto store_current;
2298 case POWERPC_EXCP_SYSCALL: /* System call exception */
2299 /* NOTE: this is a temporary hack to support graphics OSI
2300 calls from the MOL driver */
2301 /* XXX: To be removed */
2302 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2303 env->osi_call) {
2304 if (env->osi_call(env) != 0) {
2305 env->exception_index = POWERPC_EXCP_NONE;
2306 env->error_code = 0;
2307 return;
2308 }
2309 }
2310 if (loglevel & CPU_LOG_INT) {
2311 dump_syscall(env);
2312 }
2313 new_msr &= ~((target_ulong)1 << MSR_RI);
2314 lev = env->error_code;
2315 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2316 new_msr |= (target_ulong)MSR_HVB;
2317 goto store_next;
2318 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2319 new_msr &= ~((target_ulong)1 << MSR_RI);
2320 goto store_current;
2321 case POWERPC_EXCP_DECR: /* Decrementer exception */
2322 new_msr &= ~((target_ulong)1 << MSR_RI);
2323 if (lpes1 == 0)
2324 new_msr |= (target_ulong)MSR_HVB;
2325 goto store_next;
2326 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2327 /* FIT on 4xx */
2328 #if defined (DEBUG_EXCEPTIONS)
2329 if (loglevel != 0)
2330 fprintf(logfile, "FIT exception\n");
2331 #endif
2332 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2333 goto store_next;
2334 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2335 #if defined (DEBUG_EXCEPTIONS)
2336 if (loglevel != 0)
2337 fprintf(logfile, "WDT exception\n");
2338 #endif
2339 switch (excp_model) {
2340 case POWERPC_EXCP_BOOKE:
2341 srr0 = SPR_BOOKE_CSRR0;
2342 srr1 = SPR_BOOKE_CSRR1;
2343 break;
2344 default:
2345 break;
2346 }
2347 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2348 goto store_next;
2349 case POWERPC_EXCP_DTLB: /* Data TLB error */
2350 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2351 goto store_next;
2352 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2353 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2354 goto store_next;
2355 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2356 switch (excp_model) {
2357 case POWERPC_EXCP_BOOKE:
2358 srr0 = SPR_BOOKE_DSRR0;
2359 srr1 = SPR_BOOKE_DSRR1;
2360 asrr0 = SPR_BOOKE_CSRR0;
2361 asrr1 = SPR_BOOKE_CSRR1;
2362 break;
2363 default:
2364 break;
2365 }
2366 /* XXX: TODO */
2367 cpu_abort(env, "Debug exception is not implemented yet !\n");
2368 goto store_next;
2369 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2370 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2371 goto store_current;
2372 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2373 /* XXX: TODO */
2374 cpu_abort(env, "Embedded floating point data exception "
2375 "is not implemented yet !\n");
2376 goto store_next;
2377 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2378 /* XXX: TODO */
2379 cpu_abort(env, "Embedded floating point round exception "
2380 "is not implemented yet !\n");
2381 goto store_next;
2382 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2383 new_msr &= ~((target_ulong)1 << MSR_RI);
2384 /* XXX: TODO */
2385 cpu_abort(env,
2386 "Performance counter exception is not implemented yet !\n");
2387 goto store_next;
2388 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
2389 /* XXX: TODO */
2390 cpu_abort(env,
2391 "Embedded doorbell interrupt is not implemented yet !\n");
2392 goto store_next;
2393 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2394 switch (excp_model) {
2395 case POWERPC_EXCP_BOOKE:
2396 srr0 = SPR_BOOKE_CSRR0;
2397 srr1 = SPR_BOOKE_CSRR1;
2398 break;
2399 default:
2400 break;
2401 }
2402 /* XXX: TODO */
2403 cpu_abort(env, "Embedded doorbell critical interrupt "
2404 "is not implemented yet !\n");
2405 goto store_next;
2406 case POWERPC_EXCP_RESET: /* System reset exception */
2407 new_msr &= ~((target_ulong)1 << MSR_RI);
2408 if (0) {
2409 /* XXX: find a suitable condition to enable the hypervisor mode */
2410 new_msr |= (target_ulong)MSR_HVB;
2411 }
2412 goto store_next;
2413 case POWERPC_EXCP_DSEG: /* Data segment exception */
2414 new_msr &= ~((target_ulong)1 << MSR_RI);
2415 if (lpes1 == 0)
2416 new_msr |= (target_ulong)MSR_HVB;
2417 goto store_next;
2418 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2419 new_msr &= ~((target_ulong)1 << MSR_RI);
2420 if (lpes1 == 0)
2421 new_msr |= (target_ulong)MSR_HVB;
2422 goto store_next;
2423 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2424 srr0 = SPR_HSRR0;
2425 srr1 = SPR_HSRR1;
2426 new_msr |= (target_ulong)MSR_HVB;
2427 goto store_next;
2428 case POWERPC_EXCP_TRACE: /* Trace exception */
2429 new_msr &= ~((target_ulong)1 << MSR_RI);
2430 if (lpes1 == 0)
2431 new_msr |= (target_ulong)MSR_HVB;
2432 goto store_next;
2433 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2434 srr0 = SPR_HSRR0;
2435 srr1 = SPR_HSRR1;
2436 new_msr |= (target_ulong)MSR_HVB;
2437 goto store_next;
2438 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2439 srr0 = SPR_HSRR0;
2440 srr1 = SPR_HSRR1;
2441 new_msr |= (target_ulong)MSR_HVB;
2442 goto store_next;
2443 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2444 srr0 = SPR_HSRR0;
2445 srr1 = SPR_HSRR1;
2446 new_msr |= (target_ulong)MSR_HVB;
2447 goto store_next;
2448 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2449 srr0 = SPR_HSRR0;
2450 srr1 = SPR_HSRR1;
2451 new_msr |= (target_ulong)MSR_HVB;
2452 goto store_next;
2453 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2454 new_msr &= ~((target_ulong)1 << MSR_RI);
2455 if (lpes1 == 0)
2456 new_msr |= (target_ulong)MSR_HVB;
2457 goto store_current;
2458 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2459 #if defined (DEBUG_EXCEPTIONS)
2460 if (loglevel != 0)
2461 fprintf(logfile, "PIT exception\n");
2462 #endif
2463 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2464 goto store_next;
2465 case POWERPC_EXCP_IO: /* IO error exception */
2466 /* XXX: TODO */
2467 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2468 goto store_next;
2469 case POWERPC_EXCP_RUNM: /* Run mode exception */
2470 /* XXX: TODO */
2471 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2472 goto store_next;
2473 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2474 /* XXX: TODO */
2475 cpu_abort(env, "602 emulation trap exception "
2476 "is not implemented yet !\n");
2477 goto store_next;
2478 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2479 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2480 if (lpes1 == 0) /* XXX: check this */
2481 new_msr |= (target_ulong)MSR_HVB;
2482 switch (excp_model) {
2483 case POWERPC_EXCP_602:
2484 case POWERPC_EXCP_603:
2485 case POWERPC_EXCP_603E:
2486 case POWERPC_EXCP_G2:
2487 goto tlb_miss_tgpr;
2488 case POWERPC_EXCP_7x5:
2489 goto tlb_miss;
2490 case POWERPC_EXCP_74xx:
2491 goto tlb_miss_74xx;
2492 default:
2493 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2494 break;
2495 }
2496 break;
2497 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2498 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2499 if (lpes1 == 0) /* XXX: check this */
2500 new_msr |= (target_ulong)MSR_HVB;
2501 switch (excp_model) {
2502 case POWERPC_EXCP_602:
2503 case POWERPC_EXCP_603:
2504 case POWERPC_EXCP_603E:
2505 case POWERPC_EXCP_G2:
2506 goto tlb_miss_tgpr;
2507 case POWERPC_EXCP_7x5:
2508 goto tlb_miss;
2509 case POWERPC_EXCP_74xx:
2510 goto tlb_miss_74xx;
2511 default:
2512 cpu_abort(env, "Invalid data load TLB miss exception\n");
2513 break;
2514 }
2515 break;
2516 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2517 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2518 if (lpes1 == 0) /* XXX: check this */
2519 new_msr |= (target_ulong)MSR_HVB;
2520 switch (excp_model) {
2521 case POWERPC_EXCP_602:
2522 case POWERPC_EXCP_603:
2523 case POWERPC_EXCP_603E:
2524 case POWERPC_EXCP_G2:
2525 tlb_miss_tgpr:
2526 /* Swap temporary saved registers with GPRs */
2527 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
2528 new_msr |= (target_ulong)1 << MSR_TGPR;
2529 hreg_swap_gpr_tgpr(env);
2530 }
2531 goto tlb_miss;
2532 case POWERPC_EXCP_7x5:
2533 tlb_miss:
2534 #if defined (DEBUG_SOFTWARE_TLB)
2535 if (loglevel != 0) {
2536 const unsigned char *es;
2537 target_ulong *miss, *cmp;
2538 int en;
2539 if (excp == POWERPC_EXCP_IFTLB) {
2540 es = "I";
2541 en = 'I';
2542 miss = &env->spr[SPR_IMISS];
2543 cmp = &env->spr[SPR_ICMP];
2544 } else {
2545 if (excp == POWERPC_EXCP_DLTLB)
2546 es = "DL";
2547 else
2548 es = "DS";
2549 en = 'D';
2550 miss = &env->spr[SPR_DMISS];
2551 cmp = &env->spr[SPR_DCMP];
2552 }
2553 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2554 " H1 " ADDRX " H2 " ADDRX " %08x\n",
2555 es, en, *miss, en, *cmp,
2556 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2557 env->error_code);
2558 }
2559 #endif
2560 msr |= env->crf[0] << 28;
2561 msr |= env->error_code; /* key, D/I, S/L bits */
2562 /* Set way using a LRU mechanism */
2563 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2564 break;
2565 case POWERPC_EXCP_74xx:
2566 tlb_miss_74xx:
2567 #if defined (DEBUG_SOFTWARE_TLB)
2568 if (loglevel != 0) {
2569 const unsigned char *es;
2570 target_ulong *miss, *cmp;
2571 int en;
2572 if (excp == POWERPC_EXCP_IFTLB) {
2573 es = "I";
2574 en = 'I';
2575 miss = &env->spr[SPR_TLBMISS];
2576 cmp = &env->spr[SPR_PTEHI];
2577 } else {
2578 if (excp == POWERPC_EXCP_DLTLB)
2579 es = "DL";
2580 else
2581 es = "DS";
2582 en = 'D';
2583 miss = &env->spr[SPR_TLBMISS];
2584 cmp = &env->spr[SPR_PTEHI];
2585 }
2586 fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2587 " %08x\n",
2588 es, en, *miss, en, *cmp, env->error_code);
2589 }
2590 #endif
2591 msr |= env->error_code; /* key bit */
2592 break;
2593 default:
2594 cpu_abort(env, "Invalid data store TLB miss exception\n");
2595 break;
2596 }
2597 goto store_next;
2598 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2599 /* XXX: TODO */
2600 cpu_abort(env, "Floating point assist exception "
2601 "is not implemented yet !\n");
2602 goto store_next;
2603 case POWERPC_EXCP_DABR: /* Data address breakpoint */
2604 /* XXX: TODO */
2605 cpu_abort(env, "DABR exception is not implemented yet !\n");
2606 goto store_next;
2607 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2608 /* XXX: TODO */
2609 cpu_abort(env, "IABR exception is not implemented yet !\n");
2610 goto store_next;
2611 case POWERPC_EXCP_SMI: /* System management interrupt */
2612 /* XXX: TODO */
2613 cpu_abort(env, "SMI exception is not implemented yet !\n");
2614 goto store_next;
2615 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2616 /* XXX: TODO */
2617 cpu_abort(env, "Thermal management exception "
2618 "is not implemented yet !\n");
2619 goto store_next;
2620 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2621 new_msr &= ~((target_ulong)1 << MSR_RI);
2622 if (lpes1 == 0)
2623 new_msr |= (target_ulong)MSR_HVB;
2624 /* XXX: TODO */
2625 cpu_abort(env,
2626 "Performance counter exception is not implemented yet !\n");
2627 goto store_next;
2628 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2629 /* XXX: TODO */
2630 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2631 goto store_next;
2632 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2633 /* XXX: TODO */
2634 cpu_abort(env,
2635 "970 soft-patch exception is not implemented yet !\n");
2636 goto store_next;
2637 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2638 /* XXX: TODO */
2639 cpu_abort(env,
2640 "970 maintenance exception is not implemented yet !\n");
2641 goto store_next;
2642 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
2643 /* XXX: TODO */
2644 cpu_abort(env, "Maskable external exception "
2645 "is not implemented yet !\n");
2646 goto store_next;
2647 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
2648 /* XXX: TODO */
2649 cpu_abort(env, "Non maskable external exception "
2650 "is not implemented yet !\n");
2651 goto store_next;
2652 default:
2653 excp_invalid:
2654 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2655 break;
2656 store_current:
2657 /* save current instruction location */
2658 env->spr[srr0] = env->nip - 4;
2659 break;
2660 store_next:
2661 /* save next instruction location */
2662 env->spr[srr0] = env->nip;
2663 break;
2664 }
2665 /* Save MSR */
2666 env->spr[srr1] = msr;
2667 /* If any alternate SRR register are defined, duplicate saved values */
2668 if (asrr0 != -1)
2669 env->spr[asrr0] = env->spr[srr0];
2670 if (asrr1 != -1)
2671 env->spr[asrr1] = env->spr[srr1];
2672 /* If we disactivated any translation, flush TLBs */
2673 if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
2674 tlb_flush(env, 1);
2675 /* reload MSR with correct bits */
2676 new_msr &= ~((target_ulong)1 << MSR_EE);
2677 new_msr &= ~((target_ulong)1 << MSR_PR);
2678 new_msr &= ~((target_ulong)1 << MSR_FP);
2679 new_msr &= ~((target_ulong)1 << MSR_FE0);
2680 new_msr &= ~((target_ulong)1 << MSR_SE);
2681 new_msr &= ~((target_ulong)1 << MSR_BE);
2682 new_msr &= ~((target_ulong)1 << MSR_FE1);
2683 new_msr &= ~((target_ulong)1 << MSR_IR);
2684 new_msr &= ~((target_ulong)1 << MSR_DR);
2685 #if 0 /* Fix this: not on all targets */
2686 new_msr &= ~((target_ulong)1 << MSR_PMM);
2687 #endif
2688 new_msr &= ~((target_ulong)1 << MSR_LE);
2689 if (msr_ile)
2690 new_msr |= (target_ulong)1 << MSR_LE;
2691 else
2692 new_msr &= ~((target_ulong)1 << MSR_LE);
2693 /* Jump to handler */
2694 vector = env->excp_vectors[excp];
2695 if (vector == (target_ulong)-1ULL) {
2696 cpu_abort(env, "Raised an exception without defined vector %d\n",
2697 excp);
2698 }
2699 vector |= env->excp_prefix;
2700 #if defined(TARGET_PPC64)
2701 if (excp_model == POWERPC_EXCP_BOOKE) {
2702 if (!msr_icm) {
2703 new_msr &= ~((target_ulong)1 << MSR_CM);
2704 vector = (uint32_t)vector;
2705 } else {
2706 new_msr |= (target_ulong)1 << MSR_CM;
2707 }
2708 } else {
2709 if (!msr_isf) {
2710 new_msr &= ~((target_ulong)1 << MSR_SF);
2711 vector = (uint32_t)vector;
2712 } else {
2713 new_msr |= (target_ulong)1 << MSR_SF;
2714 }
2715 }
2716 #endif
2717 /* XXX: we don't use hreg_store_msr here as already have treated
2718 * any special case that could occur. Just store MSR and update hflags
2719 */
2720 env->msr = new_msr & env->msr_mask;
2721 hreg_compute_hflags(env);
2722 env->nip = vector;
2723 /* Reset exception state */
2724 env->exception_index = POWERPC_EXCP_NONE;
2725 env->error_code = 0;
2726 }
2727
2728 void do_interrupt (CPUState *env)
2729 {
2730 powerpc_excp(env, env->excp_model, env->exception_index);
2731 }
2732
2733 void ppc_hw_interrupt (CPUPPCState *env)
2734 {
2735 int hdice;
2736
2737 #if 0
2738 if (loglevel & CPU_LOG_INT) {
2739 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2740 __func__, env, env->pending_interrupts,
2741 env->interrupt_request, (int)msr_me, (int)msr_ee);
2742 }
2743 #endif
2744 /* External reset */
2745 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2746 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2747 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2748 return;
2749 }
2750 /* Machine check exception */
2751 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2752 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2753 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2754 return;
2755 }
2756 #if 0 /* TODO */
2757 /* External debug exception */
2758 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2759 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2760 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2761 return;
2762 }
2763 #endif
2764 if (0) {
2765 /* XXX: find a suitable condition to enable the hypervisor mode */
2766 hdice = env->spr[SPR_LPCR] & 1;
2767 } else {
2768 hdice = 0;
2769 }
2770 if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
2771 /* Hypervisor decrementer exception */
2772 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2773 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2774 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2775 return;
2776 }
2777 }
2778 if (msr_ce != 0) {
2779 /* External critical interrupt */
2780 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2781 /* Taking a critical external interrupt does not clear the external
2782 * critical interrupt status
2783 */
2784 #if 0
2785 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2786 #endif
2787 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2788 return;
2789 }
2790 }
2791 if (msr_ee != 0) {
2792 /* Watchdog timer on embedded PowerPC */
2793 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2794 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2795 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2796 return;
2797 }
2798 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2799 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2800 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2801 return;
2802 }
2803 /* Fixed interval timer on embedded PowerPC */
2804 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2805 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2806 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2807 return;
2808 }
2809 /* Programmable interval timer on embedded PowerPC */
2810 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2811 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2812 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2813 return;
2814 }
2815 /* Decrementer exception */
2816 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2817 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2818 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2819 return;
2820 }
2821 /* External interrupt */
2822 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2823 /* Taking an external interrupt does not clear the external
2824 * interrupt status
2825 */
2826 #if 0
2827 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2828 #endif
2829 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2830 return;
2831 }
2832 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2833 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2834 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2835 return;
2836 }
2837 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2838 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2839 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2840 return;
2841 }
2842 /* Thermal interrupt */
2843 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2844 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2845 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2846 return;
2847 }
2848 }
2849 }
2850 #endif /* !CONFIG_USER_ONLY */
2851
2852 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2853 {
2854 FILE *f;
2855
2856 if (logfile) {
2857 f = logfile;
2858 } else {
2859 f = stdout;
2860 return;
2861 }
2862 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2863 RA, msr);
2864 }
2865
2866 void cpu_ppc_reset (void *opaque)
2867 {
2868 CPUPPCState *env;
2869 target_ulong msr;
2870
2871 env = opaque;
2872 msr = (target_ulong)0;
2873 if (0) {
2874 /* XXX: find a suitable condition to enable the hypervisor mode */
2875 msr |= (target_ulong)MSR_HVB;
2876 }
2877 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
2878 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
2879 msr |= (target_ulong)1 << MSR_EP;
2880 #if defined (DO_SINGLE_STEP) && 0
2881 /* Single step trace mode */
2882 msr |= (target_ulong)1 << MSR_SE;
2883 msr |= (target_ulong)1 << MSR_BE;
2884 #endif
2885 #if defined(CONFIG_USER_ONLY)
2886 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
2887 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
2888 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
2889 msr |= (target_ulong)1 << MSR_PR;
2890 env->msr = msr & env->msr_mask;
2891 #else
2892 env->nip = env->hreset_vector | env->excp_prefix;
2893 if (env->mmu_model != POWERPC_MMU_REAL)
2894 ppc_tlb_invalidate_all(env);
2895 #endif
2896 hreg_compute_hflags(env);
2897 env->reserve = (target_ulong)-1ULL;
2898 /* Be sure no exception or interrupt is pending */
2899 env->pending_interrupts = 0;
2900 env->exception_index = POWERPC_EXCP_NONE;
2901 env->error_code = 0;
2902 /* Flush all TLBs */
2903 tlb_flush(env, 1);
2904 }
2905
2906 CPUPPCState *cpu_ppc_init (const char *cpu_model)
2907 {
2908 CPUPPCState *env;
2909 const ppc_def_t *def;
2910
2911 def = cpu_ppc_find_by_name(cpu_model);
2912 if (!def)
2913 return NULL;
2914
2915 env = qemu_mallocz(sizeof(CPUPPCState));
2916 if (!env)
2917 return NULL;
2918 cpu_exec_init(env);
2919 ppc_translate_init();
2920 env->cpu_model_str = cpu_model;
2921 cpu_ppc_register_internal(env, def);
2922 cpu_ppc_reset(env);
2923 return env;
2924 }
2925
2926 void cpu_ppc_close (CPUPPCState *env)
2927 {
2928 /* Should also remove all opcode tables... */
2929 qemu_free(env);
2930 }
jz4740 based target emulation