2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
23 #include "helper_regs.h"
24 #include "op_helper.h"
26 #define MEMSUFFIX _raw
27 #include "op_helper.h"
28 #include "op_helper_mem.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #define MEMSUFFIX _user
31 #include "op_helper.h"
32 #include "op_helper_mem.h"
33 #define MEMSUFFIX _kernel
34 #include "op_helper.h"
35 #include "op_helper_mem.h"
36 #define MEMSUFFIX _hypv
37 #include "op_helper.h"
38 #include "op_helper_mem.h"
42 //#define DEBUG_EXCEPTIONS
43 //#define DEBUG_SOFTWARE_TLB
45 /*****************************************************************************/
46 /* Exceptions processing helpers */
48 void do_raise_exception_err (uint32_t exception
, int error_code
)
51 printf("Raise exception %3x code : %d\n", exception
, error_code
);
53 env
->exception_index
= exception
;
54 env
->error_code
= error_code
;
58 void do_raise_exception (uint32_t exception
)
60 do_raise_exception_err(exception
, 0);
63 /*****************************************************************************/
64 /* Registers load and stores */
65 uint32_t helper_load_cr (void)
67 return (env
->crf
[0] << 28) |
77 void helper_store_cr (target_ulong val
, uint32_t mask
)
81 for (i
= 0, sh
= 7; i
< 8; i
++, sh
--) {
83 env
->crf
[i
] = (val
>> (sh
* 4)) & 0xFUL
;
87 #if defined(TARGET_PPC64)
88 void do_store_pri (int prio
)
90 env
->spr
[SPR_PPR
] &= ~0x001C000000000000ULL
;
91 env
->spr
[SPR_PPR
] |= ((uint64_t)prio
& 0x7) << 50;
95 target_ulong
ppc_load_dump_spr (int sprn
)
98 fprintf(logfile
, "Read SPR %d %03x => " ADDRX
"\n",
99 sprn
, sprn
, env
->spr
[sprn
]);
102 return env
->spr
[sprn
];
105 void ppc_store_dump_spr (int sprn
, target_ulong val
)
108 fprintf(logfile
, "Write SPR %d %03x => " ADDRX
" <= " ADDRX
"\n",
109 sprn
, sprn
, env
->spr
[sprn
], val
);
111 env
->spr
[sprn
] = val
;
114 /*****************************************************************************/
115 /* Fixed point operations helpers */
116 #if defined(TARGET_PPC64)
118 /* multiply high word */
119 uint64_t helper_mulhd (uint64_t arg1
, uint64_t arg2
)
123 muls64(&tl
, &th
, arg1
, arg2
);
127 /* multiply high word unsigned */
128 uint64_t helper_mulhdu (uint64_t arg1
, uint64_t arg2
)
132 mulu64(&tl
, &th
, arg1
, arg2
);
136 uint64_t helper_mulldo (uint64_t arg1
, uint64_t arg2
)
141 muls64(&tl
, (uint64_t *)&th
, arg1
, arg2
);
142 /* If th != 0 && th != -1, then we had an overflow */
143 if (likely((uint64_t)(th
+ 1) <= 1)) {
144 env
->xer
&= ~(1 << XER_OV
);
146 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
152 target_ulong
helper_cntlzw (target_ulong t
)
157 #if defined(TARGET_PPC64)
158 target_ulong
helper_cntlzd (target_ulong t
)
164 /* shift right arithmetic helper */
165 target_ulong
helper_sraw (target_ulong value
, target_ulong shift
)
169 if (likely(!(shift
& 0x20))) {
170 if (likely((uint32_t)shift
!= 0)) {
172 ret
= (int32_t)value
>> shift
;
173 if (likely(ret
>= 0 || (value
& ((1 << shift
) - 1)) == 0)) {
174 env
->xer
&= ~(1 << XER_CA
);
176 env
->xer
|= (1 << XER_CA
);
179 ret
= (int32_t)value
;
180 env
->xer
&= ~(1 << XER_CA
);
183 ret
= (int32_t)value
>> 31;
185 env
->xer
|= (1 << XER_CA
);
187 env
->xer
&= ~(1 << XER_CA
);
190 return (target_long
)ret
;
193 #if defined(TARGET_PPC64)
194 target_ulong
helper_srad (target_ulong value
, target_ulong shift
)
198 if (likely(!(shift
& 0x40))) {
199 if (likely((uint64_t)shift
!= 0)) {
201 ret
= (int64_t)value
>> shift
;
202 if (likely(ret
>= 0 || (value
& ((1 << shift
) - 1)) == 0)) {
203 env
->xer
&= ~(1 << XER_CA
);
205 env
->xer
|= (1 << XER_CA
);
208 ret
= (int64_t)value
;
209 env
->xer
&= ~(1 << XER_CA
);
212 ret
= (int64_t)value
>> 63;
214 env
->xer
|= (1 << XER_CA
);
216 env
->xer
&= ~(1 << XER_CA
);
223 target_ulong
helper_popcntb (target_ulong val
)
229 for (i
= 0; i
< 32; i
+= 8)
230 ret
|= ctpop8((val
>> i
) & 0xFF) << i
;
234 #if defined(TARGET_PPC64)
235 target_ulong
helper_popcntb_64 (target_ulong val
)
241 for (i
= 0; i
< 64; i
+= 8)
242 ret
|= ctpop8((val
>> i
) & 0xFF) << i
;
247 /*****************************************************************************/
248 /* Floating point operations helpers */
249 static always_inline
int fpisneg (float64 d
)
255 return u
.ll
>> 63 != 0;
258 static always_inline
int isden (float64 d
)
264 return ((u
.ll
>> 52) & 0x7FF) == 0;
267 static always_inline
int iszero (float64 d
)
273 return (u
.ll
& ~0x8000000000000000ULL
) == 0;
276 static always_inline
int isinfinity (float64 d
)
282 return ((u
.ll
>> 52) & 0x7FF) == 0x7FF &&
283 (u
.ll
& 0x000FFFFFFFFFFFFFULL
) == 0;
286 #ifdef CONFIG_SOFTFLOAT
287 static always_inline
int isfinite (float64 d
)
293 return (((u
.ll
>> 52) & 0x7FF) != 0x7FF);
296 static always_inline
int isnormal (float64 d
)
302 uint32_t exp
= (u
.ll
>> 52) & 0x7FF;
303 return ((0 < exp
) && (exp
< 0x7FF));
307 void do_compute_fprf (int set_fprf
)
311 isneg
= fpisneg(FT0
);
312 if (unlikely(float64_is_nan(FT0
))) {
313 if (float64_is_signaling_nan(FT0
)) {
314 /* Signaling NaN: flags are undefined */
320 } else if (unlikely(isinfinity(FT0
))) {
335 /* Denormalized numbers */
338 /* Normalized numbers */
349 /* We update FPSCR_FPRF */
350 env
->fpscr
&= ~(0x1F << FPSCR_FPRF
);
351 env
->fpscr
|= T0
<< FPSCR_FPRF
;
353 /* We just need fpcc to update Rc1 */
357 /* Floating-point invalid operations exception */
358 static always_inline
void fload_invalid_op_excp (int op
)
363 if (op
& POWERPC_EXCP_FP_VXSNAN
) {
364 /* Operation on signaling NaN */
365 env
->fpscr
|= 1 << FPSCR_VXSNAN
;
367 if (op
& POWERPC_EXCP_FP_VXSOFT
) {
368 /* Software-defined condition */
369 env
->fpscr
|= 1 << FPSCR_VXSOFT
;
371 switch (op
& ~(POWERPC_EXCP_FP_VXSOFT
| POWERPC_EXCP_FP_VXSNAN
)) {
372 case POWERPC_EXCP_FP_VXISI
:
373 /* Magnitude subtraction of infinities */
374 env
->fpscr
|= 1 << FPSCR_VXISI
;
376 case POWERPC_EXCP_FP_VXIDI
:
377 /* Division of infinity by infinity */
378 env
->fpscr
|= 1 << FPSCR_VXIDI
;
380 case POWERPC_EXCP_FP_VXZDZ
:
381 /* Division of zero by zero */
382 env
->fpscr
|= 1 << FPSCR_VXZDZ
;
384 case POWERPC_EXCP_FP_VXIMZ
:
385 /* Multiplication of zero by infinity */
386 env
->fpscr
|= 1 << FPSCR_VXIMZ
;
388 case POWERPC_EXCP_FP_VXVC
:
389 /* Ordered comparison of NaN */
390 env
->fpscr
|= 1 << FPSCR_VXVC
;
391 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
392 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
393 /* We must update the target FPR before raising the exception */
395 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
396 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_VXVC
;
397 /* Update the floating-point enabled exception summary */
398 env
->fpscr
|= 1 << FPSCR_FEX
;
399 /* Exception is differed */
403 case POWERPC_EXCP_FP_VXSQRT
:
404 /* Square root of a negative number */
405 env
->fpscr
|= 1 << FPSCR_VXSQRT
;
407 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
409 /* Set the result to quiet NaN */
411 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
412 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
415 case POWERPC_EXCP_FP_VXCVI
:
416 /* Invalid conversion */
417 env
->fpscr
|= 1 << FPSCR_VXCVI
;
418 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
420 /* Set the result to quiet NaN */
422 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
423 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
427 /* Update the floating-point invalid operation summary */
428 env
->fpscr
|= 1 << FPSCR_VX
;
429 /* Update the floating-point exception summary */
430 env
->fpscr
|= 1 << FPSCR_FX
;
432 /* Update the floating-point enabled exception summary */
433 env
->fpscr
|= 1 << FPSCR_FEX
;
434 if (msr_fe0
!= 0 || msr_fe1
!= 0)
435 do_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_FP
| op
);
439 static always_inline
void float_zero_divide_excp (void)
443 env
->fpscr
|= 1 << FPSCR_ZX
;
444 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
445 /* Update the floating-point exception summary */
446 env
->fpscr
|= 1 << FPSCR_FX
;
448 /* Update the floating-point enabled exception summary */
449 env
->fpscr
|= 1 << FPSCR_FEX
;
450 if (msr_fe0
!= 0 || msr_fe1
!= 0) {
451 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
452 POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
);
455 /* Set the result to infinity */
458 u0
.ll
= ((u0
.ll
^ u1
.ll
) & 0x8000000000000000ULL
);
459 u0
.ll
|= 0x7FFULL
<< 52;
464 static always_inline
void float_overflow_excp (void)
466 env
->fpscr
|= 1 << FPSCR_OX
;
467 /* Update the floating-point exception summary */
468 env
->fpscr
|= 1 << FPSCR_FX
;
470 /* XXX: should adjust the result */
471 /* Update the floating-point enabled exception summary */
472 env
->fpscr
|= 1 << FPSCR_FEX
;
473 /* We must update the target FPR before raising the exception */
474 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
475 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
477 env
->fpscr
|= 1 << FPSCR_XX
;
478 env
->fpscr
|= 1 << FPSCR_FI
;
482 static always_inline
void float_underflow_excp (void)
484 env
->fpscr
|= 1 << FPSCR_UX
;
485 /* Update the floating-point exception summary */
486 env
->fpscr
|= 1 << FPSCR_FX
;
488 /* XXX: should adjust the result */
489 /* Update the floating-point enabled exception summary */
490 env
->fpscr
|= 1 << FPSCR_FEX
;
491 /* We must update the target FPR before raising the exception */
492 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
493 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
497 static always_inline
void float_inexact_excp (void)
499 env
->fpscr
|= 1 << FPSCR_XX
;
500 /* Update the floating-point exception summary */
501 env
->fpscr
|= 1 << FPSCR_FX
;
503 /* Update the floating-point enabled exception summary */
504 env
->fpscr
|= 1 << FPSCR_FEX
;
505 /* We must update the target FPR before raising the exception */
506 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
507 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
511 static always_inline
void fpscr_set_rounding_mode (void)
515 /* Set rounding mode */
518 /* Best approximation (round to nearest) */
519 rnd_type
= float_round_nearest_even
;
522 /* Smaller magnitude (round toward zero) */
523 rnd_type
= float_round_to_zero
;
526 /* Round toward +infinite */
527 rnd_type
= float_round_up
;
531 /* Round toward -infinite */
532 rnd_type
= float_round_down
;
535 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
538 void do_fpscr_setbit (int bit
)
542 prev
= (env
->fpscr
>> bit
) & 1;
543 env
->fpscr
|= 1 << bit
;
547 env
->fpscr
|= 1 << FPSCR_FX
;
551 env
->fpscr
|= 1 << FPSCR_FX
;
556 env
->fpscr
|= 1 << FPSCR_FX
;
561 env
->fpscr
|= 1 << FPSCR_FX
;
566 env
->fpscr
|= 1 << FPSCR_FX
;
579 env
->fpscr
|= 1 << FPSCR_VX
;
580 env
->fpscr
|= 1 << FPSCR_FX
;
587 env
->error_code
= POWERPC_EXCP_FP
;
589 env
->error_code
|= POWERPC_EXCP_FP_VXSNAN
;
591 env
->error_code
|= POWERPC_EXCP_FP_VXISI
;
593 env
->error_code
|= POWERPC_EXCP_FP_VXIDI
;
595 env
->error_code
|= POWERPC_EXCP_FP_VXZDZ
;
597 env
->error_code
|= POWERPC_EXCP_FP_VXIMZ
;
599 env
->error_code
|= POWERPC_EXCP_FP_VXVC
;
601 env
->error_code
|= POWERPC_EXCP_FP_VXSOFT
;
603 env
->error_code
|= POWERPC_EXCP_FP_VXSQRT
;
605 env
->error_code
|= POWERPC_EXCP_FP_VXCVI
;
612 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
619 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
626 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
;
633 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
639 fpscr_set_rounding_mode();
644 /* Update the floating-point enabled exception summary */
645 env
->fpscr
|= 1 << FPSCR_FEX
;
646 /* We have to update Rc1 before raising the exception */
647 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
653 #if defined(WORDS_BIGENDIAN)
660 void do_store_fpscr (uint32_t mask
)
663 * We use only the 32 LSB of the incoming fpr
673 new |= prev
& 0x90000000;
674 for (i
= 0; i
< 7; i
++) {
675 if (mask
& (1 << i
)) {
676 env
->fpscr
&= ~(0xF << (4 * i
));
677 env
->fpscr
|= new & (0xF << (4 * i
));
680 /* Update VX and FEX */
682 env
->fpscr
|= 1 << FPSCR_VX
;
684 env
->fpscr
&= ~(1 << FPSCR_VX
);
685 if ((fpscr_ex
& fpscr_eex
) != 0) {
686 env
->fpscr
|= 1 << FPSCR_FEX
;
687 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
688 /* XXX: we should compute it properly */
689 env
->error_code
= POWERPC_EXCP_FP
;
692 env
->fpscr
&= ~(1 << FPSCR_FEX
);
693 fpscr_set_rounding_mode();
698 #ifdef CONFIG_SOFTFLOAT
699 void do_float_check_status (void)
701 if (env
->exception_index
== POWERPC_EXCP_PROGRAM
&&
702 (env
->error_code
& POWERPC_EXCP_FP
)) {
703 /* Differred floating-point exception after target FPR update */
704 if (msr_fe0
!= 0 || msr_fe1
!= 0)
705 do_raise_exception_err(env
->exception_index
, env
->error_code
);
706 } else if (env
->fp_status
.float_exception_flags
& float_flag_overflow
) {
707 float_overflow_excp();
708 } else if (env
->fp_status
.float_exception_flags
& float_flag_underflow
) {
709 float_underflow_excp();
710 } else if (env
->fp_status
.float_exception_flags
& float_flag_inexact
) {
711 float_inexact_excp();
716 #if USE_PRECISE_EMULATION
719 if (unlikely(float64_is_signaling_nan(FT0
) ||
720 float64_is_signaling_nan(FT1
))) {
722 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
723 } else if (likely(isfinite(FT0
) || isfinite(FT1
) ||
724 fpisneg(FT0
) == fpisneg(FT1
))) {
725 FT0
= float64_add(FT0
, FT1
, &env
->fp_status
);
727 /* Magnitude subtraction of infinities */
728 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
734 if (unlikely(float64_is_signaling_nan(FT0
) ||
735 float64_is_signaling_nan(FT1
))) {
736 /* sNaN subtraction */
737 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
738 } else if (likely(isfinite(FT0
) || isfinite(FT1
) ||
739 fpisneg(FT0
) != fpisneg(FT1
))) {
740 FT0
= float64_sub(FT0
, FT1
, &env
->fp_status
);
742 /* Magnitude subtraction of infinities */
743 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
749 if (unlikely(float64_is_signaling_nan(FT0
) ||
750 float64_is_signaling_nan(FT1
))) {
751 /* sNaN multiplication */
752 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
753 } else if (unlikely((isinfinity(FT0
) && iszero(FT1
)) ||
754 (iszero(FT0
) && isinfinity(FT1
)))) {
755 /* Multiplication of zero by infinity */
756 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
758 FT0
= float64_mul(FT0
, FT1
, &env
->fp_status
);
764 if (unlikely(float64_is_signaling_nan(FT0
) ||
765 float64_is_signaling_nan(FT1
))) {
767 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
768 } else if (unlikely(isinfinity(FT0
) && isinfinity(FT1
))) {
769 /* Division of infinity by infinity */
770 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI
);
771 } else if (unlikely(iszero(FT1
))) {
773 /* Division of zero by zero */
774 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ
);
776 /* Division by zero */
777 float_zero_divide_excp();
780 FT0
= float64_div(FT0
, FT1
, &env
->fp_status
);
783 #endif /* USE_PRECISE_EMULATION */
789 if (unlikely(float64_is_signaling_nan(FT0
))) {
790 /* sNaN conversion */
791 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
792 } else if (unlikely(float64_is_nan(FT0
) || isinfinity(FT0
))) {
793 /* qNan / infinity conversion */
794 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
796 p
.ll
= float64_to_int32(FT0
, &env
->fp_status
);
797 #if USE_PRECISE_EMULATION
798 /* XXX: higher bits are not supposed to be significant.
799 * to make tests easier, return the same as a real PowerPC 750
801 p
.ll
|= 0xFFF80000ULL
<< 32;
807 void do_fctiwz (void)
811 if (unlikely(float64_is_signaling_nan(FT0
))) {
812 /* sNaN conversion */
813 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
814 } else if (unlikely(float64_is_nan(FT0
) || isinfinity(FT0
))) {
815 /* qNan / infinity conversion */
816 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
818 p
.ll
= float64_to_int32_round_to_zero(FT0
, &env
->fp_status
);
819 #if USE_PRECISE_EMULATION
820 /* XXX: higher bits are not supposed to be significant.
821 * to make tests easier, return the same as a real PowerPC 750
823 p
.ll
|= 0xFFF80000ULL
<< 32;
829 #if defined(TARGET_PPC64)
835 FT0
= int64_to_float64(p
.ll
, &env
->fp_status
);
842 if (unlikely(float64_is_signaling_nan(FT0
))) {
843 /* sNaN conversion */
844 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
845 } else if (unlikely(float64_is_nan(FT0
) || isinfinity(FT0
))) {
846 /* qNan / infinity conversion */
847 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
849 p
.ll
= float64_to_int64(FT0
, &env
->fp_status
);
854 void do_fctidz (void)
858 if (unlikely(float64_is_signaling_nan(FT0
))) {
859 /* sNaN conversion */
860 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
861 } else if (unlikely(float64_is_nan(FT0
) || isinfinity(FT0
))) {
862 /* qNan / infinity conversion */
863 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
865 p
.ll
= float64_to_int64_round_to_zero(FT0
, &env
->fp_status
);
872 static always_inline
void do_fri (int rounding_mode
)
874 if (unlikely(float64_is_signaling_nan(FT0
))) {
876 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
877 } else if (unlikely(float64_is_nan(FT0
) || isinfinity(FT0
))) {
878 /* qNan / infinity round */
879 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
881 set_float_rounding_mode(rounding_mode
, &env
->fp_status
);
882 FT0
= float64_round_to_int(FT0
, &env
->fp_status
);
883 /* Restore rounding mode from FPSCR */
884 fpscr_set_rounding_mode();
890 do_fri(float_round_nearest_even
);
895 do_fri(float_round_to_zero
);
900 do_fri(float_round_up
);
905 do_fri(float_round_down
);
908 #if USE_PRECISE_EMULATION
911 if (unlikely(float64_is_signaling_nan(FT0
) ||
912 float64_is_signaling_nan(FT1
) ||
913 float64_is_signaling_nan(FT2
))) {
915 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
918 /* This is the way the PowerPC specification defines it */
919 float128 ft0_128
, ft1_128
;
921 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
922 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
923 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
924 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
925 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
926 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
928 /* This is OK on x86 hosts */
929 FT0
= (FT0
* FT1
) + FT2
;
936 if (unlikely(float64_is_signaling_nan(FT0
) ||
937 float64_is_signaling_nan(FT1
) ||
938 float64_is_signaling_nan(FT2
))) {
940 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
943 /* This is the way the PowerPC specification defines it */
944 float128 ft0_128
, ft1_128
;
946 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
947 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
948 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
949 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
950 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
951 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
953 /* This is OK on x86 hosts */
954 FT0
= (FT0
* FT1
) - FT2
;
958 #endif /* USE_PRECISE_EMULATION */
960 void do_fnmadd (void)
962 if (unlikely(float64_is_signaling_nan(FT0
) ||
963 float64_is_signaling_nan(FT1
) ||
964 float64_is_signaling_nan(FT2
))) {
966 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
968 #if USE_PRECISE_EMULATION
970 /* This is the way the PowerPC specification defines it */
971 float128 ft0_128
, ft1_128
;
973 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
974 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
975 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
976 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
977 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
978 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
980 /* This is OK on x86 hosts */
981 FT0
= (FT0
* FT1
) + FT2
;
984 FT0
= float64_mul(FT0
, FT1
, &env
->fp_status
);
985 FT0
= float64_add(FT0
, FT2
, &env
->fp_status
);
987 if (likely(!isnan(FT0
)))
988 FT0
= float64_chs(FT0
);
992 void do_fnmsub (void)
994 if (unlikely(float64_is_signaling_nan(FT0
) ||
995 float64_is_signaling_nan(FT1
) ||
996 float64_is_signaling_nan(FT2
))) {
998 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1000 #if USE_PRECISE_EMULATION
1002 /* This is the way the PowerPC specification defines it */
1003 float128 ft0_128
, ft1_128
;
1005 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
1006 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
1007 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1008 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
1009 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
1010 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
1012 /* This is OK on x86 hosts */
1013 FT0
= (FT0
* FT1
) - FT2
;
1016 FT0
= float64_mul(FT0
, FT1
, &env
->fp_status
);
1017 FT0
= float64_sub(FT0
, FT2
, &env
->fp_status
);
1019 if (likely(!isnan(FT0
)))
1020 FT0
= float64_chs(FT0
);
1024 #if USE_PRECISE_EMULATION
1027 if (unlikely(float64_is_signaling_nan(FT0
))) {
1028 /* sNaN square root */
1029 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1031 FT0
= float64_to_float32(FT0
, &env
->fp_status
);
1034 #endif /* USE_PRECISE_EMULATION */
1036 void do_fsqrt (void)
1038 if (unlikely(float64_is_signaling_nan(FT0
))) {
1039 /* sNaN square root */
1040 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1041 } else if (unlikely(fpisneg(FT0
) && !iszero(FT0
))) {
1042 /* Square root of a negative nonzero number */
1043 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT
);
1045 FT0
= float64_sqrt(FT0
, &env
->fp_status
);
1053 if (unlikely(float64_is_signaling_nan(FT0
))) {
1054 /* sNaN reciprocal */
1055 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1056 } else if (unlikely(iszero(FT0
))) {
1057 /* Zero reciprocal */
1058 float_zero_divide_excp();
1059 } else if (likely(isnormal(FT0
))) {
1060 FT0
= float64_div(1.0, FT0
, &env
->fp_status
);
1063 if (p
.ll
== 0x8000000000000000ULL
) {
1064 p
.ll
= 0xFFF0000000000000ULL
;
1065 } else if (p
.ll
== 0x0000000000000000ULL
) {
1066 p
.ll
= 0x7FF0000000000000ULL
;
1067 } else if (isnan(FT0
)) {
1068 p
.ll
= 0x7FF8000000000000ULL
;
1069 } else if (fpisneg(FT0
)) {
1070 p
.ll
= 0x8000000000000000ULL
;
1072 p
.ll
= 0x0000000000000000ULL
;
1082 if (unlikely(float64_is_signaling_nan(FT0
))) {
1083 /* sNaN reciprocal */
1084 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1085 } else if (unlikely(iszero(FT0
))) {
1086 /* Zero reciprocal */
1087 float_zero_divide_excp();
1088 } else if (likely(isnormal(FT0
))) {
1089 #if USE_PRECISE_EMULATION
1090 FT0
= float64_div(1.0, FT0
, &env
->fp_status
);
1091 FT0
= float64_to_float32(FT0
, &env
->fp_status
);
1093 FT0
= float32_div(1.0, FT0
, &env
->fp_status
);
1097 if (p
.ll
== 0x8000000000000000ULL
) {
1098 p
.ll
= 0xFFF0000000000000ULL
;
1099 } else if (p
.ll
== 0x0000000000000000ULL
) {
1100 p
.ll
= 0x7FF0000000000000ULL
;
1101 } else if (isnan(FT0
)) {
1102 p
.ll
= 0x7FF8000000000000ULL
;
1103 } else if (fpisneg(FT0
)) {
1104 p
.ll
= 0x8000000000000000ULL
;
1106 p
.ll
= 0x0000000000000000ULL
;
1112 void do_frsqrte (void)
1116 if (unlikely(float64_is_signaling_nan(FT0
))) {
1117 /* sNaN reciprocal square root */
1118 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1119 } else if (unlikely(fpisneg(FT0
) && !iszero(FT0
))) {
1120 /* Reciprocal square root of a negative nonzero number */
1121 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT
);
1122 } else if (likely(isnormal(FT0
))) {
1123 FT0
= float64_sqrt(FT0
, &env
->fp_status
);
1124 FT0
= float32_div(1.0, FT0
, &env
->fp_status
);
1127 if (p
.ll
== 0x8000000000000000ULL
) {
1128 p
.ll
= 0xFFF0000000000000ULL
;
1129 } else if (p
.ll
== 0x0000000000000000ULL
) {
1130 p
.ll
= 0x7FF0000000000000ULL
;
1131 } else if (isnan(FT0
)) {
1132 p
.ll
|= 0x000FFFFFFFFFFFFFULL
;
1133 } else if (fpisneg(FT0
)) {
1134 p
.ll
= 0x7FF8000000000000ULL
;
1136 p
.ll
= 0x0000000000000000ULL
;
1144 if (!fpisneg(FT0
) || iszero(FT0
))
1150 uint32_t helper_fcmpu (void)
1154 if (unlikely(float64_is_signaling_nan(FT0
) ||
1155 float64_is_signaling_nan(FT1
))) {
1156 /* sNaN comparison */
1157 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1159 if (float64_lt(FT0
, FT1
, &env
->fp_status
)) {
1161 } else if (!float64_le(FT0
, FT1
, &env
->fp_status
)) {
1167 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1168 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1172 uint32_t helper_fcmpo (void)
1176 if (unlikely(float64_is_nan(FT0
) ||
1177 float64_is_nan(FT1
))) {
1178 if (float64_is_signaling_nan(FT0
) ||
1179 float64_is_signaling_nan(FT1
)) {
1180 /* sNaN comparison */
1181 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
|
1182 POWERPC_EXCP_FP_VXVC
);
1184 /* qNaN comparison */
1185 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC
);
1188 if (float64_lt(FT0
, FT1
, &env
->fp_status
)) {
1190 } else if (!float64_le(FT0
, FT1
, &env
->fp_status
)) {
1196 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1197 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1201 #if !defined (CONFIG_USER_ONLY)
1202 void cpu_dump_rfi (target_ulong RA
, target_ulong msr
);
1204 void do_store_msr (void)
1206 T0
= hreg_store_msr(env
, T0
, 0);
1208 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1209 do_raise_exception(T0
);
1213 static always_inline
void __do_rfi (target_ulong nip
, target_ulong msr
,
1214 target_ulong msrm
, int keep_msrh
)
1216 #if defined(TARGET_PPC64)
1217 if (msr
& (1ULL << MSR_SF
)) {
1218 nip
= (uint64_t)nip
;
1219 msr
&= (uint64_t)msrm
;
1221 nip
= (uint32_t)nip
;
1222 msr
= (uint32_t)(msr
& msrm
);
1224 msr
|= env
->msr
& ~((uint64_t)0xFFFFFFFF);
1227 nip
= (uint32_t)nip
;
1228 msr
&= (uint32_t)msrm
;
1230 /* XXX: beware: this is false if VLE is supported */
1231 env
->nip
= nip
& ~((target_ulong
)0x00000003);
1232 hreg_store_msr(env
, msr
, 1);
1233 #if defined (DEBUG_OP)
1234 cpu_dump_rfi(env
->nip
, env
->msr
);
1236 /* No need to raise an exception here,
1237 * as rfi is always the last insn of a TB
1239 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1244 __do_rfi(env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
1245 ~((target_ulong
)0xFFFF0000), 1);
1248 #if defined(TARGET_PPC64)
1251 __do_rfi(env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
1252 ~((target_ulong
)0xFFFF0000), 0);
1255 void do_hrfid (void)
1257 __do_rfi(env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
],
1258 ~((target_ulong
)0xFFFF0000), 0);
1263 void do_tw (int flags
)
1265 if (!likely(!(((int32_t)T0
< (int32_t)T1
&& (flags
& 0x10)) ||
1266 ((int32_t)T0
> (int32_t)T1
&& (flags
& 0x08)) ||
1267 ((int32_t)T0
== (int32_t)T1
&& (flags
& 0x04)) ||
1268 ((uint32_t)T0
< (uint32_t)T1
&& (flags
& 0x02)) ||
1269 ((uint32_t)T0
> (uint32_t)T1
&& (flags
& 0x01))))) {
1270 do_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1274 #if defined(TARGET_PPC64)
1275 void do_td (int flags
)
1277 if (!likely(!(((int64_t)T0
< (int64_t)T1
&& (flags
& 0x10)) ||
1278 ((int64_t)T0
> (int64_t)T1
&& (flags
& 0x08)) ||
1279 ((int64_t)T0
== (int64_t)T1
&& (flags
& 0x04)) ||
1280 ((uint64_t)T0
< (uint64_t)T1
&& (flags
& 0x02)) ||
1281 ((uint64_t)T0
> (uint64_t)T1
&& (flags
& 0x01)))))
1282 do_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1286 /*****************************************************************************/
1287 /* PowerPC 601 specific instructions (POWER bridge) */
1288 void do_POWER_abso (void)
1290 if ((int32_t)T0
== INT32_MIN
) {
1292 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1293 } else if ((int32_t)T0
< 0) {
1295 env
->xer
&= ~(1 << XER_OV
);
1297 env
->xer
&= ~(1 << XER_OV
);
1301 void do_POWER_clcs (void)
1305 /* Instruction cache line size */
1306 T0
= env
->icache_line_size
;
1309 /* Data cache line size */
1310 T0
= env
->dcache_line_size
;
1313 /* Minimum cache line size */
1314 T0
= env
->icache_line_size
< env
->dcache_line_size
?
1315 env
->icache_line_size
: env
->dcache_line_size
;
1318 /* Maximum cache line size */
1319 T0
= env
->icache_line_size
> env
->dcache_line_size
?
1320 env
->icache_line_size
: env
->dcache_line_size
;
1328 void do_POWER_div (void)
1332 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== (int32_t)-1) ||
1334 T0
= UINT32_MAX
* ((uint32_t)T0
>> 31);
1335 env
->spr
[SPR_MQ
] = 0;
1337 tmp
= ((uint64_t)T0
<< 32) | env
->spr
[SPR_MQ
];
1338 env
->spr
[SPR_MQ
] = tmp
% T1
;
1339 T0
= tmp
/ (int32_t)T1
;
1343 void do_POWER_divo (void)
1347 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== (int32_t)-1) ||
1349 T0
= UINT32_MAX
* ((uint32_t)T0
>> 31);
1350 env
->spr
[SPR_MQ
] = 0;
1351 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1353 tmp
= ((uint64_t)T0
<< 32) | env
->spr
[SPR_MQ
];
1354 env
->spr
[SPR_MQ
] = tmp
% T1
;
1356 if (tmp
> (int64_t)INT32_MAX
|| tmp
< (int64_t)INT32_MIN
) {
1357 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1359 env
->xer
&= ~(1 << XER_OV
);
1365 void do_POWER_divs (void)
1367 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== (int32_t)-1) ||
1369 T0
= UINT32_MAX
* ((uint32_t)T0
>> 31);
1370 env
->spr
[SPR_MQ
] = 0;
1372 env
->spr
[SPR_MQ
] = T0
% T1
;
1373 T0
= (int32_t)T0
/ (int32_t)T1
;
1377 void do_POWER_divso (void)
1379 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== (int32_t)-1) ||
1381 T0
= UINT32_MAX
* ((uint32_t)T0
>> 31);
1382 env
->spr
[SPR_MQ
] = 0;
1383 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1385 T0
= (int32_t)T0
/ (int32_t)T1
;
1386 env
->spr
[SPR_MQ
] = (int32_t)T0
% (int32_t)T1
;
1387 env
->xer
&= ~(1 << XER_OV
);
1391 void do_POWER_dozo (void)
1393 if ((int32_t)T1
> (int32_t)T0
) {
1396 if (((uint32_t)(~T2
) ^ (uint32_t)T1
^ UINT32_MAX
) &
1397 ((uint32_t)(~T2
) ^ (uint32_t)T0
) & (1UL << 31)) {
1398 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1400 env
->xer
&= ~(1 << XER_OV
);
1404 env
->xer
&= ~(1 << XER_OV
);
1408 void do_POWER_maskg (void)
1412 if ((uint32_t)T0
== (uint32_t)(T1
+ 1)) {
1415 ret
= (UINT32_MAX
>> ((uint32_t)T0
)) ^
1416 ((UINT32_MAX
>> ((uint32_t)T1
)) >> 1);
1417 if ((uint32_t)T0
> (uint32_t)T1
)
1423 void do_POWER_mulo (void)
1427 tmp
= (uint64_t)T0
* (uint64_t)T1
;
1428 env
->spr
[SPR_MQ
] = tmp
>> 32;
1430 if (tmp
>> 32 != ((uint64_t)T0
>> 16) * ((uint64_t)T1
>> 16)) {
1431 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1433 env
->xer
&= ~(1 << XER_OV
);
1437 #if !defined (CONFIG_USER_ONLY)
1438 void do_POWER_rac (void)
1443 /* We don't have to generate many instances of this instruction,
1444 * as rac is supervisor only.
1446 /* XXX: FIX THIS: Pretend we have no BAT */
1447 nb_BATs
= env
->nb_BATs
;
1449 if (get_physical_address(env
, &ctx
, T0
, 0, ACCESS_INT
) == 0)
1451 env
->nb_BATs
= nb_BATs
;
1454 void do_POWER_rfsvc (void)
1456 __do_rfi(env
->lr
, env
->ctr
, 0x0000FFFF, 0);
1459 void do_store_hid0_601 (void)
1463 hid0
= env
->spr
[SPR_HID0
];
1464 if ((T0
^ hid0
) & 0x00000008) {
1465 /* Change current endianness */
1466 env
->hflags
&= ~(1 << MSR_LE
);
1467 env
->hflags_nmsr
&= ~(1 << MSR_LE
);
1468 env
->hflags_nmsr
|= (1 << MSR_LE
) & (((T0
>> 3) & 1) << MSR_LE
);
1469 env
->hflags
|= env
->hflags_nmsr
;
1470 if (loglevel
!= 0) {
1471 fprintf(logfile
, "%s: set endianness to %c => " ADDRX
"\n",
1472 __func__
, T0
& 0x8 ? 'l' : 'b', env
->hflags
);
1475 env
->spr
[SPR_HID0
] = T0
;
1479 /*****************************************************************************/
1480 /* 602 specific instructions */
1481 /* mfrom is the most crazy instruction ever seen, imho ! */
1482 /* Real implementation uses a ROM table. Do the same */
1483 #define USE_MFROM_ROM_TABLE
1484 void do_op_602_mfrom (void)
1486 if (likely(T0
< 602)) {
1487 #if defined(USE_MFROM_ROM_TABLE)
1488 #include "mfrom_table.c"
1489 T0
= mfrom_ROM_table
[T0
];
1492 /* Extremly decomposed:
1494 * T0 = 256 * log10(10 + 1.0) + 0.5
1497 d
= float64_div(d
, 256, &env
->fp_status
);
1499 d
= exp10(d
); // XXX: use float emulation function
1500 d
= float64_add(d
, 1.0, &env
->fp_status
);
1501 d
= log10(d
); // XXX: use float emulation function
1502 d
= float64_mul(d
, 256, &env
->fp_status
);
1503 d
= float64_add(d
, 0.5, &env
->fp_status
);
1504 T0
= float64_round_to_int(d
, &env
->fp_status
);
1511 /*****************************************************************************/
1512 /* Embedded PowerPC specific helpers */
1514 /* XXX: to be improved to check access rights when in user-mode */
1515 void do_load_dcr (void)
1519 if (unlikely(env
->dcr_env
== NULL
)) {
1520 if (loglevel
!= 0) {
1521 fprintf(logfile
, "No DCR environment\n");
1523 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1524 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1525 } else if (unlikely(ppc_dcr_read(env
->dcr_env
, T0
, &val
) != 0)) {
1526 if (loglevel
!= 0) {
1527 fprintf(logfile
, "DCR read error %d %03x\n", (int)T0
, (int)T0
);
1529 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1530 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1536 void do_store_dcr (void)
1538 if (unlikely(env
->dcr_env
== NULL
)) {
1539 if (loglevel
!= 0) {
1540 fprintf(logfile
, "No DCR environment\n");
1542 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1543 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1544 } else if (unlikely(ppc_dcr_write(env
->dcr_env
, T0
, T1
) != 0)) {
1545 if (loglevel
!= 0) {
1546 fprintf(logfile
, "DCR write error %d %03x\n", (int)T0
, (int)T0
);
1548 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1549 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1553 #if !defined(CONFIG_USER_ONLY)
1554 void do_40x_rfci (void)
1556 __do_rfi(env
->spr
[SPR_40x_SRR2
], env
->spr
[SPR_40x_SRR3
],
1557 ~((target_ulong
)0xFFFF0000), 0);
1562 __do_rfi(env
->spr
[SPR_BOOKE_CSRR0
], SPR_BOOKE_CSRR1
,
1563 ~((target_ulong
)0x3FFF0000), 0);
1568 __do_rfi(env
->spr
[SPR_BOOKE_DSRR0
], SPR_BOOKE_DSRR1
,
1569 ~((target_ulong
)0x3FFF0000), 0);
1572 void do_rfmci (void)
1574 __do_rfi(env
->spr
[SPR_BOOKE_MCSRR0
], SPR_BOOKE_MCSRR1
,
1575 ~((target_ulong
)0x3FFF0000), 0);
1578 void do_load_403_pb (int num
)
1583 void do_store_403_pb (int num
)
1585 if (likely(env
->pb
[num
] != T0
)) {
1587 /* Should be optimized */
1594 void do_440_dlmzb (void)
1600 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1601 if ((T0
& mask
) == 0)
1605 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1606 if ((T1
& mask
) == 0)
1614 /* SPE extension helpers */
1615 /* Use a table to make this quicker */
1616 static uint8_t hbrev
[16] = {
1617 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1618 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1621 static always_inline
uint8_t byte_reverse (uint8_t val
)
1623 return hbrev
[val
>> 4] | (hbrev
[val
& 0xF] << 4);
1626 static always_inline
uint32_t word_reverse (uint32_t val
)
1628 return byte_reverse(val
>> 24) | (byte_reverse(val
>> 16) << 8) |
1629 (byte_reverse(val
>> 8) << 16) | (byte_reverse(val
) << 24);
1632 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1633 void do_brinc (void)
1635 uint32_t a
, b
, d
, mask
;
1637 mask
= UINT32_MAX
>> (32 - MASKBITS
);
1640 d
= word_reverse(1 + word_reverse(a
| ~b
));
1641 T0
= (T0
& ~mask
) | (d
& b
);
1644 #define DO_SPE_OP2(name) \
1645 void do_ev##name (void) \
1647 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1648 (uint64_t)_do_e##name(T0_64, T1_64); \
1651 #define DO_SPE_OP1(name) \
1652 void do_ev##name (void) \
1654 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1655 (uint64_t)_do_e##name(T0_64); \
1658 /* Fixed-point vector arithmetic */
1659 static always_inline
uint32_t _do_eabs (uint32_t val
)
1661 if ((val
& 0x80000000) && val
!= 0x80000000)
1667 static always_inline
uint32_t _do_eaddw (uint32_t op1
, uint32_t op2
)
1672 static always_inline
int _do_ecntlsw (uint32_t val
)
1674 if (val
& 0x80000000)
1680 static always_inline
int _do_ecntlzw (uint32_t val
)
1685 static always_inline
uint32_t _do_eneg (uint32_t val
)
1687 if (val
!= 0x80000000)
1693 static always_inline
uint32_t _do_erlw (uint32_t op1
, uint32_t op2
)
1695 return rotl32(op1
, op2
);
1698 static always_inline
uint32_t _do_erndw (uint32_t val
)
1700 return (val
+ 0x000080000000) & 0xFFFF0000;
1703 static always_inline
uint32_t _do_eslw (uint32_t op1
, uint32_t op2
)
1705 /* No error here: 6 bits are used */
1706 return op1
<< (op2
& 0x3F);
1709 static always_inline
int32_t _do_esrws (int32_t op1
, uint32_t op2
)
1711 /* No error here: 6 bits are used */
1712 return op1
>> (op2
& 0x3F);
1715 static always_inline
uint32_t _do_esrwu (uint32_t op1
, uint32_t op2
)
1717 /* No error here: 6 bits are used */
1718 return op1
>> (op2
& 0x3F);
1721 static always_inline
uint32_t _do_esubfw (uint32_t op1
, uint32_t op2
)
1749 /* evsel is a little bit more complicated... */
1750 static always_inline
uint32_t _do_esel (uint32_t op1
, uint32_t op2
, int n
)
1758 void do_evsel (void)
1760 T0_64
= ((uint64_t)_do_esel(T0_64
>> 32, T1_64
>> 32, T0
>> 3) << 32) |
1761 (uint64_t)_do_esel(T0_64
, T1_64
, (T0
>> 2) & 1);
1764 /* Fixed-point vector comparisons */
1765 #define DO_SPE_CMP(name) \
1766 void do_ev##name (void) \
1768 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1769 T1_64 >> 32) << 32, \
1770 _do_e##name(T0_64, T1_64)); \
1773 static always_inline
uint32_t _do_evcmp_merge (int t0
, int t1
)
1775 return (t0
<< 3) | (t1
<< 2) | ((t0
| t1
) << 1) | (t0
& t1
);
1777 static always_inline
int _do_ecmpeq (uint32_t op1
, uint32_t op2
)
1779 return op1
== op2
? 1 : 0;
1782 static always_inline
int _do_ecmpgts (int32_t op1
, int32_t op2
)
1784 return op1
> op2
? 1 : 0;
1787 static always_inline
int _do_ecmpgtu (uint32_t op1
, uint32_t op2
)
1789 return op1
> op2
? 1 : 0;
1792 static always_inline
int _do_ecmplts (int32_t op1
, int32_t op2
)
1794 return op1
< op2
? 1 : 0;
1797 static always_inline
int _do_ecmpltu (uint32_t op1
, uint32_t op2
)
1799 return op1
< op2
? 1 : 0;
1813 /* Single precision floating-point conversions from/to integer */
1814 static always_inline
uint32_t _do_efscfsi (int32_t val
)
1818 u
.f
= int32_to_float32(val
, &env
->spe_status
);
1823 static always_inline
uint32_t _do_efscfui (uint32_t val
)
1827 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
1832 static always_inline
int32_t _do_efsctsi (uint32_t val
)
1837 /* NaN are not treated the same way IEEE 754 does */
1838 if (unlikely(isnan(u
.f
)))
1841 return float32_to_int32(u
.f
, &env
->spe_status
);
1844 static always_inline
uint32_t _do_efsctui (uint32_t val
)
1849 /* NaN are not treated the same way IEEE 754 does */
1850 if (unlikely(isnan(u
.f
)))
1853 return float32_to_uint32(u
.f
, &env
->spe_status
);
1856 static always_inline
int32_t _do_efsctsiz (uint32_t val
)
1861 /* NaN are not treated the same way IEEE 754 does */
1862 if (unlikely(isnan(u
.f
)))
1865 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
1868 static always_inline
uint32_t _do_efsctuiz (uint32_t val
)
1873 /* NaN are not treated the same way IEEE 754 does */
1874 if (unlikely(isnan(u
.f
)))
1877 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
1880 void do_efscfsi (void)
1882 T0_64
= _do_efscfsi(T0_64
);
1885 void do_efscfui (void)
1887 T0_64
= _do_efscfui(T0_64
);
1890 void do_efsctsi (void)
1892 T0_64
= _do_efsctsi(T0_64
);
1895 void do_efsctui (void)
1897 T0_64
= _do_efsctui(T0_64
);
1900 void do_efsctsiz (void)
1902 T0_64
= _do_efsctsiz(T0_64
);
1905 void do_efsctuiz (void)
1907 T0_64
= _do_efsctuiz(T0_64
);
1910 /* Single precision floating-point conversion to/from fractional */
1911 static always_inline
uint32_t _do_efscfsf (uint32_t val
)
1916 u
.f
= int32_to_float32(val
, &env
->spe_status
);
1917 tmp
= int64_to_float32(1ULL << 32, &env
->spe_status
);
1918 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
1923 static always_inline
uint32_t _do_efscfuf (uint32_t val
)
1928 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
1929 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1930 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
1935 static always_inline
int32_t _do_efsctsf (uint32_t val
)
1941 /* NaN are not treated the same way IEEE 754 does */
1942 if (unlikely(isnan(u
.f
)))
1944 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1945 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1947 return float32_to_int32(u
.f
, &env
->spe_status
);
1950 static always_inline
uint32_t _do_efsctuf (uint32_t val
)
1956 /* NaN are not treated the same way IEEE 754 does */
1957 if (unlikely(isnan(u
.f
)))
1959 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1960 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1962 return float32_to_uint32(u
.f
, &env
->spe_status
);
1965 static always_inline
int32_t _do_efsctsfz (uint32_t val
)
1971 /* NaN are not treated the same way IEEE 754 does */
1972 if (unlikely(isnan(u
.f
)))
1974 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1975 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1977 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
1980 static always_inline
uint32_t _do_efsctufz (uint32_t val
)
1986 /* NaN are not treated the same way IEEE 754 does */
1987 if (unlikely(isnan(u
.f
)))
1989 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1990 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1992 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
1995 void do_efscfsf (void)
1997 T0_64
= _do_efscfsf(T0_64
);
2000 void do_efscfuf (void)
2002 T0_64
= _do_efscfuf(T0_64
);
2005 void do_efsctsf (void)
2007 T0_64
= _do_efsctsf(T0_64
);
2010 void do_efsctuf (void)
2012 T0_64
= _do_efsctuf(T0_64
);
2015 void do_efsctsfz (void)
2017 T0_64
= _do_efsctsfz(T0_64
);
2020 void do_efsctufz (void)
2022 T0_64
= _do_efsctufz(T0_64
);
2025 /* Double precision floating point helpers */
2026 static always_inline
int _do_efdcmplt (uint64_t op1
, uint64_t op2
)
2028 /* XXX: TODO: test special values (NaN, infinites, ...) */
2029 return _do_efdtstlt(op1
, op2
);
2032 static always_inline
int _do_efdcmpgt (uint64_t op1
, uint64_t op2
)
2034 /* XXX: TODO: test special values (NaN, infinites, ...) */
2035 return _do_efdtstgt(op1
, op2
);
2038 static always_inline
int _do_efdcmpeq (uint64_t op1
, uint64_t op2
)
2040 /* XXX: TODO: test special values (NaN, infinites, ...) */
2041 return _do_efdtsteq(op1
, op2
);
2044 void do_efdcmplt (void)
2046 T0
= _do_efdcmplt(T0_64
, T1_64
);
2049 void do_efdcmpgt (void)
2051 T0
= _do_efdcmpgt(T0_64
, T1_64
);
2054 void do_efdcmpeq (void)
2056 T0
= _do_efdcmpeq(T0_64
, T1_64
);
2059 /* Double precision floating-point conversion to/from integer */
2060 static always_inline
uint64_t _do_efdcfsi (int64_t val
)
2064 u
.d
= int64_to_float64(val
, &env
->spe_status
);
2069 static always_inline
uint64_t _do_efdcfui (uint64_t val
)
2073 u
.d
= uint64_to_float64(val
, &env
->spe_status
);
2078 static always_inline
int64_t _do_efdctsi (uint64_t val
)
2083 /* NaN are not treated the same way IEEE 754 does */
2084 if (unlikely(isnan(u
.d
)))
2087 return float64_to_int64(u
.d
, &env
->spe_status
);
2090 static always_inline
uint64_t _do_efdctui (uint64_t val
)
2095 /* NaN are not treated the same way IEEE 754 does */
2096 if (unlikely(isnan(u
.d
)))
2099 return float64_to_uint64(u
.d
, &env
->spe_status
);
2102 static always_inline
int64_t _do_efdctsiz (uint64_t val
)
2107 /* NaN are not treated the same way IEEE 754 does */
2108 if (unlikely(isnan(u
.d
)))
2111 return float64_to_int64_round_to_zero(u
.d
, &env
->spe_status
);
2114 static always_inline
uint64_t _do_efdctuiz (uint64_t val
)
2119 /* NaN are not treated the same way IEEE 754 does */
2120 if (unlikely(isnan(u
.d
)))
2123 return float64_to_uint64_round_to_zero(u
.d
, &env
->spe_status
);
2126 void do_efdcfsi (void)
2128 T0_64
= _do_efdcfsi(T0_64
);
2131 void do_efdcfui (void)
2133 T0_64
= _do_efdcfui(T0_64
);
2136 void do_efdctsi (void)
2138 T0_64
= _do_efdctsi(T0_64
);
2141 void do_efdctui (void)
2143 T0_64
= _do_efdctui(T0_64
);
2146 void do_efdctsiz (void)
2148 T0_64
= _do_efdctsiz(T0_64
);
2151 void do_efdctuiz (void)
2153 T0_64
= _do_efdctuiz(T0_64
);
2156 /* Double precision floating-point conversion to/from fractional */
2157 static always_inline
uint64_t _do_efdcfsf (int64_t val
)
2162 u
.d
= int32_to_float64(val
, &env
->spe_status
);
2163 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2164 u
.d
= float64_div(u
.d
, tmp
, &env
->spe_status
);
2169 static always_inline
uint64_t _do_efdcfuf (uint64_t val
)
2174 u
.d
= uint32_to_float64(val
, &env
->spe_status
);
2175 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2176 u
.d
= float64_div(u
.d
, tmp
, &env
->spe_status
);
2181 static always_inline
int64_t _do_efdctsf (uint64_t val
)
2187 /* NaN are not treated the same way IEEE 754 does */
2188 if (unlikely(isnan(u
.d
)))
2190 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2191 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2193 return float64_to_int32(u
.d
, &env
->spe_status
);
2196 static always_inline
uint64_t _do_efdctuf (uint64_t val
)
2202 /* NaN are not treated the same way IEEE 754 does */
2203 if (unlikely(isnan(u
.d
)))
2205 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2206 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2208 return float64_to_uint32(u
.d
, &env
->spe_status
);
2211 static always_inline
int64_t _do_efdctsfz (uint64_t val
)
2217 /* NaN are not treated the same way IEEE 754 does */
2218 if (unlikely(isnan(u
.d
)))
2220 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2221 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2223 return float64_to_int32_round_to_zero(u
.d
, &env
->spe_status
);
2226 static always_inline
uint64_t _do_efdctufz (uint64_t val
)
2232 /* NaN are not treated the same way IEEE 754 does */
2233 if (unlikely(isnan(u
.d
)))
2235 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2236 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2238 return float64_to_uint32_round_to_zero(u
.d
, &env
->spe_status
);
2241 void do_efdcfsf (void)
2243 T0_64
= _do_efdcfsf(T0_64
);
2246 void do_efdcfuf (void)
2248 T0_64
= _do_efdcfuf(T0_64
);
2251 void do_efdctsf (void)
2253 T0_64
= _do_efdctsf(T0_64
);
2256 void do_efdctuf (void)
2258 T0_64
= _do_efdctuf(T0_64
);
2261 void do_efdctsfz (void)
2263 T0_64
= _do_efdctsfz(T0_64
);
2266 void do_efdctufz (void)
2268 T0_64
= _do_efdctufz(T0_64
);
2271 /* Floating point conversion between single and double precision */
2272 static always_inline
uint32_t _do_efscfd (uint64_t val
)
2278 u2
.f
= float64_to_float32(u1
.d
, &env
->spe_status
);
2283 static always_inline
uint64_t _do_efdcfs (uint32_t val
)
2289 u2
.d
= float32_to_float64(u1
.f
, &env
->spe_status
);
2294 void do_efscfd (void)
2296 T0_64
= _do_efscfd(T0_64
);
2299 void do_efdcfs (void)
2301 T0_64
= _do_efdcfs(T0_64
);
2304 /* Single precision fixed-point vector arithmetic */
2320 /* Single-precision floating-point comparisons */
2321 static always_inline
int _do_efscmplt (uint32_t op1
, uint32_t op2
)
2323 /* XXX: TODO: test special values (NaN, infinites, ...) */
2324 return _do_efststlt(op1
, op2
);
2327 static always_inline
int _do_efscmpgt (uint32_t op1
, uint32_t op2
)
2329 /* XXX: TODO: test special values (NaN, infinites, ...) */
2330 return _do_efststgt(op1
, op2
);
2333 static always_inline
int _do_efscmpeq (uint32_t op1
, uint32_t op2
)
2335 /* XXX: TODO: test special values (NaN, infinites, ...) */
2336 return _do_efststeq(op1
, op2
);
2339 void do_efscmplt (void)
2341 T0
= _do_efscmplt(T0_64
, T1_64
);
2344 void do_efscmpgt (void)
2346 T0
= _do_efscmpgt(T0_64
, T1_64
);
2349 void do_efscmpeq (void)
2351 T0
= _do_efscmpeq(T0_64
, T1_64
);
2354 /* Single-precision floating-point vector comparisons */
2356 DO_SPE_CMP(fscmplt
);
2358 DO_SPE_CMP(fscmpgt
);
2360 DO_SPE_CMP(fscmpeq
);
2362 DO_SPE_CMP(fststlt
);
2364 DO_SPE_CMP(fststgt
);
2366 DO_SPE_CMP(fststeq
);
2368 /* Single-precision floating-point vector conversions */
2382 DO_SPE_OP1(fsctsiz
);
2384 DO_SPE_OP1(fsctuiz
);
2390 /*****************************************************************************/
2391 /* Softmmu support */
2392 #if !defined (CONFIG_USER_ONLY)
2394 #define MMUSUFFIX _mmu
2397 #include "softmmu_template.h"
2400 #include "softmmu_template.h"
2403 #include "softmmu_template.h"
2406 #include "softmmu_template.h"
2408 /* try to fill the TLB and return an exception if error. If retaddr is
2409 NULL, it means that the function was called in C code (i.e. not
2410 from generated code or from helper.c) */
2411 /* XXX: fix it to restore all registers */
2412 void tlb_fill (target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
2414 TranslationBlock
*tb
;
2415 CPUState
*saved_env
;
2419 /* XXX: hack to restore env in all cases, even if not called from
2422 env
= cpu_single_env
;
2423 ret
= cpu_ppc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
2424 if (unlikely(ret
!= 0)) {
2425 if (likely(retaddr
)) {
2426 /* now we have a real cpu fault */
2427 pc
= (unsigned long)retaddr
;
2428 tb
= tb_find_pc(pc
);
2430 /* the PC is inside the translated code. It means that we have
2431 a virtual CPU fault */
2432 cpu_restore_state(tb
, env
, pc
, NULL
);
2435 do_raise_exception_err(env
->exception_index
, env
->error_code
);
2440 /* Software driven TLBs management */
2441 /* PowerPC 602/603 software TLB load instructions helpers */
2442 void do_load_6xx_tlb (int is_code
)
2444 target_ulong RPN
, CMP
, EPN
;
2447 RPN
= env
->spr
[SPR_RPA
];
2449 CMP
= env
->spr
[SPR_ICMP
];
2450 EPN
= env
->spr
[SPR_IMISS
];
2452 CMP
= env
->spr
[SPR_DCMP
];
2453 EPN
= env
->spr
[SPR_DMISS
];
2455 way
= (env
->spr
[SPR_SRR1
] >> 17) & 1;
2456 #if defined (DEBUG_SOFTWARE_TLB)
2457 if (loglevel
!= 0) {
2458 fprintf(logfile
, "%s: EPN " TDX
" " ADDRX
" PTE0 " ADDRX
2459 " PTE1 " ADDRX
" way %d\n",
2460 __func__
, T0
, EPN
, CMP
, RPN
, way
);
2463 /* Store this TLB */
2464 ppc6xx_tlb_store(env
, (uint32_t)(T0
& TARGET_PAGE_MASK
),
2465 way
, is_code
, CMP
, RPN
);
2468 void do_load_74xx_tlb (int is_code
)
2470 target_ulong RPN
, CMP
, EPN
;
2473 RPN
= env
->spr
[SPR_PTELO
];
2474 CMP
= env
->spr
[SPR_PTEHI
];
2475 EPN
= env
->spr
[SPR_TLBMISS
] & ~0x3;
2476 way
= env
->spr
[SPR_TLBMISS
] & 0x3;
2477 #if defined (DEBUG_SOFTWARE_TLB)
2478 if (loglevel
!= 0) {
2479 fprintf(logfile
, "%s: EPN " TDX
" " ADDRX
" PTE0 " ADDRX
2480 " PTE1 " ADDRX
" way %d\n",
2481 __func__
, T0
, EPN
, CMP
, RPN
, way
);
2484 /* Store this TLB */
2485 ppc6xx_tlb_store(env
, (uint32_t)(T0
& TARGET_PAGE_MASK
),
2486 way
, is_code
, CMP
, RPN
);
2489 static always_inline target_ulong
booke_tlb_to_page_size (int size
)
2491 return 1024 << (2 * size
);
2494 static always_inline
int booke_page_size_to_tlb (target_ulong page_size
)
2498 switch (page_size
) {
2532 #if defined (TARGET_PPC64)
2533 case 0x000100000000ULL
:
2536 case 0x000400000000ULL
:
2539 case 0x001000000000ULL
:
2542 case 0x004000000000ULL
:
2545 case 0x010000000000ULL
:
2557 /* Helpers for 4xx TLB management */
2558 void do_4xx_tlbre_lo (void)
2564 tlb
= &env
->tlb
[T0
].tlbe
;
2566 if (tlb
->prot
& PAGE_VALID
)
2568 size
= booke_page_size_to_tlb(tlb
->size
);
2569 if (size
< 0 || size
> 0x7)
2572 env
->spr
[SPR_40x_PID
] = tlb
->PID
;
2575 void do_4xx_tlbre_hi (void)
2580 tlb
= &env
->tlb
[T0
].tlbe
;
2582 if (tlb
->prot
& PAGE_EXEC
)
2584 if (tlb
->prot
& PAGE_WRITE
)
2588 void do_4xx_tlbwe_hi (void)
2591 target_ulong page
, end
;
2593 #if defined (DEBUG_SOFTWARE_TLB)
2594 if (loglevel
!= 0) {
2595 fprintf(logfile
, "%s T0 " TDX
" T1 " TDX
"\n", __func__
, T0
, T1
);
2599 tlb
= &env
->tlb
[T0
].tlbe
;
2600 /* Invalidate previous TLB (if it's valid) */
2601 if (tlb
->prot
& PAGE_VALID
) {
2602 end
= tlb
->EPN
+ tlb
->size
;
2603 #if defined (DEBUG_SOFTWARE_TLB)
2604 if (loglevel
!= 0) {
2605 fprintf(logfile
, "%s: invalidate old TLB %d start " ADDRX
2606 " end " ADDRX
"\n", __func__
, (int)T0
, tlb
->EPN
, end
);
2609 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2610 tlb_flush_page(env
, page
);
2612 tlb
->size
= booke_tlb_to_page_size((T1
>> 7) & 0x7);
2613 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2614 * If this ever occurs, one should use the ppcemb target instead
2615 * of the ppc or ppc64 one
2617 if ((T1
& 0x40) && tlb
->size
< TARGET_PAGE_SIZE
) {
2618 cpu_abort(env
, "TLB size " TARGET_FMT_lu
" < %u "
2619 "are not supported (%d)\n",
2620 tlb
->size
, TARGET_PAGE_SIZE
, (int)((T1
>> 7) & 0x7));
2622 tlb
->EPN
= T1
& ~(tlb
->size
- 1);
2624 tlb
->prot
|= PAGE_VALID
;
2626 tlb
->prot
&= ~PAGE_VALID
;
2628 /* XXX: TO BE FIXED */
2629 cpu_abort(env
, "Little-endian TLB entries are not supported by now\n");
2631 tlb
->PID
= env
->spr
[SPR_40x_PID
]; /* PID */
2632 tlb
->attr
= T1
& 0xFF;
2633 #if defined (DEBUG_SOFTWARE_TLB)
2634 if (loglevel
!= 0) {
2635 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
2636 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
2637 (int)T0
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
2638 tlb
->prot
& PAGE_READ
? 'r' : '-',
2639 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
2640 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
2641 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
2644 /* Invalidate new TLB (if valid) */
2645 if (tlb
->prot
& PAGE_VALID
) {
2646 end
= tlb
->EPN
+ tlb
->size
;
2647 #if defined (DEBUG_SOFTWARE_TLB)
2648 if (loglevel
!= 0) {
2649 fprintf(logfile
, "%s: invalidate TLB %d start " ADDRX
2650 " end " ADDRX
"\n", __func__
, (int)T0
, tlb
->EPN
, end
);
2653 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2654 tlb_flush_page(env
, page
);
2658 void do_4xx_tlbwe_lo (void)
2662 #if defined (DEBUG_SOFTWARE_TLB)
2663 if (loglevel
!= 0) {
2664 fprintf(logfile
, "%s T0 " TDX
" T1 " TDX
"\n", __func__
, T0
, T1
);
2668 tlb
= &env
->tlb
[T0
].tlbe
;
2669 tlb
->RPN
= T1
& 0xFFFFFC00;
2670 tlb
->prot
= PAGE_READ
;
2672 tlb
->prot
|= PAGE_EXEC
;
2674 tlb
->prot
|= PAGE_WRITE
;
2675 #if defined (DEBUG_SOFTWARE_TLB)
2676 if (loglevel
!= 0) {
2677 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
2678 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
2679 (int)T0
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
2680 tlb
->prot
& PAGE_READ
? 'r' : '-',
2681 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
2682 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
2683 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
2688 /* PowerPC 440 TLB management */
2689 void do_440_tlbwe (int word
)
2692 target_ulong EPN
, RPN
, size
;
2695 #if defined (DEBUG_SOFTWARE_TLB)
2696 if (loglevel
!= 0) {
2697 fprintf(logfile
, "%s word %d T0 " TDX
" T1 " TDX
"\n",
2698 __func__
, word
, T0
, T1
);
2703 tlb
= &env
->tlb
[T0
].tlbe
;
2706 /* Just here to please gcc */
2708 EPN
= T1
& 0xFFFFFC00;
2709 if ((tlb
->prot
& PAGE_VALID
) && EPN
!= tlb
->EPN
)
2712 size
= booke_tlb_to_page_size((T1
>> 4) & 0xF);
2713 if ((tlb
->prot
& PAGE_VALID
) && tlb
->size
< size
)
2717 tlb
->attr
|= (T1
>> 8) & 1;
2719 tlb
->prot
|= PAGE_VALID
;
2721 if (tlb
->prot
& PAGE_VALID
) {
2722 tlb
->prot
&= ~PAGE_VALID
;
2726 tlb
->PID
= env
->spr
[SPR_440_MMUCR
] & 0x000000FF;
2731 RPN
= T1
& 0xFFFFFC0F;
2732 if ((tlb
->prot
& PAGE_VALID
) && tlb
->RPN
!= RPN
)
2737 tlb
->attr
= (tlb
->attr
& 0x1) | (T1
& 0x0000FF00);
2738 tlb
->prot
= tlb
->prot
& PAGE_VALID
;
2740 tlb
->prot
|= PAGE_READ
<< 4;
2742 tlb
->prot
|= PAGE_WRITE
<< 4;
2744 tlb
->prot
|= PAGE_EXEC
<< 4;
2746 tlb
->prot
|= PAGE_READ
;
2748 tlb
->prot
|= PAGE_WRITE
;
2750 tlb
->prot
|= PAGE_EXEC
;
2755 void do_440_tlbre (int word
)
2761 tlb
= &env
->tlb
[T0
].tlbe
;
2764 /* Just here to please gcc */
2767 size
= booke_page_size_to_tlb(tlb
->size
);
2768 if (size
< 0 || size
> 0xF)
2771 if (tlb
->attr
& 0x1)
2773 if (tlb
->prot
& PAGE_VALID
)
2775 env
->spr
[SPR_440_MMUCR
] &= ~0x000000FF;
2776 env
->spr
[SPR_440_MMUCR
] |= tlb
->PID
;
2782 T0
= tlb
->attr
& ~0x1;
2783 if (tlb
->prot
& (PAGE_READ
<< 4))
2785 if (tlb
->prot
& (PAGE_WRITE
<< 4))
2787 if (tlb
->prot
& (PAGE_EXEC
<< 4))
2789 if (tlb
->prot
& PAGE_READ
)
2791 if (tlb
->prot
& PAGE_WRITE
)
2793 if (tlb
->prot
& PAGE_EXEC
)
2798 #endif /* !CONFIG_USER_ONLY */