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target-ppc: convert 405 MAC instructions to TCG
[qemu/qemu-JZ.git] / target-ppc / op_helper.c
blobef1035fc567138725cd11111b25530d2c70eaceb
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22
23 #include "helper_regs.h"
24 #include "op_helper.h"
25
26 #define MEMSUFFIX _raw
27 #include "op_helper.h"
28 #include "op_helper_mem.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #define MEMSUFFIX _user
31 #include "op_helper.h"
32 #include "op_helper_mem.h"
33 #define MEMSUFFIX _kernel
34 #include "op_helper.h"
35 #include "op_helper_mem.h"
36 #define MEMSUFFIX _hypv
37 #include "op_helper.h"
38 #include "op_helper_mem.h"
39 #endif
40
41 //#define DEBUG_OP
42 //#define DEBUG_EXCEPTIONS
43 //#define DEBUG_SOFTWARE_TLB
44
45 /*****************************************************************************/
46 /* Exceptions processing helpers */
47
48 void do_raise_exception_err (uint32_t exception, int error_code)
49 {
50 #if 0
51 printf("Raise exception %3x code : %d\n", exception, error_code);
52 #endif
53 env->exception_index = exception;
54 env->error_code = error_code;
55 cpu_loop_exit();
56 }
57
58 void do_raise_exception (uint32_t exception)
59 {
60 do_raise_exception_err(exception, 0);
61 }
62
63 /*****************************************************************************/
64 /* Registers load and stores */
65 uint32_t helper_load_cr (void)
66 {
67 return (env->crf[0] << 28) |
68 (env->crf[1] << 24) |
69 (env->crf[2] << 20) |
70 (env->crf[3] << 16) |
71 (env->crf[4] << 12) |
72 (env->crf[5] << 8) |
73 (env->crf[6] << 4) |
74 (env->crf[7] << 0);
75 }
76
77 void helper_store_cr (target_ulong val, uint32_t mask)
78 {
79 int i, sh;
80
81 for (i = 0, sh = 7; i < 8; i++, sh--) {
82 if (mask & (1 << sh))
83 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
84 }
85 }
86
87 #if defined(TARGET_PPC64)
88 void do_store_pri (int prio)
89 {
90 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
91 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
92 }
93 #endif
94
95 target_ulong ppc_load_dump_spr (int sprn)
96 {
97 if (loglevel != 0) {
98 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
99 sprn, sprn, env->spr[sprn]);
100 }
101
102 return env->spr[sprn];
103 }
104
105 void ppc_store_dump_spr (int sprn, target_ulong val)
106 {
107 if (loglevel != 0) {
108 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
109 sprn, sprn, env->spr[sprn], val);
110 }
111 env->spr[sprn] = val;
112 }
113
114 /*****************************************************************************/
115 /* Fixed point operations helpers */
116 #if defined(TARGET_PPC64)
117
118 /* multiply high word */
119 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
120 {
121 uint64_t tl, th;
122
123 muls64(&tl, &th, arg1, arg2);
124 return th;
125 }
126
127 /* multiply high word unsigned */
128 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
129 {
130 uint64_t tl, th;
131
132 mulu64(&tl, &th, arg1, arg2);
133 return th;
134 }
135
136 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
137 {
138 int64_t th;
139 uint64_t tl;
140
141 muls64(&tl, (uint64_t *)&th, arg1, arg2);
142 /* If th != 0 && th != -1, then we had an overflow */
143 if (likely((uint64_t)(th + 1) <= 1)) {
144 env->xer &= ~(1 << XER_OV);
145 } else {
146 env->xer |= (1 << XER_OV) | (1 << XER_SO);
147 }
148 return (int64_t)tl;
149 }
150 #endif
151
152 target_ulong helper_cntlzw (target_ulong t)
153 {
154 return clz32(t);
155 }
156
157 #if defined(TARGET_PPC64)
158 target_ulong helper_cntlzd (target_ulong t)
159 {
160 return clz64(t);
161 }
162 #endif
163
164 /* shift right arithmetic helper */
165 target_ulong helper_sraw (target_ulong value, target_ulong shift)
166 {
167 int32_t ret;
168
169 if (likely(!(shift & 0x20))) {
170 if (likely((uint32_t)shift != 0)) {
171 shift &= 0x1f;
172 ret = (int32_t)value >> shift;
173 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
174 env->xer &= ~(1 << XER_CA);
175 } else {
176 env->xer |= (1 << XER_CA);
177 }
178 } else {
179 ret = (int32_t)value;
180 env->xer &= ~(1 << XER_CA);
181 }
182 } else {
183 ret = (int32_t)value >> 31;
184 if (ret) {
185 env->xer |= (1 << XER_CA);
186 } else {
187 env->xer &= ~(1 << XER_CA);
188 }
189 }
190 return (target_long)ret;
191 }
192
193 #if defined(TARGET_PPC64)
194 target_ulong helper_srad (target_ulong value, target_ulong shift)
195 {
196 int64_t ret;
197
198 if (likely(!(shift & 0x40))) {
199 if (likely((uint64_t)shift != 0)) {
200 shift &= 0x3f;
201 ret = (int64_t)value >> shift;
202 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
203 env->xer &= ~(1 << XER_CA);
204 } else {
205 env->xer |= (1 << XER_CA);
206 }
207 } else {
208 ret = (int64_t)value;
209 env->xer &= ~(1 << XER_CA);
210 }
211 } else {
212 ret = (int64_t)value >> 63;
213 if (ret) {
214 env->xer |= (1 << XER_CA);
215 } else {
216 env->xer &= ~(1 << XER_CA);
217 }
218 }
219 return ret;
220 }
221 #endif
222
223 target_ulong helper_popcntb (target_ulong val)
224 {
225 uint32_t ret;
226 int i;
227
228 ret = 0;
229 for (i = 0; i < 32; i += 8)
230 ret |= ctpop8((val >> i) & 0xFF) << i;
231 return ret;
232 }
233
234 #if defined(TARGET_PPC64)
235 target_ulong helper_popcntb_64 (target_ulong val)
236 {
237 uint64_t ret;
238 int i;
239
240 ret = 0;
241 for (i = 0; i < 64; i += 8)
242 ret |= ctpop8((val >> i) & 0xFF) << i;
243 return ret;
244 }
245 #endif
246
247 /*****************************************************************************/
248 /* Floating point operations helpers */
249 static always_inline int fpisneg (float64 d)
250 {
251 CPU_DoubleU u;
252
253 u.d = d;
254
255 return u.ll >> 63 != 0;
256 }
257
258 static always_inline int isden (float64 d)
259 {
260 CPU_DoubleU u;
261
262 u.d = d;
263
264 return ((u.ll >> 52) & 0x7FF) == 0;
265 }
266
267 static always_inline int iszero (float64 d)
268 {
269 CPU_DoubleU u;
270
271 u.d = d;
272
273 return (u.ll & ~0x8000000000000000ULL) == 0;
274 }
275
276 static always_inline int isinfinity (float64 d)
277 {
278 CPU_DoubleU u;
279
280 u.d = d;
281
282 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
283 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
284 }
285
286 #ifdef CONFIG_SOFTFLOAT
287 static always_inline int isfinite (float64 d)
288 {
289 CPU_DoubleU u;
290
291 u.d = d;
292
293 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
294 }
295
296 static always_inline int isnormal (float64 d)
297 {
298 CPU_DoubleU u;
299
300 u.d = d;
301
302 uint32_t exp = (u.ll >> 52) & 0x7FF;
303 return ((0 < exp) && (exp < 0x7FF));
304 }
305 #endif
306
307 void do_compute_fprf (int set_fprf)
308 {
309 int isneg;
310
311 isneg = fpisneg(FT0);
312 if (unlikely(float64_is_nan(FT0))) {
313 if (float64_is_signaling_nan(FT0)) {
314 /* Signaling NaN: flags are undefined */
315 T0 = 0x00;
316 } else {
317 /* Quiet NaN */
318 T0 = 0x11;
319 }
320 } else if (unlikely(isinfinity(FT0))) {
321 /* +/- infinity */
322 if (isneg)
323 T0 = 0x09;
324 else
325 T0 = 0x05;
326 } else {
327 if (iszero(FT0)) {
328 /* +/- zero */
329 if (isneg)
330 T0 = 0x12;
331 else
332 T0 = 0x02;
333 } else {
334 if (isden(FT0)) {
335 /* Denormalized numbers */
336 T0 = 0x10;
337 } else {
338 /* Normalized numbers */
339 T0 = 0x00;
340 }
341 if (isneg) {
342 T0 |= 0x08;
343 } else {
344 T0 |= 0x04;
345 }
346 }
347 }
348 if (set_fprf) {
349 /* We update FPSCR_FPRF */
350 env->fpscr &= ~(0x1F << FPSCR_FPRF);
351 env->fpscr |= T0 << FPSCR_FPRF;
352 }
353 /* We just need fpcc to update Rc1 */
354 T0 &= 0xF;
355 }
356
357 /* Floating-point invalid operations exception */
358 static always_inline void fload_invalid_op_excp (int op)
359 {
360 int ve;
361
362 ve = fpscr_ve;
363 if (op & POWERPC_EXCP_FP_VXSNAN) {
364 /* Operation on signaling NaN */
365 env->fpscr |= 1 << FPSCR_VXSNAN;
366 }
367 if (op & POWERPC_EXCP_FP_VXSOFT) {
368 /* Software-defined condition */
369 env->fpscr |= 1 << FPSCR_VXSOFT;
370 }
371 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
372 case POWERPC_EXCP_FP_VXISI:
373 /* Magnitude subtraction of infinities */
374 env->fpscr |= 1 << FPSCR_VXISI;
375 goto update_arith;
376 case POWERPC_EXCP_FP_VXIDI:
377 /* Division of infinity by infinity */
378 env->fpscr |= 1 << FPSCR_VXIDI;
379 goto update_arith;
380 case POWERPC_EXCP_FP_VXZDZ:
381 /* Division of zero by zero */
382 env->fpscr |= 1 << FPSCR_VXZDZ;
383 goto update_arith;
384 case POWERPC_EXCP_FP_VXIMZ:
385 /* Multiplication of zero by infinity */
386 env->fpscr |= 1 << FPSCR_VXIMZ;
387 goto update_arith;
388 case POWERPC_EXCP_FP_VXVC:
389 /* Ordered comparison of NaN */
390 env->fpscr |= 1 << FPSCR_VXVC;
391 env->fpscr &= ~(0xF << FPSCR_FPCC);
392 env->fpscr |= 0x11 << FPSCR_FPCC;
393 /* We must update the target FPR before raising the exception */
394 if (ve != 0) {
395 env->exception_index = POWERPC_EXCP_PROGRAM;
396 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
397 /* Update the floating-point enabled exception summary */
398 env->fpscr |= 1 << FPSCR_FEX;
399 /* Exception is differed */
400 ve = 0;
401 }
402 break;
403 case POWERPC_EXCP_FP_VXSQRT:
404 /* Square root of a negative number */
405 env->fpscr |= 1 << FPSCR_VXSQRT;
406 update_arith:
407 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
408 if (ve == 0) {
409 /* Set the result to quiet NaN */
410 FT0 = UINT64_MAX;
411 env->fpscr &= ~(0xF << FPSCR_FPCC);
412 env->fpscr |= 0x11 << FPSCR_FPCC;
413 }
414 break;
415 case POWERPC_EXCP_FP_VXCVI:
416 /* Invalid conversion */
417 env->fpscr |= 1 << FPSCR_VXCVI;
418 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
419 if (ve == 0) {
420 /* Set the result to quiet NaN */
421 FT0 = UINT64_MAX;
422 env->fpscr &= ~(0xF << FPSCR_FPCC);
423 env->fpscr |= 0x11 << FPSCR_FPCC;
424 }
425 break;
426 }
427 /* Update the floating-point invalid operation summary */
428 env->fpscr |= 1 << FPSCR_VX;
429 /* Update the floating-point exception summary */
430 env->fpscr |= 1 << FPSCR_FX;
431 if (ve != 0) {
432 /* Update the floating-point enabled exception summary */
433 env->fpscr |= 1 << FPSCR_FEX;
434 if (msr_fe0 != 0 || msr_fe1 != 0)
435 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
436 }
437 }
438
439 static always_inline void float_zero_divide_excp (void)
440 {
441 CPU_DoubleU u0, u1;
442
443 env->fpscr |= 1 << FPSCR_ZX;
444 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
445 /* Update the floating-point exception summary */
446 env->fpscr |= 1 << FPSCR_FX;
447 if (fpscr_ze != 0) {
448 /* Update the floating-point enabled exception summary */
449 env->fpscr |= 1 << FPSCR_FEX;
450 if (msr_fe0 != 0 || msr_fe1 != 0) {
451 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
452 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
453 }
454 } else {
455 /* Set the result to infinity */
456 u0.d = FT0;
457 u1.d = FT1;
458 u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
459 u0.ll |= 0x7FFULL << 52;
460 FT0 = u0.d;
461 }
462 }
463
464 static always_inline void float_overflow_excp (void)
465 {
466 env->fpscr |= 1 << FPSCR_OX;
467 /* Update the floating-point exception summary */
468 env->fpscr |= 1 << FPSCR_FX;
469 if (fpscr_oe != 0) {
470 /* XXX: should adjust the result */
471 /* Update the floating-point enabled exception summary */
472 env->fpscr |= 1 << FPSCR_FEX;
473 /* We must update the target FPR before raising the exception */
474 env->exception_index = POWERPC_EXCP_PROGRAM;
475 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
476 } else {
477 env->fpscr |= 1 << FPSCR_XX;
478 env->fpscr |= 1 << FPSCR_FI;
479 }
480 }
481
482 static always_inline void float_underflow_excp (void)
483 {
484 env->fpscr |= 1 << FPSCR_UX;
485 /* Update the floating-point exception summary */
486 env->fpscr |= 1 << FPSCR_FX;
487 if (fpscr_ue != 0) {
488 /* XXX: should adjust the result */
489 /* Update the floating-point enabled exception summary */
490 env->fpscr |= 1 << FPSCR_FEX;
491 /* We must update the target FPR before raising the exception */
492 env->exception_index = POWERPC_EXCP_PROGRAM;
493 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
494 }
495 }
496
497 static always_inline void float_inexact_excp (void)
498 {
499 env->fpscr |= 1 << FPSCR_XX;
500 /* Update the floating-point exception summary */
501 env->fpscr |= 1 << FPSCR_FX;
502 if (fpscr_xe != 0) {
503 /* Update the floating-point enabled exception summary */
504 env->fpscr |= 1 << FPSCR_FEX;
505 /* We must update the target FPR before raising the exception */
506 env->exception_index = POWERPC_EXCP_PROGRAM;
507 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
508 }
509 }
510
511 static always_inline void fpscr_set_rounding_mode (void)
512 {
513 int rnd_type;
514
515 /* Set rounding mode */
516 switch (fpscr_rn) {
517 case 0:
518 /* Best approximation (round to nearest) */
519 rnd_type = float_round_nearest_even;
520 break;
521 case 1:
522 /* Smaller magnitude (round toward zero) */
523 rnd_type = float_round_to_zero;
524 break;
525 case 2:
526 /* Round toward +infinite */
527 rnd_type = float_round_up;
528 break;
529 default:
530 case 3:
531 /* Round toward -infinite */
532 rnd_type = float_round_down;
533 break;
534 }
535 set_float_rounding_mode(rnd_type, &env->fp_status);
536 }
537
538 void do_fpscr_setbit (int bit)
539 {
540 int prev;
541
542 prev = (env->fpscr >> bit) & 1;
543 env->fpscr |= 1 << bit;
544 if (prev == 0) {
545 switch (bit) {
546 case FPSCR_VX:
547 env->fpscr |= 1 << FPSCR_FX;
548 if (fpscr_ve)
549 goto raise_ve;
550 case FPSCR_OX:
551 env->fpscr |= 1 << FPSCR_FX;
552 if (fpscr_oe)
553 goto raise_oe;
554 break;
555 case FPSCR_UX:
556 env->fpscr |= 1 << FPSCR_FX;
557 if (fpscr_ue)
558 goto raise_ue;
559 break;
560 case FPSCR_ZX:
561 env->fpscr |= 1 << FPSCR_FX;
562 if (fpscr_ze)
563 goto raise_ze;
564 break;
565 case FPSCR_XX:
566 env->fpscr |= 1 << FPSCR_FX;
567 if (fpscr_xe)
568 goto raise_xe;
569 break;
570 case FPSCR_VXSNAN:
571 case FPSCR_VXISI:
572 case FPSCR_VXIDI:
573 case FPSCR_VXZDZ:
574 case FPSCR_VXIMZ:
575 case FPSCR_VXVC:
576 case FPSCR_VXSOFT:
577 case FPSCR_VXSQRT:
578 case FPSCR_VXCVI:
579 env->fpscr |= 1 << FPSCR_VX;
580 env->fpscr |= 1 << FPSCR_FX;
581 if (fpscr_ve != 0)
582 goto raise_ve;
583 break;
584 case FPSCR_VE:
585 if (fpscr_vx != 0) {
586 raise_ve:
587 env->error_code = POWERPC_EXCP_FP;
588 if (fpscr_vxsnan)
589 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
590 if (fpscr_vxisi)
591 env->error_code |= POWERPC_EXCP_FP_VXISI;
592 if (fpscr_vxidi)
593 env->error_code |= POWERPC_EXCP_FP_VXIDI;
594 if (fpscr_vxzdz)
595 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
596 if (fpscr_vximz)
597 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
598 if (fpscr_vxvc)
599 env->error_code |= POWERPC_EXCP_FP_VXVC;
600 if (fpscr_vxsoft)
601 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
602 if (fpscr_vxsqrt)
603 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
604 if (fpscr_vxcvi)
605 env->error_code |= POWERPC_EXCP_FP_VXCVI;
606 goto raise_excp;
607 }
608 break;
609 case FPSCR_OE:
610 if (fpscr_ox != 0) {
611 raise_oe:
612 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
613 goto raise_excp;
614 }
615 break;
616 case FPSCR_UE:
617 if (fpscr_ux != 0) {
618 raise_ue:
619 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
620 goto raise_excp;
621 }
622 break;
623 case FPSCR_ZE:
624 if (fpscr_zx != 0) {
625 raise_ze:
626 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
627 goto raise_excp;
628 }
629 break;
630 case FPSCR_XE:
631 if (fpscr_xx != 0) {
632 raise_xe:
633 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
634 goto raise_excp;
635 }
636 break;
637 case FPSCR_RN1:
638 case FPSCR_RN:
639 fpscr_set_rounding_mode();
640 break;
641 default:
642 break;
643 raise_excp:
644 /* Update the floating-point enabled exception summary */
645 env->fpscr |= 1 << FPSCR_FEX;
646 /* We have to update Rc1 before raising the exception */
647 env->exception_index = POWERPC_EXCP_PROGRAM;
648 break;
649 }
650 }
651 }
652
653 #if defined(WORDS_BIGENDIAN)
654 #define WORD0 0
655 #define WORD1 1
656 #else
657 #define WORD0 1
658 #define WORD1 0
659 #endif
660 void do_store_fpscr (uint32_t mask)
661 {
662 /*
663 * We use only the 32 LSB of the incoming fpr
664 */
665 CPU_DoubleU u;
666 uint32_t prev, new;
667 int i;
668
669 u.d = FT0;
670 prev = env->fpscr;
671 new = u.l.lower;
672 new &= ~0x90000000;
673 new |= prev & 0x90000000;
674 for (i = 0; i < 7; i++) {
675 if (mask & (1 << i)) {
676 env->fpscr &= ~(0xF << (4 * i));
677 env->fpscr |= new & (0xF << (4 * i));
678 }
679 }
680 /* Update VX and FEX */
681 if (fpscr_ix != 0)
682 env->fpscr |= 1 << FPSCR_VX;
683 else
684 env->fpscr &= ~(1 << FPSCR_VX);
685 if ((fpscr_ex & fpscr_eex) != 0) {
686 env->fpscr |= 1 << FPSCR_FEX;
687 env->exception_index = POWERPC_EXCP_PROGRAM;
688 /* XXX: we should compute it properly */
689 env->error_code = POWERPC_EXCP_FP;
690 }
691 else
692 env->fpscr &= ~(1 << FPSCR_FEX);
693 fpscr_set_rounding_mode();
694 }
695 #undef WORD0
696 #undef WORD1
697
698 #ifdef CONFIG_SOFTFLOAT
699 void do_float_check_status (void)
700 {
701 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
702 (env->error_code & POWERPC_EXCP_FP)) {
703 /* Differred floating-point exception after target FPR update */
704 if (msr_fe0 != 0 || msr_fe1 != 0)
705 do_raise_exception_err(env->exception_index, env->error_code);
706 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
707 float_overflow_excp();
708 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
709 float_underflow_excp();
710 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
711 float_inexact_excp();
712 }
713 }
714 #endif
715
716 #if USE_PRECISE_EMULATION
717 void do_fadd (void)
718 {
719 if (unlikely(float64_is_signaling_nan(FT0) ||
720 float64_is_signaling_nan(FT1))) {
721 /* sNaN addition */
722 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
723 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
724 fpisneg(FT0) == fpisneg(FT1))) {
725 FT0 = float64_add(FT0, FT1, &env->fp_status);
726 } else {
727 /* Magnitude subtraction of infinities */
728 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
729 }
730 }
731
732 void do_fsub (void)
733 {
734 if (unlikely(float64_is_signaling_nan(FT0) ||
735 float64_is_signaling_nan(FT1))) {
736 /* sNaN subtraction */
737 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
738 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
739 fpisneg(FT0) != fpisneg(FT1))) {
740 FT0 = float64_sub(FT0, FT1, &env->fp_status);
741 } else {
742 /* Magnitude subtraction of infinities */
743 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
744 }
745 }
746
747 void do_fmul (void)
748 {
749 if (unlikely(float64_is_signaling_nan(FT0) ||
750 float64_is_signaling_nan(FT1))) {
751 /* sNaN multiplication */
752 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
753 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
754 (iszero(FT0) && isinfinity(FT1)))) {
755 /* Multiplication of zero by infinity */
756 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
757 } else {
758 FT0 = float64_mul(FT0, FT1, &env->fp_status);
759 }
760 }
761
762 void do_fdiv (void)
763 {
764 if (unlikely(float64_is_signaling_nan(FT0) ||
765 float64_is_signaling_nan(FT1))) {
766 /* sNaN division */
767 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
768 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
769 /* Division of infinity by infinity */
770 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
771 } else if (unlikely(iszero(FT1))) {
772 if (iszero(FT0)) {
773 /* Division of zero by zero */
774 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
775 } else {
776 /* Division by zero */
777 float_zero_divide_excp();
778 }
779 } else {
780 FT0 = float64_div(FT0, FT1, &env->fp_status);
781 }
782 }
783 #endif /* USE_PRECISE_EMULATION */
784
785 void do_fctiw (void)
786 {
787 CPU_DoubleU p;
788
789 if (unlikely(float64_is_signaling_nan(FT0))) {
790 /* sNaN conversion */
791 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
792 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
793 /* qNan / infinity conversion */
794 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
795 } else {
796 p.ll = float64_to_int32(FT0, &env->fp_status);
797 #if USE_PRECISE_EMULATION
798 /* XXX: higher bits are not supposed to be significant.
799 * to make tests easier, return the same as a real PowerPC 750
800 */
801 p.ll |= 0xFFF80000ULL << 32;
802 #endif
803 FT0 = p.d;
804 }
805 }
806
807 void do_fctiwz (void)
808 {
809 CPU_DoubleU p;
810
811 if (unlikely(float64_is_signaling_nan(FT0))) {
812 /* sNaN conversion */
813 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
814 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
815 /* qNan / infinity conversion */
816 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
817 } else {
818 p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
819 #if USE_PRECISE_EMULATION
820 /* XXX: higher bits are not supposed to be significant.
821 * to make tests easier, return the same as a real PowerPC 750
822 */
823 p.ll |= 0xFFF80000ULL << 32;
824 #endif
825 FT0 = p.d;
826 }
827 }
828
829 #if defined(TARGET_PPC64)
830 void do_fcfid (void)
831 {
832 CPU_DoubleU p;
833
834 p.d = FT0;
835 FT0 = int64_to_float64(p.ll, &env->fp_status);
836 }
837
838 void do_fctid (void)
839 {
840 CPU_DoubleU p;
841
842 if (unlikely(float64_is_signaling_nan(FT0))) {
843 /* sNaN conversion */
844 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
845 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
846 /* qNan / infinity conversion */
847 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
848 } else {
849 p.ll = float64_to_int64(FT0, &env->fp_status);
850 FT0 = p.d;
851 }
852 }
853
854 void do_fctidz (void)
855 {
856 CPU_DoubleU p;
857
858 if (unlikely(float64_is_signaling_nan(FT0))) {
859 /* sNaN conversion */
860 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
861 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
862 /* qNan / infinity conversion */
863 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
864 } else {
865 p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
866 FT0 = p.d;
867 }
868 }
869
870 #endif
871
872 static always_inline void do_fri (int rounding_mode)
873 {
874 if (unlikely(float64_is_signaling_nan(FT0))) {
875 /* sNaN round */
876 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
877 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
878 /* qNan / infinity round */
879 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
880 } else {
881 set_float_rounding_mode(rounding_mode, &env->fp_status);
882 FT0 = float64_round_to_int(FT0, &env->fp_status);
883 /* Restore rounding mode from FPSCR */
884 fpscr_set_rounding_mode();
885 }
886 }
887
888 void do_frin (void)
889 {
890 do_fri(float_round_nearest_even);
891 }
892
893 void do_friz (void)
894 {
895 do_fri(float_round_to_zero);
896 }
897
898 void do_frip (void)
899 {
900 do_fri(float_round_up);
901 }
902
903 void do_frim (void)
904 {
905 do_fri(float_round_down);
906 }
907
908 #if USE_PRECISE_EMULATION
909 void do_fmadd (void)
910 {
911 if (unlikely(float64_is_signaling_nan(FT0) ||
912 float64_is_signaling_nan(FT1) ||
913 float64_is_signaling_nan(FT2))) {
914 /* sNaN operation */
915 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
916 } else {
917 #ifdef FLOAT128
918 /* This is the way the PowerPC specification defines it */
919 float128 ft0_128, ft1_128;
920
921 ft0_128 = float64_to_float128(FT0, &env->fp_status);
922 ft1_128 = float64_to_float128(FT1, &env->fp_status);
923 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
924 ft1_128 = float64_to_float128(FT2, &env->fp_status);
925 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
926 FT0 = float128_to_float64(ft0_128, &env->fp_status);
927 #else
928 /* This is OK on x86 hosts */
929 FT0 = (FT0 * FT1) + FT2;
930 #endif
931 }
932 }
933
934 void do_fmsub (void)
935 {
936 if (unlikely(float64_is_signaling_nan(FT0) ||
937 float64_is_signaling_nan(FT1) ||
938 float64_is_signaling_nan(FT2))) {
939 /* sNaN operation */
940 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
941 } else {
942 #ifdef FLOAT128
943 /* This is the way the PowerPC specification defines it */
944 float128 ft0_128, ft1_128;
945
946 ft0_128 = float64_to_float128(FT0, &env->fp_status);
947 ft1_128 = float64_to_float128(FT1, &env->fp_status);
948 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
949 ft1_128 = float64_to_float128(FT2, &env->fp_status);
950 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
951 FT0 = float128_to_float64(ft0_128, &env->fp_status);
952 #else
953 /* This is OK on x86 hosts */
954 FT0 = (FT0 * FT1) - FT2;
955 #endif
956 }
957 }
958 #endif /* USE_PRECISE_EMULATION */
959
960 void do_fnmadd (void)
961 {
962 if (unlikely(float64_is_signaling_nan(FT0) ||
963 float64_is_signaling_nan(FT1) ||
964 float64_is_signaling_nan(FT2))) {
965 /* sNaN operation */
966 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
967 } else {
968 #if USE_PRECISE_EMULATION
969 #ifdef FLOAT128
970 /* This is the way the PowerPC specification defines it */
971 float128 ft0_128, ft1_128;
972
973 ft0_128 = float64_to_float128(FT0, &env->fp_status);
974 ft1_128 = float64_to_float128(FT1, &env->fp_status);
975 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
976 ft1_128 = float64_to_float128(FT2, &env->fp_status);
977 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
978 FT0 = float128_to_float64(ft0_128, &env->fp_status);
979 #else
980 /* This is OK on x86 hosts */
981 FT0 = (FT0 * FT1) + FT2;
982 #endif
983 #else
984 FT0 = float64_mul(FT0, FT1, &env->fp_status);
985 FT0 = float64_add(FT0, FT2, &env->fp_status);
986 #endif
987 if (likely(!isnan(FT0)))
988 FT0 = float64_chs(FT0);
989 }
990 }
991
992 void do_fnmsub (void)
993 {
994 if (unlikely(float64_is_signaling_nan(FT0) ||
995 float64_is_signaling_nan(FT1) ||
996 float64_is_signaling_nan(FT2))) {
997 /* sNaN operation */
998 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
999 } else {
1000 #if USE_PRECISE_EMULATION
1001 #ifdef FLOAT128
1002 /* This is the way the PowerPC specification defines it */
1003 float128 ft0_128, ft1_128;
1004
1005 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1006 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1007 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1008 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1009 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1010 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1011 #else
1012 /* This is OK on x86 hosts */
1013 FT0 = (FT0 * FT1) - FT2;
1014 #endif
1015 #else
1016 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1017 FT0 = float64_sub(FT0, FT2, &env->fp_status);
1018 #endif
1019 if (likely(!isnan(FT0)))
1020 FT0 = float64_chs(FT0);
1021 }
1022 }
1023
1024 #if USE_PRECISE_EMULATION
1025 void do_frsp (void)
1026 {
1027 if (unlikely(float64_is_signaling_nan(FT0))) {
1028 /* sNaN square root */
1029 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1030 } else {
1031 FT0 = float64_to_float32(FT0, &env->fp_status);
1032 }
1033 }
1034 #endif /* USE_PRECISE_EMULATION */
1035
1036 void do_fsqrt (void)
1037 {
1038 if (unlikely(float64_is_signaling_nan(FT0))) {
1039 /* sNaN square root */
1040 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1041 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1042 /* Square root of a negative nonzero number */
1043 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1044 } else {
1045 FT0 = float64_sqrt(FT0, &env->fp_status);
1046 }
1047 }
1048
1049 void do_fre (void)
1050 {
1051 CPU_DoubleU p;
1052
1053 if (unlikely(float64_is_signaling_nan(FT0))) {
1054 /* sNaN reciprocal */
1055 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1056 } else if (unlikely(iszero(FT0))) {
1057 /* Zero reciprocal */
1058 float_zero_divide_excp();
1059 } else if (likely(isnormal(FT0))) {
1060 FT0 = float64_div(1.0, FT0, &env->fp_status);
1061 } else {
1062 p.d = FT0;
1063 if (p.ll == 0x8000000000000000ULL) {
1064 p.ll = 0xFFF0000000000000ULL;
1065 } else if (p.ll == 0x0000000000000000ULL) {
1066 p.ll = 0x7FF0000000000000ULL;
1067 } else if (isnan(FT0)) {
1068 p.ll = 0x7FF8000000000000ULL;
1069 } else if (fpisneg(FT0)) {
1070 p.ll = 0x8000000000000000ULL;
1071 } else {
1072 p.ll = 0x0000000000000000ULL;
1073 }
1074 FT0 = p.d;
1075 }
1076 }
1077
1078 void do_fres (void)
1079 {
1080 CPU_DoubleU p;
1081
1082 if (unlikely(float64_is_signaling_nan(FT0))) {
1083 /* sNaN reciprocal */
1084 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1085 } else if (unlikely(iszero(FT0))) {
1086 /* Zero reciprocal */
1087 float_zero_divide_excp();
1088 } else if (likely(isnormal(FT0))) {
1089 #if USE_PRECISE_EMULATION
1090 FT0 = float64_div(1.0, FT0, &env->fp_status);
1091 FT0 = float64_to_float32(FT0, &env->fp_status);
1092 #else
1093 FT0 = float32_div(1.0, FT0, &env->fp_status);
1094 #endif
1095 } else {
1096 p.d = FT0;
1097 if (p.ll == 0x8000000000000000ULL) {
1098 p.ll = 0xFFF0000000000000ULL;
1099 } else if (p.ll == 0x0000000000000000ULL) {
1100 p.ll = 0x7FF0000000000000ULL;
1101 } else if (isnan(FT0)) {
1102 p.ll = 0x7FF8000000000000ULL;
1103 } else if (fpisneg(FT0)) {
1104 p.ll = 0x8000000000000000ULL;
1105 } else {
1106 p.ll = 0x0000000000000000ULL;
1107 }
1108 FT0 = p.d;
1109 }
1110 }
1111
1112 void do_frsqrte (void)
1113 {
1114 CPU_DoubleU p;
1115
1116 if (unlikely(float64_is_signaling_nan(FT0))) {
1117 /* sNaN reciprocal square root */
1118 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1119 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1120 /* Reciprocal square root of a negative nonzero number */
1121 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1122 } else if (likely(isnormal(FT0))) {
1123 FT0 = float64_sqrt(FT0, &env->fp_status);
1124 FT0 = float32_div(1.0, FT0, &env->fp_status);
1125 } else {
1126 p.d = FT0;
1127 if (p.ll == 0x8000000000000000ULL) {
1128 p.ll = 0xFFF0000000000000ULL;
1129 } else if (p.ll == 0x0000000000000000ULL) {
1130 p.ll = 0x7FF0000000000000ULL;
1131 } else if (isnan(FT0)) {
1132 p.ll |= 0x000FFFFFFFFFFFFFULL;
1133 } else if (fpisneg(FT0)) {
1134 p.ll = 0x7FF8000000000000ULL;
1135 } else {
1136 p.ll = 0x0000000000000000ULL;
1137 }
1138 FT0 = p.d;
1139 }
1140 }
1141
1142 void do_fsel (void)
1143 {
1144 if (!fpisneg(FT0) || iszero(FT0))
1145 FT0 = FT1;
1146 else
1147 FT0 = FT2;
1148 }
1149
1150 uint32_t helper_fcmpu (void)
1151 {
1152 uint32_t ret = 0;
1153
1154 if (unlikely(float64_is_signaling_nan(FT0) ||
1155 float64_is_signaling_nan(FT1))) {
1156 /* sNaN comparison */
1157 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1158 } else {
1159 if (float64_lt(FT0, FT1, &env->fp_status)) {
1160 ret = 0x08UL;
1161 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1162 ret = 0x04UL;
1163 } else {
1164 ret = 0x02UL;
1165 }
1166 }
1167 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1168 env->fpscr |= ret << FPSCR_FPRF;
1169 return ret;
1170 }
1171
1172 uint32_t helper_fcmpo (void)
1173 {
1174 uint32_t ret = 0;
1175
1176 if (unlikely(float64_is_nan(FT0) ||
1177 float64_is_nan(FT1))) {
1178 if (float64_is_signaling_nan(FT0) ||
1179 float64_is_signaling_nan(FT1)) {
1180 /* sNaN comparison */
1181 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1182 POWERPC_EXCP_FP_VXVC);
1183 } else {
1184 /* qNaN comparison */
1185 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1186 }
1187 } else {
1188 if (float64_lt(FT0, FT1, &env->fp_status)) {
1189 ret = 0x08UL;
1190 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1191 ret = 0x04UL;
1192 } else {
1193 ret = 0x02UL;
1194 }
1195 }
1196 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1197 env->fpscr |= ret << FPSCR_FPRF;
1198 return ret;
1199 }
1200
1201 #if !defined (CONFIG_USER_ONLY)
1202 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1203
1204 void do_store_msr (void)
1205 {
1206 T0 = hreg_store_msr(env, T0, 0);
1207 if (T0 != 0) {
1208 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1209 do_raise_exception(T0);
1210 }
1211 }
1212
1213 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1214 target_ulong msrm, int keep_msrh)
1215 {
1216 #if defined(TARGET_PPC64)
1217 if (msr & (1ULL << MSR_SF)) {
1218 nip = (uint64_t)nip;
1219 msr &= (uint64_t)msrm;
1220 } else {
1221 nip = (uint32_t)nip;
1222 msr = (uint32_t)(msr & msrm);
1223 if (keep_msrh)
1224 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1225 }
1226 #else
1227 nip = (uint32_t)nip;
1228 msr &= (uint32_t)msrm;
1229 #endif
1230 /* XXX: beware: this is false if VLE is supported */
1231 env->nip = nip & ~((target_ulong)0x00000003);
1232 hreg_store_msr(env, msr, 1);
1233 #if defined (DEBUG_OP)
1234 cpu_dump_rfi(env->nip, env->msr);
1235 #endif
1236 /* No need to raise an exception here,
1237 * as rfi is always the last insn of a TB
1238 */
1239 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1240 }
1241
1242 void do_rfi (void)
1243 {
1244 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1245 ~((target_ulong)0xFFFF0000), 1);
1246 }
1247
1248 #if defined(TARGET_PPC64)
1249 void do_rfid (void)
1250 {
1251 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1252 ~((target_ulong)0xFFFF0000), 0);
1253 }
1254
1255 void do_hrfid (void)
1256 {
1257 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1258 ~((target_ulong)0xFFFF0000), 0);
1259 }
1260 #endif
1261 #endif
1262
1263 void do_tw (int flags)
1264 {
1265 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1266 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1267 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1268 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
1269 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
1270 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1271 }
1272 }
1273
1274 #if defined(TARGET_PPC64)
1275 void do_td (int flags)
1276 {
1277 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1278 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1279 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1280 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1281 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
1282 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1283 }
1284 #endif
1285
1286 /*****************************************************************************/
1287 /* PowerPC 601 specific instructions (POWER bridge) */
1288 void do_POWER_abso (void)
1289 {
1290 if ((int32_t)T0 == INT32_MIN) {
1291 T0 = INT32_MAX;
1292 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1293 } else if ((int32_t)T0 < 0) {
1294 T0 = -T0;
1295 env->xer &= ~(1 << XER_OV);
1296 } else {
1297 env->xer &= ~(1 << XER_OV);
1298 }
1299 }
1300
1301 void do_POWER_clcs (void)
1302 {
1303 switch (T0) {
1304 case 0x0CUL:
1305 /* Instruction cache line size */
1306 T0 = env->icache_line_size;
1307 break;
1308 case 0x0DUL:
1309 /* Data cache line size */
1310 T0 = env->dcache_line_size;
1311 break;
1312 case 0x0EUL:
1313 /* Minimum cache line size */
1314 T0 = env->icache_line_size < env->dcache_line_size ?
1315 env->icache_line_size : env->dcache_line_size;
1316 break;
1317 case 0x0FUL:
1318 /* Maximum cache line size */
1319 T0 = env->icache_line_size > env->dcache_line_size ?
1320 env->icache_line_size : env->dcache_line_size;
1321 break;
1322 default:
1323 /* Undefined */
1324 break;
1325 }
1326 }
1327
1328 void do_POWER_div (void)
1329 {
1330 uint64_t tmp;
1331
1332 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1333 (int32_t)T1 == 0) {
1334 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1335 env->spr[SPR_MQ] = 0;
1336 } else {
1337 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1338 env->spr[SPR_MQ] = tmp % T1;
1339 T0 = tmp / (int32_t)T1;
1340 }
1341 }
1342
1343 void do_POWER_divo (void)
1344 {
1345 int64_t tmp;
1346
1347 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1348 (int32_t)T1 == 0) {
1349 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1350 env->spr[SPR_MQ] = 0;
1351 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1352 } else {
1353 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1354 env->spr[SPR_MQ] = tmp % T1;
1355 tmp /= (int32_t)T1;
1356 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1357 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1358 } else {
1359 env->xer &= ~(1 << XER_OV);
1360 }
1361 T0 = tmp;
1362 }
1363 }
1364
1365 void do_POWER_divs (void)
1366 {
1367 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1368 (int32_t)T1 == 0) {
1369 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1370 env->spr[SPR_MQ] = 0;
1371 } else {
1372 env->spr[SPR_MQ] = T0 % T1;
1373 T0 = (int32_t)T0 / (int32_t)T1;
1374 }
1375 }
1376
1377 void do_POWER_divso (void)
1378 {
1379 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1380 (int32_t)T1 == 0) {
1381 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1382 env->spr[SPR_MQ] = 0;
1383 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1384 } else {
1385 T0 = (int32_t)T0 / (int32_t)T1;
1386 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1387 env->xer &= ~(1 << XER_OV);
1388 }
1389 }
1390
1391 void do_POWER_dozo (void)
1392 {
1393 if ((int32_t)T1 > (int32_t)T0) {
1394 T2 = T0;
1395 T0 = T1 - T0;
1396 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1397 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1398 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1399 } else {
1400 env->xer &= ~(1 << XER_OV);
1401 }
1402 } else {
1403 T0 = 0;
1404 env->xer &= ~(1 << XER_OV);
1405 }
1406 }
1407
1408 void do_POWER_maskg (void)
1409 {
1410 uint32_t ret;
1411
1412 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1413 ret = UINT32_MAX;
1414 } else {
1415 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1416 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1417 if ((uint32_t)T0 > (uint32_t)T1)
1418 ret = ~ret;
1419 }
1420 T0 = ret;
1421 }
1422
1423 void do_POWER_mulo (void)
1424 {
1425 uint64_t tmp;
1426
1427 tmp = (uint64_t)T0 * (uint64_t)T1;
1428 env->spr[SPR_MQ] = tmp >> 32;
1429 T0 = tmp;
1430 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1431 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1432 } else {
1433 env->xer &= ~(1 << XER_OV);
1434 }
1435 }
1436
1437 #if !defined (CONFIG_USER_ONLY)
1438 void do_POWER_rac (void)
1439 {
1440 mmu_ctx_t ctx;
1441 int nb_BATs;
1442
1443 /* We don't have to generate many instances of this instruction,
1444 * as rac is supervisor only.
1445 */
1446 /* XXX: FIX THIS: Pretend we have no BAT */
1447 nb_BATs = env->nb_BATs;
1448 env->nb_BATs = 0;
1449 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1450 T0 = ctx.raddr;
1451 env->nb_BATs = nb_BATs;
1452 }
1453
1454 void do_POWER_rfsvc (void)
1455 {
1456 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1457 }
1458
1459 void do_store_hid0_601 (void)
1460 {
1461 uint32_t hid0;
1462
1463 hid0 = env->spr[SPR_HID0];
1464 if ((T0 ^ hid0) & 0x00000008) {
1465 /* Change current endianness */
1466 env->hflags &= ~(1 << MSR_LE);
1467 env->hflags_nmsr &= ~(1 << MSR_LE);
1468 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1469 env->hflags |= env->hflags_nmsr;
1470 if (loglevel != 0) {
1471 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1472 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1473 }
1474 }
1475 env->spr[SPR_HID0] = T0;
1476 }
1477 #endif
1478
1479 /*****************************************************************************/
1480 /* 602 specific instructions */
1481 /* mfrom is the most crazy instruction ever seen, imho ! */
1482 /* Real implementation uses a ROM table. Do the same */
1483 #define USE_MFROM_ROM_TABLE
1484 void do_op_602_mfrom (void)
1485 {
1486 if (likely(T0 < 602)) {
1487 #if defined(USE_MFROM_ROM_TABLE)
1488 #include "mfrom_table.c"
1489 T0 = mfrom_ROM_table[T0];
1490 #else
1491 double d;
1492 /* Extremly decomposed:
1493 * -T0 / 256
1494 * T0 = 256 * log10(10 + 1.0) + 0.5
1495 */
1496 d = T0;
1497 d = float64_div(d, 256, &env->fp_status);
1498 d = float64_chs(d);
1499 d = exp10(d); // XXX: use float emulation function
1500 d = float64_add(d, 1.0, &env->fp_status);
1501 d = log10(d); // XXX: use float emulation function
1502 d = float64_mul(d, 256, &env->fp_status);
1503 d = float64_add(d, 0.5, &env->fp_status);
1504 T0 = float64_round_to_int(d, &env->fp_status);
1505 #endif
1506 } else {
1507 T0 = 0;
1508 }
1509 }
1510
1511 /*****************************************************************************/
1512 /* Embedded PowerPC specific helpers */
1513
1514 /* XXX: to be improved to check access rights when in user-mode */
1515 void do_load_dcr (void)
1516 {
1517 target_ulong val;
1518
1519 if (unlikely(env->dcr_env == NULL)) {
1520 if (loglevel != 0) {
1521 fprintf(logfile, "No DCR environment\n");
1522 }
1523 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1524 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1525 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1526 if (loglevel != 0) {
1527 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1528 }
1529 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1530 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1531 } else {
1532 T0 = val;
1533 }
1534 }
1535
1536 void do_store_dcr (void)
1537 {
1538 if (unlikely(env->dcr_env == NULL)) {
1539 if (loglevel != 0) {
1540 fprintf(logfile, "No DCR environment\n");
1541 }
1542 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1543 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1544 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1545 if (loglevel != 0) {
1546 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1547 }
1548 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1549 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1550 }
1551 }
1552
1553 #if !defined(CONFIG_USER_ONLY)
1554 void do_40x_rfci (void)
1555 {
1556 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1557 ~((target_ulong)0xFFFF0000), 0);
1558 }
1559
1560 void do_rfci (void)
1561 {
1562 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1563 ~((target_ulong)0x3FFF0000), 0);
1564 }
1565
1566 void do_rfdi (void)
1567 {
1568 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1569 ~((target_ulong)0x3FFF0000), 0);
1570 }
1571
1572 void do_rfmci (void)
1573 {
1574 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1575 ~((target_ulong)0x3FFF0000), 0);
1576 }
1577
1578 void do_load_403_pb (int num)
1579 {
1580 T0 = env->pb[num];
1581 }
1582
1583 void do_store_403_pb (int num)
1584 {
1585 if (likely(env->pb[num] != T0)) {
1586 env->pb[num] = T0;
1587 /* Should be optimized */
1588 tlb_flush(env, 1);
1589 }
1590 }
1591 #endif
1592
1593 /* 440 specific */
1594 void do_440_dlmzb (void)
1595 {
1596 target_ulong mask;
1597 int i;
1598
1599 i = 1;
1600 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1601 if ((T0 & mask) == 0)
1602 goto done;
1603 i++;
1604 }
1605 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1606 if ((T1 & mask) == 0)
1607 break;
1608 i++;
1609 }
1610 done:
1611 T0 = i;
1612 }
1613
1614 /* SPE extension helpers */
1615 /* Use a table to make this quicker */
1616 static uint8_t hbrev[16] = {
1617 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1618 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1619 };
1620
1621 static always_inline uint8_t byte_reverse (uint8_t val)
1622 {
1623 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1624 }
1625
1626 static always_inline uint32_t word_reverse (uint32_t val)
1627 {
1628 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1629 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1630 }
1631
1632 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1633 void do_brinc (void)
1634 {
1635 uint32_t a, b, d, mask;
1636
1637 mask = UINT32_MAX >> (32 - MASKBITS);
1638 a = T0 & mask;
1639 b = T1 & mask;
1640 d = word_reverse(1 + word_reverse(a | ~b));
1641 T0 = (T0 & ~mask) | (d & b);
1642 }
1643
1644 #define DO_SPE_OP2(name) \
1645 void do_ev##name (void) \
1646 { \
1647 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1648 (uint64_t)_do_e##name(T0_64, T1_64); \
1649 }
1650
1651 #define DO_SPE_OP1(name) \
1652 void do_ev##name (void) \
1653 { \
1654 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1655 (uint64_t)_do_e##name(T0_64); \
1656 }
1657
1658 /* Fixed-point vector arithmetic */
1659 static always_inline uint32_t _do_eabs (uint32_t val)
1660 {
1661 if ((val & 0x80000000) && val != 0x80000000)
1662 val -= val;
1663
1664 return val;
1665 }
1666
1667 static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1668 {
1669 return op1 + op2;
1670 }
1671
1672 static always_inline int _do_ecntlsw (uint32_t val)
1673 {
1674 if (val & 0x80000000)
1675 return clz32(~val);
1676 else
1677 return clz32(val);
1678 }
1679
1680 static always_inline int _do_ecntlzw (uint32_t val)
1681 {
1682 return clz32(val);
1683 }
1684
1685 static always_inline uint32_t _do_eneg (uint32_t val)
1686 {
1687 if (val != 0x80000000)
1688 val -= val;
1689
1690 return val;
1691 }
1692
1693 static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1694 {
1695 return rotl32(op1, op2);
1696 }
1697
1698 static always_inline uint32_t _do_erndw (uint32_t val)
1699 {
1700 return (val + 0x000080000000) & 0xFFFF0000;
1701 }
1702
1703 static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1704 {
1705 /* No error here: 6 bits are used */
1706 return op1 << (op2 & 0x3F);
1707 }
1708
1709 static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1710 {
1711 /* No error here: 6 bits are used */
1712 return op1 >> (op2 & 0x3F);
1713 }
1714
1715 static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1716 {
1717 /* No error here: 6 bits are used */
1718 return op1 >> (op2 & 0x3F);
1719 }
1720
1721 static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1722 {
1723 return op2 - op1;
1724 }
1725
1726 /* evabs */
1727 DO_SPE_OP1(abs);
1728 /* evaddw */
1729 DO_SPE_OP2(addw);
1730 /* evcntlsw */
1731 DO_SPE_OP1(cntlsw);
1732 /* evcntlzw */
1733 DO_SPE_OP1(cntlzw);
1734 /* evneg */
1735 DO_SPE_OP1(neg);
1736 /* evrlw */
1737 DO_SPE_OP2(rlw);
1738 /* evrnd */
1739 DO_SPE_OP1(rndw);
1740 /* evslw */
1741 DO_SPE_OP2(slw);
1742 /* evsrws */
1743 DO_SPE_OP2(srws);
1744 /* evsrwu */
1745 DO_SPE_OP2(srwu);
1746 /* evsubfw */
1747 DO_SPE_OP2(subfw);
1748
1749 /* evsel is a little bit more complicated... */
1750 static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1751 {
1752 if (n)
1753 return op1;
1754 else
1755 return op2;
1756 }
1757
1758 void do_evsel (void)
1759 {
1760 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1761 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1762 }
1763
1764 /* Fixed-point vector comparisons */
1765 #define DO_SPE_CMP(name) \
1766 void do_ev##name (void) \
1767 { \
1768 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1769 T1_64 >> 32) << 32, \
1770 _do_e##name(T0_64, T1_64)); \
1771 }
1772
1773 static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
1774 {
1775 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1776 }
1777 static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
1778 {
1779 return op1 == op2 ? 1 : 0;
1780 }
1781
1782 static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
1783 {
1784 return op1 > op2 ? 1 : 0;
1785 }
1786
1787 static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
1788 {
1789 return op1 > op2 ? 1 : 0;
1790 }
1791
1792 static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
1793 {
1794 return op1 < op2 ? 1 : 0;
1795 }
1796
1797 static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
1798 {
1799 return op1 < op2 ? 1 : 0;
1800 }
1801
1802 /* evcmpeq */
1803 DO_SPE_CMP(cmpeq);
1804 /* evcmpgts */
1805 DO_SPE_CMP(cmpgts);
1806 /* evcmpgtu */
1807 DO_SPE_CMP(cmpgtu);
1808 /* evcmplts */
1809 DO_SPE_CMP(cmplts);
1810 /* evcmpltu */
1811 DO_SPE_CMP(cmpltu);
1812
1813 /* Single precision floating-point conversions from/to integer */
1814 static always_inline uint32_t _do_efscfsi (int32_t val)
1815 {
1816 CPU_FloatU u;
1817
1818 u.f = int32_to_float32(val, &env->spe_status);
1819
1820 return u.l;
1821 }
1822
1823 static always_inline uint32_t _do_efscfui (uint32_t val)
1824 {
1825 CPU_FloatU u;
1826
1827 u.f = uint32_to_float32(val, &env->spe_status);
1828
1829 return u.l;
1830 }
1831
1832 static always_inline int32_t _do_efsctsi (uint32_t val)
1833 {
1834 CPU_FloatU u;
1835
1836 u.l = val;
1837 /* NaN are not treated the same way IEEE 754 does */
1838 if (unlikely(isnan(u.f)))
1839 return 0;
1840
1841 return float32_to_int32(u.f, &env->spe_status);
1842 }
1843
1844 static always_inline uint32_t _do_efsctui (uint32_t val)
1845 {
1846 CPU_FloatU u;
1847
1848 u.l = val;
1849 /* NaN are not treated the same way IEEE 754 does */
1850 if (unlikely(isnan(u.f)))
1851 return 0;
1852
1853 return float32_to_uint32(u.f, &env->spe_status);
1854 }
1855
1856 static always_inline int32_t _do_efsctsiz (uint32_t val)
1857 {
1858 CPU_FloatU u;
1859
1860 u.l = val;
1861 /* NaN are not treated the same way IEEE 754 does */
1862 if (unlikely(isnan(u.f)))
1863 return 0;
1864
1865 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1866 }
1867
1868 static always_inline uint32_t _do_efsctuiz (uint32_t val)
1869 {
1870 CPU_FloatU u;
1871
1872 u.l = val;
1873 /* NaN are not treated the same way IEEE 754 does */
1874 if (unlikely(isnan(u.f)))
1875 return 0;
1876
1877 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1878 }
1879
1880 void do_efscfsi (void)
1881 {
1882 T0_64 = _do_efscfsi(T0_64);
1883 }
1884
1885 void do_efscfui (void)
1886 {
1887 T0_64 = _do_efscfui(T0_64);
1888 }
1889
1890 void do_efsctsi (void)
1891 {
1892 T0_64 = _do_efsctsi(T0_64);
1893 }
1894
1895 void do_efsctui (void)
1896 {
1897 T0_64 = _do_efsctui(T0_64);
1898 }
1899
1900 void do_efsctsiz (void)
1901 {
1902 T0_64 = _do_efsctsiz(T0_64);
1903 }
1904
1905 void do_efsctuiz (void)
1906 {
1907 T0_64 = _do_efsctuiz(T0_64);
1908 }
1909
1910 /* Single precision floating-point conversion to/from fractional */
1911 static always_inline uint32_t _do_efscfsf (uint32_t val)
1912 {
1913 CPU_FloatU u;
1914 float32 tmp;
1915
1916 u.f = int32_to_float32(val, &env->spe_status);
1917 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1918 u.f = float32_div(u.f, tmp, &env->spe_status);
1919
1920 return u.l;
1921 }
1922
1923 static always_inline uint32_t _do_efscfuf (uint32_t val)
1924 {
1925 CPU_FloatU u;
1926 float32 tmp;
1927
1928 u.f = uint32_to_float32(val, &env->spe_status);
1929 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1930 u.f = float32_div(u.f, tmp, &env->spe_status);
1931
1932 return u.l;
1933 }
1934
1935 static always_inline int32_t _do_efsctsf (uint32_t val)
1936 {
1937 CPU_FloatU u;
1938 float32 tmp;
1939
1940 u.l = val;
1941 /* NaN are not treated the same way IEEE 754 does */
1942 if (unlikely(isnan(u.f)))
1943 return 0;
1944 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1945 u.f = float32_mul(u.f, tmp, &env->spe_status);
1946
1947 return float32_to_int32(u.f, &env->spe_status);
1948 }
1949
1950 static always_inline uint32_t _do_efsctuf (uint32_t val)
1951 {
1952 CPU_FloatU u;
1953 float32 tmp;
1954
1955 u.l = val;
1956 /* NaN are not treated the same way IEEE 754 does */
1957 if (unlikely(isnan(u.f)))
1958 return 0;
1959 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1960 u.f = float32_mul(u.f, tmp, &env->spe_status);
1961
1962 return float32_to_uint32(u.f, &env->spe_status);
1963 }
1964
1965 static always_inline int32_t _do_efsctsfz (uint32_t val)
1966 {
1967 CPU_FloatU u;
1968 float32 tmp;
1969
1970 u.l = val;
1971 /* NaN are not treated the same way IEEE 754 does */
1972 if (unlikely(isnan(u.f)))
1973 return 0;
1974 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1975 u.f = float32_mul(u.f, tmp, &env->spe_status);
1976
1977 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1978 }
1979
1980 static always_inline uint32_t _do_efsctufz (uint32_t val)
1981 {
1982 CPU_FloatU u;
1983 float32 tmp;
1984
1985 u.l = val;
1986 /* NaN are not treated the same way IEEE 754 does */
1987 if (unlikely(isnan(u.f)))
1988 return 0;
1989 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1990 u.f = float32_mul(u.f, tmp, &env->spe_status);
1991
1992 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1993 }
1994
1995 void do_efscfsf (void)
1996 {
1997 T0_64 = _do_efscfsf(T0_64);
1998 }
1999
2000 void do_efscfuf (void)
2001 {
2002 T0_64 = _do_efscfuf(T0_64);
2003 }
2004
2005 void do_efsctsf (void)
2006 {
2007 T0_64 = _do_efsctsf(T0_64);
2008 }
2009
2010 void do_efsctuf (void)
2011 {
2012 T0_64 = _do_efsctuf(T0_64);
2013 }
2014
2015 void do_efsctsfz (void)
2016 {
2017 T0_64 = _do_efsctsfz(T0_64);
2018 }
2019
2020 void do_efsctufz (void)
2021 {
2022 T0_64 = _do_efsctufz(T0_64);
2023 }
2024
2025 /* Double precision floating point helpers */
2026 static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
2027 {
2028 /* XXX: TODO: test special values (NaN, infinites, ...) */
2029 return _do_efdtstlt(op1, op2);
2030 }
2031
2032 static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
2033 {
2034 /* XXX: TODO: test special values (NaN, infinites, ...) */
2035 return _do_efdtstgt(op1, op2);
2036 }
2037
2038 static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
2039 {
2040 /* XXX: TODO: test special values (NaN, infinites, ...) */
2041 return _do_efdtsteq(op1, op2);
2042 }
2043
2044 void do_efdcmplt (void)
2045 {
2046 T0 = _do_efdcmplt(T0_64, T1_64);
2047 }
2048
2049 void do_efdcmpgt (void)
2050 {
2051 T0 = _do_efdcmpgt(T0_64, T1_64);
2052 }
2053
2054 void do_efdcmpeq (void)
2055 {
2056 T0 = _do_efdcmpeq(T0_64, T1_64);
2057 }
2058
2059 /* Double precision floating-point conversion to/from integer */
2060 static always_inline uint64_t _do_efdcfsi (int64_t val)
2061 {
2062 CPU_DoubleU u;
2063
2064 u.d = int64_to_float64(val, &env->spe_status);
2065
2066 return u.ll;
2067 }
2068
2069 static always_inline uint64_t _do_efdcfui (uint64_t val)
2070 {
2071 CPU_DoubleU u;
2072
2073 u.d = uint64_to_float64(val, &env->spe_status);
2074
2075 return u.ll;
2076 }
2077
2078 static always_inline int64_t _do_efdctsi (uint64_t val)
2079 {
2080 CPU_DoubleU u;
2081
2082 u.ll = val;
2083 /* NaN are not treated the same way IEEE 754 does */
2084 if (unlikely(isnan(u.d)))
2085 return 0;
2086
2087 return float64_to_int64(u.d, &env->spe_status);
2088 }
2089
2090 static always_inline uint64_t _do_efdctui (uint64_t val)
2091 {
2092 CPU_DoubleU u;
2093
2094 u.ll = val;
2095 /* NaN are not treated the same way IEEE 754 does */
2096 if (unlikely(isnan(u.d)))
2097 return 0;
2098
2099 return float64_to_uint64(u.d, &env->spe_status);
2100 }
2101
2102 static always_inline int64_t _do_efdctsiz (uint64_t val)
2103 {
2104 CPU_DoubleU u;
2105
2106 u.ll = val;
2107 /* NaN are not treated the same way IEEE 754 does */
2108 if (unlikely(isnan(u.d)))
2109 return 0;
2110
2111 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2112 }
2113
2114 static always_inline uint64_t _do_efdctuiz (uint64_t val)
2115 {
2116 CPU_DoubleU u;
2117
2118 u.ll = val;
2119 /* NaN are not treated the same way IEEE 754 does */
2120 if (unlikely(isnan(u.d)))
2121 return 0;
2122
2123 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2124 }
2125
2126 void do_efdcfsi (void)
2127 {
2128 T0_64 = _do_efdcfsi(T0_64);
2129 }
2130
2131 void do_efdcfui (void)
2132 {
2133 T0_64 = _do_efdcfui(T0_64);
2134 }
2135
2136 void do_efdctsi (void)
2137 {
2138 T0_64 = _do_efdctsi(T0_64);
2139 }
2140
2141 void do_efdctui (void)
2142 {
2143 T0_64 = _do_efdctui(T0_64);
2144 }
2145
2146 void do_efdctsiz (void)
2147 {
2148 T0_64 = _do_efdctsiz(T0_64);
2149 }
2150
2151 void do_efdctuiz (void)
2152 {
2153 T0_64 = _do_efdctuiz(T0_64);
2154 }
2155
2156 /* Double precision floating-point conversion to/from fractional */
2157 static always_inline uint64_t _do_efdcfsf (int64_t val)
2158 {
2159 CPU_DoubleU u;
2160 float64 tmp;
2161
2162 u.d = int32_to_float64(val, &env->spe_status);
2163 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2164 u.d = float64_div(u.d, tmp, &env->spe_status);
2165
2166 return u.ll;
2167 }
2168
2169 static always_inline uint64_t _do_efdcfuf (uint64_t val)
2170 {
2171 CPU_DoubleU u;
2172 float64 tmp;
2173
2174 u.d = uint32_to_float64(val, &env->spe_status);
2175 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2176 u.d = float64_div(u.d, tmp, &env->spe_status);
2177
2178 return u.ll;
2179 }
2180
2181 static always_inline int64_t _do_efdctsf (uint64_t val)
2182 {
2183 CPU_DoubleU u;
2184 float64 tmp;
2185
2186 u.ll = val;
2187 /* NaN are not treated the same way IEEE 754 does */
2188 if (unlikely(isnan(u.d)))
2189 return 0;
2190 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2191 u.d = float64_mul(u.d, tmp, &env->spe_status);
2192
2193 return float64_to_int32(u.d, &env->spe_status);
2194 }
2195
2196 static always_inline uint64_t _do_efdctuf (uint64_t val)
2197 {
2198 CPU_DoubleU u;
2199 float64 tmp;
2200
2201 u.ll = val;
2202 /* NaN are not treated the same way IEEE 754 does */
2203 if (unlikely(isnan(u.d)))
2204 return 0;
2205 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2206 u.d = float64_mul(u.d, tmp, &env->spe_status);
2207
2208 return float64_to_uint32(u.d, &env->spe_status);
2209 }
2210
2211 static always_inline int64_t _do_efdctsfz (uint64_t val)
2212 {
2213 CPU_DoubleU u;
2214 float64 tmp;
2215
2216 u.ll = val;
2217 /* NaN are not treated the same way IEEE 754 does */
2218 if (unlikely(isnan(u.d)))
2219 return 0;
2220 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2221 u.d = float64_mul(u.d, tmp, &env->spe_status);
2222
2223 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2224 }
2225
2226 static always_inline uint64_t _do_efdctufz (uint64_t val)
2227 {
2228 CPU_DoubleU u;
2229 float64 tmp;
2230
2231 u.ll = val;
2232 /* NaN are not treated the same way IEEE 754 does */
2233 if (unlikely(isnan(u.d)))
2234 return 0;
2235 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2236 u.d = float64_mul(u.d, tmp, &env->spe_status);
2237
2238 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2239 }
2240
2241 void do_efdcfsf (void)
2242 {
2243 T0_64 = _do_efdcfsf(T0_64);
2244 }
2245
2246 void do_efdcfuf (void)
2247 {
2248 T0_64 = _do_efdcfuf(T0_64);
2249 }
2250
2251 void do_efdctsf (void)
2252 {
2253 T0_64 = _do_efdctsf(T0_64);
2254 }
2255
2256 void do_efdctuf (void)
2257 {
2258 T0_64 = _do_efdctuf(T0_64);
2259 }
2260
2261 void do_efdctsfz (void)
2262 {
2263 T0_64 = _do_efdctsfz(T0_64);
2264 }
2265
2266 void do_efdctufz (void)
2267 {
2268 T0_64 = _do_efdctufz(T0_64);
2269 }
2270
2271 /* Floating point conversion between single and double precision */
2272 static always_inline uint32_t _do_efscfd (uint64_t val)
2273 {
2274 CPU_DoubleU u1;
2275 CPU_FloatU u2;
2276
2277 u1.ll = val;
2278 u2.f = float64_to_float32(u1.d, &env->spe_status);
2279
2280 return u2.l;
2281 }
2282
2283 static always_inline uint64_t _do_efdcfs (uint32_t val)
2284 {
2285 CPU_DoubleU u2;
2286 CPU_FloatU u1;
2287
2288 u1.l = val;
2289 u2.d = float32_to_float64(u1.f, &env->spe_status);
2290
2291 return u2.ll;
2292 }
2293
2294 void do_efscfd (void)
2295 {
2296 T0_64 = _do_efscfd(T0_64);
2297 }
2298
2299 void do_efdcfs (void)
2300 {
2301 T0_64 = _do_efdcfs(T0_64);
2302 }
2303
2304 /* Single precision fixed-point vector arithmetic */
2305 /* evfsabs */
2306 DO_SPE_OP1(fsabs);
2307 /* evfsnabs */
2308 DO_SPE_OP1(fsnabs);
2309 /* evfsneg */
2310 DO_SPE_OP1(fsneg);
2311 /* evfsadd */
2312 DO_SPE_OP2(fsadd);
2313 /* evfssub */
2314 DO_SPE_OP2(fssub);
2315 /* evfsmul */
2316 DO_SPE_OP2(fsmul);
2317 /* evfsdiv */
2318 DO_SPE_OP2(fsdiv);
2319
2320 /* Single-precision floating-point comparisons */
2321 static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2322 {
2323 /* XXX: TODO: test special values (NaN, infinites, ...) */
2324 return _do_efststlt(op1, op2);
2325 }
2326
2327 static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2328 {
2329 /* XXX: TODO: test special values (NaN, infinites, ...) */
2330 return _do_efststgt(op1, op2);
2331 }
2332
2333 static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2334 {
2335 /* XXX: TODO: test special values (NaN, infinites, ...) */
2336 return _do_efststeq(op1, op2);
2337 }
2338
2339 void do_efscmplt (void)
2340 {
2341 T0 = _do_efscmplt(T0_64, T1_64);
2342 }
2343
2344 void do_efscmpgt (void)
2345 {
2346 T0 = _do_efscmpgt(T0_64, T1_64);
2347 }
2348
2349 void do_efscmpeq (void)
2350 {
2351 T0 = _do_efscmpeq(T0_64, T1_64);
2352 }
2353
2354 /* Single-precision floating-point vector comparisons */
2355 /* evfscmplt */
2356 DO_SPE_CMP(fscmplt);
2357 /* evfscmpgt */
2358 DO_SPE_CMP(fscmpgt);
2359 /* evfscmpeq */
2360 DO_SPE_CMP(fscmpeq);
2361 /* evfststlt */
2362 DO_SPE_CMP(fststlt);
2363 /* evfststgt */
2364 DO_SPE_CMP(fststgt);
2365 /* evfststeq */
2366 DO_SPE_CMP(fststeq);
2367
2368 /* Single-precision floating-point vector conversions */
2369 /* evfscfsi */
2370 DO_SPE_OP1(fscfsi);
2371 /* evfscfui */
2372 DO_SPE_OP1(fscfui);
2373 /* evfscfuf */
2374 DO_SPE_OP1(fscfuf);
2375 /* evfscfsf */
2376 DO_SPE_OP1(fscfsf);
2377 /* evfsctsi */
2378 DO_SPE_OP1(fsctsi);
2379 /* evfsctui */
2380 DO_SPE_OP1(fsctui);
2381 /* evfsctsiz */
2382 DO_SPE_OP1(fsctsiz);
2383 /* evfsctuiz */
2384 DO_SPE_OP1(fsctuiz);
2385 /* evfsctsf */
2386 DO_SPE_OP1(fsctsf);
2387 /* evfsctuf */
2388 DO_SPE_OP1(fsctuf);
2389
2390 /*****************************************************************************/
2391 /* Softmmu support */
2392 #if !defined (CONFIG_USER_ONLY)
2393
2394 #define MMUSUFFIX _mmu
2395
2396 #define SHIFT 0
2397 #include "softmmu_template.h"
2398
2399 #define SHIFT 1
2400 #include "softmmu_template.h"
2401
2402 #define SHIFT 2
2403 #include "softmmu_template.h"
2404
2405 #define SHIFT 3
2406 #include "softmmu_template.h"
2407
2408 /* try to fill the TLB and return an exception if error. If retaddr is
2409 NULL, it means that the function was called in C code (i.e. not
2410 from generated code or from helper.c) */
2411 /* XXX: fix it to restore all registers */
2412 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2413 {
2414 TranslationBlock *tb;
2415 CPUState *saved_env;
2416 unsigned long pc;
2417 int ret;
2418
2419 /* XXX: hack to restore env in all cases, even if not called from
2420 generated code */
2421 saved_env = env;
2422 env = cpu_single_env;
2423 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2424 if (unlikely(ret != 0)) {
2425 if (likely(retaddr)) {
2426 /* now we have a real cpu fault */
2427 pc = (unsigned long)retaddr;
2428 tb = tb_find_pc(pc);
2429 if (likely(tb)) {
2430 /* the PC is inside the translated code. It means that we have
2431 a virtual CPU fault */
2432 cpu_restore_state(tb, env, pc, NULL);
2433 }
2434 }
2435 do_raise_exception_err(env->exception_index, env->error_code);
2436 }
2437 env = saved_env;
2438 }
2439
2440 /* Software driven TLBs management */
2441 /* PowerPC 602/603 software TLB load instructions helpers */
2442 void do_load_6xx_tlb (int is_code)
2443 {
2444 target_ulong RPN, CMP, EPN;
2445 int way;
2446
2447 RPN = env->spr[SPR_RPA];
2448 if (is_code) {
2449 CMP = env->spr[SPR_ICMP];
2450 EPN = env->spr[SPR_IMISS];
2451 } else {
2452 CMP = env->spr[SPR_DCMP];
2453 EPN = env->spr[SPR_DMISS];
2454 }
2455 way = (env->spr[SPR_SRR1] >> 17) & 1;
2456 #if defined (DEBUG_SOFTWARE_TLB)
2457 if (loglevel != 0) {
2458 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2459 " PTE1 " ADDRX " way %d\n",
2460 __func__, T0, EPN, CMP, RPN, way);
2461 }
2462 #endif
2463 /* Store this TLB */
2464 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2465 way, is_code, CMP, RPN);
2466 }
2467
2468 void do_load_74xx_tlb (int is_code)
2469 {
2470 target_ulong RPN, CMP, EPN;
2471 int way;
2472
2473 RPN = env->spr[SPR_PTELO];
2474 CMP = env->spr[SPR_PTEHI];
2475 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2476 way = env->spr[SPR_TLBMISS] & 0x3;
2477 #if defined (DEBUG_SOFTWARE_TLB)
2478 if (loglevel != 0) {
2479 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2480 " PTE1 " ADDRX " way %d\n",
2481 __func__, T0, EPN, CMP, RPN, way);
2482 }
2483 #endif
2484 /* Store this TLB */
2485 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2486 way, is_code, CMP, RPN);
2487 }
2488
2489 static always_inline target_ulong booke_tlb_to_page_size (int size)
2490 {
2491 return 1024 << (2 * size);
2492 }
2493
2494 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2495 {
2496 int size;
2497
2498 switch (page_size) {
2499 case 0x00000400UL:
2500 size = 0x0;
2501 break;
2502 case 0x00001000UL:
2503 size = 0x1;
2504 break;
2505 case 0x00004000UL:
2506 size = 0x2;
2507 break;
2508 case 0x00010000UL:
2509 size = 0x3;
2510 break;
2511 case 0x00040000UL:
2512 size = 0x4;
2513 break;
2514 case 0x00100000UL:
2515 size = 0x5;
2516 break;
2517 case 0x00400000UL:
2518 size = 0x6;
2519 break;
2520 case 0x01000000UL:
2521 size = 0x7;
2522 break;
2523 case 0x04000000UL:
2524 size = 0x8;
2525 break;
2526 case 0x10000000UL:
2527 size = 0x9;
2528 break;
2529 case 0x40000000UL:
2530 size = 0xA;
2531 break;
2532 #if defined (TARGET_PPC64)
2533 case 0x000100000000ULL:
2534 size = 0xB;
2535 break;
2536 case 0x000400000000ULL:
2537 size = 0xC;
2538 break;
2539 case 0x001000000000ULL:
2540 size = 0xD;
2541 break;
2542 case 0x004000000000ULL:
2543 size = 0xE;
2544 break;
2545 case 0x010000000000ULL:
2546 size = 0xF;
2547 break;
2548 #endif
2549 default:
2550 size = -1;
2551 break;
2552 }
2553
2554 return size;
2555 }
2556
2557 /* Helpers for 4xx TLB management */
2558 void do_4xx_tlbre_lo (void)
2559 {
2560 ppcemb_tlb_t *tlb;
2561 int size;
2562
2563 T0 &= 0x3F;
2564 tlb = &env->tlb[T0].tlbe;
2565 T0 = tlb->EPN;
2566 if (tlb->prot & PAGE_VALID)
2567 T0 |= 0x400;
2568 size = booke_page_size_to_tlb(tlb->size);
2569 if (size < 0 || size > 0x7)
2570 size = 1;
2571 T0 |= size << 7;
2572 env->spr[SPR_40x_PID] = tlb->PID;
2573 }
2574
2575 void do_4xx_tlbre_hi (void)
2576 {
2577 ppcemb_tlb_t *tlb;
2578
2579 T0 &= 0x3F;
2580 tlb = &env->tlb[T0].tlbe;
2581 T0 = tlb->RPN;
2582 if (tlb->prot & PAGE_EXEC)
2583 T0 |= 0x200;
2584 if (tlb->prot & PAGE_WRITE)
2585 T0 |= 0x100;
2586 }
2587
2588 void do_4xx_tlbwe_hi (void)
2589 {
2590 ppcemb_tlb_t *tlb;
2591 target_ulong page, end;
2592
2593 #if defined (DEBUG_SOFTWARE_TLB)
2594 if (loglevel != 0) {
2595 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2596 }
2597 #endif
2598 T0 &= 0x3F;
2599 tlb = &env->tlb[T0].tlbe;
2600 /* Invalidate previous TLB (if it's valid) */
2601 if (tlb->prot & PAGE_VALID) {
2602 end = tlb->EPN + tlb->size;
2603 #if defined (DEBUG_SOFTWARE_TLB)
2604 if (loglevel != 0) {
2605 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2606 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2607 }
2608 #endif
2609 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2610 tlb_flush_page(env, page);
2611 }
2612 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2613 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2614 * If this ever occurs, one should use the ppcemb target instead
2615 * of the ppc or ppc64 one
2616 */
2617 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2618 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2619 "are not supported (%d)\n",
2620 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2621 }
2622 tlb->EPN = T1 & ~(tlb->size - 1);
2623 if (T1 & 0x40)
2624 tlb->prot |= PAGE_VALID;
2625 else
2626 tlb->prot &= ~PAGE_VALID;
2627 if (T1 & 0x20) {
2628 /* XXX: TO BE FIXED */
2629 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2630 }
2631 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2632 tlb->attr = T1 & 0xFF;
2633 #if defined (DEBUG_SOFTWARE_TLB)
2634 if (loglevel != 0) {
2635 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2636 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2637 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2638 tlb->prot & PAGE_READ ? 'r' : '-',
2639 tlb->prot & PAGE_WRITE ? 'w' : '-',
2640 tlb->prot & PAGE_EXEC ? 'x' : '-',
2641 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2642 }
2643 #endif
2644 /* Invalidate new TLB (if valid) */
2645 if (tlb->prot & PAGE_VALID) {
2646 end = tlb->EPN + tlb->size;
2647 #if defined (DEBUG_SOFTWARE_TLB)
2648 if (loglevel != 0) {
2649 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2650 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2651 }
2652 #endif
2653 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2654 tlb_flush_page(env, page);
2655 }
2656 }
2657
2658 void do_4xx_tlbwe_lo (void)
2659 {
2660 ppcemb_tlb_t *tlb;
2661
2662 #if defined (DEBUG_SOFTWARE_TLB)
2663 if (loglevel != 0) {
2664 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2665 }
2666 #endif
2667 T0 &= 0x3F;
2668 tlb = &env->tlb[T0].tlbe;
2669 tlb->RPN = T1 & 0xFFFFFC00;
2670 tlb->prot = PAGE_READ;
2671 if (T1 & 0x200)
2672 tlb->prot |= PAGE_EXEC;
2673 if (T1 & 0x100)
2674 tlb->prot |= PAGE_WRITE;
2675 #if defined (DEBUG_SOFTWARE_TLB)
2676 if (loglevel != 0) {
2677 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2678 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2679 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2680 tlb->prot & PAGE_READ ? 'r' : '-',
2681 tlb->prot & PAGE_WRITE ? 'w' : '-',
2682 tlb->prot & PAGE_EXEC ? 'x' : '-',
2683 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2684 }
2685 #endif
2686 }
2687
2688 /* PowerPC 440 TLB management */
2689 void do_440_tlbwe (int word)
2690 {
2691 ppcemb_tlb_t *tlb;
2692 target_ulong EPN, RPN, size;
2693 int do_flush_tlbs;
2694
2695 #if defined (DEBUG_SOFTWARE_TLB)
2696 if (loglevel != 0) {
2697 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2698 __func__, word, T0, T1);
2699 }
2700 #endif
2701 do_flush_tlbs = 0;
2702 T0 &= 0x3F;
2703 tlb = &env->tlb[T0].tlbe;
2704 switch (word) {
2705 default:
2706 /* Just here to please gcc */
2707 case 0:
2708 EPN = T1 & 0xFFFFFC00;
2709 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2710 do_flush_tlbs = 1;
2711 tlb->EPN = EPN;
2712 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2713 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2714 do_flush_tlbs = 1;
2715 tlb->size = size;
2716 tlb->attr &= ~0x1;
2717 tlb->attr |= (T1 >> 8) & 1;
2718 if (T1 & 0x200) {
2719 tlb->prot |= PAGE_VALID;
2720 } else {
2721 if (tlb->prot & PAGE_VALID) {
2722 tlb->prot &= ~PAGE_VALID;
2723 do_flush_tlbs = 1;
2724 }
2725 }
2726 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2727 if (do_flush_tlbs)
2728 tlb_flush(env, 1);
2729 break;
2730 case 1:
2731 RPN = T1 & 0xFFFFFC0F;
2732 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2733 tlb_flush(env, 1);
2734 tlb->RPN = RPN;
2735 break;
2736 case 2:
2737 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2738 tlb->prot = tlb->prot & PAGE_VALID;
2739 if (T1 & 0x1)
2740 tlb->prot |= PAGE_READ << 4;
2741 if (T1 & 0x2)
2742 tlb->prot |= PAGE_WRITE << 4;
2743 if (T1 & 0x4)
2744 tlb->prot |= PAGE_EXEC << 4;
2745 if (T1 & 0x8)
2746 tlb->prot |= PAGE_READ;
2747 if (T1 & 0x10)
2748 tlb->prot |= PAGE_WRITE;
2749 if (T1 & 0x20)
2750 tlb->prot |= PAGE_EXEC;
2751 break;
2752 }
2753 }
2754
2755 void do_440_tlbre (int word)
2756 {
2757 ppcemb_tlb_t *tlb;
2758 int size;
2759
2760 T0 &= 0x3F;
2761 tlb = &env->tlb[T0].tlbe;
2762 switch (word) {
2763 default:
2764 /* Just here to please gcc */
2765 case 0:
2766 T0 = tlb->EPN;
2767 size = booke_page_size_to_tlb(tlb->size);
2768 if (size < 0 || size > 0xF)
2769 size = 1;
2770 T0 |= size << 4;
2771 if (tlb->attr & 0x1)
2772 T0 |= 0x100;
2773 if (tlb->prot & PAGE_VALID)
2774 T0 |= 0x200;
2775 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2776 env->spr[SPR_440_MMUCR] |= tlb->PID;
2777 break;
2778 case 1:
2779 T0 = tlb->RPN;
2780 break;
2781 case 2:
2782 T0 = tlb->attr & ~0x1;
2783 if (tlb->prot & (PAGE_READ << 4))
2784 T0 |= 0x1;
2785 if (tlb->prot & (PAGE_WRITE << 4))
2786 T0 |= 0x2;
2787 if (tlb->prot & (PAGE_EXEC << 4))
2788 T0 |= 0x4;
2789 if (tlb->prot & PAGE_READ)
2790 T0 |= 0x8;
2791 if (tlb->prot & PAGE_WRITE)
2792 T0 |= 0x10;
2793 if (tlb->prot & PAGE_EXEC)
2794 T0 |= 0x20;
2795 break;
2796 }
2797 }
2798 #endif /* !CONFIG_USER_ONLY */
jz4740 based target emulation