More TCG updates for CRIS
[qemu/qemu-JZ.git] / target-i386 / machine.c
blobf88d5ed811f0ae9b35d98b8b8e45c04447c4fcc9
1 #include "hw/hw.h"
2 #include "hw/boards.h"
3 #include "hw/pc.h"
4 #include "hw/isa.h"
6 #include "exec-all.h"
8 void register_machines(void)
10 qemu_register_machine(&pc_machine);
11 qemu_register_machine(&isapc_machine);
14 static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
16 qemu_put_be32(f, dt->selector);
17 qemu_put_betl(f, dt->base);
18 qemu_put_be32(f, dt->limit);
19 qemu_put_be32(f, dt->flags);
22 static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
24 dt->selector = qemu_get_be32(f);
25 dt->base = qemu_get_betl(f);
26 dt->limit = qemu_get_be32(f);
27 dt->flags = qemu_get_be32(f);
30 void cpu_save(QEMUFile *f, void *opaque)
32 CPUState *env = opaque;
33 uint16_t fptag, fpus, fpuc, fpregs_format;
34 uint32_t hflags;
35 int32_t a20_mask;
36 int i;
38 for(i = 0; i < CPU_NB_REGS; i++)
39 qemu_put_betls(f, &env->regs[i]);
40 qemu_put_betls(f, &env->eip);
41 qemu_put_betls(f, &env->eflags);
42 hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
43 qemu_put_be32s(f, &hflags);
45 /* FPU */
46 fpuc = env->fpuc;
47 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
48 fptag = 0;
49 for(i = 0; i < 8; i++) {
50 fptag |= ((!env->fptags[i]) << i);
53 qemu_put_be16s(f, &fpuc);
54 qemu_put_be16s(f, &fpus);
55 qemu_put_be16s(f, &fptag);
57 #ifdef USE_X86LDOUBLE
58 fpregs_format = 0;
59 #else
60 fpregs_format = 1;
61 #endif
62 qemu_put_be16s(f, &fpregs_format);
64 for(i = 0; i < 8; i++) {
65 #ifdef USE_X86LDOUBLE
67 uint64_t mant;
68 uint16_t exp;
69 /* we save the real CPU data (in case of MMX usage only 'mant'
70 contains the MMX register */
71 cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
72 qemu_put_be64(f, mant);
73 qemu_put_be16(f, exp);
75 #else
76 /* if we use doubles for float emulation, we save the doubles to
77 avoid losing information in case of MMX usage. It can give
78 problems if the image is restored on a CPU where long
79 doubles are used instead. */
80 qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
81 #endif
84 for(i = 0; i < 6; i++)
85 cpu_put_seg(f, &env->segs[i]);
86 cpu_put_seg(f, &env->ldt);
87 cpu_put_seg(f, &env->tr);
88 cpu_put_seg(f, &env->gdt);
89 cpu_put_seg(f, &env->idt);
91 qemu_put_be32s(f, &env->sysenter_cs);
92 qemu_put_be32s(f, &env->sysenter_esp);
93 qemu_put_be32s(f, &env->sysenter_eip);
95 qemu_put_betls(f, &env->cr[0]);
96 qemu_put_betls(f, &env->cr[2]);
97 qemu_put_betls(f, &env->cr[3]);
98 qemu_put_betls(f, &env->cr[4]);
100 for(i = 0; i < 8; i++)
101 qemu_put_betls(f, &env->dr[i]);
103 /* MMU */
104 a20_mask = (int32_t) env->a20_mask;
105 qemu_put_be32s(f, &a20_mask);
107 /* XMM */
108 qemu_put_be32s(f, &env->mxcsr);
109 for(i = 0; i < CPU_NB_REGS; i++) {
110 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
111 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
114 #ifdef TARGET_X86_64
115 qemu_put_be64s(f, &env->efer);
116 qemu_put_be64s(f, &env->star);
117 qemu_put_be64s(f, &env->lstar);
118 qemu_put_be64s(f, &env->cstar);
119 qemu_put_be64s(f, &env->fmask);
120 qemu_put_be64s(f, &env->kernelgsbase);
121 #endif
122 qemu_put_be32s(f, &env->smbase);
125 #ifdef USE_X86LDOUBLE
126 /* XXX: add that in a FPU generic layer */
127 union x86_longdouble {
128 uint64_t mant;
129 uint16_t exp;
132 #define MANTD1(fp) (fp & ((1LL << 52) - 1))
133 #define EXPBIAS1 1023
134 #define EXPD1(fp) ((fp >> 52) & 0x7FF)
135 #define SIGND1(fp) ((fp >> 32) & 0x80000000)
137 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
139 int e;
140 /* mantissa */
141 p->mant = (MANTD1(temp) << 11) | (1LL << 63);
142 /* exponent + sign */
143 e = EXPD1(temp) - EXPBIAS1 + 16383;
144 e |= SIGND1(temp) >> 16;
145 p->exp = e;
147 #endif
149 int cpu_load(QEMUFile *f, void *opaque, int version_id)
151 CPUState *env = opaque;
152 int i, guess_mmx;
153 uint32_t hflags;
154 uint16_t fpus, fpuc, fptag, fpregs_format;
155 int32_t a20_mask;
157 if (version_id != 3 && version_id != 4)
158 return -EINVAL;
159 for(i = 0; i < CPU_NB_REGS; i++)
160 qemu_get_betls(f, &env->regs[i]);
161 qemu_get_betls(f, &env->eip);
162 qemu_get_betls(f, &env->eflags);
163 qemu_get_be32s(f, &hflags);
165 qemu_get_be16s(f, &fpuc);
166 qemu_get_be16s(f, &fpus);
167 qemu_get_be16s(f, &fptag);
168 qemu_get_be16s(f, &fpregs_format);
170 /* NOTE: we cannot always restore the FPU state if the image come
171 from a host with a different 'USE_X86LDOUBLE' define. We guess
172 if we are in an MMX state to restore correctly in that case. */
173 guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
174 for(i = 0; i < 8; i++) {
175 uint64_t mant;
176 uint16_t exp;
178 switch(fpregs_format) {
179 case 0:
180 mant = qemu_get_be64(f);
181 exp = qemu_get_be16(f);
182 #ifdef USE_X86LDOUBLE
183 env->fpregs[i].d = cpu_set_fp80(mant, exp);
184 #else
185 /* difficult case */
186 if (guess_mmx)
187 env->fpregs[i].mmx.MMX_Q(0) = mant;
188 else
189 env->fpregs[i].d = cpu_set_fp80(mant, exp);
190 #endif
191 break;
192 case 1:
193 mant = qemu_get_be64(f);
194 #ifdef USE_X86LDOUBLE
196 union x86_longdouble *p;
197 /* difficult case */
198 p = (void *)&env->fpregs[i];
199 if (guess_mmx) {
200 p->mant = mant;
201 p->exp = 0xffff;
202 } else {
203 fp64_to_fp80(p, mant);
206 #else
207 env->fpregs[i].mmx.MMX_Q(0) = mant;
208 #endif
209 break;
210 default:
211 return -EINVAL;
215 env->fpuc = fpuc;
216 /* XXX: restore FPU round state */
217 env->fpstt = (fpus >> 11) & 7;
218 env->fpus = fpus & ~0x3800;
219 fptag ^= 0xff;
220 for(i = 0; i < 8; i++) {
221 env->fptags[i] = (fptag >> i) & 1;
224 for(i = 0; i < 6; i++)
225 cpu_get_seg(f, &env->segs[i]);
226 cpu_get_seg(f, &env->ldt);
227 cpu_get_seg(f, &env->tr);
228 cpu_get_seg(f, &env->gdt);
229 cpu_get_seg(f, &env->idt);
231 qemu_get_be32s(f, &env->sysenter_cs);
232 qemu_get_be32s(f, &env->sysenter_esp);
233 qemu_get_be32s(f, &env->sysenter_eip);
235 qemu_get_betls(f, &env->cr[0]);
236 qemu_get_betls(f, &env->cr[2]);
237 qemu_get_betls(f, &env->cr[3]);
238 qemu_get_betls(f, &env->cr[4]);
240 for(i = 0; i < 8; i++)
241 qemu_get_betls(f, &env->dr[i]);
243 /* MMU */
244 qemu_get_be32s(f, &a20_mask);
245 env->a20_mask = a20_mask;
247 qemu_get_be32s(f, &env->mxcsr);
248 for(i = 0; i < CPU_NB_REGS; i++) {
249 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
250 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
253 #ifdef TARGET_X86_64
254 qemu_get_be64s(f, &env->efer);
255 qemu_get_be64s(f, &env->star);
256 qemu_get_be64s(f, &env->lstar);
257 qemu_get_be64s(f, &env->cstar);
258 qemu_get_be64s(f, &env->fmask);
259 qemu_get_be64s(f, &env->kernelgsbase);
260 #endif
261 if (version_id >= 4)
262 qemu_get_be32s(f, &env->smbase);
264 /* XXX: compute hflags from scratch, except for CPL and IIF */
265 env->hflags = hflags;
266 tlb_flush(env, 1);
267 return 0;