target-arm/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3
   4 void register_machines(void)
   5 {
   6     qemu_register_machine(&integratorcp_machine);
   7     qemu_register_machine(&versatilepb_machine);
   8     qemu_register_machine(&versatileab_machine);
   9     qemu_register_machine(&realview_machine);
  10     qemu_register_machine(&akitapda_machine);
  11     qemu_register_machine(&spitzpda_machine);
  12     qemu_register_machine(&borzoipda_machine);
  13     qemu_register_machine(&terrierpda_machine);
  14     qemu_register_machine(&palmte_machine);
  15     qemu_register_machine(&n800_machine);
  16     qemu_register_machine(&lm3s811evb_machine);
  17     qemu_register_machine(&lm3s6965evb_machine);
  18     qemu_register_machine(&connex_machine);
  19     qemu_register_machine(&verdex_machine);
  20     qemu_register_machine(&mainstone2_machine);
  21     qemu_register_machine(&musicpal_machine);
  22 }
  23
  24 void cpu_save(QEMUFile *f, void *opaque)
  25 {
  26     int i;
  27     CPUARMState *env = (CPUARMState *)opaque;
  28
  29     for (i = 0; i < 16; i++) {
  30         qemu_put_be32(f, env->regs[i]);
  31     }
  32     qemu_put_be32(f, cpsr_read(env));
  33     qemu_put_be32(f, env->spsr);
  34     for (i = 0; i < 6; i++) {
  35         qemu_put_be32(f, env->banked_spsr[i]);
  36         qemu_put_be32(f, env->banked_r13[i]);
  37         qemu_put_be32(f, env->banked_r14[i]);
  38     }
  39     for (i = 0; i < 5; i++) {
  40         qemu_put_be32(f, env->usr_regs[i]);
  41         qemu_put_be32(f, env->fiq_regs[i]);
  42     }
  43     qemu_put_be32(f, env->cp15.c0_cpuid);
  44     qemu_put_be32(f, env->cp15.c0_cachetype);
  45     qemu_put_be32(f, env->cp15.c1_sys);
  46     qemu_put_be32(f, env->cp15.c1_coproc);
  47     qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
  48     qemu_put_be32(f, env->cp15.c2_base0);
  49     qemu_put_be32(f, env->cp15.c2_base1);
  50     qemu_put_be32(f, env->cp15.c2_mask);
  51     qemu_put_be32(f, env->cp15.c2_data);
  52     qemu_put_be32(f, env->cp15.c2_insn);
  53     qemu_put_be32(f, env->cp15.c3);
  54     qemu_put_be32(f, env->cp15.c5_insn);
  55     qemu_put_be32(f, env->cp15.c5_data);
  56     for (i = 0; i < 8; i++) {
  57         qemu_put_be32(f, env->cp15.c6_region[i]);
  58     }
  59     qemu_put_be32(f, env->cp15.c6_insn);
  60     qemu_put_be32(f, env->cp15.c6_data);
  61     qemu_put_be32(f, env->cp15.c9_insn);
  62     qemu_put_be32(f, env->cp15.c9_data);
  63     qemu_put_be32(f, env->cp15.c13_fcse);
  64     qemu_put_be32(f, env->cp15.c13_context);
  65     qemu_put_be32(f, env->cp15.c13_tls1);
  66     qemu_put_be32(f, env->cp15.c13_tls2);
  67     qemu_put_be32(f, env->cp15.c13_tls3);
  68     qemu_put_be32(f, env->cp15.c15_cpar);
  69
  70     qemu_put_be32(f, env->features);
  71
  72     if (arm_feature(env, ARM_FEATURE_VFP)) {
  73         for (i = 0;  i < 16; i++) {
  74             CPU_DoubleU u;
  75             u.d = env->vfp.regs[i];
  76             qemu_put_be32(f, u.l.upper);
  77             qemu_put_be32(f, u.l.lower);
  78         }
  79         for (i = 0; i < 16; i++) {
  80             qemu_put_be32(f, env->vfp.xregs[i]);
  81         }
  82
  83         /* TODO: Should use proper FPSCR access functions.  */
  84         qemu_put_be32(f, env->vfp.vec_len);
  85         qemu_put_be32(f, env->vfp.vec_stride);
  86
  87         if (arm_feature(env, ARM_FEATURE_VFP3)) {
  88             for (i = 16;  i < 32; i++) {
  89                 CPU_DoubleU u;
  90                 u.d = env->vfp.regs[i];
  91                 qemu_put_be32(f, u.l.upper);
  92                 qemu_put_be32(f, u.l.lower);
  93             }
  94         }
  95     }
  96
  97     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  98         for (i = 0; i < 16; i++) {
  99             qemu_put_be64(f, env->iwmmxt.regs[i]);
 100         }
 101         for (i = 0; i < 16; i++) {
 102             qemu_put_be32(f, env->iwmmxt.cregs[i]);
 103         }
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_M)) {
 107         qemu_put_be32(f, env->v7m.other_sp);
 108         qemu_put_be32(f, env->v7m.vecbase);
 109         qemu_put_be32(f, env->v7m.basepri);
 110         qemu_put_be32(f, env->v7m.control);
 111         qemu_put_be32(f, env->v7m.current_sp);
 112         qemu_put_be32(f, env->v7m.exception);
 113     }
 114 }
 115
 116 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 117 {
 118     CPUARMState *env = (CPUARMState *)opaque;
 119     int i;
 120
 121     if (version_id != ARM_CPU_SAVE_VERSION)
 122         return -EINVAL;
 123
 124     for (i = 0; i < 16; i++) {
 125         env->regs[i] = qemu_get_be32(f);
 126     }
 127     cpsr_write(env, qemu_get_be32(f), 0xffffffff);
 128     env->spsr = qemu_get_be32(f);
 129     for (i = 0; i < 6; i++) {
 130         env->banked_spsr[i] = qemu_get_be32(f);
 131         env->banked_r13[i] = qemu_get_be32(f);
 132         env->banked_r14[i] = qemu_get_be32(f);
 133     }
 134     for (i = 0; i < 5; i++) {
 135         env->usr_regs[i] = qemu_get_be32(f);
 136         env->fiq_regs[i] = qemu_get_be32(f);
 137     }
 138     env->cp15.c0_cpuid = qemu_get_be32(f);
 139     env->cp15.c0_cachetype = qemu_get_be32(f);
 140     env->cp15.c1_sys = qemu_get_be32(f);
 141     env->cp15.c1_coproc = qemu_get_be32(f);
 142     env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
 143     env->cp15.c2_base0 = qemu_get_be32(f);
 144     env->cp15.c2_base1 = qemu_get_be32(f);
 145     env->cp15.c2_mask = qemu_get_be32(f);
 146     env->cp15.c2_data = qemu_get_be32(f);
 147     env->cp15.c2_insn = qemu_get_be32(f);
 148     env->cp15.c3 = qemu_get_be32(f);
 149     env->cp15.c5_insn = qemu_get_be32(f);
 150     env->cp15.c5_data = qemu_get_be32(f);
 151     for (i = 0; i < 8; i++) {
 152         env->cp15.c6_region[i] = qemu_get_be32(f);
 153     }
 154     env->cp15.c6_insn = qemu_get_be32(f);
 155     env->cp15.c6_data = qemu_get_be32(f);
 156     env->cp15.c9_insn = qemu_get_be32(f);
 157     env->cp15.c9_data = qemu_get_be32(f);
 158     env->cp15.c13_fcse = qemu_get_be32(f);
 159     env->cp15.c13_context = qemu_get_be32(f);
 160     env->cp15.c13_tls1 = qemu_get_be32(f);
 161     env->cp15.c13_tls2 = qemu_get_be32(f);
 162     env->cp15.c13_tls3 = qemu_get_be32(f);
 163     env->cp15.c15_cpar = qemu_get_be32(f);
 164
 165     env->features = qemu_get_be32(f);
 166
 167     if (arm_feature(env, ARM_FEATURE_VFP)) {
 168         for (i = 0;  i < 16; i++) {
 169             CPU_DoubleU u;
 170             u.l.upper = qemu_get_be32(f);
 171             u.l.lower = qemu_get_be32(f);
 172             env->vfp.regs[i] = u.d;
 173         }
 174         for (i = 0; i < 16; i++) {
 175             env->vfp.xregs[i] = qemu_get_be32(f);
 176         }
 177
 178         /* TODO: Should use proper FPSCR access functions.  */
 179         env->vfp.vec_len = qemu_get_be32(f);
 180         env->vfp.vec_stride = qemu_get_be32(f);
 181
 182         if (arm_feature(env, ARM_FEATURE_VFP3)) {
 183             for (i = 0;  i < 16; i++) {
 184                 CPU_DoubleU u;
 185                 u.l.upper = qemu_get_be32(f);
 186                 u.l.lower = qemu_get_be32(f);
 187                 env->vfp.regs[i] = u.d;
 188             }
 189         }
 190     }
 191
 192     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 193         for (i = 0; i < 16; i++) {
 194             env->iwmmxt.regs[i] = qemu_get_be64(f);
 195         }
 196         for (i = 0; i < 16; i++) {
 197             env->iwmmxt.cregs[i] = qemu_get_be32(f);
 198         }
 199     }
 200
 201     if (arm_feature(env, ARM_FEATURE_M)) {
 202         env->v7m.other_sp = qemu_get_be32(f);
 203         env->v7m.vecbase = qemu_get_be32(f);
 204         env->v7m.basepri = qemu_get_be32(f);
 205         env->v7m.control = qemu_get_be32(f);
 206         env->v7m.current_sp = qemu_get_be32(f);
 207         env->v7m.exception = qemu_get_be32(f);
 208     }
 209
 210     return 0;
 211 }
 212
 213