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CRIS: Remove X flag from tb flags.
[qemu/qemu-JZ.git] / hw / sun4m.c
blob6c7fa46fb1ef9bd58208fb49e0d80acaa06340da
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35
36 //#define DEBUG_IRQ
37
38 /*
39 * Sun4m architecture was used in the following machines:
40 *
41 * SPARCserver 6xxMP/xx
42 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
43 * SPARCstation LX/ZX (4/30)
44 * SPARCstation Voyager
45 * SPARCstation 10/xx, SPARCserver 10/xx
46 * SPARCstation 5, SPARCserver 5
47 * SPARCstation 20/xx, SPARCserver 20
48 * SPARCstation 4
49 *
50 * Sun4d architecture was used in the following machines:
51 *
52 * SPARCcenter 2000
53 * SPARCserver 1000
54 *
55 * Sun4c architecture was used in the following machines:
56 * SPARCstation 1/1+, SPARCserver 1/1+
57 * SPARCstation SLC
58 * SPARCstation IPC
59 * SPARCstation ELC
60 * SPARCstation IPX
61 *
62 * See for example: http://www.sunhelp.org/faq/sunref1.html
63 */
64
65 #ifdef DEBUG_IRQ
66 #define DPRINTF(fmt, args...) \
67 do { printf("CPUIRQ: " fmt , ##args); } while (0)
68 #else
69 #define DPRINTF(fmt, args...)
70 #endif
71
72 #define KERNEL_LOAD_ADDR 0x00004000
73 #define CMDLINE_ADDR 0x007ff000
74 #define INITRD_LOAD_ADDR 0x00800000
75 #define PROM_SIZE_MAX (512 * 1024)
76 #define PROM_VADDR 0xffd00000
77 #define PROM_FILENAME "openbios-sparc32"
78
79 // Control plane, 8-bit and 24-bit planes
80 #define TCX_SIZE (9 * 1024 * 1024)
81
82 #define MAX_CPUS 16
83 #define MAX_PILS 16
84
85 struct hwdef {
86 target_phys_addr_t iommu_base, slavio_base;
87 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
88 target_phys_addr_t serial_base, fd_base;
89 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
90 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
91 target_phys_addr_t ecc_base;
92 uint32_t ecc_version;
93 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
94 long vram_size, nvram_size;
95 // IRQ numbers are not PIL ones, but master interrupt controller
96 // register bit numbers
97 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
98 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
99 int machine_id; // For NVRAM
100 uint32_t iommu_version;
101 uint32_t intbit_to_level[32];
102 uint64_t max_mem;
103 const char * const default_cpu_model;
104 };
105
106 #define MAX_IOUNITS 5
107
108 struct sun4d_hwdef {
109 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
110 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
111 target_phys_addr_t serial_base;
112 target_phys_addr_t espdma_base, esp_base;
113 target_phys_addr_t ledma_base, le_base;
114 target_phys_addr_t tcx_base;
115 target_phys_addr_t sbi_base;
116 unsigned long vram_size, nvram_size;
117 // IRQ numbers are not PIL ones, but SBI register bit numbers
118 int esp_irq, le_irq, clock_irq, clock1_irq;
119 int ser_irq, ms_kb_irq, me_irq;
120 int machine_id; // For NVRAM
121 uint32_t iounit_version;
122 uint64_t max_mem;
123 const char * const default_cpu_model;
124 };
125
126 /* TSC handling */
127
128 uint64_t cpu_get_tsc()
129 {
130 return qemu_get_clock(vm_clock);
131 }
132
133 int DMA_get_channel_mode (int nchan)
134 {
135 return 0;
136 }
137 int DMA_read_memory (int nchan, void *buf, int pos, int size)
138 {
139 return 0;
140 }
141 int DMA_write_memory (int nchan, void *buf, int pos, int size)
142 {
143 return 0;
144 }
145 void DMA_hold_DREQ (int nchan) {}
146 void DMA_release_DREQ (int nchan) {}
147 void DMA_schedule(int nchan) {}
148 void DMA_run (void) {}
149 void DMA_init (int high_page_enable) {}
150 void DMA_register_channel (int nchan,
151 DMA_transfer_handler transfer_handler,
152 void *opaque)
153 {
154 }
155
156 extern int nographic;
157
158 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
159 const char *boot_devices, ram_addr_t RAM_size,
160 uint32_t kernel_size,
161 int width, int height, int depth,
162 int machine_id, const char *arch)
163 {
164 unsigned int i;
165 uint32_t start, end;
166 uint8_t image[0x1ff0];
167 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
168 struct sparc_arch_cfg *sparc_header;
169 struct OpenBIOS_nvpart_v1 *part_header;
170
171 memset(image, '\0', sizeof(image));
172
173 // Try to match PPC NVRAM
174 strcpy(header->struct_ident, "QEMU_BIOS");
175 header->struct_version = cpu_to_be32(3); /* structure v3 */
176
177 header->nvram_size = cpu_to_be16(0x2000);
178 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
179 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
180 strcpy(header->arch, arch);
181 header->nb_cpus = smp_cpus & 0xff;
182 header->RAM0_base = 0;
183 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
184 strcpy(header->boot_devices, boot_devices);
185 header->nboot_devices = strlen(boot_devices) & 0xff;
186 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
187 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
188 if (cmdline) {
189 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
190 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
191 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
192 }
193 // XXX add initrd_image, initrd_size
194 header->width = cpu_to_be16(width);
195 header->height = cpu_to_be16(height);
196 header->depth = cpu_to_be16(depth);
197 if (nographic)
198 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
199
200 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
201
202 // Architecture specific header
203 start = sizeof(ohwcfg_v3_t);
204 sparc_header = (struct sparc_arch_cfg *)&image[start];
205 sparc_header->valid = 0;
206 start += sizeof(struct sparc_arch_cfg);
207
208 // OpenBIOS nvram variables
209 // Variable partition
210 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
211 part_header->signature = OPENBIOS_PART_SYSTEM;
212 strcpy(part_header->name, "system");
213
214 end = start + sizeof(struct OpenBIOS_nvpart_v1);
215 for (i = 0; i < nb_prom_envs; i++)
216 end = OpenBIOS_set_var(image, end, prom_envs[i]);
217
218 // End marker
219 image[end++] = '\0';
220
221 end = start + ((end - start + 15) & ~15);
222 OpenBIOS_finish_partition(part_header, end - start);
223
224 // free partition
225 start = end;
226 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
227 part_header->signature = OPENBIOS_PART_FREE;
228 strcpy(part_header->name, "free");
229
230 end = 0x1fd0;
231 OpenBIOS_finish_partition(part_header, end - start);
232
233 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
234
235 for (i = 0; i < sizeof(image); i++)
236 m48t59_write(nvram, i, image[i]);
237 }
238
239 static void *slavio_intctl;
240
241 void pic_info()
242 {
243 if (slavio_intctl)
244 slavio_pic_info(slavio_intctl);
245 }
246
247 void irq_info()
248 {
249 if (slavio_intctl)
250 slavio_irq_info(slavio_intctl);
251 }
252
253 void cpu_check_irqs(CPUState *env)
254 {
255 if (env->pil_in && (env->interrupt_index == 0 ||
256 (env->interrupt_index & ~15) == TT_EXTINT)) {
257 unsigned int i;
258
259 for (i = 15; i > 0; i--) {
260 if (env->pil_in & (1 << i)) {
261 int old_interrupt = env->interrupt_index;
262
263 env->interrupt_index = TT_EXTINT | i;
264 if (old_interrupt != env->interrupt_index) {
265 DPRINTF("Set CPU IRQ %d\n", i);
266 cpu_interrupt(env, CPU_INTERRUPT_HARD);
267 }
268 break;
269 }
270 }
271 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
272 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
273 env->interrupt_index = 0;
274 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
275 }
276 }
277
278 static void cpu_set_irq(void *opaque, int irq, int level)
279 {
280 CPUState *env = opaque;
281
282 if (level) {
283 DPRINTF("Raise CPU IRQ %d\n", irq);
284 env->halted = 0;
285 env->pil_in |= 1 << irq;
286 cpu_check_irqs(env);
287 } else {
288 DPRINTF("Lower CPU IRQ %d\n", irq);
289 env->pil_in &= ~(1 << irq);
290 cpu_check_irqs(env);
291 }
292 }
293
294 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
295 {
296 }
297
298 static void *slavio_misc;
299
300 void qemu_system_powerdown(void)
301 {
302 slavio_set_power_fail(slavio_misc, 1);
303 }
304
305 static void main_cpu_reset(void *opaque)
306 {
307 CPUState *env = opaque;
308
309 cpu_reset(env);
310 env->halted = 0;
311 }
312
313 static void secondary_cpu_reset(void *opaque)
314 {
315 CPUState *env = opaque;
316
317 cpu_reset(env);
318 env->halted = 1;
319 }
320
321 static unsigned long sun4m_load_kernel(const char *kernel_filename,
322 const char *kernel_cmdline,
323 const char *initrd_filename)
324 {
325 int linux_boot;
326 unsigned int i;
327 long initrd_size, kernel_size;
328
329 linux_boot = (kernel_filename != NULL);
330
331 kernel_size = 0;
332 if (linux_boot) {
333 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
334 NULL);
335 if (kernel_size < 0)
336 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
337 if (kernel_size < 0)
338 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
348 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
349 if (initrd_size < 0) {
350 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
351 initrd_filename);
352 exit(1);
353 }
354 }
355 if (initrd_size > 0) {
356 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
357 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
358 == 0x48647253) { // HdrS
359 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
360 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
361 break;
362 }
363 }
364 }
365 }
366 return kernel_size;
367 }
368
369 static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
370 const char *boot_device,
371 DisplayState *ds, const char *kernel_filename,
372 const char *kernel_cmdline,
373 const char *initrd_filename, const char *cpu_model)
374
375 {
376 CPUState *env, *envs[MAX_CPUS];
377 unsigned int i;
378 void *iommu, *espdma, *ledma, *main_esp, *nvram;
379 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
380 *espdma_irq, *ledma_irq;
381 qemu_irq *esp_reset, *le_reset;
382 qemu_irq *fdc_tc;
383 unsigned long prom_offset, kernel_size;
384 int ret;
385 char buf[1024];
386 BlockDriverState *fd[MAX_FD];
387 int index;
388
389 /* init CPUs */
390 if (!cpu_model)
391 cpu_model = hwdef->default_cpu_model;
392
393 for(i = 0; i < smp_cpus; i++) {
394 env = cpu_init(cpu_model);
395 if (!env) {
396 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
397 exit(1);
398 }
399 cpu_sparc_set_id(env, i);
400 envs[i] = env;
401 if (i == 0) {
402 qemu_register_reset(main_cpu_reset, env);
403 } else {
404 qemu_register_reset(secondary_cpu_reset, env);
405 env->halted = 1;
406 }
407 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
408 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
409 env->prom_addr = hwdef->slavio_base;
410 }
411
412 for (i = smp_cpus; i < MAX_CPUS; i++)
413 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
414
415
416 /* allocate RAM */
417 if ((uint64_t)RAM_size > hwdef->max_mem) {
418 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
419 (unsigned int)(RAM_size / (1024 * 1024)),
420 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
421 exit(1);
422 }
423 cpu_register_physical_memory(0, RAM_size, 0);
424
425 /* load boot prom */
426 prom_offset = RAM_size + hwdef->vram_size;
427 cpu_register_physical_memory(hwdef->slavio_base,
428 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
429 TARGET_PAGE_MASK,
430 prom_offset | IO_MEM_ROM);
431
432 if (bios_name == NULL)
433 bios_name = PROM_FILENAME;
434 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
435 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
436 if (ret < 0 || ret > PROM_SIZE_MAX)
437 ret = load_image(buf, phys_ram_base + prom_offset);
438 if (ret < 0 || ret > PROM_SIZE_MAX) {
439 fprintf(stderr, "qemu: could not load prom '%s'\n",
440 buf);
441 exit(1);
442 }
443 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
444
445 /* set up devices */
446 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
447 hwdef->intctl_base + 0x10000ULL,
448 &hwdef->intbit_to_level[0],
449 &slavio_irq, &slavio_cpu_irq,
450 cpu_irqs,
451 hwdef->clock_irq);
452
453 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
454 stl_raw(phys_ram_base + prom_offset, 0xfe810103);
455
456 cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t),
457 prom_offset | IO_MEM_ROM);
458 }
459
460 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
461 slavio_irq[hwdef->me_irq]);
462
463 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
464 iommu, &espdma_irq, &esp_reset);
465
466 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
467 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
468 &le_reset);
469
470 if (graphic_depth != 8 && graphic_depth != 24) {
471 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
472 exit (1);
473 }
474 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
475 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
476
477 if (nd_table[0].model == NULL
478 || strcmp(nd_table[0].model, "lance") == 0) {
479 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
480 } else if (strcmp(nd_table[0].model, "?") == 0) {
481 fprintf(stderr, "qemu: Supported NICs: lance\n");
482 exit (1);
483 } else {
484 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
485 exit (1);
486 }
487
488 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
489 hwdef->nvram_size, 8);
490
491 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
492 slavio_cpu_irq, smp_cpus);
493
494 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
495 nographic);
496 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
497 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
498 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
499 serial_hds[1], serial_hds[0]);
500
501 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
502 hwdef->aux1_base, hwdef->aux2_base,
503 slavio_irq[hwdef->me_irq], envs[0],
504 &fdc_tc);
505
506 if (hwdef->fd_base != (target_phys_addr_t)-1) {
507 /* there is zero or one floppy drive */
508 memset(fd, 0, sizeof(fd));
509 index = drive_get_index(IF_FLOPPY, 0, 0);
510 if (index != -1)
511 fd[0] = drives_table[index].bdrv;
512
513 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
514 fdc_tc);
515 }
516
517 if (drive_get_max_bus(IF_SCSI) > 0) {
518 fprintf(stderr, "qemu: too many SCSI bus\n");
519 exit(1);
520 }
521
522 main_esp = esp_init(hwdef->esp_base, 2,
523 espdma_memory_read, espdma_memory_write,
524 espdma, *espdma_irq, esp_reset);
525
526 for (i = 0; i < ESP_MAX_DEVS; i++) {
527 index = drive_get_index(IF_SCSI, 0, i);
528 if (index == -1)
529 continue;
530 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
531 }
532
533 if (hwdef->cs_base != (target_phys_addr_t)-1)
534 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
535
536 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
537 initrd_filename);
538
539 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
540 boot_device, RAM_size, kernel_size, graphic_width,
541 graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
542
543 if (hwdef->ecc_base != (target_phys_addr_t)-1)
544 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
545 hwdef->ecc_version);
546 }
547
548 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
549 const char *boot_device,
550 DisplayState *ds, const char *kernel_filename,
551 const char *kernel_cmdline,
552 const char *initrd_filename, const char *cpu_model)
553 {
554 CPUState *env;
555 unsigned int i;
556 void *iommu, *espdma, *ledma, *main_esp, *nvram;
557 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
558 qemu_irq *esp_reset, *le_reset;
559 qemu_irq *fdc_tc;
560 unsigned long prom_offset, kernel_size;
561 int ret;
562 char buf[1024];
563 BlockDriverState *fd[MAX_FD];
564 int index;
565
566 /* init CPU */
567 if (!cpu_model)
568 cpu_model = hwdef->default_cpu_model;
569
570 env = cpu_init(cpu_model);
571 if (!env) {
572 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
573 exit(1);
574 }
575
576 cpu_sparc_set_id(env, 0);
577
578 qemu_register_reset(main_cpu_reset, env);
579 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
580 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
581 env->prom_addr = hwdef->slavio_base;
582
583 /* allocate RAM */
584 if ((uint64_t)RAM_size > hwdef->max_mem) {
585 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
586 (unsigned int)(RAM_size / (1024 * 1024)),
587 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
588 exit(1);
589 }
590 cpu_register_physical_memory(0, RAM_size, 0);
591
592 /* load boot prom */
593 prom_offset = RAM_size + hwdef->vram_size;
594 cpu_register_physical_memory(hwdef->slavio_base,
595 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
596 TARGET_PAGE_MASK,
597 prom_offset | IO_MEM_ROM);
598
599 if (bios_name == NULL)
600 bios_name = PROM_FILENAME;
601 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
602 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
603 if (ret < 0 || ret > PROM_SIZE_MAX)
604 ret = load_image(buf, phys_ram_base + prom_offset);
605 if (ret < 0 || ret > PROM_SIZE_MAX) {
606 fprintf(stderr, "qemu: could not load prom '%s'\n",
607 buf);
608 exit(1);
609 }
610 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
611
612 /* set up devices */
613 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
614 &slavio_irq, cpu_irqs);
615
616 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
617 slavio_irq[hwdef->me_irq]);
618
619 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
620 iommu, &espdma_irq, &esp_reset);
621
622 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
623 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
624 &le_reset);
625
626 if (graphic_depth != 8 && graphic_depth != 24) {
627 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
628 exit (1);
629 }
630 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
631 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
632
633 if (nd_table[0].model == NULL
634 || strcmp(nd_table[0].model, "lance") == 0) {
635 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
636 } else if (strcmp(nd_table[0].model, "?") == 0) {
637 fprintf(stderr, "qemu: Supported NICs: lance\n");
638 exit (1);
639 } else {
640 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
641 exit (1);
642 }
643
644 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
645 hwdef->nvram_size, 2);
646
647 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
648 nographic);
649 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
650 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
651 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
652 serial_hds[1], serial_hds[0]);
653
654 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
655 hwdef->aux1_base, hwdef->aux2_base,
656 slavio_irq[hwdef->me_irq], env, &fdc_tc);
657
658 if (hwdef->fd_base != (target_phys_addr_t)-1) {
659 /* there is zero or one floppy drive */
660 fd[1] = fd[0] = NULL;
661 index = drive_get_index(IF_FLOPPY, 0, 0);
662 if (index != -1)
663 fd[0] = drives_table[index].bdrv;
664
665 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
666 fdc_tc);
667 }
668
669 if (drive_get_max_bus(IF_SCSI) > 0) {
670 fprintf(stderr, "qemu: too many SCSI bus\n");
671 exit(1);
672 }
673
674 main_esp = esp_init(hwdef->esp_base, 2,
675 espdma_memory_read, espdma_memory_write,
676 espdma, *espdma_irq, esp_reset);
677
678 for (i = 0; i < ESP_MAX_DEVS; i++) {
679 index = drive_get_index(IF_SCSI, 0, i);
680 if (index == -1)
681 continue;
682 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
683 }
684
685 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
686 initrd_filename);
687
688 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
689 boot_device, RAM_size, kernel_size, graphic_width,
690 graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
691 }
692
693 static const struct hwdef hwdefs[] = {
694 /* SS-5 */
695 {
696 .iommu_base = 0x10000000,
697 .tcx_base = 0x50000000,
698 .cs_base = 0x6c000000,
699 .slavio_base = 0x70000000,
700 .ms_kb_base = 0x71000000,
701 .serial_base = 0x71100000,
702 .nvram_base = 0x71200000,
703 .fd_base = 0x71400000,
704 .counter_base = 0x71d00000,
705 .intctl_base = 0x71e00000,
706 .idreg_base = 0x78000000,
707 .dma_base = 0x78400000,
708 .esp_base = 0x78800000,
709 .le_base = 0x78c00000,
710 .apc_base = 0x6a000000,
711 .aux1_base = 0x71900000,
712 .aux2_base = 0x71910000,
713 .ecc_base = -1,
714 .sun4c_intctl_base = -1,
715 .sun4c_counter_base = -1,
716 .vram_size = 0x00100000,
717 .nvram_size = 0x2000,
718 .esp_irq = 18,
719 .le_irq = 16,
720 .clock_irq = 7,
721 .clock1_irq = 19,
722 .ms_kb_irq = 14,
723 .ser_irq = 15,
724 .fd_irq = 22,
725 .me_irq = 30,
726 .cs_irq = 5,
727 .machine_id = 0x80,
728 .iommu_version = 0x05000000,
729 .intbit_to_level = {
730 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
731 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
732 },
733 .max_mem = 0x10000000,
734 .default_cpu_model = "Fujitsu MB86904",
735 },
736 /* SS-10 */
737 {
738 .iommu_base = 0xfe0000000ULL,
739 .tcx_base = 0xe20000000ULL,
740 .cs_base = -1,
741 .slavio_base = 0xff0000000ULL,
742 .ms_kb_base = 0xff1000000ULL,
743 .serial_base = 0xff1100000ULL,
744 .nvram_base = 0xff1200000ULL,
745 .fd_base = 0xff1700000ULL,
746 .counter_base = 0xff1300000ULL,
747 .intctl_base = 0xff1400000ULL,
748 .idreg_base = 0xef0000000ULL,
749 .dma_base = 0xef0400000ULL,
750 .esp_base = 0xef0800000ULL,
751 .le_base = 0xef0c00000ULL,
752 .apc_base = 0xefa000000ULL, // XXX should not exist
753 .aux1_base = 0xff1800000ULL,
754 .aux2_base = 0xff1a01000ULL,
755 .ecc_base = 0xf00000000ULL,
756 .ecc_version = 0x10000000, // version 0, implementation 1
757 .sun4c_intctl_base = -1,
758 .sun4c_counter_base = -1,
759 .vram_size = 0x00100000,
760 .nvram_size = 0x2000,
761 .esp_irq = 18,
762 .le_irq = 16,
763 .clock_irq = 7,
764 .clock1_irq = 19,
765 .ms_kb_irq = 14,
766 .ser_irq = 15,
767 .fd_irq = 22,
768 .me_irq = 30,
769 .cs_irq = -1,
770 .ecc_irq = 28,
771 .machine_id = 0x72,
772 .iommu_version = 0x03000000,
773 .intbit_to_level = {
774 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
775 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
776 },
777 .max_mem = 0xf00000000ULL,
778 .default_cpu_model = "TI SuperSparc II",
779 },
780 /* SS-600MP */
781 {
782 .iommu_base = 0xfe0000000ULL,
783 .tcx_base = 0xe20000000ULL,
784 .cs_base = -1,
785 .slavio_base = 0xff0000000ULL,
786 .ms_kb_base = 0xff1000000ULL,
787 .serial_base = 0xff1100000ULL,
788 .nvram_base = 0xff1200000ULL,
789 .fd_base = -1,
790 .counter_base = 0xff1300000ULL,
791 .intctl_base = 0xff1400000ULL,
792 .idreg_base = -1,
793 .dma_base = 0xef0081000ULL,
794 .esp_base = 0xef0080000ULL,
795 .le_base = 0xef0060000ULL,
796 .apc_base = 0xefa000000ULL, // XXX should not exist
797 .aux1_base = 0xff1800000ULL,
798 .aux2_base = 0xff1a01000ULL, // XXX should not exist
799 .ecc_base = 0xf00000000ULL,
800 .ecc_version = 0x00000000, // version 0, implementation 0
801 .sun4c_intctl_base = -1,
802 .sun4c_counter_base = -1,
803 .vram_size = 0x00100000,
804 .nvram_size = 0x2000,
805 .esp_irq = 18,
806 .le_irq = 16,
807 .clock_irq = 7,
808 .clock1_irq = 19,
809 .ms_kb_irq = 14,
810 .ser_irq = 15,
811 .fd_irq = 22,
812 .me_irq = 30,
813 .cs_irq = -1,
814 .ecc_irq = 28,
815 .machine_id = 0x71,
816 .iommu_version = 0x01000000,
817 .intbit_to_level = {
818 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
819 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
820 },
821 .max_mem = 0xf00000000ULL,
822 .default_cpu_model = "TI SuperSparc II",
823 },
824 /* SS-20 */
825 {
826 .iommu_base = 0xfe0000000ULL,
827 .tcx_base = 0xe20000000ULL,
828 .cs_base = -1,
829 .slavio_base = 0xff0000000ULL,
830 .ms_kb_base = 0xff1000000ULL,
831 .serial_base = 0xff1100000ULL,
832 .nvram_base = 0xff1200000ULL,
833 .fd_base = 0xff1700000ULL,
834 .counter_base = 0xff1300000ULL,
835 .intctl_base = 0xff1400000ULL,
836 .idreg_base = 0xef0000000ULL,
837 .dma_base = 0xef0400000ULL,
838 .esp_base = 0xef0800000ULL,
839 .le_base = 0xef0c00000ULL,
840 .apc_base = 0xefa000000ULL, // XXX should not exist
841 .aux1_base = 0xff1800000ULL,
842 .aux2_base = 0xff1a01000ULL,
843 .ecc_base = 0xf00000000ULL,
844 .ecc_version = 0x20000000, // version 0, implementation 2
845 .sun4c_intctl_base = -1,
846 .sun4c_counter_base = -1,
847 .vram_size = 0x00100000,
848 .nvram_size = 0x2000,
849 .esp_irq = 18,
850 .le_irq = 16,
851 .clock_irq = 7,
852 .clock1_irq = 19,
853 .ms_kb_irq = 14,
854 .ser_irq = 15,
855 .fd_irq = 22,
856 .me_irq = 30,
857 .cs_irq = -1,
858 .ecc_irq = 28,
859 .machine_id = 0x72,
860 .iommu_version = 0x13000000,
861 .intbit_to_level = {
862 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
863 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
864 },
865 .max_mem = 0xf00000000ULL,
866 .default_cpu_model = "TI SuperSparc II",
867 },
868 /* SS-2 */
869 {
870 .iommu_base = 0xf8000000,
871 .tcx_base = 0xfe000000,
872 .cs_base = -1,
873 .slavio_base = 0xf6000000,
874 .ms_kb_base = 0xf0000000,
875 .serial_base = 0xf1000000,
876 .nvram_base = 0xf2000000,
877 .fd_base = 0xf7200000,
878 .counter_base = -1,
879 .intctl_base = -1,
880 .dma_base = 0xf8400000,
881 .esp_base = 0xf8800000,
882 .le_base = 0xf8c00000,
883 .apc_base = -1,
884 .aux1_base = 0xf7400003,
885 .aux2_base = -1,
886 .sun4c_intctl_base = 0xf5000000,
887 .sun4c_counter_base = 0xf3000000,
888 .vram_size = 0x00100000,
889 .nvram_size = 0x800,
890 .esp_irq = 2,
891 .le_irq = 3,
892 .clock_irq = 5,
893 .clock1_irq = 7,
894 .ms_kb_irq = 1,
895 .ser_irq = 1,
896 .fd_irq = 1,
897 .me_irq = 1,
898 .cs_irq = -1,
899 .machine_id = 0x55,
900 .max_mem = 0x10000000,
901 .default_cpu_model = "Cypress CY7C601",
902 },
903 /* Voyager */
904 {
905 .iommu_base = 0x10000000,
906 .tcx_base = 0x50000000,
907 .cs_base = -1,
908 .slavio_base = 0x70000000,
909 .ms_kb_base = 0x71000000,
910 .serial_base = 0x71100000,
911 .nvram_base = 0x71200000,
912 .fd_base = 0x71400000,
913 .counter_base = 0x71d00000,
914 .intctl_base = 0x71e00000,
915 .idreg_base = 0x78000000,
916 .dma_base = 0x78400000,
917 .esp_base = 0x78800000,
918 .le_base = 0x78c00000,
919 .apc_base = 0x71300000, // pmc
920 .aux1_base = 0x71900000,
921 .aux2_base = 0x71910000,
922 .ecc_base = -1,
923 .sun4c_intctl_base = -1,
924 .sun4c_counter_base = -1,
925 .vram_size = 0x00100000,
926 .nvram_size = 0x2000,
927 .esp_irq = 18,
928 .le_irq = 16,
929 .clock_irq = 7,
930 .clock1_irq = 19,
931 .ms_kb_irq = 14,
932 .ser_irq = 15,
933 .fd_irq = 22,
934 .me_irq = 30,
935 .cs_irq = -1,
936 .machine_id = 0x80,
937 .iommu_version = 0x05000000,
938 .intbit_to_level = {
939 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
940 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
941 },
942 .max_mem = 0x10000000,
943 .default_cpu_model = "Fujitsu MB86904",
944 },
945 /* LX */
946 {
947 .iommu_base = 0x10000000,
948 .tcx_base = 0x50000000,
949 .cs_base = -1,
950 .slavio_base = 0x70000000,
951 .ms_kb_base = 0x71000000,
952 .serial_base = 0x71100000,
953 .nvram_base = 0x71200000,
954 .fd_base = 0x71400000,
955 .counter_base = 0x71d00000,
956 .intctl_base = 0x71e00000,
957 .idreg_base = 0x78000000,
958 .dma_base = 0x78400000,
959 .esp_base = 0x78800000,
960 .le_base = 0x78c00000,
961 .apc_base = -1,
962 .aux1_base = 0x71900000,
963 .aux2_base = 0x71910000,
964 .ecc_base = -1,
965 .sun4c_intctl_base = -1,
966 .sun4c_counter_base = -1,
967 .vram_size = 0x00100000,
968 .nvram_size = 0x2000,
969 .esp_irq = 18,
970 .le_irq = 16,
971 .clock_irq = 7,
972 .clock1_irq = 19,
973 .ms_kb_irq = 14,
974 .ser_irq = 15,
975 .fd_irq = 22,
976 .me_irq = 30,
977 .cs_irq = -1,
978 .machine_id = 0x80,
979 .iommu_version = 0x04000000,
980 .intbit_to_level = {
981 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
982 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
983 },
984 .max_mem = 0x10000000,
985 .default_cpu_model = "TI MicroSparc I",
986 },
987 /* SS-4 */
988 {
989 .iommu_base = 0x10000000,
990 .tcx_base = 0x50000000,
991 .cs_base = 0x6c000000,
992 .slavio_base = 0x70000000,
993 .ms_kb_base = 0x71000000,
994 .serial_base = 0x71100000,
995 .nvram_base = 0x71200000,
996 .fd_base = 0x71400000,
997 .counter_base = 0x71d00000,
998 .intctl_base = 0x71e00000,
999 .idreg_base = 0x78000000,
1000 .dma_base = 0x78400000,
1001 .esp_base = 0x78800000,
1002 .le_base = 0x78c00000,
1003 .apc_base = 0x6a000000,
1004 .aux1_base = 0x71900000,
1005 .aux2_base = 0x71910000,
1006 .ecc_base = -1,
1007 .sun4c_intctl_base = -1,
1008 .sun4c_counter_base = -1,
1009 .vram_size = 0x00100000,
1010 .nvram_size = 0x2000,
1011 .esp_irq = 18,
1012 .le_irq = 16,
1013 .clock_irq = 7,
1014 .clock1_irq = 19,
1015 .ms_kb_irq = 14,
1016 .ser_irq = 15,
1017 .fd_irq = 22,
1018 .me_irq = 30,
1019 .cs_irq = 5,
1020 .machine_id = 0x80,
1021 .iommu_version = 0x05000000,
1022 .intbit_to_level = {
1023 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1024 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1025 },
1026 .max_mem = 0x10000000,
1027 .default_cpu_model = "Fujitsu MB86904",
1028 },
1029 /* SPARCClassic */
1030 {
1031 .iommu_base = 0x10000000,
1032 .tcx_base = 0x50000000,
1033 .cs_base = -1,
1034 .slavio_base = 0x70000000,
1035 .ms_kb_base = 0x71000000,
1036 .serial_base = 0x71100000,
1037 .nvram_base = 0x71200000,
1038 .fd_base = 0x71400000,
1039 .counter_base = 0x71d00000,
1040 .intctl_base = 0x71e00000,
1041 .idreg_base = 0x78000000,
1042 .dma_base = 0x78400000,
1043 .esp_base = 0x78800000,
1044 .le_base = 0x78c00000,
1045 .apc_base = 0x6a000000,
1046 .aux1_base = 0x71900000,
1047 .aux2_base = 0x71910000,
1048 .ecc_base = -1,
1049 .sun4c_intctl_base = -1,
1050 .sun4c_counter_base = -1,
1051 .vram_size = 0x00100000,
1052 .nvram_size = 0x2000,
1053 .esp_irq = 18,
1054 .le_irq = 16,
1055 .clock_irq = 7,
1056 .clock1_irq = 19,
1057 .ms_kb_irq = 14,
1058 .ser_irq = 15,
1059 .fd_irq = 22,
1060 .me_irq = 30,
1061 .cs_irq = -1,
1062 .machine_id = 0x80,
1063 .iommu_version = 0x05000000,
1064 .intbit_to_level = {
1065 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1066 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1067 },
1068 .max_mem = 0x10000000,
1069 .default_cpu_model = "TI MicroSparc I",
1070 },
1071 /* SPARCbook */
1072 {
1073 .iommu_base = 0x10000000,
1074 .tcx_base = 0x50000000, // XXX
1075 .cs_base = -1,
1076 .slavio_base = 0x70000000,
1077 .ms_kb_base = 0x71000000,
1078 .serial_base = 0x71100000,
1079 .nvram_base = 0x71200000,
1080 .fd_base = 0x71400000,
1081 .counter_base = 0x71d00000,
1082 .intctl_base = 0x71e00000,
1083 .idreg_base = 0x78000000,
1084 .dma_base = 0x78400000,
1085 .esp_base = 0x78800000,
1086 .le_base = 0x78c00000,
1087 .apc_base = 0x6a000000,
1088 .aux1_base = 0x71900000,
1089 .aux2_base = 0x71910000,
1090 .ecc_base = -1,
1091 .sun4c_intctl_base = -1,
1092 .sun4c_counter_base = -1,
1093 .vram_size = 0x00100000,
1094 .nvram_size = 0x2000,
1095 .esp_irq = 18,
1096 .le_irq = 16,
1097 .clock_irq = 7,
1098 .clock1_irq = 19,
1099 .ms_kb_irq = 14,
1100 .ser_irq = 15,
1101 .fd_irq = 22,
1102 .me_irq = 30,
1103 .cs_irq = -1,
1104 .machine_id = 0x80,
1105 .iommu_version = 0x05000000,
1106 .intbit_to_level = {
1107 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1108 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1109 },
1110 .max_mem = 0x10000000,
1111 .default_cpu_model = "TI MicroSparc I",
1112 },
1113 };
1114
1115 /* SPARCstation 5 hardware initialisation */
1116 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1117 const char *boot_device, DisplayState *ds,
1118 const char *kernel_filename, const char *kernel_cmdline,
1119 const char *initrd_filename, const char *cpu_model)
1120 {
1121 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1122 kernel_cmdline, initrd_filename, cpu_model);
1123 }
1124
1125 /* SPARCstation 10 hardware initialisation */
1126 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1127 const char *boot_device, DisplayState *ds,
1128 const char *kernel_filename, const char *kernel_cmdline,
1129 const char *initrd_filename, const char *cpu_model)
1130 {
1131 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1132 kernel_cmdline, initrd_filename, cpu_model);
1133 }
1134
1135 /* SPARCserver 600MP hardware initialisation */
1136 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1137 const char *boot_device, DisplayState *ds,
1138 const char *kernel_filename, const char *kernel_cmdline,
1139 const char *initrd_filename, const char *cpu_model)
1140 {
1141 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1142 kernel_cmdline, initrd_filename, cpu_model);
1143 }
1144
1145 /* SPARCstation 20 hardware initialisation */
1146 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1147 const char *boot_device, DisplayState *ds,
1148 const char *kernel_filename, const char *kernel_cmdline,
1149 const char *initrd_filename, const char *cpu_model)
1150 {
1151 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1152 kernel_cmdline, initrd_filename, cpu_model);
1153 }
1154
1155 /* SPARCstation 2 hardware initialisation */
1156 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1157 const char *boot_device, DisplayState *ds,
1158 const char *kernel_filename, const char *kernel_cmdline,
1159 const char *initrd_filename, const char *cpu_model)
1160 {
1161 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1162 kernel_cmdline, initrd_filename, cpu_model);
1163 }
1164
1165 /* SPARCstation Voyager hardware initialisation */
1166 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1167 const char *boot_device, DisplayState *ds,
1168 const char *kernel_filename, const char *kernel_cmdline,
1169 const char *initrd_filename, const char *cpu_model)
1170 {
1171 sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1172 kernel_cmdline, initrd_filename, cpu_model);
1173 }
1174
1175 /* SPARCstation LX hardware initialisation */
1176 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1177 const char *boot_device, DisplayState *ds,
1178 const char *kernel_filename, const char *kernel_cmdline,
1179 const char *initrd_filename, const char *cpu_model)
1180 {
1181 sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1182 kernel_cmdline, initrd_filename, cpu_model);
1183 }
1184
1185 /* SPARCstation 4 hardware initialisation */
1186 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1187 const char *boot_device, DisplayState *ds,
1188 const char *kernel_filename, const char *kernel_cmdline,
1189 const char *initrd_filename, const char *cpu_model)
1190 {
1191 sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1192 kernel_cmdline, initrd_filename, cpu_model);
1193 }
1194
1195 /* SPARCClassic hardware initialisation */
1196 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1197 const char *boot_device, DisplayState *ds,
1198 const char *kernel_filename, const char *kernel_cmdline,
1199 const char *initrd_filename, const char *cpu_model)
1200 {
1201 sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1202 kernel_cmdline, initrd_filename, cpu_model);
1203 }
1204
1205 /* SPARCbook hardware initialisation */
1206 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1207 const char *boot_device, DisplayState *ds,
1208 const char *kernel_filename, const char *kernel_cmdline,
1209 const char *initrd_filename, const char *cpu_model)
1210 {
1211 sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1212 kernel_cmdline, initrd_filename, cpu_model);
1213 }
1214
1215 QEMUMachine ss5_machine = {
1216 "SS-5",
1217 "Sun4m platform, SPARCstation 5",
1218 ss5_init,
1219 PROM_SIZE_MAX + TCX_SIZE,
1220 };
1221
1222 QEMUMachine ss10_machine = {
1223 "SS-10",
1224 "Sun4m platform, SPARCstation 10",
1225 ss10_init,
1226 PROM_SIZE_MAX + TCX_SIZE,
1227 };
1228
1229 QEMUMachine ss600mp_machine = {
1230 "SS-600MP",
1231 "Sun4m platform, SPARCserver 600MP",
1232 ss600mp_init,
1233 PROM_SIZE_MAX + TCX_SIZE,
1234 };
1235
1236 QEMUMachine ss20_machine = {
1237 "SS-20",
1238 "Sun4m platform, SPARCstation 20",
1239 ss20_init,
1240 PROM_SIZE_MAX + TCX_SIZE,
1241 };
1242
1243 QEMUMachine ss2_machine = {
1244 "SS-2",
1245 "Sun4c platform, SPARCstation 2",
1246 ss2_init,
1247 PROM_SIZE_MAX + TCX_SIZE,
1248 };
1249
1250 QEMUMachine voyager_machine = {
1251 "Voyager",
1252 "Sun4m platform, SPARCstation Voyager",
1253 vger_init,
1254 PROM_SIZE_MAX + TCX_SIZE,
1255 };
1256
1257 QEMUMachine ss_lx_machine = {
1258 "LX",
1259 "Sun4m platform, SPARCstation LX",
1260 ss_lx_init,
1261 PROM_SIZE_MAX + TCX_SIZE,
1262 };
1263
1264 QEMUMachine ss4_machine = {
1265 "SS-4",
1266 "Sun4m platform, SPARCstation 4",
1267 ss4_init,
1268 PROM_SIZE_MAX + TCX_SIZE,
1269 };
1270
1271 QEMUMachine scls_machine = {
1272 "SPARCClassic",
1273 "Sun4m platform, SPARCClassic",
1274 scls_init,
1275 PROM_SIZE_MAX + TCX_SIZE,
1276 };
1277
1278 QEMUMachine sbook_machine = {
1279 "SPARCbook",
1280 "Sun4m platform, SPARCbook",
1281 sbook_init,
1282 PROM_SIZE_MAX + TCX_SIZE,
1283 };
1284
1285 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1286 /* SS-1000 */
1287 {
1288 .iounit_bases = {
1289 0xfe0200000ULL,
1290 0xfe1200000ULL,
1291 0xfe2200000ULL,
1292 0xfe3200000ULL,
1293 -1,
1294 },
1295 .tcx_base = 0x820000000ULL,
1296 .slavio_base = 0xf00000000ULL,
1297 .ms_kb_base = 0xf00240000ULL,
1298 .serial_base = 0xf00200000ULL,
1299 .nvram_base = 0xf00280000ULL,
1300 .counter_base = 0xf00300000ULL,
1301 .espdma_base = 0x800081000ULL,
1302 .esp_base = 0x800080000ULL,
1303 .ledma_base = 0x800040000ULL,
1304 .le_base = 0x800060000ULL,
1305 .sbi_base = 0xf02800000ULL,
1306 .vram_size = 0x00100000,
1307 .nvram_size = 0x2000,
1308 .esp_irq = 3,
1309 .le_irq = 4,
1310 .clock_irq = 14,
1311 .clock1_irq = 10,
1312 .ms_kb_irq = 12,
1313 .ser_irq = 12,
1314 .machine_id = 0x80,
1315 .iounit_version = 0x03000000,
1316 .max_mem = 0xf00000000ULL,
1317 .default_cpu_model = "TI SuperSparc II",
1318 },
1319 /* SS-2000 */
1320 {
1321 .iounit_bases = {
1322 0xfe0200000ULL,
1323 0xfe1200000ULL,
1324 0xfe2200000ULL,
1325 0xfe3200000ULL,
1326 0xfe4200000ULL,
1327 },
1328 .tcx_base = 0x820000000ULL,
1329 .slavio_base = 0xf00000000ULL,
1330 .ms_kb_base = 0xf00240000ULL,
1331 .serial_base = 0xf00200000ULL,
1332 .nvram_base = 0xf00280000ULL,
1333 .counter_base = 0xf00300000ULL,
1334 .espdma_base = 0x800081000ULL,
1335 .esp_base = 0x800080000ULL,
1336 .ledma_base = 0x800040000ULL,
1337 .le_base = 0x800060000ULL,
1338 .sbi_base = 0xf02800000ULL,
1339 .vram_size = 0x00100000,
1340 .nvram_size = 0x2000,
1341 .esp_irq = 3,
1342 .le_irq = 4,
1343 .clock_irq = 14,
1344 .clock1_irq = 10,
1345 .ms_kb_irq = 12,
1346 .ser_irq = 12,
1347 .machine_id = 0x80,
1348 .iounit_version = 0x03000000,
1349 .max_mem = 0xf00000000ULL,
1350 .default_cpu_model = "TI SuperSparc II",
1351 },
1352 };
1353
1354 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1355 const char *boot_device,
1356 DisplayState *ds, const char *kernel_filename,
1357 const char *kernel_cmdline,
1358 const char *initrd_filename, const char *cpu_model)
1359 {
1360 CPUState *env, *envs[MAX_CPUS];
1361 unsigned int i;
1362 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1363 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1364 *espdma_irq, *ledma_irq;
1365 qemu_irq *esp_reset, *le_reset;
1366 unsigned long prom_offset, kernel_size;
1367 int ret;
1368 char buf[1024];
1369 int index;
1370
1371 /* init CPUs */
1372 if (!cpu_model)
1373 cpu_model = hwdef->default_cpu_model;
1374
1375 for (i = 0; i < smp_cpus; i++) {
1376 env = cpu_init(cpu_model);
1377 if (!env) {
1378 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1379 exit(1);
1380 }
1381 cpu_sparc_set_id(env, i);
1382 envs[i] = env;
1383 if (i == 0) {
1384 qemu_register_reset(main_cpu_reset, env);
1385 } else {
1386 qemu_register_reset(secondary_cpu_reset, env);
1387 env->halted = 1;
1388 }
1389 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
1390 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1391 env->prom_addr = hwdef->slavio_base;
1392 }
1393
1394 for (i = smp_cpus; i < MAX_CPUS; i++)
1395 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1396
1397 /* allocate RAM */
1398 if ((uint64_t)RAM_size > hwdef->max_mem) {
1399 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
1400 (unsigned int)(RAM_size / (1024 * 1024)),
1401 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1402 exit(1);
1403 }
1404 cpu_register_physical_memory(0, RAM_size, 0);
1405
1406 /* load boot prom */
1407 prom_offset = RAM_size + hwdef->vram_size;
1408 cpu_register_physical_memory(hwdef->slavio_base,
1409 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1410 TARGET_PAGE_MASK,
1411 prom_offset | IO_MEM_ROM);
1412
1413 if (bios_name == NULL)
1414 bios_name = PROM_FILENAME;
1415 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1416 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1417 if (ret < 0 || ret > PROM_SIZE_MAX)
1418 ret = load_image(buf, phys_ram_base + prom_offset);
1419 if (ret < 0 || ret > PROM_SIZE_MAX) {
1420 fprintf(stderr, "qemu: could not load prom '%s'\n",
1421 buf);
1422 exit(1);
1423 }
1424
1425 /* set up devices */
1426 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1427
1428 for (i = 0; i < MAX_IOUNITS; i++)
1429 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1430 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1431 hwdef->iounit_version,
1432 sbi_irq[hwdef->me_irq]);
1433
1434 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1435 iounits[0], &espdma_irq, &esp_reset);
1436
1437 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1438 iounits[0], &ledma_irq, &le_reset);
1439
1440 if (graphic_depth != 8 && graphic_depth != 24) {
1441 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1442 exit (1);
1443 }
1444 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1445 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1446
1447 if (nd_table[0].model == NULL
1448 || strcmp(nd_table[0].model, "lance") == 0) {
1449 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1450 } else if (strcmp(nd_table[0].model, "?") == 0) {
1451 fprintf(stderr, "qemu: Supported NICs: lance\n");
1452 exit (1);
1453 } else {
1454 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1455 exit (1);
1456 }
1457
1458 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1459 hwdef->nvram_size, 8);
1460
1461 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1462 sbi_cpu_irq, smp_cpus);
1463
1464 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1465 nographic);
1466 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1467 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1468 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1469 serial_hds[1], serial_hds[0]);
1470
1471 if (drive_get_max_bus(IF_SCSI) > 0) {
1472 fprintf(stderr, "qemu: too many SCSI bus\n");
1473 exit(1);
1474 }
1475
1476 main_esp = esp_init(hwdef->esp_base, 2,
1477 espdma_memory_read, espdma_memory_write,
1478 espdma, *espdma_irq, esp_reset);
1479
1480 for (i = 0; i < ESP_MAX_DEVS; i++) {
1481 index = drive_get_index(IF_SCSI, 0, i);
1482 if (index == -1)
1483 continue;
1484 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
1485 }
1486
1487 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
1488 initrd_filename);
1489
1490 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1491 boot_device, RAM_size, kernel_size, graphic_width,
1492 graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
1493 }
1494
1495 /* SPARCserver 1000 hardware initialisation */
1496 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1497 const char *boot_device, DisplayState *ds,
1498 const char *kernel_filename, const char *kernel_cmdline,
1499 const char *initrd_filename, const char *cpu_model)
1500 {
1501 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1502 kernel_cmdline, initrd_filename, cpu_model);
1503 }
1504
1505 /* SPARCcenter 2000 hardware initialisation */
1506 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1507 const char *boot_device, DisplayState *ds,
1508 const char *kernel_filename, const char *kernel_cmdline,
1509 const char *initrd_filename, const char *cpu_model)
1510 {
1511 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1512 kernel_cmdline, initrd_filename, cpu_model);
1513 }
1514
1515 QEMUMachine ss1000_machine = {
1516 "SS-1000",
1517 "Sun4d platform, SPARCserver 1000",
1518 ss1000_init,
1519 PROM_SIZE_MAX + TCX_SIZE,
1520 };
1521
1522 QEMUMachine ss2000_machine = {
1523 "SS-2000",
1524 "Sun4d platform, SPARCcenter 2000",
1525 ss2000_init,
1526 PROM_SIZE_MAX + TCX_SIZE,
1527 };
jz4740 based target emulation