hw/prep_pci.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "prep_pci.h"
  29
  30 typedef PCIHostState PREPPCIState;
  31
  32 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
  33 {
  34     int i;
  35
  36     for(i = 0; i < 11; i++) {
  37         if ((addr & (1 << (11 + i))) != 0)
  38             break;
  39     }
  40     return (addr & 0x7ff) |  (i << 11);
  41 }
  42
  43 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
  44 {
  45     PREPPCIState *s = opaque;
  46     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
  47 }
  48
  49 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
  50 {
  51     PREPPCIState *s = opaque;
  52 #ifdef TARGET_WORDS_BIGENDIAN
  53     val = bswap16(val);
  54 #endif
  55     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
  56 }
  57
  58 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
  59 {
  60     PREPPCIState *s = opaque;
  61 #ifdef TARGET_WORDS_BIGENDIAN
  62     val = bswap32(val);
  63 #endif
  64     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
  65 }
  66
  67 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
  68 {
  69     PREPPCIState *s = opaque;
  70     uint32_t val;
  71     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
  72     return val;
  73 }
  74
  75 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
  76 {
  77     PREPPCIState *s = opaque;
  78     uint32_t val;
  79     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
  80 #ifdef TARGET_WORDS_BIGENDIAN
  81     val = bswap16(val);
  82 #endif
  83     return val;
  84 }
  85
  86 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
  87 {
  88     PREPPCIState *s = opaque;
  89     uint32_t val;
  90     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
  91 #ifdef TARGET_WORDS_BIGENDIAN
  92     val = bswap32(val);
  93 #endif
  94     return val;
  95 }
  96
  97 static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
  98     &PPC_PCIIO_writeb,
  99     &PPC_PCIIO_writew,
 100     &PPC_PCIIO_writel,
 101 };
 102
 103 static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
 104     &PPC_PCIIO_readb,
 105     &PPC_PCIIO_readw,
 106     &PPC_PCIIO_readl,
 107 };
 108
 109 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 110 {
 111     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 112 }
 113
 114 static void prep_set_irq(void *opaque, int irq_num, int level)
 115 {
 116     qemu_irq *pic = opaque;
 117
 118     qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
 119 }
 120
 121 PCIBus *pci_prep_init(qemu_irq *pic)
 122 {
 123     PREPPCIState *s;
 124     PCIDevice *d;
 125     int PPC_io_memory;
 126
 127     s = qemu_mallocz(sizeof(PREPPCIState));
 128     s->bus = pci_register_bus(NULL, "pci",
 129                               prep_set_irq, prep_map_irq, pic, 0, 4);
 130
 131     pci_host_conf_register_ioport(0xcf8, s);
 132
 133     pci_host_data_register_ioport(0xcfc, s);
 134
 135     PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
 136                                            PPC_PCIIO_write, s);
 137     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 138
 139     /* PCI host bridge */
 140     d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
 141                             sizeof(PCIDevice), 0, NULL, NULL);
 142     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 143     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
 144     d->config[0x08] = 0x00; // revision
 145     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 146     d->config[0x0C] = 0x08; // cache_line_size
 147     d->config[0x0D] = 0x10; // latency_timer
 148     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 149     d->config[0x34] = 0x00; // capabilities_pointer
 150
 151     return s->bus;
 152 }