target-s390x/helper.c

   1 /*
   2  *  S/390 helpers
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2011 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "exec/gdbstub.h"
  23 #include "qemu/timer.h"
  24 #ifndef CONFIG_USER_ONLY
  25 #include "sysemu/sysemu.h"
  26 #endif
  27
  28 //#define DEBUG_S390
  29 //#define DEBUG_S390_PTE
  30 //#define DEBUG_S390_STDOUT
  31
  32 #ifdef DEBUG_S390
  33 #ifdef DEBUG_S390_STDOUT
  34 #define DPRINTF(fmt, ...) \
  35     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  36          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  37 #else
  38 #define DPRINTF(fmt, ...) \
  39     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  40 #endif
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #ifdef DEBUG_S390_PTE
  47 #define PTE_DPRINTF DPRINTF
  48 #else
  49 #define PTE_DPRINTF(fmt, ...) \
  50     do { } while (0)
  51 #endif
  52
  53 #ifndef CONFIG_USER_ONLY
  54 void s390x_tod_timer(void *opaque)
  55 {
  56     S390CPU *cpu = opaque;
  57     CPUS390XState *env = &cpu->env;
  58
  59     env->pending_int |= INTERRUPT_TOD;
  60     cpu_interrupt(env, CPU_INTERRUPT_HARD);
  61 }
  62
  63 void s390x_cpu_timer(void *opaque)
  64 {
  65     S390CPU *cpu = opaque;
  66     CPUS390XState *env = &cpu->env;
  67
  68     env->pending_int |= INTERRUPT_CPUTIMER;
  69     cpu_interrupt(env, CPU_INTERRUPT_HARD);
  70 }
  71 #endif
  72
  73 S390CPU *cpu_s390x_init(const char *cpu_model)
  74 {
  75     S390CPU *cpu;
  76     CPUS390XState *env;
  77
  78     cpu = S390_CPU(object_new(TYPE_S390_CPU));
  79     env = &cpu->env;
  80     env->cpu_model_str = cpu_model;
  81
  82     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  83
  84     return cpu;
  85 }
  86
  87 #if defined(CONFIG_USER_ONLY)
  88
  89 void do_interrupt(CPUS390XState *env)
  90 {
  91     env->exception_index = -1;
  92 }
  93
  94 int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
  95                                int rw, int mmu_idx)
  96 {
  97     env->exception_index = EXCP_PGM;
  98     env->int_pgm_code = PGM_ADDRESSING;
  99     /* On real machines this value is dropped into LowMem.  Since this
 100        is userland, simply put this someplace that cpu_loop can find it.  */
 101     env->__excp_addr = address;
 102     return 1;
 103 }
 104
 105 #else /* !CONFIG_USER_ONLY */
 106
 107 /* Ensure to exit the TB after this call! */
 108 static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
 109                                   uint32_t ilen)
 110 {
 111     env->exception_index = EXCP_PGM;
 112     env->int_pgm_code = code;
 113     env->int_pgm_ilen = ilen;
 114 }
 115
 116 static int trans_bits(CPUS390XState *env, uint64_t mode)
 117 {
 118     int bits = 0;
 119
 120     switch (mode) {
 121     case PSW_ASC_PRIMARY:
 122         bits = 1;
 123         break;
 124     case PSW_ASC_SECONDARY:
 125         bits = 2;
 126         break;
 127     case PSW_ASC_HOME:
 128         bits = 3;
 129         break;
 130     default:
 131         cpu_abort(env, "unknown asc mode\n");
 132         break;
 133     }
 134
 135     return bits;
 136 }
 137
 138 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
 139                                uint64_t mode)
 140 {
 141     int ilen = ILEN_LATER_INC;
 142     int bits = trans_bits(env, mode) | 4;
 143
 144     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
 145
 146     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 147     trigger_pgm_exception(env, PGM_PROTECTION, ilen);
 148 }
 149
 150 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
 151                                uint32_t type, uint64_t asc, int rw)
 152 {
 153     int ilen = ILEN_LATER;
 154     int bits = trans_bits(env, asc);
 155
 156     /* Code accesses have an undefined ilc.  */
 157     if (rw == 2) {
 158         ilen = 2;
 159     }
 160
 161     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
 162
 163     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 164     trigger_pgm_exception(env, type, ilen);
 165 }
 166
 167 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
 168                               uint64_t asc, uint64_t asce, int level,
 169                               target_ulong *raddr, int *flags, int rw)
 170 {
 171     uint64_t offs = 0;
 172     uint64_t origin;
 173     uint64_t new_asce;
 174
 175     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
 176
 177     if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
 178         ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
 179         /* XXX different regions have different faults */
 180         DPRINTF("%s: invalid region\n", __func__);
 181         trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
 182         return -1;
 183     }
 184
 185     if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
 186         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 187         return -1;
 188     }
 189
 190     if (asce & _ASCE_REAL_SPACE) {
 191         /* direct mapping */
 192
 193         *raddr = vaddr;
 194         return 0;
 195     }
 196
 197     origin = asce & _ASCE_ORIGIN;
 198
 199     switch (level) {
 200     case _ASCE_TYPE_REGION1 + 4:
 201         offs = (vaddr >> 50) & 0x3ff8;
 202         break;
 203     case _ASCE_TYPE_REGION1:
 204         offs = (vaddr >> 39) & 0x3ff8;
 205         break;
 206     case _ASCE_TYPE_REGION2:
 207         offs = (vaddr >> 28) & 0x3ff8;
 208         break;
 209     case _ASCE_TYPE_REGION3:
 210         offs = (vaddr >> 17) & 0x3ff8;
 211         break;
 212     case _ASCE_TYPE_SEGMENT:
 213         offs = (vaddr >> 9) & 0x07f8;
 214         origin = asce & _SEGMENT_ENTRY_ORIGIN;
 215         break;
 216     }
 217
 218     /* XXX region protection flags */
 219     /* *flags &= ~PAGE_WRITE */
 220
 221     new_asce = ldq_phys(origin + offs);
 222     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 223                 __func__, origin, offs, new_asce);
 224
 225     if (level != _ASCE_TYPE_SEGMENT) {
 226         /* yet another region */
 227         return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
 228                                   flags, rw);
 229     }
 230
 231     /* PTE */
 232     if (new_asce & _PAGE_INVALID) {
 233         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
 234         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
 235         return -1;
 236     }
 237
 238     if (new_asce & _PAGE_RO) {
 239         *flags &= ~PAGE_WRITE;
 240     }
 241
 242     *raddr = new_asce & _ASCE_ORIGIN;
 243
 244     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
 245
 246     return 0;
 247 }
 248
 249 static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
 250                              uint64_t asc, target_ulong *raddr, int *flags,
 251                              int rw)
 252 {
 253     uint64_t asce = 0;
 254     int level, new_level;
 255     int r;
 256
 257     switch (asc) {
 258     case PSW_ASC_PRIMARY:
 259         PTE_DPRINTF("%s: asc=primary\n", __func__);
 260         asce = env->cregs[1];
 261         break;
 262     case PSW_ASC_SECONDARY:
 263         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 264         asce = env->cregs[7];
 265         break;
 266     case PSW_ASC_HOME:
 267         PTE_DPRINTF("%s: asc=home\n", __func__);
 268         asce = env->cregs[13];
 269         break;
 270     }
 271
 272     switch (asce & _ASCE_TYPE_MASK) {
 273     case _ASCE_TYPE_REGION1:
 274         break;
 275     case _ASCE_TYPE_REGION2:
 276         if (vaddr & 0xffe0000000000000ULL) {
 277             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 278                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 279             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 280             return -1;
 281         }
 282         break;
 283     case _ASCE_TYPE_REGION3:
 284         if (vaddr & 0xfffffc0000000000ULL) {
 285             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 286                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 287             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 288             return -1;
 289         }
 290         break;
 291     case _ASCE_TYPE_SEGMENT:
 292         if (vaddr & 0xffffffff80000000ULL) {
 293             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 294                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 295             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 296             return -1;
 297         }
 298         break;
 299     }
 300
 301     /* fake level above current */
 302     level = asce & _ASCE_TYPE_MASK;
 303     new_level = level + 4;
 304     asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
 305
 306     r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
 307
 308     if ((rw == 1) && !(*flags & PAGE_WRITE)) {
 309         trigger_prot_fault(env, vaddr, asc);
 310         return -1;
 311     }
 312
 313     return r;
 314 }
 315
 316 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 317                   target_ulong *raddr, int *flags)
 318 {
 319     int r = -1;
 320     uint8_t *sk;
 321
 322     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 323     vaddr &= TARGET_PAGE_MASK;
 324
 325     if (!(env->psw.mask & PSW_MASK_DAT)) {
 326         *raddr = vaddr;
 327         r = 0;
 328         goto out;
 329     }
 330
 331     switch (asc) {
 332     case PSW_ASC_PRIMARY:
 333     case PSW_ASC_HOME:
 334         r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
 335         break;
 336     case PSW_ASC_SECONDARY:
 337         /*
 338          * Instruction: Primary
 339          * Data: Secondary
 340          */
 341         if (rw == 2) {
 342             r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
 343                                   rw);
 344             *flags &= ~(PAGE_READ | PAGE_WRITE);
 345         } else {
 346             r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
 347                                   rw);
 348             *flags &= ~(PAGE_EXEC);
 349         }
 350         break;
 351     case PSW_ASC_ACCREG:
 352     default:
 353         hw_error("guest switched to unknown asc mode\n");
 354         break;
 355     }
 356
 357  out:
 358     /* Convert real address -> absolute address */
 359     if (*raddr < 0x2000) {
 360         *raddr = *raddr + env->psa;
 361     }
 362
 363     if (*raddr <= ram_size) {
 364         sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
 365         if (*flags & PAGE_READ) {
 366             *sk |= SK_R;
 367         }
 368
 369         if (*flags & PAGE_WRITE) {
 370             *sk |= SK_C;
 371         }
 372     }
 373
 374     return r;
 375 }
 376
 377 int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
 378                                int rw, int mmu_idx)
 379 {
 380     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 381     target_ulong vaddr, raddr;
 382     int prot;
 383
 384     DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
 385             __func__, orig_vaddr, rw, mmu_idx);
 386
 387     orig_vaddr &= TARGET_PAGE_MASK;
 388     vaddr = orig_vaddr;
 389
 390     /* 31-Bit mode */
 391     if (!(env->psw.mask & PSW_MASK_64)) {
 392         vaddr &= 0x7fffffff;
 393     }
 394
 395     if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
 396         /* Translation ended in exception */
 397         return 1;
 398     }
 399
 400     /* check out of RAM access */
 401     if (raddr > (ram_size + virtio_size)) {
 402         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
 403                 (uint64_t)raddr, (uint64_t)ram_size);
 404         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER);
 405         return 1;
 406     }
 407
 408     DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
 409             (uint64_t)vaddr, (uint64_t)raddr, prot);
 410
 411     tlb_set_page(env, orig_vaddr, raddr, prot,
 412                  mmu_idx, TARGET_PAGE_SIZE);
 413
 414     return 0;
 415 }
 416
 417 hwaddr cpu_get_phys_page_debug(CPUS390XState *env,
 418                                            target_ulong vaddr)
 419 {
 420     target_ulong raddr;
 421     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 422     int old_exc = env->exception_index;
 423     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 424
 425     /* 31-Bit mode */
 426     if (!(env->psw.mask & PSW_MASK_64)) {
 427         vaddr &= 0x7fffffff;
 428     }
 429
 430     mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
 431     env->exception_index = old_exc;
 432
 433     return raddr;
 434 }
 435
 436 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
 437 {
 438     if (mask & PSW_MASK_WAIT) {
 439         S390CPU *cpu = s390_env_get_cpu(env);
 440         if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
 441             if (s390_del_running_cpu(cpu) == 0) {
 442 #ifndef CONFIG_USER_ONLY
 443                 qemu_system_shutdown_request();
 444 #endif
 445             }
 446         }
 447         env->halted = 1;
 448         env->exception_index = EXCP_HLT;
 449     }
 450
 451     env->psw.addr = addr;
 452     env->psw.mask = mask;
 453     env->cc_op = (mask >> 44) & 3;
 454 }
 455
 456 static uint64_t get_psw_mask(CPUS390XState *env)
 457 {
 458     uint64_t r;
 459
 460     env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
 461
 462     r = env->psw.mask;
 463     r &= ~PSW_MASK_CC;
 464     assert(!(env->cc_op & ~3));
 465     r |= (uint64_t)env->cc_op << 44;
 466
 467     return r;
 468 }
 469
 470 static LowCore *cpu_map_lowcore(CPUS390XState *env)
 471 {
 472     LowCore *lowcore;
 473     hwaddr len = sizeof(LowCore);
 474
 475     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 476
 477     if (len < sizeof(LowCore)) {
 478         cpu_abort(env, "Could not map lowcore\n");
 479     }
 480
 481     return lowcore;
 482 }
 483
 484 static void cpu_unmap_lowcore(LowCore *lowcore)
 485 {
 486     cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
 487 }
 488
 489 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 490                                    int is_write)
 491 {
 492     hwaddr start = addr;
 493
 494     /* Mind the prefix area. */
 495     if (addr < 8192) {
 496         /* Map the lowcore. */
 497         start += env->psa;
 498         *len = MIN(*len, 8192 - addr);
 499     } else if ((addr >= env->psa) && (addr < env->psa + 8192)) {
 500         /* Map the 0 page. */
 501         start -= env->psa;
 502         *len = MIN(*len, 8192 - start);
 503     }
 504
 505     return cpu_physical_memory_map(start, len, is_write);
 506 }
 507
 508 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 509                                     int is_write)
 510 {
 511     cpu_physical_memory_unmap(addr, len, is_write, len);
 512 }
 513
 514 static void do_svc_interrupt(CPUS390XState *env)
 515 {
 516     uint64_t mask, addr;
 517     LowCore *lowcore;
 518
 519     lowcore = cpu_map_lowcore(env);
 520
 521     lowcore->svc_code = cpu_to_be16(env->int_svc_code);
 522     lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
 523     lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 524     lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
 525     mask = be64_to_cpu(lowcore->svc_new_psw.mask);
 526     addr = be64_to_cpu(lowcore->svc_new_psw.addr);
 527
 528     cpu_unmap_lowcore(lowcore);
 529
 530     load_psw(env, mask, addr);
 531 }
 532
 533 static void do_program_interrupt(CPUS390XState *env)
 534 {
 535     uint64_t mask, addr;
 536     LowCore *lowcore;
 537     int ilen = env->int_pgm_ilen;
 538
 539     switch (ilen) {
 540     case ILEN_LATER:
 541         ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
 542         break;
 543     case ILEN_LATER_INC:
 544         ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
 545         env->psw.addr += ilen;
 546         break;
 547     default:
 548         assert(ilen == 2 || ilen == 4 || ilen == 6);
 549     }
 550
 551     qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
 552                   __func__, env->int_pgm_code, ilen);
 553
 554     lowcore = cpu_map_lowcore(env);
 555
 556     lowcore->pgm_ilen = cpu_to_be16(ilen);
 557     lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
 558     lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 559     lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
 560     mask = be64_to_cpu(lowcore->program_new_psw.mask);
 561     addr = be64_to_cpu(lowcore->program_new_psw.addr);
 562
 563     cpu_unmap_lowcore(lowcore);
 564
 565     DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
 566             env->int_pgm_code, ilen, env->psw.mask,
 567             env->psw.addr);
 568
 569     load_psw(env, mask, addr);
 570 }
 571
 572 #define VIRTIO_SUBCODE_64 0x0D00
 573
 574 static void do_ext_interrupt(CPUS390XState *env)
 575 {
 576     uint64_t mask, addr;
 577     LowCore *lowcore;
 578     ExtQueue *q;
 579
 580     if (!(env->psw.mask & PSW_MASK_EXT)) {
 581         cpu_abort(env, "Ext int w/o ext mask\n");
 582     }
 583
 584     if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
 585         cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
 586     }
 587
 588     q = &env->ext_queue[env->ext_index];
 589     lowcore = cpu_map_lowcore(env);
 590
 591     lowcore->ext_int_code = cpu_to_be16(q->code);
 592     lowcore->ext_params = cpu_to_be32(q->param);
 593     lowcore->ext_params2 = cpu_to_be64(q->param64);
 594     lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 595     lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
 596     lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
 597     mask = be64_to_cpu(lowcore->external_new_psw.mask);
 598     addr = be64_to_cpu(lowcore->external_new_psw.addr);
 599
 600     cpu_unmap_lowcore(lowcore);
 601
 602     env->ext_index--;
 603     if (env->ext_index == -1) {
 604         env->pending_int &= ~INTERRUPT_EXT;
 605     }
 606
 607     DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
 608             env->psw.mask, env->psw.addr);
 609
 610     load_psw(env, mask, addr);
 611 }
 612
 613 static void do_io_interrupt(CPUS390XState *env)
 614 {
 615     LowCore *lowcore;
 616     IOIntQueue *q;
 617     uint8_t isc;
 618     int disable = 1;
 619     int found = 0;
 620
 621     if (!(env->psw.mask & PSW_MASK_IO)) {
 622         cpu_abort(env, "I/O int w/o I/O mask\n");
 623     }
 624
 625     for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
 626         uint64_t isc_bits;
 627
 628         if (env->io_index[isc] < 0) {
 629             continue;
 630         }
 631         if (env->io_index[isc] > MAX_IO_QUEUE) {
 632             cpu_abort(env, "I/O queue overrun for isc %d: %d\n",
 633                       isc, env->io_index[isc]);
 634         }
 635
 636         q = &env->io_queue[env->io_index[isc]][isc];
 637         isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word));
 638         if (!(env->cregs[6] & isc_bits)) {
 639             disable = 0;
 640             continue;
 641         }
 642         if (!found) {
 643             uint64_t mask, addr;
 644
 645             found = 1;
 646             lowcore = cpu_map_lowcore(env);
 647
 648             lowcore->subchannel_id = cpu_to_be16(q->id);
 649             lowcore->subchannel_nr = cpu_to_be16(q->nr);
 650             lowcore->io_int_parm = cpu_to_be32(q->parm);
 651             lowcore->io_int_word = cpu_to_be32(q->word);
 652             lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 653             lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
 654             mask = be64_to_cpu(lowcore->io_new_psw.mask);
 655             addr = be64_to_cpu(lowcore->io_new_psw.addr);
 656
 657             cpu_unmap_lowcore(lowcore);
 658
 659             env->io_index[isc]--;
 660
 661             DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
 662                     env->psw.mask, env->psw.addr);
 663             load_psw(env, mask, addr);
 664         }
 665         if (env->io_index[isc] >= 0) {
 666             disable = 0;
 667         }
 668         continue;
 669     }
 670
 671     if (disable) {
 672         env->pending_int &= ~INTERRUPT_IO;
 673     }
 674
 675 }
 676
 677 static void do_mchk_interrupt(CPUS390XState *env)
 678 {
 679     uint64_t mask, addr;
 680     LowCore *lowcore;
 681     MchkQueue *q;
 682     int i;
 683
 684     if (!(env->psw.mask & PSW_MASK_MCHECK)) {
 685         cpu_abort(env, "Machine check w/o mchk mask\n");
 686     }
 687
 688     if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) {
 689         cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index);
 690     }
 691
 692     q = &env->mchk_queue[env->mchk_index];
 693
 694     if (q->type != 1) {
 695         /* Don't know how to handle this... */
 696         cpu_abort(env, "Unknown machine check type %d\n", q->type);
 697     }
 698     if (!(env->cregs[14] & (1 << 28))) {
 699         /* CRW machine checks disabled */
 700         return;
 701     }
 702
 703     lowcore = cpu_map_lowcore(env);
 704
 705     for (i = 0; i < 16; i++) {
 706         lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll);
 707         lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
 708         lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
 709         lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
 710     }
 711     lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
 712     lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
 713     lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
 714     lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32);
 715     lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
 716     lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32);
 717     lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
 718
 719     lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d);
 720     lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000);
 721     lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 722     lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
 723     mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
 724     addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
 725
 726     cpu_unmap_lowcore(lowcore);
 727
 728     env->mchk_index--;
 729     if (env->mchk_index == -1) {
 730         env->pending_int &= ~INTERRUPT_MCHK;
 731     }
 732
 733     DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
 734             env->psw.mask, env->psw.addr);
 735
 736     load_psw(env, mask, addr);
 737 }
 738
 739 void do_interrupt(CPUS390XState *env)
 740 {
 741     S390CPU *cpu = s390_env_get_cpu(env);
 742
 743     qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
 744                   __func__, env->exception_index, env->psw.addr);
 745
 746     s390_add_running_cpu(cpu);
 747     /* handle machine checks */
 748     if ((env->psw.mask & PSW_MASK_MCHECK) &&
 749         (env->exception_index == -1)) {
 750         if (env->pending_int & INTERRUPT_MCHK) {
 751             env->exception_index = EXCP_MCHK;
 752         }
 753     }
 754     /* handle external interrupts */
 755     if ((env->psw.mask & PSW_MASK_EXT) &&
 756         env->exception_index == -1) {
 757         if (env->pending_int & INTERRUPT_EXT) {
 758             /* code is already in env */
 759             env->exception_index = EXCP_EXT;
 760         } else if (env->pending_int & INTERRUPT_TOD) {
 761             cpu_inject_ext(cpu, 0x1004, 0, 0);
 762             env->exception_index = EXCP_EXT;
 763             env->pending_int &= ~INTERRUPT_EXT;
 764             env->pending_int &= ~INTERRUPT_TOD;
 765         } else if (env->pending_int & INTERRUPT_CPUTIMER) {
 766             cpu_inject_ext(cpu, 0x1005, 0, 0);
 767             env->exception_index = EXCP_EXT;
 768             env->pending_int &= ~INTERRUPT_EXT;
 769             env->pending_int &= ~INTERRUPT_TOD;
 770         }
 771     }
 772     /* handle I/O interrupts */
 773     if ((env->psw.mask & PSW_MASK_IO) &&
 774         (env->exception_index == -1)) {
 775         if (env->pending_int & INTERRUPT_IO) {
 776             env->exception_index = EXCP_IO;
 777         }
 778     }
 779
 780     switch (env->exception_index) {
 781     case EXCP_PGM:
 782         do_program_interrupt(env);
 783         break;
 784     case EXCP_SVC:
 785         do_svc_interrupt(env);
 786         break;
 787     case EXCP_EXT:
 788         do_ext_interrupt(env);
 789         break;
 790     case EXCP_IO:
 791         do_io_interrupt(env);
 792         break;
 793     case EXCP_MCHK:
 794         do_mchk_interrupt(env);
 795         break;
 796     }
 797     env->exception_index = -1;
 798
 799     if (!env->pending_int) {
 800         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 801     }
 802 }
 803
 804 #endif /* CONFIG_USER_ONLY */