target-openrisc/translate.c

   1 /*
   2  * OpenRISC translation
   3  *
   4  *  Copyright (c) 2008-2009 Stuart Brady <stuart.brady@gmail.com>
   5  *  Copyright (c) 2009 Laurent Desnogues
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Library General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Library General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Library General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  20  */
  21 #include <stdio.h>
  22 #include <stdlib.h>
  23
  24 #include "cpu.h"
  25 #include "disas.h"
  26 #include "tcg-op.h"
  27
  28 typedef struct {
  29     target_ulong pc;
  30     target_ulong npc;
  31     int is_jmp;
  32     int mem_idx;
  33     const TranslationBlock *tb;
  34 } DisasContext;
  35
  36 /* global register indexes */
  37
  38 static TCGv_ptr cpu_env;
  39
  40 static TCGv cpu_gpr[32];
  41
  42 static char cpu_reg_names[
  43     10*3 + 22*4 /* GPR */
  44 ];
  45
  46 void openrisc_translate_init(void)
  47 {
  48     int i;
  49     char *p;
  50
  51     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
  52
  53     p = cpu_reg_names;
  54
  55     for (i = 0; i < 32; i++) {
  56         sprintf(p, "r%d", i);
  57         cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
  58                                         offsetof(CPUState, gpr[i]), p);
  59         p += (i < 10) ? 3 : 4;
  60     }
  61 }
  62
  63 static inline void store_cpu_offset(TCGv var, int offset)
  64 {
  65     tcg_gen_st_tl(var, cpu_env, offset);
  66     tcg_temp_free(var);
  67 }
  68
  69 #define store_cpu_field(var, name) \
  70     store_cpu_offset(var, offsetof(CPUState, name))
  71
  72 static inline void gen_set_pc_im(target_ulong val)
  73 {
  74     TCGv tmp = tcg_temp_new();
  75     tcg_gen_movi_tl(tmp, val);
  76     store_cpu_field(tmp, pc);
  77 }
  78
  79 static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
  80 {
  81     const TranslationBlock *tb;
  82
  83     tb = s->tb;
  84     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
  85         tcg_gen_goto_tb(n);
  86         gen_set_pc_im(dest);
  87         tcg_gen_exit_tb((long)tb + n);
  88     } else {
  89         gen_set_pc_im(dest);
  90         tcg_gen_exit_tb(0);
  91     }
  92 }
  93
  94 static inline uint32_t field(uint32_t val, int start, int length)
  95 {
  96     val >>= start;
  97     val &= ~(~0 << length);
  98     return val;
  99 }
 100
 101 static void disas_openrisc_insn(DisasContext *dc)
 102 {
 103     uint32_t insn;
 104     int op, opext, opext2, d, a, b;
 105     target_ulong im16, im16b;
 106     TCGv t0;
 107     int l1, l2;
 108
 109     insn = ldl_code(dc->pc);
 110     dc->pc += 4;
 111
 112     op = field(insn, 26, 6);
 113     /* opext = field(insn, 21, 5); */
 114     d = field(insn, 21, 5);
 115     a = field(insn, 16, 5);
 116     b = field(insn, 11, 5);
 117     im16 = field(insn, 0, 16);
 118     im16b = field(insn, 0, 11) | (d << 11);
 119
 120     switch (op) {
 121     case 0x00: /* l.j */
 122         goto unimp;
 123     case 0x01: /* l.jal */
 124         goto unimp;
 125     case 0x03: /* l.bnf */
 126         goto unimp;
 127     case 0x04: /* l.bf */
 128         goto unimp;
 129     case 0x05: /* l.nop */
 130         goto unimp;
 131     case 0x06:
 132         /* [l.macrc] */
 133         /* l.movhi */
 134         goto unimp;
 135     case 0x08:
 136         /* l.sys */
 137         /* [l.trap] */
 138         /* csync, msync, psync */
 139         goto unimp;
 140     case 0x09: /* l.rfe */
 141         goto unimp;
 142
 143 #ifdef TARGET_OPENRISC64
 144     case 0x0a: /* [vector ops] */
 145         switch (opext) {
 146         case 0x10: /* lv.all_eq.b */
 147             goto unimp;
 148         case 0x11: /* lv.all_eq.h */
 149             goto unimp;
 150         case 0x12: /* lv.all_ge.b */
 151             goto unimp;
 152         case 0x13: /* lv.all_ge.h */
 153             goto unimp;
 154         case 0x14: /* lv.all_gt.b */
 155             goto unimp;
 156         case 0x15: /* lv.all_gt.h */
 157             goto unimp;
 158         case 0x16: /* lv.all_le.b */
 159             goto unimp;
 160         case 0x17: /* lv.all_le.h */
 161             goto unimp;
 162         case 0x18: /* lv.all_lt.b */
 163             goto unimp;
 164         case 0x19: /* lv.all_lt.h */
 165             goto unimp;
 166         case 0x1a: /* lv.all_ne.b */
 167             goto unimp;
 168         case 0x1b: /* lv.all_ne.h */
 169             goto unimp;
 170         case 0x20: /* lv.any_eq.b */
 171             goto unimp;
 172         case 0x21: /* lv.any_eq.h */
 173             goto unimp;
 174         case 0x22: /* lv.any_ge.b */
 175             goto unimp;
 176         case 0x23: /* lv.any_ge.h */
 177             goto unimp;
 178         case 0x24: /* lv.any_gt.b */
 179             goto unimp;
 180         case 0x25: /* lv.any_gt.h */
 181             goto unimp;
 182         case 0x26: /* lv.any_le.b */
 183             goto unimp;
 184         case 0x27: /* lv.any_le.h */
 185             goto unimp;
 186         case 0x28: /* lv.any_lt.b */
 187             goto unimp;
 188         case 0x29: /* lv.any_lt.h */
 189             goto unimp;
 190         case 0x2a: /* lv.any_ne.b */
 191             goto unimp;
 192         case 0x2b: /* lv.any_ne.h */
 193             goto unimp;
 194         case 0x30: /* lv.add.b */
 195             goto unimp;
 196         case 0x31: /* lv.add.h */
 197             goto unimp;
 198         case 0x32: /* lv.adds.b */
 199             goto unimp;
 200         case 0x33: /* lv.adds.h */
 201             goto unimp;
 202         case 0x34: /* lv.addu.b */
 203             goto unimp;
 204         case 0x35: /* lv.addu.h */
 205             goto unimp;
 206         case 0x36: /* lv.addus.b */
 207             goto unimp;
 208         case 0x37: /* lv.addus.h */
 209             goto unimp;
 210         case 0x38: /* lv.and */
 211             goto unimp;
 212         case 0x39: /* lv.avg.b */
 213             goto unimp;
 214         case 0x3a: /* lv.avg.h */
 215             goto unimp;
 216         case 0x40: /* lv.cmp_eq.b */
 217             goto unimp;
 218         case 0x41: /* lv.cmp_eq.h */
 219             goto unimp;
 220         case 0x42: /* lv.cmp_ge.b */
 221             goto unimp;
 222         case 0x43: /* lv.cmp_ge.h */
 223             goto unimp;
 224         case 0x44: /* lv.cmp_gt.b */
 225             goto unimp;
 226         case 0x45: /* lv.cmp_gt.h */
 227             goto unimp;
 228         case 0x46: /* lv.cmp_le.b */
 229             goto unimp;
 230         case 0x47: /* lv.cmp_le.h */
 231             goto unimp;
 232         case 0x48: /* lv.cmp_lt.b */
 233             goto unimp;
 234         case 0x49: /* lv.cmp_lt.h */
 235             goto unimp;
 236         case 0x4a: /* lv.cmp_ne.b */
 237             goto unimp;
 238         case 0x4b: /* lv.cmp_ne.h */
 239             goto unimp;
 240         case 0x54: /* lv.madds.h */
 241             goto unimp;
 242         case 0x55: /* lv.max.b */
 243             goto unimp;
 244         case 0x56: /* lv.max.h */
 245             goto unimp;
 246         case 0x57: /* lv.merge.b */
 247             goto unimp;
 248         case 0x58: /* lv.merge.h */
 249             goto unimp;
 250         case 0x59: /* lv.min.b */
 251             goto unimp;
 252         case 0x5a: /* lv.min.h */
 253             goto unimp;
 254         case 0x5b: /* lv.msubs.h */
 255             goto unimp;
 256         case 0x5c: /* lv.muls.h */
 257             goto unimp;
 258         case 0x5d: /* lv.nand */
 259             goto unimp;
 260         case 0x5e: /* lv.nor */
 261             goto unimp;
 262         case 0x5f: /* lv.or */
 263             goto unimp;
 264         case 0x60: /* lv.pack.b */
 265             goto unimp;
 266         case 0x61: /* lv.pack.h */
 267             goto unimp;
 268         case 0x62: /* lv.packs.b */
 269             goto unimp;
 270         case 0x63: /* lv.packs.h */
 271             goto unimp;
 272         case 0x64: /* lv.packus.b */
 273             goto unimp;
 274         case 0x65: /* lv.packus.h */
 275             goto unimp;
 276         case 0x66: /* lv.perm.n */
 277             goto unimp;
 278         case 0x67: /* lv.rl.b */
 279             goto unimp;
 280         case 0x68: /* lv.rl.h */
 281             goto unimp;
 282         case 0x69: /* lv.sll.b */
 283             goto unimp;
 284         case 0x6a: /* lv.sll.h */
 285             goto unimp;
 286         case 0x6b: /* lv.sll */
 287             goto unimp;
 288         case 0x6c: /* lv.srl.b */
 289             goto unimp;
 290         case 0x6d: /* lv.srl.h */
 291             goto unimp;
 292         case 0x6e: /* lv.sra.b */
 293             goto unimp;
 294         case 0x6f: /* lv.sra.h */
 295             goto unimp;
 296         case 0x70: /* lv.sra */
 297             goto unimp;
 298         case 0x71: /* lv.sub.b */
 299             goto unimp;
 300         case 0x72: /* lv.sub.h */
 301             goto unimp;
 302         case 0x73: /* lv.subs.b */
 303             goto unimp;
 304         case 0x74: /* lv.subs.h */
 305             goto unimp;
 306         case 0x75: /* lv.subu.b */
 307             goto unimp;
 308         case 0x76: /* lv.subu.h */
 309             goto unimp;
 310         case 0x77: /* lv.subus.b */
 311             goto unimp;
 312         case 0x78: /* lv.subus.h */
 313             goto unimp;
 314         case 0x79: /* lv.unpack.b */
 315             goto unimp;
 316         case 0x7a: /* lv.unpack.h */
 317             goto unimp;
 318         case 0x7b: /* lv.xor.h */
 319             goto unimp;
 320         case 0xc0 ... 0xff: /* lv.cust[1234] */
 321             goto unimp;
 322         }
 323         break;
 324 #endif
 325
 326     case 0x11: /* l.jr */
 327         goto unimp;
 328     case 0x12: /* l.jalr */
 329         goto unimp;
 330     case 0x13: /* [l.maci] */
 331         goto unimp;
 332     case 0x1c: /* [l.cust1] */
 333         goto unimp;
 334     case 0x1d: /* [l.cust2] */
 335         goto unimp;
 336     case 0x1e: /* [l.cust3] */
 337         goto unimp;
 338     case 0x1f: /* [l.cust4] */
 339         goto unimp;
 340
 341     case 0x20 ... 0x26: /* Loads */
 342         t0 = tcg_temp_new();
 343         tcg_gen_addi_tl(t0, cpu_gpr[a], (int16_t)im16);
 344         switch (op) {
 345 #ifdef TARGET_OPENRISC64
 346         case 0x20: /* l.ld */
 347             tcg_gen_qemu_ld64(cpu_gpr[d], t0, dc->mem_idx);
 348             break;
 349 #endif
 350         case 0x21: /* l.lwz */
 351             tcg_gen_qemu_ld32u(cpu_gpr[d], t0, dc->mem_idx);
 352             break;
 353         case 0x22: /* l.lws */
 354             tcg_gen_qemu_ld32s(cpu_gpr[d], t0, dc->mem_idx);
 355             break;
 356         case 0x23: /* l.lbz */
 357             tcg_gen_qemu_ld8u(cpu_gpr[d], t0, dc->mem_idx);
 358             break;
 359         case 0x24: /* l.lbs */
 360             tcg_gen_qemu_ld8s(cpu_gpr[d], t0, dc->mem_idx);
 361             break;
 362         case 0x25: /* l.lhz */
 363             tcg_gen_qemu_ld16u(cpu_gpr[d], t0, dc->mem_idx);
 364             break;
 365         case 0x26: /* l.lhs */
 366             tcg_gen_qemu_ld16s(cpu_gpr[d], t0, dc->mem_idx);
 367             break;
 368         }
 369         tcg_temp_free(t0);
 370         break;
 371
 372     case 0x27: /* l.addi */
 373         tcg_gen_addi_tl(cpu_gpr[d], cpu_gpr[a], (int16_t)im16);
 374         break;
 375     case 0x28: /* l.addic */
 376         //tcg_gen_addi_tl(cpu_gpr[d], cpu_gpr[a], im);
 377         /* FIXME: also adds carry */
 378         goto unimp;
 379         break;
 380     case 0x29: /* l.andi */
 381         tcg_gen_andi_tl(cpu_gpr[d], cpu_gpr[a], im16);
 382         break;
 383     case 0x2a: /* l.ori */
 384         tcg_gen_ori_tl(cpu_gpr[d], cpu_gpr[a], im16);
 385         break;
 386     case 0x2b: /* l.xori */
 387         tcg_gen_ori_tl(cpu_gpr[d], cpu_gpr[a], im16);
 388         break;
 389     case 0x2c: /* l.muli */
 390         tcg_gen_muli_tl(cpu_gpr[d], cpu_gpr[a], im16);
 391         break;
 392
 393     case 0x2d: /* l.mfspr */
 394         goto unimp;
 395
 396     case 0x2e:
 397         switch (opext) {
 398         case 0x00: /* l.slli */
 399             // tcg_gen_shli_tl(cpu_gpr[d], cpu_gpr[a], im);
 400             goto unimp;
 401         case 0x01: /* l.srli */
 402             // tcg_gen_shri_tl(cpu_gpr[d], cpu_gpr[a], im);
 403             goto unimp;
 404         case 0x02: /* l.srai */
 405             // tcg_gen_sari_tl(cpu_gpr[d], cpu_gpr[a], im);
 406             goto unimp;
 407         case 0x03: /* [l.rori] */
 408             /* illegal instruction */
 409             goto unimp;
 410         }
 411         break;
 412
 413     case 0x30: /* l.mtspr */
 414
 415     case 0x31:
 416         switch (opext) {
 417         case 0x01: /* [l.mac] */
 418             goto unimp;
 419         case 0x02: /* [l.msb] */
 420             goto unimp;
 421         }
 422         break;
 423
 424     case 0x32: /* [floating point ops] */
 425         goto unimp;
 426
 427     case 0x34 ... 0x37: /* Stores */
 428         t0 = tcg_temp_new();
 429         tcg_gen_addi_tl(t0, cpu_gpr[a], (int16_t)im16b);
 430         switch (op) {
 431 #ifdef TARGET_OPENRISC64
 432         case 0x34: /* l.sd */
 433             tcg_gen_qemu_st64(cpu_gpr[b], t0, dc->mem_idx);
 434             break;
 435 #endif
 436         case 0x35: /* l.sw */
 437             tcg_gen_qemu_st32(cpu_gpr[b], t0, dc->mem_idx);
 438             break;
 439         case 0x36: /* l.sb */
 440             tcg_gen_qemu_st8(cpu_gpr[b], t0, dc->mem_idx);
 441             break;
 442         case 0x37: /* l.sh */
 443             tcg_gen_qemu_st16(cpu_gpr[b], t0, dc->mem_idx);
 444             break;
 445         }
 446         tcg_temp_free(t0);
 447         break;
 448
 449     case 0x38:
 450         switch (opext) {
 451         case 0x0: /* l.add */
 452             tcg_gen_add_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 453             break;
 454         case 0x1: /* l.addc */
 455             /* tcg_gen_add_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]); */
 456             /* FIXME: also adds carry */
 457             goto unimp;
 458         case 0x2: /* l.sub */
 459             tcg_gen_sub_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 460             break;
 461         case 0x3: /* l.and */
 462             tcg_gen_and_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 463             break;
 464         case 0x4: /* l.or */
 465             tcg_gen_or_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 466             break;
 467         case 0x5: /* l.xor */
 468             tcg_gen_xor_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 469             break;
 470         case 0x6: /* l.mul */
 471             tcg_gen_mul_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 472             break;
 473
 474         case 0x8: /* Shifts */
 475 #ifdef TARGET_OPENRISC64
 476             /* FIXME: only use bits 0..5 of shift reg */
 477 #else
 478             /* FIXME: only use bits 0..4 of shift reg */
 479 #endif
 480             switch (opext2) {
 481             case 0x0: /* l.sll */
 482                 tcg_gen_shl_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 483                 break;
 484             case 0x1: /* l.srl */
 485                 tcg_gen_shr_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 486                 break;
 487             case 0x2: /* l.sra */
 488                 tcg_gen_sar_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]);
 489                 break;
 490             case 0x3: /* [l.ror] */
 491                 /* tcg_gen_ror_tl(cpu_gpr[d], cpu_gpr[a], cpu_gpr[b]); */
 492                 /* illegal instruction */
 493                 goto unimp;
 494             }
 495             break;
 496
 497         case 0xb: /* l.mulu */
 498             goto unimp;
 499
 500         /* optional: */
 501         case 0x9: /* l.div */
 502             goto unimp;
 503         case 0xa: /* l.divu */
 504             goto unimp;
 505
 506         case 0xc:
 507             switch (opext2) {
 508             case 0x00: /* l.exths */
 509                 tcg_gen_ext16s_tl(cpu_gpr[d], cpu_gpr[a]);
 510                 break;
 511             case 0x01: /* l.extbs */
 512                 tcg_gen_ext8s_tl(cpu_gpr[d], cpu_gpr[a]);
 513                 break;
 514             case 0x02: /* l.exthz */
 515                 tcg_gen_ext16u_tl(cpu_gpr[d], cpu_gpr[a]);
 516                 break;
 517             case 0x03: /* l.extbz */
 518                 tcg_gen_ext8u_tl(cpu_gpr[d], cpu_gpr[a]);
 519                 break;
 520             }
 521             break;
 522
 523         case 0xd:
 524             switch (opext2) {
 525 #ifdef TARGET_OPENRISC64
 526             case 0x00: /* l.extws */
 527                 tcg_gen_ext32s_tl(cpu_gpr[d], cpu_gpr[a]);
 528                 break;
 529             case 0x01: /* l.extwz */
 530                 tcg_gen_ext32u_tl(cpu_gpr[d], cpu_gpr[a]);
 531                 break;
 532 #endif
 533             }
 534             break;
 535
 536         case 0x0e: /* l.cmov */
 537
 538         case 0xf:
 539             switch (opext2) {
 540             case 0x00: /* l.ff1 */
 541                 /* tcg_gen_clz_tl(cpu_gpr[d], cpu_gpr[a]); */
 542                 goto unimp;
 543             case 0x01: /* l.fl1 */
 544                 /* tcg_gen_ctz_tl(cpu_gpr[d], cpu_gpr[a]); */
 545                 goto unimp;
 546             }
 547             break;
 548         }
 549         break;
 550
 551     case 0x2f:
 552         l1 = gen_new_label();
 553         l2 = gen_new_label();
 554         switch (opext) {
 555         case 0x00: /* l.sfeqi */
 556             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a], im16, l1);
 557             break;
 558         case 0x01: /* l.sfnei */
 559             tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[a], im16, l1);
 560             break;
 561         case 0x02: /* l.sfgtui */
 562             tcg_gen_brcondi_tl(TCG_COND_GTU, cpu_gpr[a], im16, l1);
 563             break;
 564         case 0x03: /* l.sfgeui */
 565             tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_gpr[a], im16, l1);
 566             break;
 567         case 0x04: /* l.sfltui */
 568             tcg_gen_brcondi_tl(TCG_COND_LTU, cpu_gpr[a], im16, l1);
 569             break;
 570         case 0x05: /* l.sfleui */
 571             tcg_gen_brcondi_tl(TCG_COND_LEU, cpu_gpr[a], im16, l1);
 572             break;
 573         case 0x0a: /* l.sfgtsi */
 574             tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[a], im16, l1);
 575             break;
 576         case 0x0b: /* l.sfgesi */
 577             tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[a], im16, l1);
 578             break;
 579         case 0x0c: /* l.sfltsi */
 580             tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[a], im16, l1);
 581             break;
 582         case 0x0d: /* l.sflesi */
 583             tcg_gen_brcondi_tl(TCG_COND_LE, cpu_gpr[a], im16, l1);
 584             break;
 585         }
 586 //      use andi to clear the compare flag
 587 //      tcg_gen_movi_tl(t, 0);
 588         tcg_gen_br(l2);
 589         gen_set_label(l1);
 590 //      use ori to set the compare flag
 591 //      tcg_gen_movi_tl(t, 1);
 592         gen_set_label(l2);
 593         break;
 594
 595     case 0x39:
 596         l1 = gen_new_label();
 597         l2 = gen_new_label();
 598         switch (opext) {
 599         case 0x00: /* l.sfeq */
 600             tcg_gen_brcond_tl(TCG_COND_EQ, cpu_gpr[a], cpu_gpr[b], l1);
 601             break;
 602         case 0x01: /* l.sfne */
 603             tcg_gen_brcond_tl(TCG_COND_NE, cpu_gpr[a], cpu_gpr[b], l1);
 604             break;
 605         case 0x02: /* l.sfgtu */
 606             tcg_gen_brcond_tl(TCG_COND_GTU, cpu_gpr[a], cpu_gpr[b], l1);
 607             break;
 608         case 0x03: /* l.sfgeu */
 609             tcg_gen_brcond_tl(TCG_COND_GEU, cpu_gpr[a], cpu_gpr[b], l1);
 610             break;
 611         case 0x04: /* l.sfltu */
 612             tcg_gen_brcond_tl(TCG_COND_LTU, cpu_gpr[a], cpu_gpr[b], l1);
 613             break;
 614         case 0x05: /* l.sfleu */
 615             tcg_gen_brcond_tl(TCG_COND_LEU, cpu_gpr[a], cpu_gpr[b], l1);
 616             break;
 617         case 0x0a: /* l.sfgts */
 618             tcg_gen_brcond_tl(TCG_COND_GT, cpu_gpr[a], cpu_gpr[b], l1);
 619             break;
 620         case 0x0b: /* l.sfges */
 621             tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[a], cpu_gpr[b], l1);
 622             break;
 623         case 0x0c: /* l.sflts */
 624             tcg_gen_brcond_tl(TCG_COND_LT, cpu_gpr[a], cpu_gpr[b], l1);
 625             break;
 626         case 0x0d: /* l.sfles */
 627             tcg_gen_brcond_tl(TCG_COND_LE, cpu_gpr[a], cpu_gpr[b], l1);
 628             break;
 629         }
 630 //      use andi to clear the compare flag
 631 //      tcg_gen_movi_tl(t, 0);
 632         tcg_gen_br(l2);
 633         gen_set_label(l1);
 634 //      use ori to set the compare flag
 635 //      tcg_gen_movi_tl(t, 1);
 636         gen_set_label(l2);
 637         break;
 638
 639     case 0x3c: /* [l.cust5] */
 640         goto unimp;
 641     case 0x3d: /* [l.cust6] */
 642         goto unimp;
 643     case 0x3e: /* [l.cust7] */
 644         goto unimp;
 645     case 0x3f: /* [l.cust8] */
 646         goto unimp;
 647     }
 648     return;
 649  unimp:
 650     fprintf(stderr, "Unimp @" TARGET_FMT_lx " %08x\n", dc->pc, insn);
 651     abort();
 652 }
 653
 654 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
 655    basic block 'tb'. If search_pc is TRUE, also generate PC
 656    information for each intermediate instruction. */
 657 /* XXX: tempo */
 658 static inline void gen_intermediate_code_internal(CPUState *env,
 659                                                   TranslationBlock *tb,
 660                                                   int search_pc)
 661 {
 662     DisasContext dc1, *dc = &dc1;
 663     target_ulong pc_start;
 664
 665     pc_start = tb->pc;
 666
 667     dc->tb = tb;
 668
 669     dc->is_jmp = DISAS_NEXT;
 670     dc->pc = pc_start;
 671
 672     do {
 673         disas_openrisc_insn(dc);
 674     } while (0);
 675
 676     switch (dc->is_jmp) {
 677     case DISAS_NEXT:
 678         gen_goto_tb(dc, 1, dc->pc);
 679         break;
 680     }
 681
 682     *gen_opc_ptr = INDEX_op_end;
 683
 684 #ifdef DEBUG_DISAS
 685     if (loglevel & CPU_LOG_TB_IN_ASM) {
 686         fprintf(logfile, "----------------\n");
 687         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
 688         target_disas(logfile, pc_start, dc->pc - pc_start, 0);
 689         fprintf(logfile, "\n");
 690     }
 691 #endif
 692
 693     tb->size = dc->pc - pc_start;
 694 }
 695
 696 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
 697 {
 698     gen_intermediate_code_internal(env, tb, 0);
 699 }
 700
 701 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
 702 {
 703     gen_intermediate_code_internal(env, tb, 1);
 704 }
 705
 706 /* XXX: tempo */
 707 void cpu_dump_state(CPUState *env, FILE *f,
 708                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 709                     int flags)
 710 {
 711     fprintf(stderr, "pc=" TARGET_FMT_lx "\n", env->pc);
 712 }
 713
 714 /* XXX: tempo */
 715 void gen_pc_load(CPUState *env, TranslationBlock *tb,
 716                  unsigned long searched_pc, int pc_pos, void *puc)
 717 {
 718     env->pc = gen_opc_pc[pc_pos];
 719 }