2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
33 #include "qemu-common.h"
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
42 /* MIPS major opcodes */
43 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
46 /* indirect opcode tables */
47 OPC_SPECIAL
= (0x00 << 26),
48 OPC_REGIMM
= (0x01 << 26),
49 OPC_CP0
= (0x10 << 26),
50 OPC_CP1
= (0x11 << 26),
51 OPC_CP2
= (0x12 << 26),
52 OPC_CP3
= (0x13 << 26),
53 OPC_SPECIAL2
= (0x1C << 26),
54 OPC_SPECIAL3
= (0x1F << 26),
55 /* arithmetic with immediate */
56 OPC_ADDI
= (0x08 << 26),
57 OPC_ADDIU
= (0x09 << 26),
58 OPC_SLTI
= (0x0A << 26),
59 OPC_SLTIU
= (0x0B << 26),
60 OPC_ANDI
= (0x0C << 26),
61 OPC_ORI
= (0x0D << 26),
62 OPC_XORI
= (0x0E << 26),
63 OPC_LUI
= (0x0F << 26),
64 OPC_DADDI
= (0x18 << 26),
65 OPC_DADDIU
= (0x19 << 26),
66 /* Jump and branches */
68 OPC_JAL
= (0x03 << 26),
69 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
70 OPC_BEQL
= (0x14 << 26),
71 OPC_BNE
= (0x05 << 26),
72 OPC_BNEL
= (0x15 << 26),
73 OPC_BLEZ
= (0x06 << 26),
74 OPC_BLEZL
= (0x16 << 26),
75 OPC_BGTZ
= (0x07 << 26),
76 OPC_BGTZL
= (0x17 << 26),
77 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
79 OPC_LDL
= (0x1A << 26),
80 OPC_LDR
= (0x1B << 26),
81 OPC_LB
= (0x20 << 26),
82 OPC_LH
= (0x21 << 26),
83 OPC_LWL
= (0x22 << 26),
84 OPC_LW
= (0x23 << 26),
85 OPC_LBU
= (0x24 << 26),
86 OPC_LHU
= (0x25 << 26),
87 OPC_LWR
= (0x26 << 26),
88 OPC_LWU
= (0x27 << 26),
89 OPC_SB
= (0x28 << 26),
90 OPC_SH
= (0x29 << 26),
91 OPC_SWL
= (0x2A << 26),
92 OPC_SW
= (0x2B << 26),
93 OPC_SDL
= (0x2C << 26),
94 OPC_SDR
= (0x2D << 26),
95 OPC_SWR
= (0x2E << 26),
96 OPC_LL
= (0x30 << 26),
97 OPC_LLD
= (0x34 << 26),
98 OPC_LD
= (0x37 << 26),
99 OPC_SC
= (0x38 << 26),
100 OPC_SCD
= (0x3C << 26),
101 OPC_SD
= (0x3F << 26),
102 /* Floating point load/store */
103 OPC_LWC1
= (0x31 << 26),
104 OPC_LWC2
= (0x32 << 26),
105 OPC_LDC1
= (0x35 << 26),
106 OPC_LDC2
= (0x36 << 26),
107 OPC_SWC1
= (0x39 << 26),
108 OPC_SWC2
= (0x3A << 26),
109 OPC_SDC1
= (0x3D << 26),
110 OPC_SDC2
= (0x3E << 26),
111 /* MDMX ASE specific */
112 OPC_MDMX
= (0x1E << 26),
113 /* Cache and prefetch */
114 OPC_CACHE
= (0x2F << 26),
115 OPC_PREF
= (0x33 << 26),
116 /* Reserved major opcode */
117 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
120 /* MIPS special opcodes */
121 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
125 OPC_SLL
= 0x00 | OPC_SPECIAL
,
126 /* NOP is SLL r0, r0, 0 */
127 /* SSNOP is SLL r0, r0, 1 */
128 /* EHB is SLL r0, r0, 3 */
129 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
130 OPC_SRA
= 0x03 | OPC_SPECIAL
,
131 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
132 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
133 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
134 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
135 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
136 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
137 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
138 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
139 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
140 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
141 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
142 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
143 /* Multiplication / division */
144 OPC_MULT
= 0x18 | OPC_SPECIAL
,
145 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
146 OPC_DIV
= 0x1A | OPC_SPECIAL
,
147 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
148 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
149 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
150 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
151 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
152 /* 2 registers arithmetic / logic */
153 OPC_ADD
= 0x20 | OPC_SPECIAL
,
154 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
155 OPC_SUB
= 0x22 | OPC_SPECIAL
,
156 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
157 OPC_AND
= 0x24 | OPC_SPECIAL
,
158 OPC_OR
= 0x25 | OPC_SPECIAL
,
159 OPC_XOR
= 0x26 | OPC_SPECIAL
,
160 OPC_NOR
= 0x27 | OPC_SPECIAL
,
161 OPC_SLT
= 0x2A | OPC_SPECIAL
,
162 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
163 OPC_DADD
= 0x2C | OPC_SPECIAL
,
164 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
165 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
166 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
168 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
169 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
171 OPC_TGE
= 0x30 | OPC_SPECIAL
,
172 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
173 OPC_TLT
= 0x32 | OPC_SPECIAL
,
174 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
175 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
176 OPC_TNE
= 0x36 | OPC_SPECIAL
,
177 /* HI / LO registers load & stores */
178 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
179 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
180 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
181 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
182 /* Conditional moves */
183 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
184 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
186 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
189 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
190 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
191 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
192 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
193 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
195 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
196 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
197 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
198 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
199 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
200 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
201 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
204 /* Multiplication variants of the vr54xx. */
205 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
208 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
209 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
210 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
211 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
212 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
213 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
214 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
215 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
216 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
217 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
218 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
219 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
220 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
221 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
224 /* REGIMM (rt field) opcodes */
225 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
228 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
229 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
230 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
231 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
232 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
233 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
234 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
235 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
236 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
237 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
238 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
239 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
240 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
241 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
242 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
245 /* Special2 opcodes */
246 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
249 /* Multiply & xxx operations */
250 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
251 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
252 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
253 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
254 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
256 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
257 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
258 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
259 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
261 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
264 /* Special3 opcodes */
265 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
268 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
269 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
270 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
271 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
272 OPC_INS
= 0x04 | OPC_SPECIAL3
,
273 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
274 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
275 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
276 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
277 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
278 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
279 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
280 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
284 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
287 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
288 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
289 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
293 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
296 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
297 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
300 /* Coprocessor 0 (rs field) */
301 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
304 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
305 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
306 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
307 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
308 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
309 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
310 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
311 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
312 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
313 OPC_C0
= (0x10 << 21) | OPC_CP0
,
314 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
315 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
319 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
322 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
323 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
324 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
325 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
326 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
327 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
330 /* Coprocessor 0 (with rs == C0) */
331 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
334 OPC_TLBR
= 0x01 | OPC_C0
,
335 OPC_TLBWI
= 0x02 | OPC_C0
,
336 OPC_TLBWR
= 0x06 | OPC_C0
,
337 OPC_TLBP
= 0x08 | OPC_C0
,
338 OPC_RFE
= 0x10 | OPC_C0
,
339 OPC_ERET
= 0x18 | OPC_C0
,
340 OPC_DERET
= 0x1F | OPC_C0
,
341 OPC_WAIT
= 0x20 | OPC_C0
,
344 /* Coprocessor 1 (rs field) */
345 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
348 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
349 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
350 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
351 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
352 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
353 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
354 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
355 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
356 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
357 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
358 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
359 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
360 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
361 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
362 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
363 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
364 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
365 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
368 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
369 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
372 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
373 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
374 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
375 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
379 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
380 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
384 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
385 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
388 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
391 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
392 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
393 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
394 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
395 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
396 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
397 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
398 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
399 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
402 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
405 OPC_LWXC1
= 0x00 | OPC_CP3
,
406 OPC_LDXC1
= 0x01 | OPC_CP3
,
407 OPC_LUXC1
= 0x05 | OPC_CP3
,
408 OPC_SWXC1
= 0x08 | OPC_CP3
,
409 OPC_SDXC1
= 0x09 | OPC_CP3
,
410 OPC_SUXC1
= 0x0D | OPC_CP3
,
411 OPC_PREFX
= 0x0F | OPC_CP3
,
412 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
413 OPC_MADD_S
= 0x20 | OPC_CP3
,
414 OPC_MADD_D
= 0x21 | OPC_CP3
,
415 OPC_MADD_PS
= 0x26 | OPC_CP3
,
416 OPC_MSUB_S
= 0x28 | OPC_CP3
,
417 OPC_MSUB_D
= 0x29 | OPC_CP3
,
418 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
419 OPC_NMADD_S
= 0x30 | OPC_CP3
,
420 OPC_NMADD_D
= 0x31 | OPC_CP3
,
421 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
422 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
423 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
424 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
427 /* global register indices */
428 static TCGv_ptr cpu_env
;
429 static TCGv cpu_gpr
[32], cpu_PC
;
430 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
431 static TCGv cpu_dspctrl
, btarget
, bcond
;
432 static TCGv_i32 hflags
;
433 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
435 #include "gen-icount.h"
437 #define gen_helper_0i(name, arg) do { \
438 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
439 gen_helper_##name(helper_tmp); \
440 tcg_temp_free_i32(helper_tmp); \
443 #define gen_helper_1i(name, arg1, arg2) do { \
444 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
445 gen_helper_##name(arg1, helper_tmp); \
446 tcg_temp_free_i32(helper_tmp); \
449 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
450 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
451 gen_helper_##name(arg1, arg2, helper_tmp); \
452 tcg_temp_free_i32(helper_tmp); \
455 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
456 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
457 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
458 tcg_temp_free_i32(helper_tmp); \
461 typedef struct DisasContext
{
462 struct TranslationBlock
*tb
;
463 target_ulong pc
, saved_pc
;
465 /* Routine used to access memory */
467 uint32_t hflags
, saved_hflags
;
469 target_ulong btarget
;
473 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
474 * exception condition */
475 BS_STOP
= 1, /* We want to stop translation for any reason */
476 BS_BRANCH
= 2, /* We reached a branch condition */
477 BS_EXCP
= 3, /* We reached an exception condition */
480 static const char *regnames
[] =
481 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
482 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
483 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
484 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
486 static const char *regnames_HI
[] =
487 { "HI0", "HI1", "HI2", "HI3", };
489 static const char *regnames_LO
[] =
490 { "LO0", "LO1", "LO2", "LO3", };
492 static const char *regnames_ACX
[] =
493 { "ACX0", "ACX1", "ACX2", "ACX3", };
495 static const char *fregnames
[] =
496 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
501 #ifdef MIPS_DEBUG_DISAS
502 #define MIPS_DEBUG(fmt, args...) \
503 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
504 TARGET_FMT_lx ": %08x " fmt "\n", \
505 ctx->pc, ctx->opcode , ##args)
506 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
508 #define MIPS_DEBUG(fmt, args...) do { } while(0)
509 #define LOG_DISAS(...) do { } while (0)
512 #define MIPS_INVAL(op) \
514 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
515 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
518 /* General purpose registers moves. */
519 static inline void gen_load_gpr (TCGv t
, int reg
)
522 tcg_gen_movi_tl(t
, 0);
524 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
527 static inline void gen_store_gpr (TCGv t
, int reg
)
530 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
533 /* Moves to/from ACX register. */
534 static inline void gen_load_ACX (TCGv t
, int reg
)
536 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
539 static inline void gen_store_ACX (TCGv t
, int reg
)
541 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
544 /* Moves to/from shadow registers. */
545 static inline void gen_load_srsgpr (int from
, int to
)
547 TCGv r_tmp1
= tcg_temp_new();
550 tcg_gen_movi_tl(r_tmp1
, 0);
552 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
553 TCGv_ptr addr
= tcg_temp_new_ptr();
555 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
556 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
557 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
558 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
559 tcg_gen_ext_i32_ptr(addr
, r_tmp2
);
560 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
562 tcg_gen_ld_tl(r_tmp1
, addr
, sizeof(target_ulong
) * from
);
563 tcg_temp_free_ptr(addr
);
564 tcg_temp_free_i32(r_tmp2
);
566 gen_store_gpr(r_tmp1
, to
);
567 tcg_temp_free(r_tmp1
);
570 static inline void gen_store_srsgpr (int from
, int to
)
573 TCGv r_tmp1
= tcg_temp_new();
574 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
575 TCGv_ptr addr
= tcg_temp_new_ptr();
577 gen_load_gpr(r_tmp1
, from
);
578 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
579 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
580 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
581 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
582 tcg_gen_ext_i32_ptr(addr
, r_tmp2
);
583 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
585 tcg_gen_st_tl(r_tmp1
, addr
, sizeof(target_ulong
) * to
);
586 tcg_temp_free_ptr(addr
);
587 tcg_temp_free_i32(r_tmp2
);
588 tcg_temp_free(r_tmp1
);
592 /* Floating point register moves. */
593 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
595 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
598 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
600 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
603 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
605 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
608 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
610 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
613 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
615 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
616 tcg_gen_ld_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
618 TCGv_i32 t0
= tcg_temp_new_i32();
619 TCGv_i32 t1
= tcg_temp_new_i32();
620 gen_load_fpr32(t0
, reg
& ~1);
621 gen_load_fpr32(t1
, reg
| 1);
622 tcg_gen_concat_i32_i64(t
, t0
, t1
);
623 tcg_temp_free_i32(t0
);
624 tcg_temp_free_i32(t1
);
628 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
630 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
631 tcg_gen_st_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
633 TCGv_i64 t0
= tcg_temp_new_i64();
634 TCGv_i32 t1
= tcg_temp_new_i32();
635 tcg_gen_trunc_i64_i32(t1
, t
);
636 gen_store_fpr32(t1
, reg
& ~1);
637 tcg_gen_shri_i64(t0
, t
, 32);
638 tcg_gen_trunc_i64_i32(t1
, t0
);
639 gen_store_fpr32(t1
, reg
| 1);
640 tcg_temp_free_i32(t1
);
641 tcg_temp_free_i64(t0
);
645 static inline int get_fp_bit (int cc
)
653 #define FOP_CONDS(type, fmt, bits) \
654 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
655 TCGv_i##bits b, int cc) \
658 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
659 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
660 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
661 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
662 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
663 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
664 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
665 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
666 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
667 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
668 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
669 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
670 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
671 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
672 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
673 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
679 FOP_CONDS(abs
, d
, 64)
681 FOP_CONDS(abs
, s
, 32)
683 FOP_CONDS(abs
, ps
, 64)
687 #define OP_COND(name, cond) \
688 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \
690 int l1 = gen_new_label(); \
691 int l2 = gen_new_label(); \
693 tcg_gen_brcond_tl(cond, t0, t1, l1); \
694 tcg_gen_movi_tl(ret, 0); \
697 tcg_gen_movi_tl(ret, 1); \
700 OP_COND(eq
, TCG_COND_EQ
);
701 OP_COND(ne
, TCG_COND_NE
);
702 OP_COND(ge
, TCG_COND_GE
);
703 OP_COND(geu
, TCG_COND_GEU
);
704 OP_COND(lt
, TCG_COND_LT
);
705 OP_COND(ltu
, TCG_COND_LTU
);
708 #define OP_CONDI(name, cond) \
709 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \
711 int l1 = gen_new_label(); \
712 int l2 = gen_new_label(); \
714 tcg_gen_brcondi_tl(cond, t0, val, l1); \
715 tcg_gen_movi_tl(ret, 0); \
718 tcg_gen_movi_tl(ret, 1); \
721 OP_CONDI(lti
, TCG_COND_LT
);
722 OP_CONDI(ltiu
, TCG_COND_LTU
);
725 #define OP_CONDZ(name, cond) \
726 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \
728 int l1 = gen_new_label(); \
729 int l2 = gen_new_label(); \
731 tcg_gen_brcondi_tl(cond, t0, 0, l1); \
732 tcg_gen_movi_tl(ret, 0); \
735 tcg_gen_movi_tl(ret, 1); \
738 OP_CONDZ(gez
, TCG_COND_GE
);
739 OP_CONDZ(gtz
, TCG_COND_GT
);
740 OP_CONDZ(lez
, TCG_COND_LE
);
741 OP_CONDZ(ltz
, TCG_COND_LT
);
744 static inline void gen_save_pc(target_ulong pc
)
746 tcg_gen_movi_tl(cpu_PC
, pc
);
749 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
751 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
752 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
753 gen_save_pc(ctx
->pc
);
754 ctx
->saved_pc
= ctx
->pc
;
756 if (ctx
->hflags
!= ctx
->saved_hflags
) {
757 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
758 ctx
->saved_hflags
= ctx
->hflags
;
759 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
765 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
771 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
773 ctx
->saved_hflags
= ctx
->hflags
;
774 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
780 ctx
->btarget
= env
->btarget
;
786 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
788 TCGv_i32 texcp
= tcg_const_i32(excp
);
789 TCGv_i32 terr
= tcg_const_i32(err
);
790 save_cpu_state(ctx
, 1);
791 gen_helper_raise_exception_err(texcp
, terr
);
792 tcg_temp_free_i32(terr
);
793 tcg_temp_free_i32(texcp
);
794 gen_helper_interrupt_restart();
799 generate_exception (DisasContext
*ctx
, int excp
)
801 save_cpu_state(ctx
, 1);
802 gen_helper_0i(raise_exception
, excp
);
803 gen_helper_interrupt_restart();
807 /* Addresses computation */
808 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv t0
, TCGv t1
)
810 tcg_gen_add_tl(t0
, t0
, t1
);
812 #if defined(TARGET_MIPS64)
813 /* For compatibility with 32-bit code, data reference in user mode
814 with Status_UX = 0 should be casted to 32-bit and sign extended.
815 See the MIPS64 PRA manual, section 4.10. */
816 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
817 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
818 tcg_gen_ext32s_i64(t0
, t0
);
823 static inline void check_cp0_enabled(DisasContext
*ctx
)
825 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
826 generate_exception_err(ctx
, EXCP_CpU
, 1);
829 static inline void check_cp1_enabled(DisasContext
*ctx
)
831 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
832 generate_exception_err(ctx
, EXCP_CpU
, 1);
835 /* Verify that the processor is running with COP1X instructions enabled.
836 This is associated with the nabla symbol in the MIPS32 and MIPS64
839 static inline void check_cop1x(DisasContext
*ctx
)
841 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
842 generate_exception(ctx
, EXCP_RI
);
845 /* Verify that the processor is running with 64-bit floating-point
846 operations enabled. */
848 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
850 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
851 generate_exception(ctx
, EXCP_RI
);
855 * Verify if floating point register is valid; an operation is not defined
856 * if bit 0 of any register specification is set and the FR bit in the
857 * Status register equals zero, since the register numbers specify an
858 * even-odd pair of adjacent coprocessor general registers. When the FR bit
859 * in the Status register equals one, both even and odd register numbers
860 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
862 * Multiple 64 bit wide registers can be checked by calling
863 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
865 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
867 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
868 generate_exception(ctx
, EXCP_RI
);
871 /* This code generates a "reserved instruction" exception if the
872 CPU does not support the instruction set corresponding to flags. */
873 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
875 if (unlikely(!(env
->insn_flags
& flags
)))
876 generate_exception(ctx
, EXCP_RI
);
879 /* This code generates a "reserved instruction" exception if 64-bit
880 instructions are not enabled. */
881 static inline void check_mips_64(DisasContext
*ctx
)
883 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
884 generate_exception(ctx
, EXCP_RI
);
887 /* load/store instructions. */
888 #define OP_LD(insn,fname) \
889 static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
891 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
898 #if defined(TARGET_MIPS64)
904 #define OP_ST(insn,fname) \
905 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
907 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
912 #if defined(TARGET_MIPS64)
917 #define OP_LD_ATOMIC(insn,fname) \
918 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
920 tcg_gen_mov_tl(t1, t0); \
921 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
922 tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
924 OP_LD_ATOMIC(ll
,ld32s
);
925 #if defined(TARGET_MIPS64)
926 OP_LD_ATOMIC(lld
,ld64
);
930 #define OP_ST_ATOMIC(insn,fname,almask) \
931 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
933 TCGv r_tmp = tcg_temp_local_new(); \
934 int l1 = gen_new_label(); \
935 int l2 = gen_new_label(); \
936 int l3 = gen_new_label(); \
938 tcg_gen_andi_tl(r_tmp, t0, almask); \
939 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
940 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
941 generate_exception(ctx, EXCP_AdES); \
943 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
944 tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
945 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
946 tcg_gen_movi_tl(t0, 1); \
949 tcg_gen_movi_tl(t0, 0); \
951 tcg_temp_free(r_tmp); \
953 OP_ST_ATOMIC(sc
,st32
,0x3);
954 #if defined(TARGET_MIPS64)
955 OP_ST_ATOMIC(scd
,st64
,0x7);
960 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
961 int base
, int16_t offset
)
963 const char *opn
= "ldst";
964 TCGv t0
= tcg_temp_local_new();
965 TCGv t1
= tcg_temp_local_new();
968 tcg_gen_movi_tl(t0
, offset
);
969 } else if (offset
== 0) {
970 gen_load_gpr(t0
, base
);
972 tcg_gen_movi_tl(t0
, offset
);
973 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
975 /* Don't do NOP if destination is zero: we must perform the actual
978 #if defined(TARGET_MIPS64)
980 op_ldst_lwu(t0
, ctx
);
981 gen_store_gpr(t0
, rt
);
986 gen_store_gpr(t0
, rt
);
990 op_ldst_lld(t0
, t1
, ctx
);
991 gen_store_gpr(t0
, rt
);
995 gen_load_gpr(t1
, rt
);
996 op_ldst_sd(t0
, t1
, ctx
);
1000 save_cpu_state(ctx
, 1);
1001 gen_load_gpr(t1
, rt
);
1002 op_ldst_scd(t0
, t1
, ctx
);
1003 gen_store_gpr(t0
, rt
);
1007 save_cpu_state(ctx
, 1);
1008 gen_load_gpr(t1
, rt
);
1009 gen_helper_3i(ldl
, t1
, t0
, t1
, ctx
->mem_idx
);
1010 gen_store_gpr(t1
, rt
);
1014 save_cpu_state(ctx
, 1);
1015 gen_load_gpr(t1
, rt
);
1016 gen_helper_2i(sdl
, t0
, t1
, ctx
->mem_idx
);
1020 save_cpu_state(ctx
, 1);
1021 gen_load_gpr(t1
, rt
);
1022 gen_helper_3i(ldr
, t1
, t0
, t1
, ctx
->mem_idx
);
1023 gen_store_gpr(t1
, rt
);
1027 save_cpu_state(ctx
, 1);
1028 gen_load_gpr(t1
, rt
);
1029 gen_helper_2i(sdr
, t0
, t1
, ctx
->mem_idx
);
1034 op_ldst_lw(t0
, ctx
);
1035 gen_store_gpr(t0
, rt
);
1039 gen_load_gpr(t1
, rt
);
1040 op_ldst_sw(t0
, t1
, ctx
);
1044 op_ldst_lh(t0
, ctx
);
1045 gen_store_gpr(t0
, rt
);
1049 gen_load_gpr(t1
, rt
);
1050 op_ldst_sh(t0
, t1
, ctx
);
1054 op_ldst_lhu(t0
, ctx
);
1055 gen_store_gpr(t0
, rt
);
1059 op_ldst_lb(t0
, ctx
);
1060 gen_store_gpr(t0
, rt
);
1064 gen_load_gpr(t1
, rt
);
1065 op_ldst_sb(t0
, t1
, ctx
);
1069 op_ldst_lbu(t0
, ctx
);
1070 gen_store_gpr(t0
, rt
);
1074 save_cpu_state(ctx
, 1);
1075 gen_load_gpr(t1
, rt
);
1076 gen_helper_3i(lwl
, t1
, t0
, t1
, ctx
->mem_idx
);
1077 gen_store_gpr(t1
, rt
);
1081 save_cpu_state(ctx
, 1);
1082 gen_load_gpr(t1
, rt
);
1083 gen_helper_2i(swl
, t0
, t1
, ctx
->mem_idx
);
1087 save_cpu_state(ctx
, 1);
1088 gen_load_gpr(t1
, rt
);
1089 gen_helper_3i(lwr
, t1
, t0
, t1
, ctx
->mem_idx
);
1090 gen_store_gpr(t1
, rt
);
1094 save_cpu_state(ctx
, 1);
1095 gen_load_gpr(t1
, rt
);
1096 gen_helper_2i(swr
, t0
, t1
, ctx
->mem_idx
);
1100 op_ldst_ll(t0
, t1
, ctx
);
1101 gen_store_gpr(t0
, rt
);
1105 save_cpu_state(ctx
, 1);
1106 gen_load_gpr(t1
, rt
);
1107 op_ldst_sc(t0
, t1
, ctx
);
1108 gen_store_gpr(t0
, rt
);
1113 generate_exception(ctx
, EXCP_RI
);
1116 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1122 /* Load and store */
1123 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1124 int base
, int16_t offset
)
1126 const char *opn
= "flt_ldst";
1127 TCGv t0
= tcg_temp_local_new();
1130 tcg_gen_movi_tl(t0
, offset
);
1131 } else if (offset
== 0) {
1132 gen_load_gpr(t0
, base
);
1134 tcg_gen_movi_tl(t0
, offset
);
1135 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
1137 /* Don't do NOP if destination is zero: we must perform the actual
1142 TCGv_i32 fp0
= tcg_temp_new_i32();
1143 TCGv t1
= tcg_temp_new();
1145 tcg_gen_qemu_ld32s(t1
, t0
, ctx
->mem_idx
);
1146 tcg_gen_trunc_tl_i32(fp0
, t1
);
1147 gen_store_fpr32(fp0
, ft
);
1149 tcg_temp_free_i32(fp0
);
1155 TCGv_i32 fp0
= tcg_temp_new_i32();
1156 TCGv t1
= tcg_temp_new();
1158 gen_load_fpr32(fp0
, ft
);
1159 tcg_gen_extu_i32_tl(t1
, fp0
);
1160 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1162 tcg_temp_free_i32(fp0
);
1168 TCGv_i64 fp0
= tcg_temp_new_i64();
1170 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1171 gen_store_fpr64(ctx
, fp0
, ft
);
1172 tcg_temp_free_i64(fp0
);
1178 TCGv_i64 fp0
= tcg_temp_new_i64();
1180 gen_load_fpr64(ctx
, fp0
, ft
);
1181 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1182 tcg_temp_free_i64(fp0
);
1188 generate_exception(ctx
, EXCP_RI
);
1191 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1196 /* Arithmetic with immediate operand */
1197 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1198 int rt
, int rs
, int16_t imm
)
1201 const char *opn
= "imm arith";
1202 TCGv t0
= tcg_temp_local_new();
1204 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1205 /* If no destination, treat it as a NOP.
1206 For addi, we must generate the overflow exception when needed. */
1210 uimm
= (uint16_t)imm
;
1214 #if defined(TARGET_MIPS64)
1220 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1225 gen_load_gpr(t0
, rs
);
1228 tcg_gen_movi_tl(t0
, imm
<< 16);
1233 #if defined(TARGET_MIPS64)
1242 gen_load_gpr(t0
, rs
);
1248 TCGv r_tmp1
= tcg_temp_new();
1249 TCGv r_tmp2
= tcg_temp_new();
1250 int l1
= gen_new_label();
1252 save_cpu_state(ctx
, 1);
1253 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1254 tcg_gen_addi_tl(t0
, r_tmp1
, uimm
);
1256 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, ~uimm
);
1257 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1258 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1259 tcg_temp_free(r_tmp2
);
1260 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1261 /* operands of same sign, result different sign */
1262 generate_exception(ctx
, EXCP_OVERFLOW
);
1264 tcg_temp_free(r_tmp1
);
1266 tcg_gen_ext32s_tl(t0
, t0
);
1271 tcg_gen_addi_tl(t0
, t0
, uimm
);
1272 tcg_gen_ext32s_tl(t0
, t0
);
1275 #if defined(TARGET_MIPS64)
1278 TCGv r_tmp1
= tcg_temp_new();
1279 TCGv r_tmp2
= tcg_temp_new();
1280 int l1
= gen_new_label();
1282 save_cpu_state(ctx
, 1);
1283 tcg_gen_mov_tl(r_tmp1
, t0
);
1284 tcg_gen_addi_tl(t0
, t0
, uimm
);
1286 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, ~uimm
);
1287 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1288 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1289 tcg_temp_free(r_tmp2
);
1290 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1291 /* operands of same sign, result different sign */
1292 generate_exception(ctx
, EXCP_OVERFLOW
);
1294 tcg_temp_free(r_tmp1
);
1299 tcg_gen_addi_tl(t0
, t0
, uimm
);
1304 gen_op_lti(t0
, t0
, uimm
);
1308 gen_op_ltiu(t0
, t0
, uimm
);
1312 tcg_gen_andi_tl(t0
, t0
, uimm
);
1316 tcg_gen_ori_tl(t0
, t0
, uimm
);
1320 tcg_gen_xori_tl(t0
, t0
, uimm
);
1327 tcg_gen_shli_tl(t0
, t0
, uimm
);
1328 tcg_gen_ext32s_tl(t0
, t0
);
1332 tcg_gen_ext32s_tl(t0
, t0
);
1333 tcg_gen_sari_tl(t0
, t0
, uimm
);
1337 switch ((ctx
->opcode
>> 21) & 0x1f) {
1340 tcg_gen_ext32u_tl(t0
, t0
);
1341 tcg_gen_shri_tl(t0
, t0
, uimm
);
1343 tcg_gen_ext32s_tl(t0
, t0
);
1348 /* rotr is decoded as srl on non-R2 CPUs */
1349 if (env
->insn_flags
& ISA_MIPS32R2
) {
1351 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
1353 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1354 tcg_gen_rotri_i32(r_tmp1
, r_tmp1
, uimm
);
1355 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
1356 tcg_temp_free_i32(r_tmp1
);
1361 tcg_gen_ext32u_tl(t0
, t0
);
1362 tcg_gen_shri_tl(t0
, t0
, uimm
);
1364 tcg_gen_ext32s_tl(t0
, t0
);
1370 MIPS_INVAL("invalid srl flag");
1371 generate_exception(ctx
, EXCP_RI
);
1375 #if defined(TARGET_MIPS64)
1377 tcg_gen_shli_tl(t0
, t0
, uimm
);
1381 tcg_gen_sari_tl(t0
, t0
, uimm
);
1385 switch ((ctx
->opcode
>> 21) & 0x1f) {
1387 tcg_gen_shri_tl(t0
, t0
, uimm
);
1391 /* drotr is decoded as dsrl on non-R2 CPUs */
1392 if (env
->insn_flags
& ISA_MIPS32R2
) {
1394 tcg_gen_rotri_tl(t0
, t0
, uimm
);
1398 tcg_gen_shri_tl(t0
, t0
, uimm
);
1403 MIPS_INVAL("invalid dsrl flag");
1404 generate_exception(ctx
, EXCP_RI
);
1409 tcg_gen_shli_tl(t0
, t0
, uimm
+ 32);
1413 tcg_gen_sari_tl(t0
, t0
, uimm
+ 32);
1417 switch ((ctx
->opcode
>> 21) & 0x1f) {
1419 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1423 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1424 if (env
->insn_flags
& ISA_MIPS32R2
) {
1425 tcg_gen_rotri_tl(t0
, t0
, uimm
+ 32);
1428 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1433 MIPS_INVAL("invalid dsrl32 flag");
1434 generate_exception(ctx
, EXCP_RI
);
1441 generate_exception(ctx
, EXCP_RI
);
1444 gen_store_gpr(t0
, rt
);
1445 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1451 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1452 int rd
, int rs
, int rt
)
1454 const char *opn
= "arith";
1455 TCGv t0
= tcg_temp_local_new();
1456 TCGv t1
= tcg_temp_local_new();
1458 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1459 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1460 /* If no destination, treat it as a NOP.
1461 For add & sub, we must generate the overflow exception when needed. */
1465 gen_load_gpr(t0
, rs
);
1466 /* Specialcase the conventional move operation. */
1467 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1468 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1469 gen_store_gpr(t0
, rd
);
1472 gen_load_gpr(t1
, rt
);
1476 TCGv r_tmp1
= tcg_temp_new();
1477 TCGv r_tmp2
= tcg_temp_new();
1478 int l1
= gen_new_label();
1480 save_cpu_state(ctx
, 1);
1481 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1482 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1483 tcg_gen_add_tl(t0
, r_tmp1
, r_tmp2
);
1485 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1486 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1487 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1488 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1489 tcg_temp_free(r_tmp2
);
1490 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1491 /* operands of same sign, result different sign */
1492 generate_exception(ctx
, EXCP_OVERFLOW
);
1494 tcg_temp_free(r_tmp1
);
1496 tcg_gen_ext32s_tl(t0
, t0
);
1501 tcg_gen_add_tl(t0
, t0
, t1
);
1502 tcg_gen_ext32s_tl(t0
, t0
);
1507 TCGv r_tmp1
= tcg_temp_new();
1508 TCGv r_tmp2
= tcg_temp_new();
1509 int l1
= gen_new_label();
1511 save_cpu_state(ctx
, 1);
1512 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1513 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1514 tcg_gen_sub_tl(t0
, r_tmp1
, r_tmp2
);
1516 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1517 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1518 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1519 tcg_temp_free(r_tmp2
);
1520 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1521 /* operands of different sign, first operand and result different sign */
1522 generate_exception(ctx
, EXCP_OVERFLOW
);
1524 tcg_temp_free(r_tmp1
);
1526 tcg_gen_ext32s_tl(t0
, t0
);
1531 tcg_gen_sub_tl(t0
, t0
, t1
);
1532 tcg_gen_ext32s_tl(t0
, t0
);
1535 #if defined(TARGET_MIPS64)
1538 TCGv r_tmp1
= tcg_temp_new();
1539 TCGv r_tmp2
= tcg_temp_new();
1540 int l1
= gen_new_label();
1542 save_cpu_state(ctx
, 1);
1543 tcg_gen_mov_tl(r_tmp1
, t0
);
1544 tcg_gen_add_tl(t0
, t0
, t1
);
1546 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1547 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1548 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1549 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1550 tcg_temp_free(r_tmp2
);
1551 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1552 /* operands of same sign, result different sign */
1553 generate_exception(ctx
, EXCP_OVERFLOW
);
1555 tcg_temp_free(r_tmp1
);
1560 tcg_gen_add_tl(t0
, t0
, t1
);
1565 TCGv r_tmp1
= tcg_temp_new();
1566 TCGv r_tmp2
= tcg_temp_new();
1567 int l1
= gen_new_label();
1569 save_cpu_state(ctx
, 1);
1570 tcg_gen_mov_tl(r_tmp1
, t0
);
1571 tcg_gen_sub_tl(t0
, t0
, t1
);
1573 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1574 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1575 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1576 tcg_temp_free(r_tmp2
);
1577 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1578 /* operands of different sign, first operand and result different sign */
1579 generate_exception(ctx
, EXCP_OVERFLOW
);
1581 tcg_temp_free(r_tmp1
);
1586 tcg_gen_sub_tl(t0
, t0
, t1
);
1591 gen_op_lt(t0
, t0
, t1
);
1595 gen_op_ltu(t0
, t0
, t1
);
1599 tcg_gen_and_tl(t0
, t0
, t1
);
1603 tcg_gen_nor_tl(t0
, t0
, t1
);
1607 tcg_gen_or_tl(t0
, t0
, t1
);
1611 tcg_gen_xor_tl(t0
, t0
, t1
);
1615 tcg_gen_mul_tl(t0
, t0
, t1
);
1616 tcg_gen_ext32s_tl(t0
, t0
);
1621 int l1
= gen_new_label();
1623 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1624 gen_store_gpr(t0
, rd
);
1631 int l1
= gen_new_label();
1633 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
1634 gen_store_gpr(t0
, rd
);
1640 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1641 tcg_gen_shl_tl(t0
, t1
, t0
);
1642 tcg_gen_ext32s_tl(t0
, t0
);
1646 tcg_gen_ext32s_tl(t1
, t1
);
1647 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1648 tcg_gen_sar_tl(t0
, t1
, t0
);
1652 switch ((ctx
->opcode
>> 6) & 0x1f) {
1654 tcg_gen_ext32u_tl(t1
, t1
);
1655 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1656 tcg_gen_shr_tl(t0
, t1
, t0
);
1657 tcg_gen_ext32s_tl(t0
, t0
);
1661 /* rotrv is decoded as srlv on non-R2 CPUs */
1662 if (env
->insn_flags
& ISA_MIPS32R2
) {
1663 int l1
= gen_new_label();
1664 int l2
= gen_new_label();
1666 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1667 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1669 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
1670 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
1672 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1673 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1674 tcg_gen_rotr_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1675 tcg_temp_free_i32(r_tmp1
);
1676 tcg_temp_free_i32(r_tmp2
);
1680 tcg_gen_mov_tl(t0
, t1
);
1684 tcg_gen_ext32u_tl(t1
, t1
);
1685 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1686 tcg_gen_shr_tl(t0
, t1
, t0
);
1687 tcg_gen_ext32s_tl(t0
, t0
);
1692 MIPS_INVAL("invalid srlv flag");
1693 generate_exception(ctx
, EXCP_RI
);
1697 #if defined(TARGET_MIPS64)
1699 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1700 tcg_gen_shl_tl(t0
, t1
, t0
);
1704 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1705 tcg_gen_sar_tl(t0
, t1
, t0
);
1709 switch ((ctx
->opcode
>> 6) & 0x1f) {
1711 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1712 tcg_gen_shr_tl(t0
, t1
, t0
);
1716 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1717 if (env
->insn_flags
& ISA_MIPS32R2
) {
1718 int l1
= gen_new_label();
1719 int l2
= gen_new_label();
1721 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1722 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1724 tcg_gen_rotr_tl(t0
, t1
, t0
);
1728 tcg_gen_mov_tl(t0
, t1
);
1732 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1733 tcg_gen_shr_tl(t0
, t1
, t0
);
1738 MIPS_INVAL("invalid dsrlv flag");
1739 generate_exception(ctx
, EXCP_RI
);
1746 generate_exception(ctx
, EXCP_RI
);
1749 gen_store_gpr(t0
, rd
);
1751 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1757 /* Arithmetic on HI/LO registers */
1758 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1760 const char *opn
= "hilo";
1762 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1769 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[0]);
1773 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[0]);
1778 tcg_gen_mov_tl(cpu_HI
[0], cpu_gpr
[reg
]);
1780 tcg_gen_movi_tl(cpu_HI
[0], 0);
1785 tcg_gen_mov_tl(cpu_LO
[0], cpu_gpr
[reg
]);
1787 tcg_gen_movi_tl(cpu_LO
[0], 0);
1791 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1794 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1797 const char *opn
= "mul/div";
1803 #if defined(TARGET_MIPS64)
1807 t0
= tcg_temp_local_new();
1808 t1
= tcg_temp_local_new();
1811 t0
= tcg_temp_new();
1812 t1
= tcg_temp_new();
1816 gen_load_gpr(t0
, rs
);
1817 gen_load_gpr(t1
, rt
);
1821 int l1
= gen_new_label();
1822 int l2
= gen_new_label();
1824 tcg_gen_ext32s_tl(t0
, t0
);
1825 tcg_gen_ext32s_tl(t1
, t1
);
1826 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1827 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
1828 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
1830 tcg_gen_mov_tl(cpu_LO
[0], t0
);
1831 tcg_gen_movi_tl(cpu_HI
[0], 0);
1834 tcg_gen_div_tl(cpu_LO
[0], t0
, t1
);
1835 tcg_gen_rem_tl(cpu_HI
[0], t0
, t1
);
1836 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
1837 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
1844 int l1
= gen_new_label();
1846 tcg_gen_ext32u_tl(t0
, t0
);
1847 tcg_gen_ext32u_tl(t1
, t1
);
1848 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1849 tcg_gen_divu_tl(cpu_LO
[0], t0
, t1
);
1850 tcg_gen_remu_tl(cpu_HI
[0], t0
, t1
);
1851 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
1852 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
1859 TCGv_i64 t2
= tcg_temp_new_i64();
1860 TCGv_i64 t3
= tcg_temp_new_i64();
1862 tcg_gen_ext_tl_i64(t2
, t0
);
1863 tcg_gen_ext_tl_i64(t3
, t1
);
1864 tcg_gen_mul_i64(t2
, t2
, t3
);
1865 tcg_temp_free_i64(t3
);
1866 tcg_gen_trunc_i64_tl(t0
, t2
);
1867 tcg_gen_shri_i64(t2
, t2
, 32);
1868 tcg_gen_trunc_i64_tl(t1
, t2
);
1869 tcg_temp_free_i64(t2
);
1870 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1871 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1877 TCGv_i64 t2
= tcg_temp_new_i64();
1878 TCGv_i64 t3
= tcg_temp_new_i64();
1880 tcg_gen_ext32u_tl(t0
, t0
);
1881 tcg_gen_ext32u_tl(t1
, t1
);
1882 tcg_gen_extu_tl_i64(t2
, t0
);
1883 tcg_gen_extu_tl_i64(t3
, t1
);
1884 tcg_gen_mul_i64(t2
, t2
, t3
);
1885 tcg_temp_free_i64(t3
);
1886 tcg_gen_trunc_i64_tl(t0
, t2
);
1887 tcg_gen_shri_i64(t2
, t2
, 32);
1888 tcg_gen_trunc_i64_tl(t1
, t2
);
1889 tcg_temp_free_i64(t2
);
1890 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1891 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1895 #if defined(TARGET_MIPS64)
1898 int l1
= gen_new_label();
1899 int l2
= gen_new_label();
1901 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1902 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
1903 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
1904 tcg_gen_mov_tl(cpu_LO
[0], t0
);
1905 tcg_gen_movi_tl(cpu_HI
[0], 0);
1908 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
1909 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
1916 int l1
= gen_new_label();
1918 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1919 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
1920 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
1926 gen_helper_dmult(t0
, t1
);
1930 gen_helper_dmultu(t0
, t1
);
1936 TCGv_i64 t2
= tcg_temp_new_i64();
1937 TCGv_i64 t3
= tcg_temp_new_i64();
1939 tcg_gen_ext_tl_i64(t2
, t0
);
1940 tcg_gen_ext_tl_i64(t3
, t1
);
1941 tcg_gen_mul_i64(t2
, t2
, t3
);
1942 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
1943 tcg_gen_add_i64(t2
, t2
, t3
);
1944 tcg_temp_free_i64(t3
);
1945 tcg_gen_trunc_i64_tl(t0
, t2
);
1946 tcg_gen_shri_i64(t2
, t2
, 32);
1947 tcg_gen_trunc_i64_tl(t1
, t2
);
1948 tcg_temp_free_i64(t2
);
1949 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1950 tcg_gen_ext32s_tl(cpu_LO
[1], t1
);
1956 TCGv_i64 t2
= tcg_temp_new_i64();
1957 TCGv_i64 t3
= tcg_temp_new_i64();
1959 tcg_gen_ext32u_tl(t0
, t0
);
1960 tcg_gen_ext32u_tl(t1
, t1
);
1961 tcg_gen_extu_tl_i64(t2
, t0
);
1962 tcg_gen_extu_tl_i64(t3
, t1
);
1963 tcg_gen_mul_i64(t2
, t2
, t3
);
1964 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
1965 tcg_gen_add_i64(t2
, t2
, t3
);
1966 tcg_temp_free_i64(t3
);
1967 tcg_gen_trunc_i64_tl(t0
, t2
);
1968 tcg_gen_shri_i64(t2
, t2
, 32);
1969 tcg_gen_trunc_i64_tl(t1
, t2
);
1970 tcg_temp_free_i64(t2
);
1971 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1972 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1978 TCGv_i64 t2
= tcg_temp_new_i64();
1979 TCGv_i64 t3
= tcg_temp_new_i64();
1981 tcg_gen_ext_tl_i64(t2
, t0
);
1982 tcg_gen_ext_tl_i64(t3
, t1
);
1983 tcg_gen_mul_i64(t2
, t2
, t3
);
1984 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
1985 tcg_gen_sub_i64(t2
, t2
, t3
);
1986 tcg_temp_free_i64(t3
);
1987 tcg_gen_trunc_i64_tl(t0
, t2
);
1988 tcg_gen_shri_i64(t2
, t2
, 32);
1989 tcg_gen_trunc_i64_tl(t1
, t2
);
1990 tcg_temp_free_i64(t2
);
1991 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1992 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1998 TCGv_i64 t2
= tcg_temp_new_i64();
1999 TCGv_i64 t3
= tcg_temp_new_i64();
2001 tcg_gen_ext32u_tl(t0
, t0
);
2002 tcg_gen_ext32u_tl(t1
, t1
);
2003 tcg_gen_extu_tl_i64(t2
, t0
);
2004 tcg_gen_extu_tl_i64(t3
, t1
);
2005 tcg_gen_mul_i64(t2
, t2
, t3
);
2006 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2007 tcg_gen_sub_i64(t2
, t2
, t3
);
2008 tcg_temp_free_i64(t3
);
2009 tcg_gen_trunc_i64_tl(t0
, t2
);
2010 tcg_gen_shri_i64(t2
, t2
, 32);
2011 tcg_gen_trunc_i64_tl(t1
, t2
);
2012 tcg_temp_free_i64(t2
);
2013 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2014 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2020 generate_exception(ctx
, EXCP_RI
);
2023 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2029 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2030 int rd
, int rs
, int rt
)
2032 const char *opn
= "mul vr54xx";
2033 TCGv t0
= tcg_temp_new();
2034 TCGv t1
= tcg_temp_new();
2036 gen_load_gpr(t0
, rs
);
2037 gen_load_gpr(t1
, rt
);
2040 case OPC_VR54XX_MULS
:
2041 gen_helper_muls(t0
, t0
, t1
);
2044 case OPC_VR54XX_MULSU
:
2045 gen_helper_mulsu(t0
, t0
, t1
);
2048 case OPC_VR54XX_MACC
:
2049 gen_helper_macc(t0
, t0
, t1
);
2052 case OPC_VR54XX_MACCU
:
2053 gen_helper_maccu(t0
, t0
, t1
);
2056 case OPC_VR54XX_MSAC
:
2057 gen_helper_msac(t0
, t0
, t1
);
2060 case OPC_VR54XX_MSACU
:
2061 gen_helper_msacu(t0
, t0
, t1
);
2064 case OPC_VR54XX_MULHI
:
2065 gen_helper_mulhi(t0
, t0
, t1
);
2068 case OPC_VR54XX_MULHIU
:
2069 gen_helper_mulhiu(t0
, t0
, t1
);
2072 case OPC_VR54XX_MULSHI
:
2073 gen_helper_mulshi(t0
, t0
, t1
);
2076 case OPC_VR54XX_MULSHIU
:
2077 gen_helper_mulshiu(t0
, t0
, t1
);
2080 case OPC_VR54XX_MACCHI
:
2081 gen_helper_macchi(t0
, t0
, t1
);
2084 case OPC_VR54XX_MACCHIU
:
2085 gen_helper_macchiu(t0
, t0
, t1
);
2088 case OPC_VR54XX_MSACHI
:
2089 gen_helper_msachi(t0
, t0
, t1
);
2092 case OPC_VR54XX_MSACHIU
:
2093 gen_helper_msachiu(t0
, t0
, t1
);
2097 MIPS_INVAL("mul vr54xx");
2098 generate_exception(ctx
, EXCP_RI
);
2101 gen_store_gpr(t0
, rd
);
2102 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2109 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2112 const char *opn
= "CLx";
2120 t0
= tcg_temp_new();
2121 gen_load_gpr(t0
, rs
);
2124 gen_helper_clo(cpu_gpr
[rd
], t0
);
2128 gen_helper_clz(cpu_gpr
[rd
], t0
);
2131 #if defined(TARGET_MIPS64)
2133 gen_helper_dclo(cpu_gpr
[rd
], t0
);
2137 gen_helper_dclz(cpu_gpr
[rd
], t0
);
2142 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2147 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2148 int rs
, int rt
, int16_t imm
)
2151 TCGv t0
= tcg_temp_new();
2152 TCGv t1
= tcg_temp_new();
2155 /* Load needed operands */
2163 /* Compare two registers */
2165 gen_load_gpr(t0
, rs
);
2166 gen_load_gpr(t1
, rt
);
2176 /* Compare register to immediate */
2177 if (rs
!= 0 || imm
!= 0) {
2178 gen_load_gpr(t0
, rs
);
2179 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2186 case OPC_TEQ
: /* rs == rs */
2187 case OPC_TEQI
: /* r0 == 0 */
2188 case OPC_TGE
: /* rs >= rs */
2189 case OPC_TGEI
: /* r0 >= 0 */
2190 case OPC_TGEU
: /* rs >= rs unsigned */
2191 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2193 generate_exception(ctx
, EXCP_TRAP
);
2195 case OPC_TLT
: /* rs < rs */
2196 case OPC_TLTI
: /* r0 < 0 */
2197 case OPC_TLTU
: /* rs < rs unsigned */
2198 case OPC_TLTIU
: /* r0 < 0 unsigned */
2199 case OPC_TNE
: /* rs != rs */
2200 case OPC_TNEI
: /* r0 != 0 */
2201 /* Never trap: treat as NOP. */
2205 int l1
= gen_new_label();
2210 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
2214 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
2218 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
2222 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
2226 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
2230 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
2233 generate_exception(ctx
, EXCP_TRAP
);
2240 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2242 TranslationBlock
*tb
;
2244 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2247 tcg_gen_exit_tb((long)tb
+ n
);
2254 /* Branches (before delay slot) */
2255 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2256 int rs
, int rt
, int32_t offset
)
2258 target_ulong btgt
= -1;
2260 int bcond_compute
= 0;
2261 TCGv t0
= tcg_temp_new();
2262 TCGv t1
= tcg_temp_new();
2264 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2265 #ifdef MIPS_DEBUG_DISAS
2266 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n", ctx
->pc
);
2268 generate_exception(ctx
, EXCP_RI
);
2272 /* Load needed operands */
2278 /* Compare two registers */
2280 gen_load_gpr(t0
, rs
);
2281 gen_load_gpr(t1
, rt
);
2284 btgt
= ctx
->pc
+ 4 + offset
;
2298 /* Compare to zero */
2300 gen_load_gpr(t0
, rs
);
2303 btgt
= ctx
->pc
+ 4 + offset
;
2307 /* Jump to immediate */
2308 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2312 /* Jump to register */
2313 if (offset
!= 0 && offset
!= 16) {
2314 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2315 others are reserved. */
2316 MIPS_INVAL("jump hint");
2317 generate_exception(ctx
, EXCP_RI
);
2320 gen_load_gpr(btarget
, rs
);
2323 MIPS_INVAL("branch/jump");
2324 generate_exception(ctx
, EXCP_RI
);
2327 if (bcond_compute
== 0) {
2328 /* No condition to be computed */
2330 case OPC_BEQ
: /* rx == rx */
2331 case OPC_BEQL
: /* rx == rx likely */
2332 case OPC_BGEZ
: /* 0 >= 0 */
2333 case OPC_BGEZL
: /* 0 >= 0 likely */
2334 case OPC_BLEZ
: /* 0 <= 0 */
2335 case OPC_BLEZL
: /* 0 <= 0 likely */
2337 ctx
->hflags
|= MIPS_HFLAG_B
;
2338 MIPS_DEBUG("balways");
2340 case OPC_BGEZAL
: /* 0 >= 0 */
2341 case OPC_BGEZALL
: /* 0 >= 0 likely */
2342 /* Always take and link */
2344 ctx
->hflags
|= MIPS_HFLAG_B
;
2345 MIPS_DEBUG("balways and link");
2347 case OPC_BNE
: /* rx != rx */
2348 case OPC_BGTZ
: /* 0 > 0 */
2349 case OPC_BLTZ
: /* 0 < 0 */
2351 MIPS_DEBUG("bnever (NOP)");
2353 case OPC_BLTZAL
: /* 0 < 0 */
2354 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2355 MIPS_DEBUG("bnever and link");
2357 case OPC_BLTZALL
: /* 0 < 0 likely */
2358 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2359 /* Skip the instruction in the delay slot */
2360 MIPS_DEBUG("bnever, link and skip");
2363 case OPC_BNEL
: /* rx != rx likely */
2364 case OPC_BGTZL
: /* 0 > 0 likely */
2365 case OPC_BLTZL
: /* 0 < 0 likely */
2366 /* Skip the instruction in the delay slot */
2367 MIPS_DEBUG("bnever and skip");
2371 ctx
->hflags
|= MIPS_HFLAG_B
;
2372 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2376 ctx
->hflags
|= MIPS_HFLAG_B
;
2377 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2380 ctx
->hflags
|= MIPS_HFLAG_BR
;
2381 MIPS_DEBUG("jr %s", regnames
[rs
]);
2385 ctx
->hflags
|= MIPS_HFLAG_BR
;
2386 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2389 MIPS_INVAL("branch/jump");
2390 generate_exception(ctx
, EXCP_RI
);
2396 gen_op_eq(bcond
, t0
, t1
);
2397 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2398 regnames
[rs
], regnames
[rt
], btgt
);
2401 gen_op_eq(bcond
, t0
, t1
);
2402 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2403 regnames
[rs
], regnames
[rt
], btgt
);
2406 gen_op_ne(bcond
, t0
, t1
);
2407 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2408 regnames
[rs
], regnames
[rt
], btgt
);
2411 gen_op_ne(bcond
, t0
, t1
);
2412 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2413 regnames
[rs
], regnames
[rt
], btgt
);
2416 gen_op_gez(bcond
, t0
);
2417 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2420 gen_op_gez(bcond
, t0
);
2421 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2424 gen_op_gez(bcond
, t0
);
2425 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2429 gen_op_gez(bcond
, t0
);
2431 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2434 gen_op_gtz(bcond
, t0
);
2435 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2438 gen_op_gtz(bcond
, t0
);
2439 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2442 gen_op_lez(bcond
, t0
);
2443 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2446 gen_op_lez(bcond
, t0
);
2447 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2450 gen_op_ltz(bcond
, t0
);
2451 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2454 gen_op_ltz(bcond
, t0
);
2455 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2458 gen_op_ltz(bcond
, t0
);
2460 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2462 ctx
->hflags
|= MIPS_HFLAG_BC
;
2465 gen_op_ltz(bcond
, t0
);
2467 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2469 ctx
->hflags
|= MIPS_HFLAG_BL
;
2472 MIPS_INVAL("conditional branch/jump");
2473 generate_exception(ctx
, EXCP_RI
);
2477 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2478 blink
, ctx
->hflags
, btgt
);
2480 ctx
->btarget
= btgt
;
2482 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ 8);
2490 /* special3 bitfield operations */
2491 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2492 int rs
, int lsb
, int msb
)
2494 TCGv t0
= tcg_temp_new();
2495 TCGv t1
= tcg_temp_new();
2498 gen_load_gpr(t1
, rs
);
2503 tcg_gen_shri_tl(t0
, t1
, lsb
);
2505 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2507 tcg_gen_ext32s_tl(t0
, t0
);
2510 #if defined(TARGET_MIPS64)
2512 tcg_gen_shri_tl(t0
, t1
, lsb
);
2514 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2518 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2519 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2522 tcg_gen_shri_tl(t0
, t1
, lsb
);
2523 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2529 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2530 gen_load_gpr(t0
, rt
);
2531 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2532 tcg_gen_shli_tl(t1
, t1
, lsb
);
2533 tcg_gen_andi_tl(t1
, t1
, mask
);
2534 tcg_gen_or_tl(t0
, t0
, t1
);
2535 tcg_gen_ext32s_tl(t0
, t0
);
2537 #if defined(TARGET_MIPS64)
2541 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2542 gen_load_gpr(t0
, rt
);
2543 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2544 tcg_gen_shli_tl(t1
, t1
, lsb
);
2545 tcg_gen_andi_tl(t1
, t1
, mask
);
2546 tcg_gen_or_tl(t0
, t0
, t1
);
2551 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2552 gen_load_gpr(t0
, rt
);
2553 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2554 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2555 tcg_gen_andi_tl(t1
, t1
, mask
);
2556 tcg_gen_or_tl(t0
, t0
, t1
);
2561 gen_load_gpr(t0
, rt
);
2562 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2563 gen_load_gpr(t0
, rt
);
2564 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2565 tcg_gen_shli_tl(t1
, t1
, lsb
);
2566 tcg_gen_andi_tl(t1
, t1
, mask
);
2567 tcg_gen_or_tl(t0
, t0
, t1
);
2572 MIPS_INVAL("bitops");
2573 generate_exception(ctx
, EXCP_RI
);
2578 gen_store_gpr(t0
, rt
);
2583 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2588 /* If no destination, treat it as a NOP. */
2593 t0
= tcg_temp_new();
2594 gen_load_gpr(t0
, rt
);
2598 TCGv t1
= tcg_temp_new();
2600 tcg_gen_shri_tl(t1
, t0
, 8);
2601 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
2602 tcg_gen_shli_tl(t0
, t0
, 8);
2603 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
2604 tcg_gen_or_tl(t0
, t0
, t1
);
2606 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
2610 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
2613 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
2615 #if defined(TARGET_MIPS64)
2618 TCGv t1
= tcg_temp_new();
2620 tcg_gen_shri_tl(t1
, t0
, 8);
2621 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
2622 tcg_gen_shli_tl(t0
, t0
, 8);
2623 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
2624 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2630 TCGv t1
= tcg_temp_new();
2632 tcg_gen_shri_tl(t1
, t0
, 16);
2633 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
2634 tcg_gen_shli_tl(t0
, t0
, 16);
2635 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
2636 tcg_gen_or_tl(t0
, t0
, t1
);
2637 tcg_gen_shri_tl(t1
, t0
, 32);
2638 tcg_gen_shli_tl(t0
, t0
, 32);
2639 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2645 MIPS_INVAL("bsfhl");
2646 generate_exception(ctx
, EXCP_RI
);
2653 #ifndef CONFIG_USER_ONLY
2654 /* CP0 (MMU and control) */
2655 static inline void gen_mfc0_load32 (TCGv t
, target_ulong off
)
2657 TCGv_i32 r_tmp
= tcg_temp_new_i32();
2659 tcg_gen_ld_i32(r_tmp
, cpu_env
, off
);
2660 tcg_gen_ext_i32_tl(t
, r_tmp
);
2661 tcg_temp_free_i32(r_tmp
);
2664 static inline void gen_mfc0_load64 (TCGv t
, target_ulong off
)
2666 tcg_gen_ld_tl(t
, cpu_env
, off
);
2667 tcg_gen_ext32s_tl(t
, t
);
2670 static inline void gen_mtc0_store32 (TCGv t
, target_ulong off
)
2672 TCGv_i32 r_tmp
= tcg_temp_new_i32();
2674 tcg_gen_trunc_tl_i32(r_tmp
, t
);
2675 tcg_gen_st_i32(r_tmp
, cpu_env
, off
);
2676 tcg_temp_free_i32(r_tmp
);
2679 static inline void gen_mtc0_store64 (TCGv t
, target_ulong off
)
2681 tcg_gen_ext32s_tl(t
, t
);
2682 tcg_gen_st_tl(t
, cpu_env
, off
);
2685 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
2687 const char *rn
= "invalid";
2690 check_insn(env
, ctx
, ISA_MIPS32
);
2696 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
2700 check_insn(env
, ctx
, ASE_MT
);
2701 gen_helper_mfc0_mvpcontrol(t0
);
2705 check_insn(env
, ctx
, ASE_MT
);
2706 gen_helper_mfc0_mvpconf0(t0
);
2710 check_insn(env
, ctx
, ASE_MT
);
2711 gen_helper_mfc0_mvpconf1(t0
);
2721 gen_helper_mfc0_random(t0
);
2725 check_insn(env
, ctx
, ASE_MT
);
2726 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
2730 check_insn(env
, ctx
, ASE_MT
);
2731 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
2735 check_insn(env
, ctx
, ASE_MT
);
2736 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
2740 check_insn(env
, ctx
, ASE_MT
);
2741 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_YQMask
));
2745 check_insn(env
, ctx
, ASE_MT
);
2746 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
2750 check_insn(env
, ctx
, ASE_MT
);
2751 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
2752 rn
= "VPEScheFBack";
2755 check_insn(env
, ctx
, ASE_MT
);
2756 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
2766 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2767 tcg_gen_ext32s_tl(t0
, t0
);
2771 check_insn(env
, ctx
, ASE_MT
);
2772 gen_helper_mfc0_tcstatus(t0
);
2776 check_insn(env
, ctx
, ASE_MT
);
2777 gen_helper_mfc0_tcbind(t0
);
2781 check_insn(env
, ctx
, ASE_MT
);
2782 gen_helper_mfc0_tcrestart(t0
);
2786 check_insn(env
, ctx
, ASE_MT
);
2787 gen_helper_mfc0_tchalt(t0
);
2791 check_insn(env
, ctx
, ASE_MT
);
2792 gen_helper_mfc0_tccontext(t0
);
2796 check_insn(env
, ctx
, ASE_MT
);
2797 gen_helper_mfc0_tcschedule(t0
);
2801 check_insn(env
, ctx
, ASE_MT
);
2802 gen_helper_mfc0_tcschefback(t0
);
2812 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
2813 tcg_gen_ext32s_tl(t0
, t0
);
2823 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
2824 tcg_gen_ext32s_tl(t0
, t0
);
2828 // gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
2829 rn
= "ContextConfig";
2838 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
2842 check_insn(env
, ctx
, ISA_MIPS32R2
);
2843 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
2853 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
2857 check_insn(env
, ctx
, ISA_MIPS32R2
);
2858 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
2862 check_insn(env
, ctx
, ISA_MIPS32R2
);
2863 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
2867 check_insn(env
, ctx
, ISA_MIPS32R2
);
2868 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
2872 check_insn(env
, ctx
, ISA_MIPS32R2
);
2873 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
2877 check_insn(env
, ctx
, ISA_MIPS32R2
);
2878 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
2888 check_insn(env
, ctx
, ISA_MIPS32R2
);
2889 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
2899 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
2900 tcg_gen_ext32s_tl(t0
, t0
);
2910 /* Mark as an IO operation because we read the time. */
2913 gen_helper_mfc0_count(t0
);
2916 ctx
->bstate
= BS_STOP
;
2920 /* 6,7 are implementation dependent */
2928 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
2929 tcg_gen_ext32s_tl(t0
, t0
);
2939 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
2942 /* 6,7 are implementation dependent */
2950 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
2954 check_insn(env
, ctx
, ISA_MIPS32R2
);
2955 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
2959 check_insn(env
, ctx
, ISA_MIPS32R2
);
2960 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
2964 check_insn(env
, ctx
, ISA_MIPS32R2
);
2965 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
2975 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
2985 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
2986 tcg_gen_ext32s_tl(t0
, t0
);
2996 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
3000 check_insn(env
, ctx
, ISA_MIPS32R2
);
3001 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
3011 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
3015 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
3019 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
3023 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
3026 /* 4,5 are reserved */
3027 /* 6,7 are implementation dependent */
3029 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
3033 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
3043 gen_helper_mfc0_lladdr(t0
);
3053 gen_helper_1i(mfc0_watchlo
, t0
, sel
);
3063 gen_helper_1i(mfc0_watchhi
, t0
, sel
);
3073 #if defined(TARGET_MIPS64)
3074 check_insn(env
, ctx
, ISA_MIPS3
);
3075 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3076 tcg_gen_ext32s_tl(t0
, t0
);
3085 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3088 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
3096 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
3097 rn
= "'Diagnostic"; /* implementation dependent */
3102 gen_helper_mfc0_debug(t0
); /* EJTAG support */
3106 // gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
3107 rn
= "TraceControl";
3110 // gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
3111 rn
= "TraceControl2";
3114 // gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
3115 rn
= "UserTraceData";
3118 // gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
3129 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3130 tcg_gen_ext32s_tl(t0
, t0
);
3140 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
3141 rn
= "Performance0";
3144 // gen_helper_mfc0_performance1(t0);
3145 rn
= "Performance1";
3148 // gen_helper_mfc0_performance2(t0);
3149 rn
= "Performance2";
3152 // gen_helper_mfc0_performance3(t0);
3153 rn
= "Performance3";
3156 // gen_helper_mfc0_performance4(t0);
3157 rn
= "Performance4";
3160 // gen_helper_mfc0_performance5(t0);
3161 rn
= "Performance5";
3164 // gen_helper_mfc0_performance6(t0);
3165 rn
= "Performance6";
3168 // gen_helper_mfc0_performance7(t0);
3169 rn
= "Performance7";
3176 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
3182 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
3195 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
3202 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
3215 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
3222 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
3232 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3233 tcg_gen_ext32s_tl(t0
, t0
);
3244 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3254 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3258 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3259 generate_exception(ctx
, EXCP_RI
);
3262 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3264 const char *rn
= "invalid";
3267 check_insn(env
, ctx
, ISA_MIPS32
);
3276 gen_helper_mtc0_index(t0
);
3280 check_insn(env
, ctx
, ASE_MT
);
3281 gen_helper_mtc0_mvpcontrol(t0
);
3285 check_insn(env
, ctx
, ASE_MT
);
3290 check_insn(env
, ctx
, ASE_MT
);
3305 check_insn(env
, ctx
, ASE_MT
);
3306 gen_helper_mtc0_vpecontrol(t0
);
3310 check_insn(env
, ctx
, ASE_MT
);
3311 gen_helper_mtc0_vpeconf0(t0
);
3315 check_insn(env
, ctx
, ASE_MT
);
3316 gen_helper_mtc0_vpeconf1(t0
);
3320 check_insn(env
, ctx
, ASE_MT
);
3321 gen_helper_mtc0_yqmask(t0
);
3325 check_insn(env
, ctx
, ASE_MT
);
3326 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
3330 check_insn(env
, ctx
, ASE_MT
);
3331 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
3332 rn
= "VPEScheFBack";
3335 check_insn(env
, ctx
, ASE_MT
);
3336 gen_helper_mtc0_vpeopt(t0
);
3346 gen_helper_mtc0_entrylo0(t0
);
3350 check_insn(env
, ctx
, ASE_MT
);
3351 gen_helper_mtc0_tcstatus(t0
);
3355 check_insn(env
, ctx
, ASE_MT
);
3356 gen_helper_mtc0_tcbind(t0
);
3360 check_insn(env
, ctx
, ASE_MT
);
3361 gen_helper_mtc0_tcrestart(t0
);
3365 check_insn(env
, ctx
, ASE_MT
);
3366 gen_helper_mtc0_tchalt(t0
);
3370 check_insn(env
, ctx
, ASE_MT
);
3371 gen_helper_mtc0_tccontext(t0
);
3375 check_insn(env
, ctx
, ASE_MT
);
3376 gen_helper_mtc0_tcschedule(t0
);
3380 check_insn(env
, ctx
, ASE_MT
);
3381 gen_helper_mtc0_tcschefback(t0
);
3391 gen_helper_mtc0_entrylo1(t0
);
3401 gen_helper_mtc0_context(t0
);
3405 // gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
3406 rn
= "ContextConfig";
3415 gen_helper_mtc0_pagemask(t0
);
3419 check_insn(env
, ctx
, ISA_MIPS32R2
);
3420 gen_helper_mtc0_pagegrain(t0
);
3430 gen_helper_mtc0_wired(t0
);
3434 check_insn(env
, ctx
, ISA_MIPS32R2
);
3435 gen_helper_mtc0_srsconf0(t0
);
3439 check_insn(env
, ctx
, ISA_MIPS32R2
);
3440 gen_helper_mtc0_srsconf1(t0
);
3444 check_insn(env
, ctx
, ISA_MIPS32R2
);
3445 gen_helper_mtc0_srsconf2(t0
);
3449 check_insn(env
, ctx
, ISA_MIPS32R2
);
3450 gen_helper_mtc0_srsconf3(t0
);
3454 check_insn(env
, ctx
, ISA_MIPS32R2
);
3455 gen_helper_mtc0_srsconf4(t0
);
3465 check_insn(env
, ctx
, ISA_MIPS32R2
);
3466 gen_helper_mtc0_hwrena(t0
);
3480 gen_helper_mtc0_count(t0
);
3483 /* 6,7 are implementation dependent */
3487 /* Stop translation as we may have switched the execution mode */
3488 ctx
->bstate
= BS_STOP
;
3493 gen_helper_mtc0_entryhi(t0
);
3503 gen_helper_mtc0_compare(t0
);
3506 /* 6,7 are implementation dependent */
3510 /* Stop translation as we may have switched the execution mode */
3511 ctx
->bstate
= BS_STOP
;
3516 gen_helper_mtc0_status(t0
);
3517 /* BS_STOP isn't good enough here, hflags may have changed. */
3518 gen_save_pc(ctx
->pc
+ 4);
3519 ctx
->bstate
= BS_EXCP
;
3523 check_insn(env
, ctx
, ISA_MIPS32R2
);
3524 gen_helper_mtc0_intctl(t0
);
3525 /* Stop translation as we may have switched the execution mode */
3526 ctx
->bstate
= BS_STOP
;
3530 check_insn(env
, ctx
, ISA_MIPS32R2
);
3531 gen_helper_mtc0_srsctl(t0
);
3532 /* Stop translation as we may have switched the execution mode */
3533 ctx
->bstate
= BS_STOP
;
3537 check_insn(env
, ctx
, ISA_MIPS32R2
);
3538 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3539 /* Stop translation as we may have switched the execution mode */
3540 ctx
->bstate
= BS_STOP
;
3550 gen_helper_mtc0_cause(t0
);
3556 /* Stop translation as we may have switched the execution mode */
3557 ctx
->bstate
= BS_STOP
;
3562 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_EPC
));
3576 check_insn(env
, ctx
, ISA_MIPS32R2
);
3577 gen_helper_mtc0_ebase(t0
);
3587 gen_helper_mtc0_config0(t0
);
3589 /* Stop translation as we may have switched the execution mode */
3590 ctx
->bstate
= BS_STOP
;
3593 /* ignored, read only */
3597 gen_helper_mtc0_config2(t0
);
3599 /* Stop translation as we may have switched the execution mode */
3600 ctx
->bstate
= BS_STOP
;
3603 /* ignored, read only */
3606 /* 4,5 are reserved */
3607 /* 6,7 are implementation dependent */
3617 rn
= "Invalid config selector";
3634 gen_helper_1i(mtc0_watchlo
, t0
, sel
);
3644 gen_helper_1i(mtc0_watchhi
, t0
, sel
);
3654 #if defined(TARGET_MIPS64)
3655 check_insn(env
, ctx
, ISA_MIPS3
);
3656 gen_helper_mtc0_xcontext(t0
);
3665 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3668 gen_helper_mtc0_framemask(t0
);
3677 rn
= "Diagnostic"; /* implementation dependent */
3682 gen_helper_mtc0_debug(t0
); /* EJTAG support */
3683 /* BS_STOP isn't good enough here, hflags may have changed. */
3684 gen_save_pc(ctx
->pc
+ 4);
3685 ctx
->bstate
= BS_EXCP
;
3689 // gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
3690 rn
= "TraceControl";
3691 /* Stop translation as we may have switched the execution mode */
3692 ctx
->bstate
= BS_STOP
;
3695 // gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
3696 rn
= "TraceControl2";
3697 /* Stop translation as we may have switched the execution mode */
3698 ctx
->bstate
= BS_STOP
;
3701 /* Stop translation as we may have switched the execution mode */
3702 ctx
->bstate
= BS_STOP
;
3703 // gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
3704 rn
= "UserTraceData";
3705 /* Stop translation as we may have switched the execution mode */
3706 ctx
->bstate
= BS_STOP
;
3709 // gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
3710 /* Stop translation as we may have switched the execution mode */
3711 ctx
->bstate
= BS_STOP
;
3722 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_DEPC
));
3732 gen_helper_mtc0_performance0(t0
);
3733 rn
= "Performance0";
3736 // gen_helper_mtc0_performance1(t0);
3737 rn
= "Performance1";
3740 // gen_helper_mtc0_performance2(t0);
3741 rn
= "Performance2";
3744 // gen_helper_mtc0_performance3(t0);
3745 rn
= "Performance3";
3748 // gen_helper_mtc0_performance4(t0);
3749 rn
= "Performance4";
3752 // gen_helper_mtc0_performance5(t0);
3753 rn
= "Performance5";
3756 // gen_helper_mtc0_performance6(t0);
3757 rn
= "Performance6";
3760 // gen_helper_mtc0_performance7(t0);
3761 rn
= "Performance7";
3787 gen_helper_mtc0_taglo(t0
);
3794 gen_helper_mtc0_datalo(t0
);
3807 gen_helper_mtc0_taghi(t0
);
3814 gen_helper_mtc0_datahi(t0
);
3825 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_ErrorEPC
));
3836 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3842 /* Stop translation as we may have switched the execution mode */
3843 ctx
->bstate
= BS_STOP
;
3848 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3849 /* For simplicity assume that all writes can cause interrupts. */
3852 ctx
->bstate
= BS_STOP
;
3857 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3858 generate_exception(ctx
, EXCP_RI
);
3861 #if defined(TARGET_MIPS64)
3862 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3864 const char *rn
= "invalid";
3867 check_insn(env
, ctx
, ISA_MIPS64
);
3873 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
3877 check_insn(env
, ctx
, ASE_MT
);
3878 gen_helper_mfc0_mvpcontrol(t0
);
3882 check_insn(env
, ctx
, ASE_MT
);
3883 gen_helper_mfc0_mvpconf0(t0
);
3887 check_insn(env
, ctx
, ASE_MT
);
3888 gen_helper_mfc0_mvpconf1(t0
);
3898 gen_helper_mfc0_random(t0
);
3902 check_insn(env
, ctx
, ASE_MT
);
3903 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
3907 check_insn(env
, ctx
, ASE_MT
);
3908 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
3912 check_insn(env
, ctx
, ASE_MT
);
3913 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
3917 check_insn(env
, ctx
, ASE_MT
);
3918 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
3922 check_insn(env
, ctx
, ASE_MT
);
3923 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
3927 check_insn(env
, ctx
, ASE_MT
);
3928 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
3929 rn
= "VPEScheFBack";
3932 check_insn(env
, ctx
, ASE_MT
);
3933 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
3943 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
3947 check_insn(env
, ctx
, ASE_MT
);
3948 gen_helper_mfc0_tcstatus(t0
);
3952 check_insn(env
, ctx
, ASE_MT
);
3953 gen_helper_mfc0_tcbind(t0
);
3957 check_insn(env
, ctx
, ASE_MT
);
3958 gen_helper_dmfc0_tcrestart(t0
);
3962 check_insn(env
, ctx
, ASE_MT
);
3963 gen_helper_dmfc0_tchalt(t0
);
3967 check_insn(env
, ctx
, ASE_MT
);
3968 gen_helper_dmfc0_tccontext(t0
);
3972 check_insn(env
, ctx
, ASE_MT
);
3973 gen_helper_dmfc0_tcschedule(t0
);
3977 check_insn(env
, ctx
, ASE_MT
);
3978 gen_helper_dmfc0_tcschefback(t0
);
3988 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
3998 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4002 // gen_helper_dmfc0_contextconfig(t0); /* SmartMIPS ASE */
4003 rn
= "ContextConfig";
4012 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
4016 check_insn(env
, ctx
, ISA_MIPS32R2
);
4017 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
4027 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
4031 check_insn(env
, ctx
, ISA_MIPS32R2
);
4032 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
4036 check_insn(env
, ctx
, ISA_MIPS32R2
);
4037 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
4041 check_insn(env
, ctx
, ISA_MIPS32R2
);
4042 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
4046 check_insn(env
, ctx
, ISA_MIPS32R2
);
4047 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
4051 check_insn(env
, ctx
, ISA_MIPS32R2
);
4052 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
4062 check_insn(env
, ctx
, ISA_MIPS32R2
);
4063 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
4073 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4083 /* Mark as an IO operation because we read the time. */
4086 gen_helper_mfc0_count(t0
);
4089 ctx
->bstate
= BS_STOP
;
4093 /* 6,7 are implementation dependent */
4101 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4111 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
4114 /* 6,7 are implementation dependent */
4122 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
4126 check_insn(env
, ctx
, ISA_MIPS32R2
);
4127 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
4131 check_insn(env
, ctx
, ISA_MIPS32R2
);
4132 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
4136 check_insn(env
, ctx
, ISA_MIPS32R2
);
4137 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4147 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
4157 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4167 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
4171 check_insn(env
, ctx
, ISA_MIPS32R2
);
4172 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
4182 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
4186 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
4190 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
4194 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
4197 /* 6,7 are implementation dependent */
4199 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
4203 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
4213 gen_helper_dmfc0_lladdr(t0
);
4223 gen_helper_1i(dmfc0_watchlo
, t0
, sel
);
4233 gen_helper_1i(mfc0_watchhi
, t0
, sel
);
4243 check_insn(env
, ctx
, ISA_MIPS3
);
4244 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4252 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4255 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
4263 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
4264 rn
= "'Diagnostic"; /* implementation dependent */
4269 gen_helper_mfc0_debug(t0
); /* EJTAG support */
4273 // gen_helper_dmfc0_tracecontrol(t0); /* PDtrace support */
4274 rn
= "TraceControl";
4277 // gen_helper_dmfc0_tracecontrol2(t0); /* PDtrace support */
4278 rn
= "TraceControl2";
4281 // gen_helper_dmfc0_usertracedata(t0); /* PDtrace support */
4282 rn
= "UserTraceData";
4285 // gen_helper_dmfc0_tracebpc(t0); /* PDtrace support */
4296 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4306 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
4307 rn
= "Performance0";
4310 // gen_helper_dmfc0_performance1(t0);
4311 rn
= "Performance1";
4314 // gen_helper_dmfc0_performance2(t0);
4315 rn
= "Performance2";
4318 // gen_helper_dmfc0_performance3(t0);
4319 rn
= "Performance3";
4322 // gen_helper_dmfc0_performance4(t0);
4323 rn
= "Performance4";
4326 // gen_helper_dmfc0_performance5(t0);
4327 rn
= "Performance5";
4330 // gen_helper_dmfc0_performance6(t0);
4331 rn
= "Performance6";
4334 // gen_helper_dmfc0_performance7(t0);
4335 rn
= "Performance7";
4342 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
4349 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
4362 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
4369 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
4382 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
4389 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
4399 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4410 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
4420 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4424 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4425 generate_exception(ctx
, EXCP_RI
);
4428 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
4430 const char *rn
= "invalid";
4433 check_insn(env
, ctx
, ISA_MIPS64
);
4442 gen_helper_mtc0_index(t0
);
4446 check_insn(env
, ctx
, ASE_MT
);
4447 gen_helper_mtc0_mvpcontrol(t0
);
4451 check_insn(env
, ctx
, ASE_MT
);
4456 check_insn(env
, ctx
, ASE_MT
);
4471 check_insn(env
, ctx
, ASE_MT
);
4472 gen_helper_mtc0_vpecontrol(t0
);
4476 check_insn(env
, ctx
, ASE_MT
);
4477 gen_helper_mtc0_vpeconf0(t0
);
4481 check_insn(env
, ctx
, ASE_MT
);
4482 gen_helper_mtc0_vpeconf1(t0
);
4486 check_insn(env
, ctx
, ASE_MT
);
4487 gen_helper_mtc0_yqmask(t0
);
4491 check_insn(env
, ctx
, ASE_MT
);
4492 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4496 check_insn(env
, ctx
, ASE_MT
);
4497 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4498 rn
= "VPEScheFBack";
4501 check_insn(env
, ctx
, ASE_MT
);
4502 gen_helper_mtc0_vpeopt(t0
);
4512 gen_helper_mtc0_entrylo0(t0
);
4516 check_insn(env
, ctx
, ASE_MT
);
4517 gen_helper_mtc0_tcstatus(t0
);
4521 check_insn(env
, ctx
, ASE_MT
);
4522 gen_helper_mtc0_tcbind(t0
);
4526 check_insn(env
, ctx
, ASE_MT
);
4527 gen_helper_mtc0_tcrestart(t0
);
4531 check_insn(env
, ctx
, ASE_MT
);
4532 gen_helper_mtc0_tchalt(t0
);
4536 check_insn(env
, ctx
, ASE_MT
);
4537 gen_helper_mtc0_tccontext(t0
);
4541 check_insn(env
, ctx
, ASE_MT
);
4542 gen_helper_mtc0_tcschedule(t0
);
4546 check_insn(env
, ctx
, ASE_MT
);
4547 gen_helper_mtc0_tcschefback(t0
);
4557 gen_helper_mtc0_entrylo1(t0
);
4567 gen_helper_mtc0_context(t0
);
4571 // gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
4572 rn
= "ContextConfig";
4581 gen_helper_mtc0_pagemask(t0
);
4585 check_insn(env
, ctx
, ISA_MIPS32R2
);
4586 gen_helper_mtc0_pagegrain(t0
);
4596 gen_helper_mtc0_wired(t0
);
4600 check_insn(env
, ctx
, ISA_MIPS32R2
);
4601 gen_helper_mtc0_srsconf0(t0
);
4605 check_insn(env
, ctx
, ISA_MIPS32R2
);
4606 gen_helper_mtc0_srsconf1(t0
);
4610 check_insn(env
, ctx
, ISA_MIPS32R2
);
4611 gen_helper_mtc0_srsconf2(t0
);
4615 check_insn(env
, ctx
, ISA_MIPS32R2
);
4616 gen_helper_mtc0_srsconf3(t0
);
4620 check_insn(env
, ctx
, ISA_MIPS32R2
);
4621 gen_helper_mtc0_srsconf4(t0
);
4631 check_insn(env
, ctx
, ISA_MIPS32R2
);
4632 gen_helper_mtc0_hwrena(t0
);
4646 gen_helper_mtc0_count(t0
);
4649 /* 6,7 are implementation dependent */
4653 /* Stop translation as we may have switched the execution mode */
4654 ctx
->bstate
= BS_STOP
;
4659 gen_helper_mtc0_entryhi(t0
);
4669 gen_helper_mtc0_compare(t0
);
4672 /* 6,7 are implementation dependent */
4676 /* Stop translation as we may have switched the execution mode */
4677 ctx
->bstate
= BS_STOP
;
4682 gen_helper_mtc0_status(t0
);
4683 /* BS_STOP isn't good enough here, hflags may have changed. */
4684 gen_save_pc(ctx
->pc
+ 4);
4685 ctx
->bstate
= BS_EXCP
;
4689 check_insn(env
, ctx
, ISA_MIPS32R2
);
4690 gen_helper_mtc0_intctl(t0
);
4691 /* Stop translation as we may have switched the execution mode */
4692 ctx
->bstate
= BS_STOP
;
4696 check_insn(env
, ctx
, ISA_MIPS32R2
);
4697 gen_helper_mtc0_srsctl(t0
);
4698 /* Stop translation as we may have switched the execution mode */
4699 ctx
->bstate
= BS_STOP
;
4703 check_insn(env
, ctx
, ISA_MIPS32R2
);
4704 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4705 /* Stop translation as we may have switched the execution mode */
4706 ctx
->bstate
= BS_STOP
;
4716 gen_helper_mtc0_cause(t0
);
4722 /* Stop translation as we may have switched the execution mode */
4723 ctx
->bstate
= BS_STOP
;
4728 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4742 check_insn(env
, ctx
, ISA_MIPS32R2
);
4743 gen_helper_mtc0_ebase(t0
);
4753 gen_helper_mtc0_config0(t0
);
4755 /* Stop translation as we may have switched the execution mode */
4756 ctx
->bstate
= BS_STOP
;
4763 gen_helper_mtc0_config2(t0
);
4765 /* Stop translation as we may have switched the execution mode */
4766 ctx
->bstate
= BS_STOP
;
4772 /* 6,7 are implementation dependent */
4774 rn
= "Invalid config selector";
4791 gen_helper_1i(mtc0_watchlo
, t0
, sel
);
4801 gen_helper_1i(mtc0_watchhi
, t0
, sel
);
4811 check_insn(env
, ctx
, ISA_MIPS3
);
4812 gen_helper_mtc0_xcontext(t0
);
4820 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4823 gen_helper_mtc0_framemask(t0
);
4832 rn
= "Diagnostic"; /* implementation dependent */
4837 gen_helper_mtc0_debug(t0
); /* EJTAG support */
4838 /* BS_STOP isn't good enough here, hflags may have changed. */
4839 gen_save_pc(ctx
->pc
+ 4);
4840 ctx
->bstate
= BS_EXCP
;
4844 // gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
4845 /* Stop translation as we may have switched the execution mode */
4846 ctx
->bstate
= BS_STOP
;
4847 rn
= "TraceControl";
4850 // gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
4851 /* Stop translation as we may have switched the execution mode */
4852 ctx
->bstate
= BS_STOP
;
4853 rn
= "TraceControl2";
4856 // gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
4857 /* Stop translation as we may have switched the execution mode */
4858 ctx
->bstate
= BS_STOP
;
4859 rn
= "UserTraceData";
4862 // gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
4863 /* Stop translation as we may have switched the execution mode */
4864 ctx
->bstate
= BS_STOP
;
4875 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4885 gen_helper_mtc0_performance0(t0
);
4886 rn
= "Performance0";
4889 // gen_helper_mtc0_performance1(t0);
4890 rn
= "Performance1";
4893 // gen_helper_mtc0_performance2(t0);
4894 rn
= "Performance2";
4897 // gen_helper_mtc0_performance3(t0);
4898 rn
= "Performance3";
4901 // gen_helper_mtc0_performance4(t0);
4902 rn
= "Performance4";
4905 // gen_helper_mtc0_performance5(t0);
4906 rn
= "Performance5";
4909 // gen_helper_mtc0_performance6(t0);
4910 rn
= "Performance6";
4913 // gen_helper_mtc0_performance7(t0);
4914 rn
= "Performance7";
4940 gen_helper_mtc0_taglo(t0
);
4947 gen_helper_mtc0_datalo(t0
);
4960 gen_helper_mtc0_taghi(t0
);
4967 gen_helper_mtc0_datahi(t0
);
4978 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4989 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
4995 /* Stop translation as we may have switched the execution mode */
4996 ctx
->bstate
= BS_STOP
;
5001 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5002 /* For simplicity assume that all writes can cause interrupts. */
5005 ctx
->bstate
= BS_STOP
;
5010 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5011 generate_exception(ctx
, EXCP_RI
);
5013 #endif /* TARGET_MIPS64 */
5015 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5016 int u
, int sel
, int h
)
5018 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5019 TCGv t0
= tcg_temp_local_new();
5021 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5022 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5023 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5024 tcg_gen_movi_tl(t0
, -1);
5025 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5026 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5027 tcg_gen_movi_tl(t0
, -1);
5033 gen_helper_mftc0_tcstatus(t0
);
5036 gen_helper_mftc0_tcbind(t0
);
5039 gen_helper_mftc0_tcrestart(t0
);
5042 gen_helper_mftc0_tchalt(t0
);
5045 gen_helper_mftc0_tccontext(t0
);
5048 gen_helper_mftc0_tcschedule(t0
);
5051 gen_helper_mftc0_tcschefback(t0
);
5054 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5061 gen_helper_mftc0_entryhi(t0
);
5064 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5070 gen_helper_mftc0_status(t0
);
5073 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5079 gen_helper_mftc0_debug(t0
);
5082 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5087 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5089 } else switch (sel
) {
5090 /* GPR registers. */
5092 gen_helper_1i(mftgpr
, t0
, rt
);
5094 /* Auxiliary CPU registers */
5098 gen_helper_1i(mftlo
, t0
, 0);
5101 gen_helper_1i(mfthi
, t0
, 0);
5104 gen_helper_1i(mftacx
, t0
, 0);
5107 gen_helper_1i(mftlo
, t0
, 1);
5110 gen_helper_1i(mfthi
, t0
, 1);
5113 gen_helper_1i(mftacx
, t0
, 1);
5116 gen_helper_1i(mftlo
, t0
, 2);
5119 gen_helper_1i(mfthi
, t0
, 2);
5122 gen_helper_1i(mftacx
, t0
, 2);
5125 gen_helper_1i(mftlo
, t0
, 3);
5128 gen_helper_1i(mfthi
, t0
, 3);
5131 gen_helper_1i(mftacx
, t0
, 3);
5134 gen_helper_mftdsp(t0
);
5140 /* Floating point (COP1). */
5142 /* XXX: For now we support only a single FPU context. */
5144 TCGv_i32 fp0
= tcg_temp_new_i32();
5146 gen_load_fpr32(fp0
, rt
);
5147 tcg_gen_ext_i32_tl(t0
, fp0
);
5148 tcg_temp_free_i32(fp0
);
5150 TCGv_i32 fp0
= tcg_temp_new_i32();
5152 gen_load_fpr32h(fp0
, rt
);
5153 tcg_gen_ext_i32_tl(t0
, fp0
);
5154 tcg_temp_free_i32(fp0
);
5158 /* XXX: For now we support only a single FPU context. */
5159 gen_helper_1i(cfc1
, t0
, rt
);
5161 /* COP2: Not implemented. */
5168 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5169 gen_store_gpr(t0
, rd
);
5175 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5176 generate_exception(ctx
, EXCP_RI
);
5179 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5180 int u
, int sel
, int h
)
5182 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5183 TCGv t0
= tcg_temp_local_new();
5185 gen_load_gpr(t0
, rt
);
5186 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5187 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5188 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5190 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5191 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5198 gen_helper_mttc0_tcstatus(t0
);
5201 gen_helper_mttc0_tcbind(t0
);
5204 gen_helper_mttc0_tcrestart(t0
);
5207 gen_helper_mttc0_tchalt(t0
);
5210 gen_helper_mttc0_tccontext(t0
);
5213 gen_helper_mttc0_tcschedule(t0
);
5216 gen_helper_mttc0_tcschefback(t0
);
5219 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5226 gen_helper_mttc0_entryhi(t0
);
5229 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5235 gen_helper_mttc0_status(t0
);
5238 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5244 gen_helper_mttc0_debug(t0
);
5247 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5252 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5254 } else switch (sel
) {
5255 /* GPR registers. */
5257 gen_helper_1i(mttgpr
, t0
, rd
);
5259 /* Auxiliary CPU registers */
5263 gen_helper_1i(mttlo
, t0
, 0);
5266 gen_helper_1i(mtthi
, t0
, 0);
5269 gen_helper_1i(mttacx
, t0
, 0);
5272 gen_helper_1i(mttlo
, t0
, 1);
5275 gen_helper_1i(mtthi
, t0
, 1);
5278 gen_helper_1i(mttacx
, t0
, 1);
5281 gen_helper_1i(mttlo
, t0
, 2);
5284 gen_helper_1i(mtthi
, t0
, 2);
5287 gen_helper_1i(mttacx
, t0
, 2);
5290 gen_helper_1i(mttlo
, t0
, 3);
5293 gen_helper_1i(mtthi
, t0
, 3);
5296 gen_helper_1i(mttacx
, t0
, 3);
5299 gen_helper_mttdsp(t0
);
5305 /* Floating point (COP1). */
5307 /* XXX: For now we support only a single FPU context. */
5309 TCGv_i32 fp0
= tcg_temp_new_i32();
5311 tcg_gen_trunc_tl_i32(fp0
, t0
);
5312 gen_store_fpr32(fp0
, rd
);
5313 tcg_temp_free_i32(fp0
);
5315 TCGv_i32 fp0
= tcg_temp_new_i32();
5317 tcg_gen_trunc_tl_i32(fp0
, t0
);
5318 gen_store_fpr32h(fp0
, rd
);
5319 tcg_temp_free_i32(fp0
);
5323 /* XXX: For now we support only a single FPU context. */
5324 gen_helper_1i(ctc1
, t0
, rd
);
5326 /* COP2: Not implemented. */
5333 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5339 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5340 generate_exception(ctx
, EXCP_RI
);
5343 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5345 const char *opn
= "ldst";
5354 TCGv t0
= tcg_temp_local_new();
5356 gen_mfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5357 gen_store_gpr(t0
, rt
);
5364 TCGv t0
= tcg_temp_local_new();
5366 gen_load_gpr(t0
, rt
);
5367 save_cpu_state(ctx
, 1);
5368 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5373 #if defined(TARGET_MIPS64)
5375 check_insn(env
, ctx
, ISA_MIPS3
);
5381 TCGv t0
= tcg_temp_local_new();
5383 gen_dmfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5384 gen_store_gpr(t0
, rt
);
5390 check_insn(env
, ctx
, ISA_MIPS3
);
5392 TCGv t0
= tcg_temp_local_new();
5394 gen_load_gpr(t0
, rt
);
5395 save_cpu_state(ctx
, 1);
5396 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5403 check_insn(env
, ctx
, ASE_MT
);
5408 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5409 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5413 check_insn(env
, ctx
, ASE_MT
);
5414 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5415 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5420 if (!env
->tlb
->helper_tlbwi
)
5426 if (!env
->tlb
->helper_tlbwr
)
5432 if (!env
->tlb
->helper_tlbp
)
5438 if (!env
->tlb
->helper_tlbr
)
5444 check_insn(env
, ctx
, ISA_MIPS2
);
5445 save_cpu_state(ctx
, 1);
5447 ctx
->bstate
= BS_EXCP
;
5451 check_insn(env
, ctx
, ISA_MIPS32
);
5452 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5454 generate_exception(ctx
, EXCP_RI
);
5456 save_cpu_state(ctx
, 1);
5458 ctx
->bstate
= BS_EXCP
;
5463 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5464 /* If we get an exception, we want to restart at next instruction */
5466 save_cpu_state(ctx
, 1);
5469 ctx
->bstate
= BS_EXCP
;
5474 generate_exception(ctx
, EXCP_RI
);
5477 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5479 #endif /* !CONFIG_USER_ONLY */
5481 /* CP1 Branches (before delay slot) */
5482 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5483 int32_t cc
, int32_t offset
)
5485 target_ulong btarget
;
5486 const char *opn
= "cp1 cond branch";
5487 TCGv_i32 t0
= tcg_temp_new_i32();
5490 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5492 btarget
= ctx
->pc
+ 4 + offset
;
5496 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5497 tcg_gen_not_i32(t0
, t0
);
5498 tcg_gen_andi_i32(t0
, t0
, 1);
5499 tcg_gen_extu_i32_tl(bcond
, t0
);
5503 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5504 tcg_gen_not_i32(t0
, t0
);
5505 tcg_gen_andi_i32(t0
, t0
, 1);
5506 tcg_gen_extu_i32_tl(bcond
, t0
);
5510 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5511 tcg_gen_andi_i32(t0
, t0
, 1);
5512 tcg_gen_extu_i32_tl(bcond
, t0
);
5516 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5517 tcg_gen_andi_i32(t0
, t0
, 1);
5518 tcg_gen_extu_i32_tl(bcond
, t0
);
5521 ctx
->hflags
|= MIPS_HFLAG_BL
;
5525 TCGv_i32 t1
= tcg_temp_new_i32();
5526 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5527 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5528 tcg_gen_or_i32(t0
, t0
, t1
);
5529 tcg_temp_free_i32(t1
);
5530 tcg_gen_not_i32(t0
, t0
);
5531 tcg_gen_andi_i32(t0
, t0
, 1);
5532 tcg_gen_extu_i32_tl(bcond
, t0
);
5538 TCGv_i32 t1
= tcg_temp_new_i32();
5539 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5540 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5541 tcg_gen_or_i32(t0
, t0
, t1
);
5542 tcg_temp_free_i32(t1
);
5543 tcg_gen_andi_i32(t0
, t0
, 1);
5544 tcg_gen_extu_i32_tl(bcond
, t0
);
5550 TCGv_i32 t1
= tcg_temp_new_i32();
5551 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5552 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5553 tcg_gen_or_i32(t0
, t0
, t1
);
5554 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5555 tcg_gen_or_i32(t0
, t0
, t1
);
5556 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5557 tcg_gen_or_i32(t0
, t0
, t1
);
5558 tcg_temp_free_i32(t1
);
5559 tcg_gen_not_i32(t0
, t0
);
5560 tcg_gen_andi_i32(t0
, t0
, 1);
5561 tcg_gen_extu_i32_tl(bcond
, t0
);
5567 TCGv_i32 t1
= tcg_temp_new_i32();
5568 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5569 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5570 tcg_gen_or_i32(t0
, t0
, t1
);
5571 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5572 tcg_gen_or_i32(t0
, t0
, t1
);
5573 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5574 tcg_gen_or_i32(t0
, t0
, t1
);
5575 tcg_temp_free_i32(t1
);
5576 tcg_gen_andi_i32(t0
, t0
, 1);
5577 tcg_gen_extu_i32_tl(bcond
, t0
);
5581 ctx
->hflags
|= MIPS_HFLAG_BC
;
5585 generate_exception (ctx
, EXCP_RI
);
5588 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5589 ctx
->hflags
, btarget
);
5590 ctx
->btarget
= btarget
;
5593 tcg_temp_free_i32(t0
);
5596 /* Coprocessor 1 (FPU) */
5598 #define FOP(func, fmt) (((fmt) << 21) | (func))
5600 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5602 const char *opn
= "cp1 move";
5603 TCGv t0
= tcg_temp_local_new();
5608 TCGv_i32 fp0
= tcg_temp_new_i32();
5610 gen_load_fpr32(fp0
, fs
);
5611 tcg_gen_ext_i32_tl(t0
, fp0
);
5612 tcg_temp_free_i32(fp0
);
5614 gen_store_gpr(t0
, rt
);
5618 gen_load_gpr(t0
, rt
);
5620 TCGv_i32 fp0
= tcg_temp_new_i32();
5622 tcg_gen_trunc_tl_i32(fp0
, t0
);
5623 gen_store_fpr32(fp0
, fs
);
5624 tcg_temp_free_i32(fp0
);
5629 gen_helper_1i(cfc1
, t0
, fs
);
5630 gen_store_gpr(t0
, rt
);
5634 gen_load_gpr(t0
, rt
);
5635 gen_helper_1i(ctc1
, t0
, fs
);
5640 TCGv_i64 fp0
= tcg_temp_new_i64();
5642 gen_load_fpr64(ctx
, fp0
, fs
);
5643 tcg_gen_trunc_i64_tl(t0
, fp0
);
5644 tcg_temp_free_i64(fp0
);
5646 gen_store_gpr(t0
, rt
);
5650 gen_load_gpr(t0
, rt
);
5652 TCGv_i64 fp0
= tcg_temp_new_i64();
5654 tcg_gen_extu_tl_i64(fp0
, t0
);
5655 gen_store_fpr64(ctx
, fp0
, fs
);
5656 tcg_temp_free_i64(fp0
);
5662 TCGv_i32 fp0
= tcg_temp_new_i32();
5664 gen_load_fpr32h(fp0
, fs
);
5665 tcg_gen_ext_i32_tl(t0
, fp0
);
5666 tcg_temp_free_i32(fp0
);
5668 gen_store_gpr(t0
, rt
);
5672 gen_load_gpr(t0
, rt
);
5674 TCGv_i32 fp0
= tcg_temp_new_i32();
5676 tcg_gen_trunc_tl_i32(fp0
, t0
);
5677 gen_store_fpr32h(fp0
, fs
);
5678 tcg_temp_free_i32(fp0
);
5684 generate_exception (ctx
, EXCP_RI
);
5687 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5693 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5709 l1
= gen_new_label();
5710 t0
= tcg_temp_new_i32();
5711 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5712 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5714 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5716 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
5719 tcg_temp_free_i32(t0
);
5722 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5725 TCGv_i32 t0
= tcg_temp_new_i32();
5726 int l1
= gen_new_label();
5733 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5734 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5735 gen_load_fpr32(t0
, fs
);
5736 gen_store_fpr32(t0
, fd
);
5738 tcg_temp_free_i32(t0
);
5741 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
5744 TCGv_i32 t0
= tcg_temp_new_i32();
5746 int l1
= gen_new_label();
5753 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5754 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5755 fp0
= tcg_temp_local_new_i64();
5756 gen_load_fpr64(ctx
, fp0
, fs
);
5757 gen_store_fpr64(ctx
, fp0
, fd
);
5758 tcg_temp_free_i64(fp0
);
5760 tcg_temp_free_i32(t0
);
5763 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
5766 TCGv_i32 t0
= tcg_temp_new_i32();
5767 int l1
= gen_new_label();
5768 int l2
= gen_new_label();
5775 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5776 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5777 gen_load_fpr32(t0
, fs
);
5778 gen_store_fpr32(t0
, fd
);
5781 tcg_gen_andi_i32(t0
, fpu_fcr31
, get_fp_bit(cc
+1));
5782 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
5783 gen_load_fpr32h(t0
, fs
);
5784 gen_store_fpr32h(t0
, fd
);
5787 tcg_temp_free_i32(t0
);
5791 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5792 int ft
, int fs
, int fd
, int cc
)
5794 const char *opn
= "farith";
5795 const char *condnames
[] = {
5813 const char *condnames_abs
[] = {
5831 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
5832 uint32_t func
= ctx
->opcode
& 0x3f;
5834 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
5837 TCGv_i32 fp0
= tcg_temp_new_i32();
5838 TCGv_i32 fp1
= tcg_temp_new_i32();
5840 gen_load_fpr32(fp0
, fs
);
5841 gen_load_fpr32(fp1
, ft
);
5842 gen_helper_float_add_s(fp0
, fp0
, fp1
);
5843 tcg_temp_free_i32(fp1
);
5844 gen_store_fpr32(fp0
, fd
);
5845 tcg_temp_free_i32(fp0
);
5852 TCGv_i32 fp0
= tcg_temp_new_i32();
5853 TCGv_i32 fp1
= tcg_temp_new_i32();
5855 gen_load_fpr32(fp0
, fs
);
5856 gen_load_fpr32(fp1
, ft
);
5857 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
5858 tcg_temp_free_i32(fp1
);
5859 gen_store_fpr32(fp0
, fd
);
5860 tcg_temp_free_i32(fp0
);
5867 TCGv_i32 fp0
= tcg_temp_new_i32();
5868 TCGv_i32 fp1
= tcg_temp_new_i32();
5870 gen_load_fpr32(fp0
, fs
);
5871 gen_load_fpr32(fp1
, ft
);
5872 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
5873 tcg_temp_free_i32(fp1
);
5874 gen_store_fpr32(fp0
, fd
);
5875 tcg_temp_free_i32(fp0
);
5882 TCGv_i32 fp0
= tcg_temp_new_i32();
5883 TCGv_i32 fp1
= tcg_temp_new_i32();
5885 gen_load_fpr32(fp0
, fs
);
5886 gen_load_fpr32(fp1
, ft
);
5887 gen_helper_float_div_s(fp0
, fp0
, fp1
);
5888 tcg_temp_free_i32(fp1
);
5889 gen_store_fpr32(fp0
, fd
);
5890 tcg_temp_free_i32(fp0
);
5897 TCGv_i32 fp0
= tcg_temp_new_i32();
5899 gen_load_fpr32(fp0
, fs
);
5900 gen_helper_float_sqrt_s(fp0
, fp0
);
5901 gen_store_fpr32(fp0
, fd
);
5902 tcg_temp_free_i32(fp0
);
5908 TCGv_i32 fp0
= tcg_temp_new_i32();
5910 gen_load_fpr32(fp0
, fs
);
5911 gen_helper_float_abs_s(fp0
, fp0
);
5912 gen_store_fpr32(fp0
, fd
);
5913 tcg_temp_free_i32(fp0
);
5919 TCGv_i32 fp0
= tcg_temp_new_i32();
5921 gen_load_fpr32(fp0
, fs
);
5922 gen_store_fpr32(fp0
, fd
);
5923 tcg_temp_free_i32(fp0
);
5929 TCGv_i32 fp0
= tcg_temp_new_i32();
5931 gen_load_fpr32(fp0
, fs
);
5932 gen_helper_float_chs_s(fp0
, fp0
);
5933 gen_store_fpr32(fp0
, fd
);
5934 tcg_temp_free_i32(fp0
);
5939 check_cp1_64bitmode(ctx
);
5941 TCGv_i32 fp32
= tcg_temp_new_i32();
5942 TCGv_i64 fp64
= tcg_temp_new_i64();
5944 gen_load_fpr32(fp32
, fs
);
5945 gen_helper_float_roundl_s(fp64
, fp32
);
5946 tcg_temp_free_i32(fp32
);
5947 gen_store_fpr64(ctx
, fp64
, fd
);
5948 tcg_temp_free_i64(fp64
);
5953 check_cp1_64bitmode(ctx
);
5955 TCGv_i32 fp32
= tcg_temp_new_i32();
5956 TCGv_i64 fp64
= tcg_temp_new_i64();
5958 gen_load_fpr32(fp32
, fs
);
5959 gen_helper_float_truncl_s(fp64
, fp32
);
5960 tcg_temp_free_i32(fp32
);
5961 gen_store_fpr64(ctx
, fp64
, fd
);
5962 tcg_temp_free_i64(fp64
);
5967 check_cp1_64bitmode(ctx
);
5969 TCGv_i32 fp32
= tcg_temp_new_i32();
5970 TCGv_i64 fp64
= tcg_temp_new_i64();
5972 gen_load_fpr32(fp32
, fs
);
5973 gen_helper_float_ceill_s(fp64
, fp32
);
5974 tcg_temp_free_i32(fp32
);
5975 gen_store_fpr64(ctx
, fp64
, fd
);
5976 tcg_temp_free_i64(fp64
);
5981 check_cp1_64bitmode(ctx
);
5983 TCGv_i32 fp32
= tcg_temp_new_i32();
5984 TCGv_i64 fp64
= tcg_temp_new_i64();
5986 gen_load_fpr32(fp32
, fs
);
5987 gen_helper_float_floorl_s(fp64
, fp32
);
5988 tcg_temp_free_i32(fp32
);
5989 gen_store_fpr64(ctx
, fp64
, fd
);
5990 tcg_temp_free_i64(fp64
);
5996 TCGv_i32 fp0
= tcg_temp_new_i32();
5998 gen_load_fpr32(fp0
, fs
);
5999 gen_helper_float_roundw_s(fp0
, fp0
);
6000 gen_store_fpr32(fp0
, fd
);
6001 tcg_temp_free_i32(fp0
);
6007 TCGv_i32 fp0
= tcg_temp_new_i32();
6009 gen_load_fpr32(fp0
, fs
);
6010 gen_helper_float_truncw_s(fp0
, fp0
);
6011 gen_store_fpr32(fp0
, fd
);
6012 tcg_temp_free_i32(fp0
);
6018 TCGv_i32 fp0
= tcg_temp_new_i32();
6020 gen_load_fpr32(fp0
, fs
);
6021 gen_helper_float_ceilw_s(fp0
, fp0
);
6022 gen_store_fpr32(fp0
, fd
);
6023 tcg_temp_free_i32(fp0
);
6029 TCGv_i32 fp0
= tcg_temp_new_i32();
6031 gen_load_fpr32(fp0
, fs
);
6032 gen_helper_float_floorw_s(fp0
, fp0
);
6033 gen_store_fpr32(fp0
, fd
);
6034 tcg_temp_free_i32(fp0
);
6039 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6044 int l1
= gen_new_label();
6045 TCGv t0
= tcg_temp_new();
6046 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6048 gen_load_gpr(t0
, ft
);
6049 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6050 gen_load_fpr32(fp0
, fs
);
6051 gen_store_fpr32(fp0
, fd
);
6052 tcg_temp_free_i32(fp0
);
6060 int l1
= gen_new_label();
6061 TCGv t0
= tcg_temp_new();
6062 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6064 gen_load_gpr(t0
, ft
);
6065 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6066 gen_load_fpr32(fp0
, fs
);
6067 gen_store_fpr32(fp0
, fd
);
6068 tcg_temp_free_i32(fp0
);
6077 TCGv_i32 fp0
= tcg_temp_new_i32();
6079 gen_load_fpr32(fp0
, fs
);
6080 gen_helper_float_recip_s(fp0
, fp0
);
6081 gen_store_fpr32(fp0
, fd
);
6082 tcg_temp_free_i32(fp0
);
6089 TCGv_i32 fp0
= tcg_temp_new_i32();
6091 gen_load_fpr32(fp0
, fs
);
6092 gen_helper_float_rsqrt_s(fp0
, fp0
);
6093 gen_store_fpr32(fp0
, fd
);
6094 tcg_temp_free_i32(fp0
);
6099 check_cp1_64bitmode(ctx
);
6101 TCGv_i32 fp0
= tcg_temp_new_i32();
6102 TCGv_i32 fp1
= tcg_temp_new_i32();
6104 gen_load_fpr32(fp0
, fs
);
6105 gen_load_fpr32(fp1
, fd
);
6106 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6107 tcg_temp_free_i32(fp1
);
6108 gen_store_fpr32(fp0
, fd
);
6109 tcg_temp_free_i32(fp0
);
6114 check_cp1_64bitmode(ctx
);
6116 TCGv_i32 fp0
= tcg_temp_new_i32();
6118 gen_load_fpr32(fp0
, fs
);
6119 gen_helper_float_recip1_s(fp0
, fp0
);
6120 gen_store_fpr32(fp0
, fd
);
6121 tcg_temp_free_i32(fp0
);
6126 check_cp1_64bitmode(ctx
);
6128 TCGv_i32 fp0
= tcg_temp_new_i32();
6130 gen_load_fpr32(fp0
, fs
);
6131 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6132 gen_store_fpr32(fp0
, fd
);
6133 tcg_temp_free_i32(fp0
);
6138 check_cp1_64bitmode(ctx
);
6140 TCGv_i32 fp0
= tcg_temp_new_i32();
6141 TCGv_i32 fp1
= tcg_temp_new_i32();
6143 gen_load_fpr32(fp0
, fs
);
6144 gen_load_fpr32(fp1
, ft
);
6145 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6146 tcg_temp_free_i32(fp1
);
6147 gen_store_fpr32(fp0
, fd
);
6148 tcg_temp_free_i32(fp0
);
6153 check_cp1_registers(ctx
, fd
);
6155 TCGv_i32 fp32
= tcg_temp_new_i32();
6156 TCGv_i64 fp64
= tcg_temp_new_i64();
6158 gen_load_fpr32(fp32
, fs
);
6159 gen_helper_float_cvtd_s(fp64
, fp32
);
6160 tcg_temp_free_i32(fp32
);
6161 gen_store_fpr64(ctx
, fp64
, fd
);
6162 tcg_temp_free_i64(fp64
);
6168 TCGv_i32 fp0
= tcg_temp_new_i32();
6170 gen_load_fpr32(fp0
, fs
);
6171 gen_helper_float_cvtw_s(fp0
, fp0
);
6172 gen_store_fpr32(fp0
, fd
);
6173 tcg_temp_free_i32(fp0
);
6178 check_cp1_64bitmode(ctx
);
6180 TCGv_i32 fp32
= tcg_temp_new_i32();
6181 TCGv_i64 fp64
= tcg_temp_new_i64();
6183 gen_load_fpr32(fp32
, fs
);
6184 gen_helper_float_cvtl_s(fp64
, fp32
);
6185 tcg_temp_free_i32(fp32
);
6186 gen_store_fpr64(ctx
, fp64
, fd
);
6187 tcg_temp_free_i64(fp64
);
6192 check_cp1_64bitmode(ctx
);
6194 TCGv_i64 fp64
= tcg_temp_new_i64();
6195 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6196 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6198 gen_load_fpr32(fp32_0
, fs
);
6199 gen_load_fpr32(fp32_1
, ft
);
6200 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6201 tcg_temp_free_i32(fp32_1
);
6202 tcg_temp_free_i32(fp32_0
);
6203 gen_store_fpr64(ctx
, fp64
, fd
);
6204 tcg_temp_free_i64(fp64
);
6225 TCGv_i32 fp0
= tcg_temp_new_i32();
6226 TCGv_i32 fp1
= tcg_temp_new_i32();
6228 gen_load_fpr32(fp0
, fs
);
6229 gen_load_fpr32(fp1
, ft
);
6230 if (ctx
->opcode
& (1 << 6)) {
6232 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6233 opn
= condnames_abs
[func
-48];
6235 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6236 opn
= condnames
[func
-48];
6238 tcg_temp_free_i32(fp0
);
6239 tcg_temp_free_i32(fp1
);
6243 check_cp1_registers(ctx
, fs
| ft
| fd
);
6245 TCGv_i64 fp0
= tcg_temp_new_i64();
6246 TCGv_i64 fp1
= tcg_temp_new_i64();
6248 gen_load_fpr64(ctx
, fp0
, fs
);
6249 gen_load_fpr64(ctx
, fp1
, ft
);
6250 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6251 tcg_temp_free_i64(fp1
);
6252 gen_store_fpr64(ctx
, fp0
, fd
);
6253 tcg_temp_free_i64(fp0
);
6259 check_cp1_registers(ctx
, fs
| ft
| fd
);
6261 TCGv_i64 fp0
= tcg_temp_new_i64();
6262 TCGv_i64 fp1
= tcg_temp_new_i64();
6264 gen_load_fpr64(ctx
, fp0
, fs
);
6265 gen_load_fpr64(ctx
, fp1
, ft
);
6266 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6267 tcg_temp_free_i64(fp1
);
6268 gen_store_fpr64(ctx
, fp0
, fd
);
6269 tcg_temp_free_i64(fp0
);
6275 check_cp1_registers(ctx
, fs
| ft
| fd
);
6277 TCGv_i64 fp0
= tcg_temp_new_i64();
6278 TCGv_i64 fp1
= tcg_temp_new_i64();
6280 gen_load_fpr64(ctx
, fp0
, fs
);
6281 gen_load_fpr64(ctx
, fp1
, ft
);
6282 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6283 tcg_temp_free_i64(fp1
);
6284 gen_store_fpr64(ctx
, fp0
, fd
);
6285 tcg_temp_free_i64(fp0
);
6291 check_cp1_registers(ctx
, fs
| ft
| fd
);
6293 TCGv_i64 fp0
= tcg_temp_new_i64();
6294 TCGv_i64 fp1
= tcg_temp_new_i64();
6296 gen_load_fpr64(ctx
, fp0
, fs
);
6297 gen_load_fpr64(ctx
, fp1
, ft
);
6298 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6299 tcg_temp_free_i64(fp1
);
6300 gen_store_fpr64(ctx
, fp0
, fd
);
6301 tcg_temp_free_i64(fp0
);
6307 check_cp1_registers(ctx
, fs
| fd
);
6309 TCGv_i64 fp0
= tcg_temp_new_i64();
6311 gen_load_fpr64(ctx
, fp0
, fs
);
6312 gen_helper_float_sqrt_d(fp0
, fp0
);
6313 gen_store_fpr64(ctx
, fp0
, fd
);
6314 tcg_temp_free_i64(fp0
);
6319 check_cp1_registers(ctx
, fs
| fd
);
6321 TCGv_i64 fp0
= tcg_temp_new_i64();
6323 gen_load_fpr64(ctx
, fp0
, fs
);
6324 gen_helper_float_abs_d(fp0
, fp0
);
6325 gen_store_fpr64(ctx
, fp0
, fd
);
6326 tcg_temp_free_i64(fp0
);
6331 check_cp1_registers(ctx
, fs
| fd
);
6333 TCGv_i64 fp0
= tcg_temp_new_i64();
6335 gen_load_fpr64(ctx
, fp0
, fs
);
6336 gen_store_fpr64(ctx
, fp0
, fd
);
6337 tcg_temp_free_i64(fp0
);
6342 check_cp1_registers(ctx
, fs
| fd
);
6344 TCGv_i64 fp0
= tcg_temp_new_i64();
6346 gen_load_fpr64(ctx
, fp0
, fs
);
6347 gen_helper_float_chs_d(fp0
, fp0
);
6348 gen_store_fpr64(ctx
, fp0
, fd
);
6349 tcg_temp_free_i64(fp0
);
6354 check_cp1_64bitmode(ctx
);
6356 TCGv_i64 fp0
= tcg_temp_new_i64();
6358 gen_load_fpr64(ctx
, fp0
, fs
);
6359 gen_helper_float_roundl_d(fp0
, fp0
);
6360 gen_store_fpr64(ctx
, fp0
, fd
);
6361 tcg_temp_free_i64(fp0
);
6366 check_cp1_64bitmode(ctx
);
6368 TCGv_i64 fp0
= tcg_temp_new_i64();
6370 gen_load_fpr64(ctx
, fp0
, fs
);
6371 gen_helper_float_truncl_d(fp0
, fp0
);
6372 gen_store_fpr64(ctx
, fp0
, fd
);
6373 tcg_temp_free_i64(fp0
);
6378 check_cp1_64bitmode(ctx
);
6380 TCGv_i64 fp0
= tcg_temp_new_i64();
6382 gen_load_fpr64(ctx
, fp0
, fs
);
6383 gen_helper_float_ceill_d(fp0
, fp0
);
6384 gen_store_fpr64(ctx
, fp0
, fd
);
6385 tcg_temp_free_i64(fp0
);
6390 check_cp1_64bitmode(ctx
);
6392 TCGv_i64 fp0
= tcg_temp_new_i64();
6394 gen_load_fpr64(ctx
, fp0
, fs
);
6395 gen_helper_float_floorl_d(fp0
, fp0
);
6396 gen_store_fpr64(ctx
, fp0
, fd
);
6397 tcg_temp_free_i64(fp0
);
6402 check_cp1_registers(ctx
, fs
);
6404 TCGv_i32 fp32
= tcg_temp_new_i32();
6405 TCGv_i64 fp64
= tcg_temp_new_i64();
6407 gen_load_fpr64(ctx
, fp64
, fs
);
6408 gen_helper_float_roundw_d(fp32
, fp64
);
6409 tcg_temp_free_i64(fp64
);
6410 gen_store_fpr32(fp32
, fd
);
6411 tcg_temp_free_i32(fp32
);
6416 check_cp1_registers(ctx
, fs
);
6418 TCGv_i32 fp32
= tcg_temp_new_i32();
6419 TCGv_i64 fp64
= tcg_temp_new_i64();
6421 gen_load_fpr64(ctx
, fp64
, fs
);
6422 gen_helper_float_truncw_d(fp32
, fp64
);
6423 tcg_temp_free_i64(fp64
);
6424 gen_store_fpr32(fp32
, fd
);
6425 tcg_temp_free_i32(fp32
);
6430 check_cp1_registers(ctx
, fs
);
6432 TCGv_i32 fp32
= tcg_temp_new_i32();
6433 TCGv_i64 fp64
= tcg_temp_new_i64();
6435 gen_load_fpr64(ctx
, fp64
, fs
);
6436 gen_helper_float_ceilw_d(fp32
, fp64
);
6437 tcg_temp_free_i64(fp64
);
6438 gen_store_fpr32(fp32
, fd
);
6439 tcg_temp_free_i32(fp32
);
6444 check_cp1_registers(ctx
, fs
);
6446 TCGv_i32 fp32
= tcg_temp_new_i32();
6447 TCGv_i64 fp64
= tcg_temp_new_i64();
6449 gen_load_fpr64(ctx
, fp64
, fs
);
6450 gen_helper_float_floorw_d(fp32
, fp64
);
6451 tcg_temp_free_i64(fp64
);
6452 gen_store_fpr32(fp32
, fd
);
6453 tcg_temp_free_i32(fp32
);
6458 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6463 int l1
= gen_new_label();
6464 TCGv t0
= tcg_temp_new();
6465 TCGv_i64 fp0
= tcg_temp_local_new_i64();
6467 gen_load_gpr(t0
, ft
);
6468 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6469 gen_load_fpr64(ctx
, fp0
, fs
);
6470 gen_store_fpr64(ctx
, fp0
, fd
);
6471 tcg_temp_free_i64(fp0
);
6479 int l1
= gen_new_label();
6480 TCGv t0
= tcg_temp_new();
6481 TCGv_i64 fp0
= tcg_temp_local_new_i64();
6483 gen_load_gpr(t0
, ft
);
6484 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6485 gen_load_fpr64(ctx
, fp0
, fs
);
6486 gen_store_fpr64(ctx
, fp0
, fd
);
6487 tcg_temp_free_i64(fp0
);
6494 check_cp1_64bitmode(ctx
);
6496 TCGv_i64 fp0
= tcg_temp_new_i64();
6498 gen_load_fpr64(ctx
, fp0
, fs
);
6499 gen_helper_float_recip_d(fp0
, fp0
);
6500 gen_store_fpr64(ctx
, fp0
, fd
);
6501 tcg_temp_free_i64(fp0
);
6506 check_cp1_64bitmode(ctx
);
6508 TCGv_i64 fp0
= tcg_temp_new_i64();
6510 gen_load_fpr64(ctx
, fp0
, fs
);
6511 gen_helper_float_rsqrt_d(fp0
, fp0
);
6512 gen_store_fpr64(ctx
, fp0
, fd
);
6513 tcg_temp_free_i64(fp0
);
6518 check_cp1_64bitmode(ctx
);
6520 TCGv_i64 fp0
= tcg_temp_new_i64();
6521 TCGv_i64 fp1
= tcg_temp_new_i64();
6523 gen_load_fpr64(ctx
, fp0
, fs
);
6524 gen_load_fpr64(ctx
, fp1
, ft
);
6525 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
6526 tcg_temp_free_i64(fp1
);
6527 gen_store_fpr64(ctx
, fp0
, fd
);
6528 tcg_temp_free_i64(fp0
);
6533 check_cp1_64bitmode(ctx
);
6535 TCGv_i64 fp0
= tcg_temp_new_i64();
6537 gen_load_fpr64(ctx
, fp0
, fs
);
6538 gen_helper_float_recip1_d(fp0
, fp0
);
6539 gen_store_fpr64(ctx
, fp0
, fd
);
6540 tcg_temp_free_i64(fp0
);
6545 check_cp1_64bitmode(ctx
);
6547 TCGv_i64 fp0
= tcg_temp_new_i64();
6549 gen_load_fpr64(ctx
, fp0
, fs
);
6550 gen_helper_float_rsqrt1_d(fp0
, fp0
);
6551 gen_store_fpr64(ctx
, fp0
, fd
);
6552 tcg_temp_free_i64(fp0
);
6557 check_cp1_64bitmode(ctx
);
6559 TCGv_i64 fp0
= tcg_temp_new_i64();
6560 TCGv_i64 fp1
= tcg_temp_new_i64();
6562 gen_load_fpr64(ctx
, fp0
, fs
);
6563 gen_load_fpr64(ctx
, fp1
, ft
);
6564 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
6565 tcg_temp_free_i64(fp1
);
6566 gen_store_fpr64(ctx
, fp0
, fd
);
6567 tcg_temp_free_i64(fp0
);
6588 TCGv_i64 fp0
= tcg_temp_new_i64();
6589 TCGv_i64 fp1
= tcg_temp_new_i64();
6591 gen_load_fpr64(ctx
, fp0
, fs
);
6592 gen_load_fpr64(ctx
, fp1
, ft
);
6593 if (ctx
->opcode
& (1 << 6)) {
6595 check_cp1_registers(ctx
, fs
| ft
);
6596 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6597 opn
= condnames_abs
[func
-48];
6599 check_cp1_registers(ctx
, fs
| ft
);
6600 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6601 opn
= condnames
[func
-48];
6603 tcg_temp_free_i64(fp0
);
6604 tcg_temp_free_i64(fp1
);
6608 check_cp1_registers(ctx
, fs
);
6610 TCGv_i32 fp32
= tcg_temp_new_i32();
6611 TCGv_i64 fp64
= tcg_temp_new_i64();
6613 gen_load_fpr64(ctx
, fp64
, fs
);
6614 gen_helper_float_cvts_d(fp32
, fp64
);
6615 tcg_temp_free_i64(fp64
);
6616 gen_store_fpr32(fp32
, fd
);
6617 tcg_temp_free_i32(fp32
);
6622 check_cp1_registers(ctx
, fs
);
6624 TCGv_i32 fp32
= tcg_temp_new_i32();
6625 TCGv_i64 fp64
= tcg_temp_new_i64();
6627 gen_load_fpr64(ctx
, fp64
, fs
);
6628 gen_helper_float_cvtw_d(fp32
, fp64
);
6629 tcg_temp_free_i64(fp64
);
6630 gen_store_fpr32(fp32
, fd
);
6631 tcg_temp_free_i32(fp32
);
6636 check_cp1_64bitmode(ctx
);
6638 TCGv_i64 fp0
= tcg_temp_new_i64();
6640 gen_load_fpr64(ctx
, fp0
, fs
);
6641 gen_helper_float_cvtl_d(fp0
, fp0
);
6642 gen_store_fpr64(ctx
, fp0
, fd
);
6643 tcg_temp_free_i64(fp0
);
6649 TCGv_i32 fp0
= tcg_temp_new_i32();
6651 gen_load_fpr32(fp0
, fs
);
6652 gen_helper_float_cvts_w(fp0
, fp0
);
6653 gen_store_fpr32(fp0
, fd
);
6654 tcg_temp_free_i32(fp0
);
6659 check_cp1_registers(ctx
, fd
);
6661 TCGv_i32 fp32
= tcg_temp_new_i32();
6662 TCGv_i64 fp64
= tcg_temp_new_i64();
6664 gen_load_fpr32(fp32
, fs
);
6665 gen_helper_float_cvtd_w(fp64
, fp32
);
6666 tcg_temp_free_i32(fp32
);
6667 gen_store_fpr64(ctx
, fp64
, fd
);
6668 tcg_temp_free_i64(fp64
);
6673 check_cp1_64bitmode(ctx
);
6675 TCGv_i32 fp32
= tcg_temp_new_i32();
6676 TCGv_i64 fp64
= tcg_temp_new_i64();
6678 gen_load_fpr64(ctx
, fp64
, fs
);
6679 gen_helper_float_cvts_l(fp32
, fp64
);
6680 tcg_temp_free_i64(fp64
);
6681 gen_store_fpr32(fp32
, fd
);
6682 tcg_temp_free_i32(fp32
);
6687 check_cp1_64bitmode(ctx
);
6689 TCGv_i64 fp0
= tcg_temp_new_i64();
6691 gen_load_fpr64(ctx
, fp0
, fs
);
6692 gen_helper_float_cvtd_l(fp0
, fp0
);
6693 gen_store_fpr64(ctx
, fp0
, fd
);
6694 tcg_temp_free_i64(fp0
);
6699 check_cp1_64bitmode(ctx
);
6701 TCGv_i64 fp0
= tcg_temp_new_i64();
6703 gen_load_fpr64(ctx
, fp0
, fs
);
6704 gen_helper_float_cvtps_pw(fp0
, fp0
);
6705 gen_store_fpr64(ctx
, fp0
, fd
);
6706 tcg_temp_free_i64(fp0
);
6711 check_cp1_64bitmode(ctx
);
6713 TCGv_i64 fp0
= tcg_temp_new_i64();
6714 TCGv_i64 fp1
= tcg_temp_new_i64();
6716 gen_load_fpr64(ctx
, fp0
, fs
);
6717 gen_load_fpr64(ctx
, fp1
, ft
);
6718 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
6719 tcg_temp_free_i64(fp1
);
6720 gen_store_fpr64(ctx
, fp0
, fd
);
6721 tcg_temp_free_i64(fp0
);
6726 check_cp1_64bitmode(ctx
);
6728 TCGv_i64 fp0
= tcg_temp_new_i64();
6729 TCGv_i64 fp1
= tcg_temp_new_i64();
6731 gen_load_fpr64(ctx
, fp0
, fs
);
6732 gen_load_fpr64(ctx
, fp1
, ft
);
6733 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
6734 tcg_temp_free_i64(fp1
);
6735 gen_store_fpr64(ctx
, fp0
, fd
);
6736 tcg_temp_free_i64(fp0
);
6741 check_cp1_64bitmode(ctx
);
6743 TCGv_i64 fp0
= tcg_temp_new_i64();
6744 TCGv_i64 fp1
= tcg_temp_new_i64();
6746 gen_load_fpr64(ctx
, fp0
, fs
);
6747 gen_load_fpr64(ctx
, fp1
, ft
);
6748 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
6749 tcg_temp_free_i64(fp1
);
6750 gen_store_fpr64(ctx
, fp0
, fd
);
6751 tcg_temp_free_i64(fp0
);
6756 check_cp1_64bitmode(ctx
);
6758 TCGv_i64 fp0
= tcg_temp_new_i64();
6760 gen_load_fpr64(ctx
, fp0
, fs
);
6761 gen_helper_float_abs_ps(fp0
, fp0
);
6762 gen_store_fpr64(ctx
, fp0
, fd
);
6763 tcg_temp_free_i64(fp0
);
6768 check_cp1_64bitmode(ctx
);
6770 TCGv_i64 fp0
= tcg_temp_new_i64();
6772 gen_load_fpr64(ctx
, fp0
, fs
);
6773 gen_store_fpr64(ctx
, fp0
, fd
);
6774 tcg_temp_free_i64(fp0
);
6779 check_cp1_64bitmode(ctx
);
6781 TCGv_i64 fp0
= tcg_temp_new_i64();
6783 gen_load_fpr64(ctx
, fp0
, fs
);
6784 gen_helper_float_chs_ps(fp0
, fp0
);
6785 gen_store_fpr64(ctx
, fp0
, fd
);
6786 tcg_temp_free_i64(fp0
);
6791 check_cp1_64bitmode(ctx
);
6792 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6796 check_cp1_64bitmode(ctx
);
6798 int l1
= gen_new_label();
6799 TCGv t0
= tcg_temp_new();
6800 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6801 TCGv_i32 fph0
= tcg_temp_local_new_i32();
6803 gen_load_gpr(t0
, ft
);
6804 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6805 gen_load_fpr32(fp0
, fs
);
6806 gen_load_fpr32h(fph0
, fs
);
6807 gen_store_fpr32(fp0
, fd
);
6808 gen_store_fpr32h(fph0
, fd
);
6809 tcg_temp_free_i32(fp0
);
6810 tcg_temp_free_i32(fph0
);
6817 check_cp1_64bitmode(ctx
);
6819 int l1
= gen_new_label();
6820 TCGv t0
= tcg_temp_new();
6821 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6822 TCGv_i32 fph0
= tcg_temp_local_new_i32();
6824 gen_load_gpr(t0
, ft
);
6825 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6826 gen_load_fpr32(fp0
, fs
);
6827 gen_load_fpr32h(fph0
, fs
);
6828 gen_store_fpr32(fp0
, fd
);
6829 gen_store_fpr32h(fph0
, fd
);
6830 tcg_temp_free_i32(fp0
);
6831 tcg_temp_free_i32(fph0
);
6838 check_cp1_64bitmode(ctx
);
6840 TCGv_i64 fp0
= tcg_temp_new_i64();
6841 TCGv_i64 fp1
= tcg_temp_new_i64();
6843 gen_load_fpr64(ctx
, fp0
, ft
);
6844 gen_load_fpr64(ctx
, fp1
, fs
);
6845 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
6846 tcg_temp_free_i64(fp1
);
6847 gen_store_fpr64(ctx
, fp0
, fd
);
6848 tcg_temp_free_i64(fp0
);
6853 check_cp1_64bitmode(ctx
);
6855 TCGv_i64 fp0
= tcg_temp_new_i64();
6856 TCGv_i64 fp1
= tcg_temp_new_i64();
6858 gen_load_fpr64(ctx
, fp0
, ft
);
6859 gen_load_fpr64(ctx
, fp1
, fs
);
6860 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
6861 tcg_temp_free_i64(fp1
);
6862 gen_store_fpr64(ctx
, fp0
, fd
);
6863 tcg_temp_free_i64(fp0
);
6868 check_cp1_64bitmode(ctx
);
6870 TCGv_i64 fp0
= tcg_temp_new_i64();
6871 TCGv_i64 fp1
= tcg_temp_new_i64();
6873 gen_load_fpr64(ctx
, fp0
, fs
);
6874 gen_load_fpr64(ctx
, fp1
, fd
);
6875 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
6876 tcg_temp_free_i64(fp1
);
6877 gen_store_fpr64(ctx
, fp0
, fd
);
6878 tcg_temp_free_i64(fp0
);
6883 check_cp1_64bitmode(ctx
);
6885 TCGv_i64 fp0
= tcg_temp_new_i64();
6887 gen_load_fpr64(ctx
, fp0
, fs
);
6888 gen_helper_float_recip1_ps(fp0
, fp0
);
6889 gen_store_fpr64(ctx
, fp0
, fd
);
6890 tcg_temp_free_i64(fp0
);
6895 check_cp1_64bitmode(ctx
);
6897 TCGv_i64 fp0
= tcg_temp_new_i64();
6899 gen_load_fpr64(ctx
, fp0
, fs
);
6900 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
6901 gen_store_fpr64(ctx
, fp0
, fd
);
6902 tcg_temp_free_i64(fp0
);
6907 check_cp1_64bitmode(ctx
);
6909 TCGv_i64 fp0
= tcg_temp_new_i64();
6910 TCGv_i64 fp1
= tcg_temp_new_i64();
6912 gen_load_fpr64(ctx
, fp0
, fs
);
6913 gen_load_fpr64(ctx
, fp1
, ft
);
6914 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
6915 tcg_temp_free_i64(fp1
);
6916 gen_store_fpr64(ctx
, fp0
, fd
);
6917 tcg_temp_free_i64(fp0
);
6922 check_cp1_64bitmode(ctx
);
6924 TCGv_i32 fp0
= tcg_temp_new_i32();
6926 gen_load_fpr32h(fp0
, fs
);
6927 gen_helper_float_cvts_pu(fp0
, fp0
);
6928 gen_store_fpr32(fp0
, fd
);
6929 tcg_temp_free_i32(fp0
);
6934 check_cp1_64bitmode(ctx
);
6936 TCGv_i64 fp0
= tcg_temp_new_i64();
6938 gen_load_fpr64(ctx
, fp0
, fs
);
6939 gen_helper_float_cvtpw_ps(fp0
, fp0
);
6940 gen_store_fpr64(ctx
, fp0
, fd
);
6941 tcg_temp_free_i64(fp0
);
6946 check_cp1_64bitmode(ctx
);
6948 TCGv_i32 fp0
= tcg_temp_new_i32();
6950 gen_load_fpr32(fp0
, fs
);
6951 gen_helper_float_cvts_pl(fp0
, fp0
);
6952 gen_store_fpr32(fp0
, fd
);
6953 tcg_temp_free_i32(fp0
);
6958 check_cp1_64bitmode(ctx
);
6960 TCGv_i32 fp0
= tcg_temp_new_i32();
6961 TCGv_i32 fp1
= tcg_temp_new_i32();
6963 gen_load_fpr32(fp0
, fs
);
6964 gen_load_fpr32(fp1
, ft
);
6965 gen_store_fpr32h(fp0
, fd
);
6966 gen_store_fpr32(fp1
, fd
);
6967 tcg_temp_free_i32(fp0
);
6968 tcg_temp_free_i32(fp1
);
6973 check_cp1_64bitmode(ctx
);
6975 TCGv_i32 fp0
= tcg_temp_new_i32();
6976 TCGv_i32 fp1
= tcg_temp_new_i32();
6978 gen_load_fpr32(fp0
, fs
);
6979 gen_load_fpr32h(fp1
, ft
);
6980 gen_store_fpr32(fp1
, fd
);
6981 gen_store_fpr32h(fp0
, fd
);
6982 tcg_temp_free_i32(fp0
);
6983 tcg_temp_free_i32(fp1
);
6988 check_cp1_64bitmode(ctx
);
6990 TCGv_i32 fp0
= tcg_temp_new_i32();
6991 TCGv_i32 fp1
= tcg_temp_new_i32();
6993 gen_load_fpr32h(fp0
, fs
);
6994 gen_load_fpr32(fp1
, ft
);
6995 gen_store_fpr32(fp1
, fd
);
6996 gen_store_fpr32h(fp0
, fd
);
6997 tcg_temp_free_i32(fp0
);
6998 tcg_temp_free_i32(fp1
);
7003 check_cp1_64bitmode(ctx
);
7005 TCGv_i32 fp0
= tcg_temp_new_i32();
7006 TCGv_i32 fp1
= tcg_temp_new_i32();
7008 gen_load_fpr32h(fp0
, fs
);
7009 gen_load_fpr32h(fp1
, ft
);
7010 gen_store_fpr32(fp1
, fd
);
7011 gen_store_fpr32h(fp0
, fd
);
7012 tcg_temp_free_i32(fp0
);
7013 tcg_temp_free_i32(fp1
);
7033 check_cp1_64bitmode(ctx
);
7035 TCGv_i64 fp0
= tcg_temp_new_i64();
7036 TCGv_i64 fp1
= tcg_temp_new_i64();
7038 gen_load_fpr64(ctx
, fp0
, fs
);
7039 gen_load_fpr64(ctx
, fp1
, ft
);
7040 if (ctx
->opcode
& (1 << 6)) {
7041 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7042 opn
= condnames_abs
[func
-48];
7044 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7045 opn
= condnames
[func
-48];
7047 tcg_temp_free_i64(fp0
);
7048 tcg_temp_free_i64(fp1
);
7053 generate_exception (ctx
, EXCP_RI
);
7058 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7061 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7064 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7069 /* Coprocessor 3 (FPU) */
7070 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7071 int fd
, int fs
, int base
, int index
)
7073 const char *opn
= "extended float load/store";
7075 TCGv t0
= tcg_temp_local_new();
7076 TCGv t1
= tcg_temp_local_new();
7079 gen_load_gpr(t0
, index
);
7080 } else if (index
== 0) {
7081 gen_load_gpr(t0
, base
);
7083 gen_load_gpr(t0
, index
);
7084 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
7086 /* Don't do NOP if destination is zero: we must perform the actual
7092 TCGv_i32 fp0
= tcg_temp_new_i32();
7094 tcg_gen_qemu_ld32s(t1
, t0
, ctx
->mem_idx
);
7095 tcg_gen_trunc_tl_i32(fp0
, t1
);
7096 gen_store_fpr32(fp0
, fd
);
7097 tcg_temp_free_i32(fp0
);
7103 check_cp1_registers(ctx
, fd
);
7105 TCGv_i64 fp0
= tcg_temp_new_i64();
7107 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7108 gen_store_fpr64(ctx
, fp0
, fd
);
7109 tcg_temp_free_i64(fp0
);
7114 check_cp1_64bitmode(ctx
);
7115 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7117 TCGv_i64 fp0
= tcg_temp_new_i64();
7119 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7120 gen_store_fpr64(ctx
, fp0
, fd
);
7121 tcg_temp_free_i64(fp0
);
7128 TCGv_i32 fp0
= tcg_temp_new_i32();
7130 gen_load_fpr32(fp0
, fs
);
7131 tcg_gen_extu_i32_tl(t1
, fp0
);
7132 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7133 tcg_temp_free_i32(fp0
);
7140 check_cp1_registers(ctx
, fs
);
7142 TCGv_i64 fp0
= tcg_temp_new_i64();
7144 gen_load_fpr64(ctx
, fp0
, fs
);
7145 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7146 tcg_temp_free_i64(fp0
);
7152 check_cp1_64bitmode(ctx
);
7153 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7155 TCGv_i64 fp0
= tcg_temp_new_i64();
7157 gen_load_fpr64(ctx
, fp0
, fs
);
7158 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7159 tcg_temp_free_i64(fp0
);
7166 generate_exception(ctx
, EXCP_RI
);
7173 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7174 regnames
[index
], regnames
[base
]);
7177 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7178 int fd
, int fr
, int fs
, int ft
)
7180 const char *opn
= "flt3_arith";
7184 check_cp1_64bitmode(ctx
);
7186 TCGv t0
= tcg_temp_local_new();
7187 TCGv_i32 fp0
= tcg_temp_local_new_i32();
7188 TCGv_i32 fph0
= tcg_temp_local_new_i32();
7189 TCGv_i32 fp1
= tcg_temp_local_new_i32();
7190 TCGv_i32 fph1
= tcg_temp_local_new_i32();
7191 int l1
= gen_new_label();
7192 int l2
= gen_new_label();
7194 gen_load_gpr(t0
, fr
);
7195 tcg_gen_andi_tl(t0
, t0
, 0x7);
7196 gen_load_fpr32(fp0
, fs
);
7197 gen_load_fpr32h(fph0
, fs
);
7198 gen_load_fpr32(fp1
, ft
);
7199 gen_load_fpr32h(fph1
, ft
);
7201 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7202 gen_store_fpr32(fp0
, fd
);
7203 gen_store_fpr32h(fph0
, fd
);
7206 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7208 #ifdef TARGET_WORDS_BIGENDIAN
7209 gen_store_fpr32(fph1
, fd
);
7210 gen_store_fpr32h(fp0
, fd
);
7212 gen_store_fpr32(fph0
, fd
);
7213 gen_store_fpr32h(fp1
, fd
);
7216 tcg_temp_free_i32(fp0
);
7217 tcg_temp_free_i32(fph0
);
7218 tcg_temp_free_i32(fp1
);
7219 tcg_temp_free_i32(fph1
);
7226 TCGv_i32 fp0
= tcg_temp_new_i32();
7227 TCGv_i32 fp1
= tcg_temp_new_i32();
7228 TCGv_i32 fp2
= tcg_temp_new_i32();
7230 gen_load_fpr32(fp0
, fs
);
7231 gen_load_fpr32(fp1
, ft
);
7232 gen_load_fpr32(fp2
, fr
);
7233 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7234 tcg_temp_free_i32(fp0
);
7235 tcg_temp_free_i32(fp1
);
7236 gen_store_fpr32(fp2
, fd
);
7237 tcg_temp_free_i32(fp2
);
7243 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7245 TCGv_i64 fp0
= tcg_temp_new_i64();
7246 TCGv_i64 fp1
= tcg_temp_new_i64();
7247 TCGv_i64 fp2
= tcg_temp_new_i64();
7249 gen_load_fpr64(ctx
, fp0
, fs
);
7250 gen_load_fpr64(ctx
, fp1
, ft
);
7251 gen_load_fpr64(ctx
, fp2
, fr
);
7252 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7253 tcg_temp_free_i64(fp0
);
7254 tcg_temp_free_i64(fp1
);
7255 gen_store_fpr64(ctx
, fp2
, fd
);
7256 tcg_temp_free_i64(fp2
);
7261 check_cp1_64bitmode(ctx
);
7263 TCGv_i64 fp0
= tcg_temp_new_i64();
7264 TCGv_i64 fp1
= tcg_temp_new_i64();
7265 TCGv_i64 fp2
= tcg_temp_new_i64();
7267 gen_load_fpr64(ctx
, fp0
, fs
);
7268 gen_load_fpr64(ctx
, fp1
, ft
);
7269 gen_load_fpr64(ctx
, fp2
, fr
);
7270 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7271 tcg_temp_free_i64(fp0
);
7272 tcg_temp_free_i64(fp1
);
7273 gen_store_fpr64(ctx
, fp2
, fd
);
7274 tcg_temp_free_i64(fp2
);
7281 TCGv_i32 fp0
= tcg_temp_new_i32();
7282 TCGv_i32 fp1
= tcg_temp_new_i32();
7283 TCGv_i32 fp2
= tcg_temp_new_i32();
7285 gen_load_fpr32(fp0
, fs
);
7286 gen_load_fpr32(fp1
, ft
);
7287 gen_load_fpr32(fp2
, fr
);
7288 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7289 tcg_temp_free_i32(fp0
);
7290 tcg_temp_free_i32(fp1
);
7291 gen_store_fpr32(fp2
, fd
);
7292 tcg_temp_free_i32(fp2
);
7298 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7300 TCGv_i64 fp0
= tcg_temp_new_i64();
7301 TCGv_i64 fp1
= tcg_temp_new_i64();
7302 TCGv_i64 fp2
= tcg_temp_new_i64();
7304 gen_load_fpr64(ctx
, fp0
, fs
);
7305 gen_load_fpr64(ctx
, fp1
, ft
);
7306 gen_load_fpr64(ctx
, fp2
, fr
);
7307 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7308 tcg_temp_free_i64(fp0
);
7309 tcg_temp_free_i64(fp1
);
7310 gen_store_fpr64(ctx
, fp2
, fd
);
7311 tcg_temp_free_i64(fp2
);
7316 check_cp1_64bitmode(ctx
);
7318 TCGv_i64 fp0
= tcg_temp_new_i64();
7319 TCGv_i64 fp1
= tcg_temp_new_i64();
7320 TCGv_i64 fp2
= tcg_temp_new_i64();
7322 gen_load_fpr64(ctx
, fp0
, fs
);
7323 gen_load_fpr64(ctx
, fp1
, ft
);
7324 gen_load_fpr64(ctx
, fp2
, fr
);
7325 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7326 tcg_temp_free_i64(fp0
);
7327 tcg_temp_free_i64(fp1
);
7328 gen_store_fpr64(ctx
, fp2
, fd
);
7329 tcg_temp_free_i64(fp2
);
7336 TCGv_i32 fp0
= tcg_temp_new_i32();
7337 TCGv_i32 fp1
= tcg_temp_new_i32();
7338 TCGv_i32 fp2
= tcg_temp_new_i32();
7340 gen_load_fpr32(fp0
, fs
);
7341 gen_load_fpr32(fp1
, ft
);
7342 gen_load_fpr32(fp2
, fr
);
7343 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7344 tcg_temp_free_i32(fp0
);
7345 tcg_temp_free_i32(fp1
);
7346 gen_store_fpr32(fp2
, fd
);
7347 tcg_temp_free_i32(fp2
);
7353 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7355 TCGv_i64 fp0
= tcg_temp_new_i64();
7356 TCGv_i64 fp1
= tcg_temp_new_i64();
7357 TCGv_i64 fp2
= tcg_temp_new_i64();
7359 gen_load_fpr64(ctx
, fp0
, fs
);
7360 gen_load_fpr64(ctx
, fp1
, ft
);
7361 gen_load_fpr64(ctx
, fp2
, fr
);
7362 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7363 tcg_temp_free_i64(fp0
);
7364 tcg_temp_free_i64(fp1
);
7365 gen_store_fpr64(ctx
, fp2
, fd
);
7366 tcg_temp_free_i64(fp2
);
7371 check_cp1_64bitmode(ctx
);
7373 TCGv_i64 fp0
= tcg_temp_new_i64();
7374 TCGv_i64 fp1
= tcg_temp_new_i64();
7375 TCGv_i64 fp2
= tcg_temp_new_i64();
7377 gen_load_fpr64(ctx
, fp0
, fs
);
7378 gen_load_fpr64(ctx
, fp1
, ft
);
7379 gen_load_fpr64(ctx
, fp2
, fr
);
7380 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7381 tcg_temp_free_i64(fp0
);
7382 tcg_temp_free_i64(fp1
);
7383 gen_store_fpr64(ctx
, fp2
, fd
);
7384 tcg_temp_free_i64(fp2
);
7391 TCGv_i32 fp0
= tcg_temp_new_i32();
7392 TCGv_i32 fp1
= tcg_temp_new_i32();
7393 TCGv_i32 fp2
= tcg_temp_new_i32();
7395 gen_load_fpr32(fp0
, fs
);
7396 gen_load_fpr32(fp1
, ft
);
7397 gen_load_fpr32(fp2
, fr
);
7398 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7399 tcg_temp_free_i32(fp0
);
7400 tcg_temp_free_i32(fp1
);
7401 gen_store_fpr32(fp2
, fd
);
7402 tcg_temp_free_i32(fp2
);
7408 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7410 TCGv_i64 fp0
= tcg_temp_new_i64();
7411 TCGv_i64 fp1
= tcg_temp_new_i64();
7412 TCGv_i64 fp2
= tcg_temp_new_i64();
7414 gen_load_fpr64(ctx
, fp0
, fs
);
7415 gen_load_fpr64(ctx
, fp1
, ft
);
7416 gen_load_fpr64(ctx
, fp2
, fr
);
7417 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7418 tcg_temp_free_i64(fp0
);
7419 tcg_temp_free_i64(fp1
);
7420 gen_store_fpr64(ctx
, fp2
, fd
);
7421 tcg_temp_free_i64(fp2
);
7426 check_cp1_64bitmode(ctx
);
7428 TCGv_i64 fp0
= tcg_temp_new_i64();
7429 TCGv_i64 fp1
= tcg_temp_new_i64();
7430 TCGv_i64 fp2
= tcg_temp_new_i64();
7432 gen_load_fpr64(ctx
, fp0
, fs
);
7433 gen_load_fpr64(ctx
, fp1
, ft
);
7434 gen_load_fpr64(ctx
, fp2
, fr
);
7435 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
7436 tcg_temp_free_i64(fp0
);
7437 tcg_temp_free_i64(fp1
);
7438 gen_store_fpr64(ctx
, fp2
, fd
);
7439 tcg_temp_free_i64(fp2
);
7445 generate_exception (ctx
, EXCP_RI
);
7448 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7449 fregnames
[fs
], fregnames
[ft
]);
7452 /* ISA extensions (ASEs) */
7453 /* MIPS16 extension to MIPS32 */
7454 /* SmartMIPS extension to MIPS32 */
7456 #if defined(TARGET_MIPS64)
7458 /* MDMX extension to MIPS64 */
7462 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7466 uint32_t op
, op1
, op2
;
7469 /* make sure instructions are on a word boundary */
7470 if (ctx
->pc
& 0x3) {
7471 env
->CP0_BadVAddr
= ctx
->pc
;
7472 generate_exception(ctx
, EXCP_AdEL
);
7476 /* Handle blikely not taken case */
7477 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7478 int l1
= gen_new_label();
7480 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7481 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
7482 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7483 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7486 op
= MASK_OP_MAJOR(ctx
->opcode
);
7487 rs
= (ctx
->opcode
>> 21) & 0x1f;
7488 rt
= (ctx
->opcode
>> 16) & 0x1f;
7489 rd
= (ctx
->opcode
>> 11) & 0x1f;
7490 sa
= (ctx
->opcode
>> 6) & 0x1f;
7491 imm
= (int16_t)ctx
->opcode
;
7494 op1
= MASK_SPECIAL(ctx
->opcode
);
7496 case OPC_SLL
: /* Arithmetic with immediate */
7497 case OPC_SRL
... OPC_SRA
:
7498 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7500 case OPC_MOVZ
... OPC_MOVN
:
7501 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7502 case OPC_SLLV
: /* Arithmetic */
7503 case OPC_SRLV
... OPC_SRAV
:
7504 case OPC_ADD
... OPC_NOR
:
7505 case OPC_SLT
... OPC_SLTU
:
7506 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7508 case OPC_MULT
... OPC_DIVU
:
7510 check_insn(env
, ctx
, INSN_VR54XX
);
7511 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7512 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7514 gen_muldiv(ctx
, op1
, rs
, rt
);
7516 case OPC_JR
... OPC_JALR
:
7517 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7519 case OPC_TGE
... OPC_TEQ
: /* Traps */
7521 gen_trap(ctx
, op1
, rs
, rt
, -1);
7523 case OPC_MFHI
: /* Move from HI/LO */
7525 gen_HILO(ctx
, op1
, rd
);
7528 case OPC_MTLO
: /* Move to HI/LO */
7529 gen_HILO(ctx
, op1
, rs
);
7531 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7532 #ifdef MIPS_STRICT_STANDARD
7533 MIPS_INVAL("PMON / selsl");
7534 generate_exception(ctx
, EXCP_RI
);
7536 gen_helper_0i(pmon
, sa
);
7540 generate_exception(ctx
, EXCP_SYSCALL
);
7543 generate_exception(ctx
, EXCP_BREAK
);
7546 #ifdef MIPS_STRICT_STANDARD
7548 generate_exception(ctx
, EXCP_RI
);
7550 /* Implemented as RI exception for now. */
7551 MIPS_INVAL("spim (unofficial)");
7552 generate_exception(ctx
, EXCP_RI
);
7560 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7561 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7562 save_cpu_state(ctx
, 1);
7563 check_cp1_enabled(ctx
);
7564 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7565 (ctx
->opcode
>> 16) & 1);
7567 generate_exception_err(ctx
, EXCP_CpU
, 1);
7571 #if defined(TARGET_MIPS64)
7572 /* MIPS64 specific opcodes */
7574 case OPC_DSRL
... OPC_DSRA
:
7576 case OPC_DSRL32
... OPC_DSRA32
:
7577 check_insn(env
, ctx
, ISA_MIPS3
);
7579 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7582 case OPC_DSRLV
... OPC_DSRAV
:
7583 case OPC_DADD
... OPC_DSUBU
:
7584 check_insn(env
, ctx
, ISA_MIPS3
);
7586 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7588 case OPC_DMULT
... OPC_DDIVU
:
7589 check_insn(env
, ctx
, ISA_MIPS3
);
7591 gen_muldiv(ctx
, op1
, rs
, rt
);
7594 default: /* Invalid */
7595 MIPS_INVAL("special");
7596 generate_exception(ctx
, EXCP_RI
);
7601 op1
= MASK_SPECIAL2(ctx
->opcode
);
7603 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7604 case OPC_MSUB
... OPC_MSUBU
:
7605 check_insn(env
, ctx
, ISA_MIPS32
);
7606 gen_muldiv(ctx
, op1
, rs
, rt
);
7609 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7613 check_insn(env
, ctx
, ISA_MIPS32
);
7614 gen_cl(ctx
, op1
, rd
, rs
);
7617 /* XXX: not clear which exception should be raised
7618 * when in debug mode...
7620 check_insn(env
, ctx
, ISA_MIPS32
);
7621 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7622 generate_exception(ctx
, EXCP_DBp
);
7624 generate_exception(ctx
, EXCP_DBp
);
7628 #if defined(TARGET_MIPS64)
7631 check_insn(env
, ctx
, ISA_MIPS64
);
7633 gen_cl(ctx
, op1
, rd
, rs
);
7636 default: /* Invalid */
7637 MIPS_INVAL("special2");
7638 generate_exception(ctx
, EXCP_RI
);
7643 op1
= MASK_SPECIAL3(ctx
->opcode
);
7647 check_insn(env
, ctx
, ISA_MIPS32R2
);
7648 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7651 check_insn(env
, ctx
, ISA_MIPS32R2
);
7652 op2
= MASK_BSHFL(ctx
->opcode
);
7653 gen_bshfl(ctx
, op2
, rt
, rd
);
7656 check_insn(env
, ctx
, ISA_MIPS32R2
);
7658 TCGv t0
= tcg_temp_local_new();
7662 save_cpu_state(ctx
, 1);
7663 gen_helper_rdhwr_cpunum(t0
);
7666 save_cpu_state(ctx
, 1);
7667 gen_helper_rdhwr_synci_step(t0
);
7670 save_cpu_state(ctx
, 1);
7671 gen_helper_rdhwr_cc(t0
);
7674 save_cpu_state(ctx
, 1);
7675 gen_helper_rdhwr_ccres(t0
);
7678 #if defined(CONFIG_USER_ONLY)
7679 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7682 /* XXX: Some CPUs implement this in hardware.
7683 Not supported yet. */
7685 default: /* Invalid */
7686 MIPS_INVAL("rdhwr");
7687 generate_exception(ctx
, EXCP_RI
);
7690 gen_store_gpr(t0
, rt
);
7695 check_insn(env
, ctx
, ASE_MT
);
7697 TCGv t0
= tcg_temp_local_new();
7698 TCGv t1
= tcg_temp_local_new();
7700 gen_load_gpr(t0
, rt
);
7701 gen_load_gpr(t1
, rs
);
7702 gen_helper_fork(t0
, t1
);
7708 check_insn(env
, ctx
, ASE_MT
);
7710 TCGv t0
= tcg_temp_local_new();
7712 gen_load_gpr(t0
, rs
);
7713 gen_helper_yield(t0
, t0
);
7714 gen_store_gpr(t0
, rd
);
7718 #if defined(TARGET_MIPS64)
7719 case OPC_DEXTM
... OPC_DEXT
:
7720 case OPC_DINSM
... OPC_DINS
:
7721 check_insn(env
, ctx
, ISA_MIPS64R2
);
7723 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7726 check_insn(env
, ctx
, ISA_MIPS64R2
);
7728 op2
= MASK_DBSHFL(ctx
->opcode
);
7729 gen_bshfl(ctx
, op2
, rt
, rd
);
7732 default: /* Invalid */
7733 MIPS_INVAL("special3");
7734 generate_exception(ctx
, EXCP_RI
);
7739 op1
= MASK_REGIMM(ctx
->opcode
);
7741 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
7742 case OPC_BLTZAL
... OPC_BGEZALL
:
7743 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
7745 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
7747 gen_trap(ctx
, op1
, rs
, -1, imm
);
7750 check_insn(env
, ctx
, ISA_MIPS32R2
);
7753 default: /* Invalid */
7754 MIPS_INVAL("regimm");
7755 generate_exception(ctx
, EXCP_RI
);
7760 check_cp0_enabled(ctx
);
7761 op1
= MASK_CP0(ctx
->opcode
);
7767 #if defined(TARGET_MIPS64)
7771 #ifndef CONFIG_USER_ONLY
7772 gen_cp0(env
, ctx
, op1
, rt
, rd
);
7773 #endif /* !CONFIG_USER_ONLY */
7775 case OPC_C0_FIRST
... OPC_C0_LAST
:
7776 #ifndef CONFIG_USER_ONLY
7777 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
7778 #endif /* !CONFIG_USER_ONLY */
7781 #ifndef CONFIG_USER_ONLY
7783 TCGv t0
= tcg_temp_local_new();
7785 op2
= MASK_MFMC0(ctx
->opcode
);
7788 check_insn(env
, ctx
, ASE_MT
);
7789 gen_helper_dmt(t0
, t0
);
7792 check_insn(env
, ctx
, ASE_MT
);
7793 gen_helper_emt(t0
, t0
);
7796 check_insn(env
, ctx
, ASE_MT
);
7797 gen_helper_dvpe(t0
, t0
);
7800 check_insn(env
, ctx
, ASE_MT
);
7801 gen_helper_evpe(t0
, t0
);
7804 check_insn(env
, ctx
, ISA_MIPS32R2
);
7805 save_cpu_state(ctx
, 1);
7807 /* Stop translation as we may have switched the execution mode */
7808 ctx
->bstate
= BS_STOP
;
7811 check_insn(env
, ctx
, ISA_MIPS32R2
);
7812 save_cpu_state(ctx
, 1);
7814 /* Stop translation as we may have switched the execution mode */
7815 ctx
->bstate
= BS_STOP
;
7817 default: /* Invalid */
7818 MIPS_INVAL("mfmc0");
7819 generate_exception(ctx
, EXCP_RI
);
7822 gen_store_gpr(t0
, rt
);
7825 #endif /* !CONFIG_USER_ONLY */
7828 check_insn(env
, ctx
, ISA_MIPS32R2
);
7829 gen_load_srsgpr(rt
, rd
);
7832 check_insn(env
, ctx
, ISA_MIPS32R2
);
7833 gen_store_srsgpr(rt
, rd
);
7837 generate_exception(ctx
, EXCP_RI
);
7841 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
7842 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
7844 case OPC_J
... OPC_JAL
: /* Jump */
7845 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
7846 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
7848 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
7849 case OPC_BEQL
... OPC_BGTZL
:
7850 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
7852 case OPC_LB
... OPC_LWR
: /* Load and stores */
7853 case OPC_SB
... OPC_SW
:
7857 gen_ldst(ctx
, op
, rt
, rs
, imm
);
7860 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
7864 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7868 /* Floating point (COP1). */
7873 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7874 save_cpu_state(ctx
, 1);
7875 check_cp1_enabled(ctx
);
7876 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
7878 generate_exception_err(ctx
, EXCP_CpU
, 1);
7883 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7884 save_cpu_state(ctx
, 1);
7885 check_cp1_enabled(ctx
);
7886 op1
= MASK_CP1(ctx
->opcode
);
7890 check_insn(env
, ctx
, ISA_MIPS32R2
);
7895 gen_cp1(ctx
, op1
, rt
, rd
);
7897 #if defined(TARGET_MIPS64)
7900 check_insn(env
, ctx
, ISA_MIPS3
);
7901 gen_cp1(ctx
, op1
, rt
, rd
);
7907 check_insn(env
, ctx
, ASE_MIPS3D
);
7910 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
7911 (rt
>> 2) & 0x7, imm
<< 2);
7918 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
7923 generate_exception (ctx
, EXCP_RI
);
7927 generate_exception_err(ctx
, EXCP_CpU
, 1);
7937 /* COP2: Not implemented. */
7938 generate_exception_err(ctx
, EXCP_CpU
, 2);
7942 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7943 save_cpu_state(ctx
, 1);
7944 check_cp1_enabled(ctx
);
7945 op1
= MASK_CP3(ctx
->opcode
);
7953 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
7971 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
7975 generate_exception (ctx
, EXCP_RI
);
7979 generate_exception_err(ctx
, EXCP_CpU
, 1);
7983 #if defined(TARGET_MIPS64)
7984 /* MIPS64 opcodes */
7986 case OPC_LDL
... OPC_LDR
:
7987 case OPC_SDL
... OPC_SDR
:
7992 check_insn(env
, ctx
, ISA_MIPS3
);
7994 gen_ldst(ctx
, op
, rt
, rs
, imm
);
7996 case OPC_DADDI
... OPC_DADDIU
:
7997 check_insn(env
, ctx
, ISA_MIPS3
);
7999 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8003 check_insn(env
, ctx
, ASE_MIPS16
);
8004 /* MIPS16: Not implemented. */
8006 check_insn(env
, ctx
, ASE_MDMX
);
8007 /* MDMX: Not implemented. */
8008 default: /* Invalid */
8009 MIPS_INVAL("major opcode");
8010 generate_exception(ctx
, EXCP_RI
);
8013 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8014 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8015 /* Branches completion */
8016 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8017 ctx
->bstate
= BS_BRANCH
;
8018 save_cpu_state(ctx
, 0);
8019 /* FIXME: Need to clear can_do_io. */
8022 /* unconditional branch */
8023 MIPS_DEBUG("unconditional branch");
8024 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8027 /* blikely taken case */
8028 MIPS_DEBUG("blikely branch taken");
8029 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8032 /* Conditional branch */
8033 MIPS_DEBUG("conditional branch");
8035 int l1
= gen_new_label();
8037 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
8038 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8040 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8044 /* unconditional branch to register */
8045 MIPS_DEBUG("branch to register");
8046 tcg_gen_mov_tl(cpu_PC
, btarget
);
8050 MIPS_DEBUG("unknown branch");
8057 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
8061 target_ulong pc_start
;
8062 uint16_t *gen_opc_end
;
8069 qemu_log("search pc %d\n", search_pc
);
8072 /* Leave some spare opc slots for branch handling. */
8073 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
- 16;
8077 ctx
.bstate
= BS_NONE
;
8078 /* Restore delay slot state from the tb context. */
8079 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
8080 restore_cpu_state(env
, &ctx
);
8081 #ifdef CONFIG_USER_ONLY
8082 ctx
.mem_idx
= MIPS_HFLAG_UM
;
8084 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
8087 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8089 max_insns
= CF_COUNT_MASK
;
8091 qemu_log_mask(CPU_LOG_TB_CPU
, "------------------------------------------------\n");
8092 /* FIXME: This may print out stale hflags from env... */
8093 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
8095 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
8097 while (ctx
.bstate
== BS_NONE
) {
8098 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
8099 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8100 if (bp
->pc
== ctx
.pc
) {
8101 save_cpu_state(&ctx
, 1);
8102 ctx
.bstate
= BS_BRANCH
;
8103 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8104 /* Include the breakpoint location or the tb won't
8105 * be flushed when it must be. */
8107 goto done_generating
;
8113 j
= gen_opc_ptr
- gen_opc_buf
;
8117 gen_opc_instr_start
[lj
++] = 0;
8119 gen_opc_pc
[lj
] = ctx
.pc
;
8120 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
8121 gen_opc_instr_start
[lj
] = 1;
8122 gen_opc_icount
[lj
] = num_insns
;
8124 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8126 ctx
.opcode
= ldl_code(ctx
.pc
);
8127 decode_opc(env
, &ctx
);
8131 if (env
->singlestep_enabled
)
8134 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
8137 if (gen_opc_ptr
>= gen_opc_end
)
8140 if (num_insns
>= max_insns
)
8146 if (tb
->cflags
& CF_LAST_IO
)
8148 if (env
->singlestep_enabled
) {
8149 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
8150 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8152 switch (ctx
.bstate
) {
8154 gen_helper_interrupt_restart();
8155 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8158 save_cpu_state(&ctx
, 0);
8159 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8162 gen_helper_interrupt_restart();
8171 gen_icount_end(tb
, num_insns
);
8172 *gen_opc_ptr
= INDEX_op_end
;
8174 j
= gen_opc_ptr
- gen_opc_buf
;
8177 gen_opc_instr_start
[lj
++] = 0;
8179 tb
->size
= ctx
.pc
- pc_start
;
8180 tb
->icount
= num_insns
;
8184 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8185 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8186 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
8189 qemu_log_mask(CPU_LOG_TB_CPU
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
8193 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8195 gen_intermediate_code_internal(env
, tb
, 0);
8198 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8200 gen_intermediate_code_internal(env
, tb
, 1);
8203 static void fpu_dump_state(CPUState
*env
, FILE *f
,
8204 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8208 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
8210 #define printfpr(fp) \
8213 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8214 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8215 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8218 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8219 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8220 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8221 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8222 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8227 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8228 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
8229 get_float_exception_flags(&env
->active_fpu
.fp_status
));
8230 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8231 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8232 printfpr(&env
->active_fpu
.fpr
[i
]);
8238 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8239 /* Debug help: The architecture requires 32bit code to maintain proper
8240 sign-extended values on 64bit machines. */
8242 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8245 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8246 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8251 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8252 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8253 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8254 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8255 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8256 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8257 if (!SIGN_EXT_P(env
->btarget
))
8258 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8260 for (i
= 0; i
< 32; i
++) {
8261 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8262 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8265 if (!SIGN_EXT_P(env
->CP0_EPC
))
8266 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8267 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
8268 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
8272 void cpu_dump_state (CPUState
*env
, FILE *f
,
8273 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8278 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8279 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
8280 env
->hflags
, env
->btarget
, env
->bcond
);
8281 for (i
= 0; i
< 32; i
++) {
8283 cpu_fprintf(f
, "GPR%02d:", i
);
8284 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8286 cpu_fprintf(f
, "\n");
8289 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8290 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8291 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8292 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
8293 if (env
->hflags
& MIPS_HFLAG_FPU
)
8294 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8295 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8296 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8300 static void mips_tcg_init(void)
8305 /* Initialize various static tables. */
8309 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8310 for (i
= 0; i
< 32; i
++)
8311 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
8312 offsetof(CPUState
, active_tc
.gpr
[i
]),
8314 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
8315 offsetof(CPUState
, active_tc
.PC
), "PC");
8316 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
8317 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
8318 offsetof(CPUState
, active_tc
.HI
[i
]),
8320 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
8321 offsetof(CPUState
, active_tc
.LO
[i
]),
8323 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
8324 offsetof(CPUState
, active_tc
.ACX
[i
]),
8327 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
8328 offsetof(CPUState
, active_tc
.DSPControl
),
8330 bcond
= tcg_global_mem_new(TCG_AREG0
,
8331 offsetof(CPUState
, bcond
), "bcond");
8332 btarget
= tcg_global_mem_new(TCG_AREG0
,
8333 offsetof(CPUState
, btarget
), "btarget");
8334 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
8335 offsetof(CPUState
, hflags
), "hflags");
8337 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
8338 offsetof(CPUState
, active_fpu
.fcr0
),
8340 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
8341 offsetof(CPUState
, active_fpu
.fcr31
),
8344 /* register helpers */
8345 #define GEN_HELPER 2
8351 #include "translate_init.c"
8353 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8356 const mips_def_t
*def
;
8358 def
= cpu_mips_find_by_name(cpu_model
);
8361 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8362 env
->cpu_model
= def
;
8365 env
->cpu_model_str
= cpu_model
;
8371 void cpu_reset (CPUMIPSState
*env
)
8373 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
8374 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
8375 log_cpu_state(env
, 0);
8378 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8383 #if defined(CONFIG_USER_ONLY)
8384 env
->hflags
= MIPS_HFLAG_UM
;
8386 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8387 /* If the exception was raised from a delay slot,
8388 come back to the jump. */
8389 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8391 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8393 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8395 /* SMP not implemented */
8396 env
->CP0_EBase
= 0x80000000;
8397 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8398 /* vectored interrupts not implemented, timer on int 7,
8399 no performance counters. */
8400 env
->CP0_IntCtl
= 0xe0000000;
8404 for (i
= 0; i
< 7; i
++) {
8405 env
->CP0_WatchLo
[i
] = 0;
8406 env
->CP0_WatchHi
[i
] = 0x80000000;
8408 env
->CP0_WatchLo
[7] = 0;
8409 env
->CP0_WatchHi
[7] = 0;
8411 /* Count register increments in debug mode, EJTAG version 1 */
8412 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8413 env
->hflags
= MIPS_HFLAG_CP0
;
8415 env
->exception_index
= EXCP_NONE
;
8416 cpu_mips_register(env
, env
->cpu_model
);
8419 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8420 unsigned long searched_pc
, int pc_pos
, void *puc
)
8422 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8423 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8424 env
->hflags
|= gen_opc_hflags
[pc_pos
];