hw/stellaris_enet.c

   1 /*
   2  * Luminary Micro Stellaris Ethernet Controller
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9 #include "hw.h"
  10 #include "arm-misc.h"
  11 #include "net.h"
  12 #include <zlib.h>
  13
  14 //#define DEBUG_STELLARIS_ENET 1
  15
  16 #ifdef DEBUG_STELLARIS_ENET
  17 #define DPRINTF(fmt, args...) \
  18 do { printf("stellaris_enet: " fmt , ##args); } while (0)
  19 #define BADF(fmt, args...) \
  20 do { fprintf(stderr, "stellaris_enet: error: " fmt , ##args); exit(1);} while (0)
  21 #else
  22 #define DPRINTF(fmt, args...) do {} while(0)
  23 #define BADF(fmt, args...) \
  24 do { fprintf(stderr, "stellaris_enet: error: " fmt , ##args);} while (0)
  25 #endif
  26
  27 #define SE_INT_RX       0x01
  28 #define SE_INT_TXER     0x02
  29 #define SE_INT_TXEMP    0x04
  30 #define SE_INT_FOV      0x08
  31 #define SE_INT_RXER     0x10
  32 #define SE_INT_MD       0x20
  33 #define SE_INT_PHY      0x40
  34
  35 #define SE_RCTL_RXEN    0x01
  36 #define SE_RCTL_AMUL    0x02
  37 #define SE_RCTL_PRMS    0x04
  38 #define SE_RCTL_BADCRC  0x08
  39 #define SE_RCTL_RSTFIFO 0x10
  40
  41 #define SE_TCTL_TXEN    0x01
  42 #define SE_TCTL_PADEN   0x02
  43 #define SE_TCTL_CRC     0x04
  44 #define SE_TCTL_DUPLEX  0x08
  45
  46 typedef struct {
  47     uint32_t ris;
  48     uint32_t im;
  49     uint32_t rctl;
  50     uint32_t tctl;
  51     uint32_t thr;
  52     uint32_t mctl;
  53     uint32_t mdv;
  54     uint32_t mtxd;
  55     uint32_t mrxd;
  56     uint32_t np;
  57     int tx_frame_len;
  58     int tx_fifo_len;
  59     uint8_t tx_fifo[2048];
  60     /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
  61        We implement a full 31 packet fifo.  */
  62     struct {
  63         uint8_t data[2048];
  64         int len;
  65     } rx[31];
  66     uint8_t *rx_fifo;
  67     int rx_fifo_len;
  68     int next_packet;
  69     VLANClientState *vc;
  70     qemu_irq irq;
  71     uint8_t macaddr[6];
  72     int mmio_index;
  73 } stellaris_enet_state;
  74
  75 static void stellaris_enet_update(stellaris_enet_state *s)
  76 {
  77     qemu_set_irq(s->irq, (s->ris & s->im) != 0);
  78 }
  79
  80 /* TODO: Implement MAC address filtering.  */
  81 static void stellaris_enet_receive(void *opaque, const uint8_t *buf, int size)
  82 {
  83     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
  84     int n;
  85     uint8_t *p;
  86     uint32_t crc;
  87
  88     if ((s->rctl & SE_RCTL_RXEN) == 0)
  89         return;
  90     if (s->np >= 31) {
  91         DPRINTF("Packet dropped\n");
  92         return;
  93     }
  94
  95     DPRINTF("Received packet len=%d\n", size);
  96     n = s->next_packet + s->np;
  97     if (n >= 31)
  98         n -= 31;
  99     s->np++;
 100
 101     s->rx[n].len = size + 6;
 102     p = s->rx[n].data;
 103     *(p++) = (size + 6);
 104     *(p++) = (size + 6) >> 8;
 105     memcpy (p, buf, size);
 106     p += size;
 107     crc = crc32(~0, buf, size);
 108     *(p++) = crc;
 109     *(p++) = crc >> 8;
 110     *(p++) = crc >> 16;
 111     *(p++) = crc >> 24;
 112     /* Clear the remaining bytes in the last word.  */
 113     if ((size & 3) != 2) {
 114         memset(p, 0, (6 - size) & 3);
 115     }
 116
 117     s->ris |= SE_INT_RX;
 118     stellaris_enet_update(s);
 119 }
 120
 121 static int stellaris_enet_can_receive(void *opaque)
 122 {
 123     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 124
 125     if ((s->rctl & SE_RCTL_RXEN) == 0)
 126         return 1;
 127
 128     return (s->np < 31);
 129 }
 130
 131 static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
 132 {
 133     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 134     uint32_t val;
 135
 136     switch (offset) {
 137     case 0x00: /* RIS */
 138         DPRINTF("IRQ status %02x\n", s->ris);
 139         return s->ris;
 140     case 0x04: /* IM */
 141         return s->im;
 142     case 0x08: /* RCTL */
 143         return s->rctl;
 144     case 0x0c: /* TCTL */
 145         return s->tctl;
 146     case 0x10: /* DATA */
 147         if (s->rx_fifo_len == 0) {
 148             if (s->np == 0) {
 149                 BADF("RX underflow\n");
 150                 return 0;
 151             }
 152             s->rx_fifo_len = s->rx[s->next_packet].len;
 153             s->rx_fifo = s->rx[s->next_packet].data;
 154             DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
 155         }
 156         val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
 157               | (s->rx_fifo[3] << 24);
 158         s->rx_fifo += 4;
 159         s->rx_fifo_len -= 4;
 160         if (s->rx_fifo_len <= 0) {
 161             s->rx_fifo_len = 0;
 162             s->next_packet++;
 163             if (s->next_packet >= 31)
 164                 s->next_packet = 0;
 165             s->np--;
 166             DPRINTF("RX done np=%d\n", s->np);
 167         }
 168         return val;
 169     case 0x14: /* IA0 */
 170         return s->macaddr[0] | (s->macaddr[1] << 8)
 171                | (s->macaddr[2] << 16) | (s->macaddr[3] << 24);
 172     case 0x18: /* IA1 */
 173         return s->macaddr[4] | (s->macaddr[5] << 8);
 174     case 0x1c: /* THR */
 175         return s->thr;
 176     case 0x20: /* MCTL */
 177         return s->mctl;
 178     case 0x24: /* MDV */
 179         return s->mdv;
 180     case 0x28: /* MADD */
 181         return 0;
 182     case 0x2c: /* MTXD */
 183         return s->mtxd;
 184     case 0x30: /* MRXD */
 185         return s->mrxd;
 186     case 0x34: /* NP */
 187         return s->np;
 188     case 0x38: /* TR */
 189         return 0;
 190     case 0x3c: /* Undocuented: Timestamp? */
 191         return 0;
 192     default:
 193         cpu_abort (cpu_single_env, "stellaris_enet_read: Bad offset %x\n",
 194                    (int)offset);
 195         return 0;
 196     }
 197 }
 198
 199 static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
 200                         uint32_t value)
 201 {
 202     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 203
 204     switch (offset) {
 205     case 0x00: /* IACK */
 206         s->ris &= ~value;
 207         DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
 208         stellaris_enet_update(s);
 209         /* Clearing TXER also resets the TX fifo.  */
 210         if (value & SE_INT_TXER)
 211             s->tx_frame_len = -1;
 212         break;
 213     case 0x04: /* IM */
 214         DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
 215         s->im = value;
 216         stellaris_enet_update(s);
 217         break;
 218     case 0x08: /* RCTL */
 219         s->rctl = value;
 220         if (value & SE_RCTL_RSTFIFO) {
 221             s->rx_fifo_len = 0;
 222             s->np = 0;
 223             stellaris_enet_update(s);
 224         }
 225         break;
 226     case 0x0c: /* TCTL */
 227         s->tctl = value;
 228         break;
 229     case 0x10: /* DATA */
 230         if (s->tx_frame_len == -1) {
 231             s->tx_frame_len = value & 0xffff;
 232             if (s->tx_frame_len > 2032) {
 233                 DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
 234                 s->tx_frame_len = 0;
 235                 s->ris |= SE_INT_TXER;
 236                 stellaris_enet_update(s);
 237             } else {
 238                 DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
 239                 /* The value written does not include the ethernet header.  */
 240                 s->tx_frame_len += 14;
 241                 if ((s->tctl & SE_TCTL_CRC) == 0)
 242                     s->tx_frame_len += 4;
 243                 s->tx_fifo_len = 0;
 244                 s->tx_fifo[s->tx_fifo_len++] = value >> 16;
 245                 s->tx_fifo[s->tx_fifo_len++] = value >> 24;
 246             }
 247         } else {
 248             s->tx_fifo[s->tx_fifo_len++] = value;
 249             s->tx_fifo[s->tx_fifo_len++] = value >> 8;
 250             s->tx_fifo[s->tx_fifo_len++] = value >> 16;
 251             s->tx_fifo[s->tx_fifo_len++] = value >> 24;
 252             if (s->tx_fifo_len >= s->tx_frame_len) {
 253                 /* We don't implement explicit CRC, so just chop it off.  */
 254                 if ((s->tctl & SE_TCTL_CRC) == 0)
 255                     s->tx_frame_len -= 4;
 256                 if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
 257                     memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
 258                     s->tx_fifo_len = 60;
 259                 }
 260                 qemu_send_packet(s->vc, s->tx_fifo, s->tx_frame_len);
 261                 s->tx_frame_len = -1;
 262                 s->ris |= SE_INT_TXEMP;
 263                 stellaris_enet_update(s);
 264                 DPRINTF("Done TX\n");
 265             }
 266         }
 267         break;
 268     case 0x14: /* IA0 */
 269         s->macaddr[0] = value;
 270         s->macaddr[1] = value >> 8;
 271         s->macaddr[2] = value >> 16;
 272         s->macaddr[3] = value >> 24;
 273         break;
 274     case 0x18: /* IA1 */
 275         s->macaddr[4] = value;
 276         s->macaddr[5] = value >> 8;
 277         break;
 278     case 0x1c: /* THR */
 279         s->thr = value;
 280         break;
 281     case 0x20: /* MCTL */
 282         s->mctl = value;
 283         break;
 284     case 0x24: /* MDV */
 285         s->mdv = value;
 286         break;
 287     case 0x28: /* MADD */
 288         /* ignored.  */
 289         break;
 290     case 0x2c: /* MTXD */
 291         s->mtxd = value & 0xff;
 292         break;
 293     case 0x30: /* MRXD */
 294     case 0x34: /* NP */
 295     case 0x38: /* TR */
 296         /* Ignored.  */
 297     case 0x3c: /* Undocuented: Timestamp? */
 298         /* Ignored.  */
 299         break;
 300     default:
 301         cpu_abort (cpu_single_env, "stellaris_enet_write: Bad offset %x\n",
 302                    (int)offset);
 303     }
 304 }
 305
 306 static CPUReadMemoryFunc *stellaris_enet_readfn[] = {
 307    stellaris_enet_read,
 308    stellaris_enet_read,
 309    stellaris_enet_read
 310 };
 311
 312 static CPUWriteMemoryFunc *stellaris_enet_writefn[] = {
 313    stellaris_enet_write,
 314    stellaris_enet_write,
 315    stellaris_enet_write
 316 };
 317 static void stellaris_enet_reset(stellaris_enet_state *s)
 318 {
 319     s->mdv = 0x80;
 320     s->rctl = SE_RCTL_BADCRC;
 321     s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
 322             | SE_INT_TXER | SE_INT_RX;
 323     s->thr = 0x3f;
 324     s->tx_frame_len = -1;
 325 }
 326
 327 static void stellaris_enet_save(QEMUFile *f, void *opaque)
 328 {
 329     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 330     int i;
 331
 332     qemu_put_be32(f, s->ris);
 333     qemu_put_be32(f, s->im);
 334     qemu_put_be32(f, s->rctl);
 335     qemu_put_be32(f, s->tctl);
 336     qemu_put_be32(f, s->thr);
 337     qemu_put_be32(f, s->mctl);
 338     qemu_put_be32(f, s->mdv);
 339     qemu_put_be32(f, s->mtxd);
 340     qemu_put_be32(f, s->mrxd);
 341     qemu_put_be32(f, s->np);
 342     qemu_put_be32(f, s->tx_frame_len);
 343     qemu_put_be32(f, s->tx_fifo_len);
 344     qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
 345     for (i = 0; i < 31; i++) {
 346         qemu_put_be32(f, s->rx[i].len);
 347         qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
 348
 349     }
 350     qemu_put_be32(f, s->next_packet);
 351     qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
 352     qemu_put_be32(f, s->rx_fifo_len);
 353 }
 354
 355 static int stellaris_enet_load(QEMUFile *f, void *opaque, int version_id)
 356 {
 357     stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 358     int i;
 359
 360     if (version_id != 1)
 361         return -EINVAL;
 362
 363     s->ris = qemu_get_be32(f);
 364     s->im = qemu_get_be32(f);
 365     s->rctl = qemu_get_be32(f);
 366     s->tctl = qemu_get_be32(f);
 367     s->thr = qemu_get_be32(f);
 368     s->mctl = qemu_get_be32(f);
 369     s->mdv = qemu_get_be32(f);
 370     s->mtxd = qemu_get_be32(f);
 371     s->mrxd = qemu_get_be32(f);
 372     s->np = qemu_get_be32(f);
 373     s->tx_frame_len = qemu_get_be32(f);
 374     s->tx_fifo_len = qemu_get_be32(f);
 375     qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
 376     for (i = 0; i < 31; i++) {
 377         s->rx[i].len = qemu_get_be32(f);
 378         qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
 379
 380     }
 381     s->next_packet = qemu_get_be32(f);
 382     s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
 383     s->rx_fifo_len = qemu_get_be32(f);
 384
 385     return 0;
 386 }
 387
 388 static void stellaris_enet_cleanup(VLANClientState *vc)
 389 {
 390     stellaris_enet_state *s = vc->opaque;
 391
 392     unregister_savevm("stellaris_enet", s);
 393
 394     cpu_unregister_io_memory(s->mmio_index);
 395
 396     qemu_free(s);
 397 }
 398
 399 void stellaris_enet_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 400 {
 401     stellaris_enet_state *s;
 402
 403     qemu_check_nic_model(nd, "stellaris");
 404
 405     s = (stellaris_enet_state *)qemu_mallocz(sizeof(stellaris_enet_state));
 406     s->mmio_index = cpu_register_io_memory(0, stellaris_enet_readfn,
 407                                            stellaris_enet_writefn, s);
 408     cpu_register_physical_memory(base, 0x00001000, s->mmio_index);
 409     s->irq = irq;
 410     memcpy(s->macaddr, nd->macaddr, 6);
 411
 412     if (nd->vlan) {
 413         s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
 414                                      stellaris_enet_receive,
 415                                      stellaris_enet_can_receive,
 416                                      stellaris_enet_cleanup, s);
 417         qemu_format_nic_info_str(s->vc, s->macaddr);
 418     }
 419
 420     stellaris_enet_reset(s);
 421     register_savevm("stellaris_enet", -1, 1,
 422                     stellaris_enet_save, stellaris_enet_load, s);
 423 }