6 //#define DEBUG_MIPSNET_SEND
7 //#define DEBUG_MIPSNET_RECEIVE
8 //#define DEBUG_MIPSNET_DATA
9 //#define DEBUG_MIPSNET_IRQ
11 /* MIPSnet register offsets */
13 #define MIPSNET_DEV_ID 0x00
14 #define MIPSNET_BUSY 0x08
15 #define MIPSNET_RX_DATA_COUNT 0x0c
16 #define MIPSNET_TX_DATA_COUNT 0x10
17 #define MIPSNET_INT_CTL 0x14
18 # define MIPSNET_INTCTL_TXDONE 0x00000001
19 # define MIPSNET_INTCTL_RXDONE 0x00000002
20 # define MIPSNET_INTCTL_TESTBIT 0x80000000
21 #define MIPSNET_INTERRUPT_INFO 0x18
22 #define MIPSNET_RX_DATA_BUFFER 0x1c
23 #define MIPSNET_TX_DATA_BUFFER 0x20
25 #define MAX_ETH_FRAME_SIZE 1514
27 typedef struct MIPSnetState
{
34 uint8_t rx_buffer
[MAX_ETH_FRAME_SIZE
];
35 uint8_t tx_buffer
[MAX_ETH_FRAME_SIZE
];
40 static void mipsnet_reset(MIPSnetState
*s
)
48 memset(s
->rx_buffer
, 0, MAX_ETH_FRAME_SIZE
);
49 memset(s
->tx_buffer
, 0, MAX_ETH_FRAME_SIZE
);
52 static void mipsnet_update_irq(MIPSnetState
*s
)
54 int isr
= !!s
->intctl
;
55 #ifdef DEBUG_MIPSNET_IRQ
56 printf("mipsnet: Set IRQ to %d (%02x)\n", isr
, s
->intctl
);
58 qemu_set_irq(s
->irq
, isr
);
61 static int mipsnet_buffer_full(MIPSnetState
*s
)
63 if (s
->rx_count
>= MAX_ETH_FRAME_SIZE
)
68 static int mipsnet_can_receive(void *opaque
)
70 MIPSnetState
*s
= opaque
;
74 return !mipsnet_buffer_full(s
);
77 static void mipsnet_receive(void *opaque
, const uint8_t *buf
, int size
)
79 MIPSnetState
*s
= opaque
;
81 #ifdef DEBUG_MIPSNET_RECEIVE
82 printf("mipsnet: receiving len=%d\n", size
);
84 if (!mipsnet_can_receive(opaque
))
89 /* Just accept everything. */
91 /* Write packet data. */
92 memcpy(s
->rx_buffer
, buf
, size
);
97 /* Now we can signal we have received something. */
98 s
->intctl
|= MIPSNET_INTCTL_RXDONE
;
99 mipsnet_update_irq(s
);
102 static uint32_t mipsnet_ioport_read(void *opaque
, uint32_t addr
)
104 MIPSnetState
*s
= opaque
;
110 ret
= be32_to_cpu(0x4d495053); /* MIPS */
112 case MIPSNET_DEV_ID
+ 4:
113 ret
= be32_to_cpu(0x4e455430); /* NET0 */
118 case MIPSNET_RX_DATA_COUNT
:
121 case MIPSNET_TX_DATA_COUNT
:
124 case MIPSNET_INT_CTL
:
126 s
->intctl
&= ~MIPSNET_INTCTL_TESTBIT
;
128 case MIPSNET_INTERRUPT_INFO
:
129 /* XXX: This seems to be a per-VPE interrupt number. */
132 case MIPSNET_RX_DATA_BUFFER
:
135 ret
= s
->rx_buffer
[s
->rx_read
++];
139 case MIPSNET_TX_DATA_BUFFER
:
143 #ifdef DEBUG_MIPSNET_DATA
144 printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr
, ret
);
149 static void mipsnet_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
151 MIPSnetState
*s
= opaque
;
154 #ifdef DEBUG_MIPSNET_DATA
155 printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr
, val
);
158 case MIPSNET_TX_DATA_COUNT
:
159 s
->tx_count
= (val
<= MAX_ETH_FRAME_SIZE
) ? val
: 0;
162 case MIPSNET_INT_CTL
:
163 if (val
& MIPSNET_INTCTL_TXDONE
) {
164 s
->intctl
&= ~MIPSNET_INTCTL_TXDONE
;
165 } else if (val
& MIPSNET_INTCTL_RXDONE
) {
166 s
->intctl
&= ~MIPSNET_INTCTL_RXDONE
;
167 } else if (val
& MIPSNET_INTCTL_TESTBIT
) {
169 s
->intctl
|= MIPSNET_INTCTL_TESTBIT
;
171 /* ACK testbit interrupt, flag was cleared on read. */
173 s
->busy
= !!s
->intctl
;
174 mipsnet_update_irq(s
);
176 case MIPSNET_TX_DATA_BUFFER
:
177 s
->tx_buffer
[s
->tx_written
++] = val
;
178 if (s
->tx_written
== s
->tx_count
) {
180 #ifdef DEBUG_MIPSNET_SEND
181 printf("mipsnet: sending len=%d\n", s
->tx_count
);
183 qemu_send_packet(s
->vc
, s
->tx_buffer
, s
->tx_count
);
184 s
->tx_count
= s
->tx_written
= 0;
185 s
->intctl
|= MIPSNET_INTCTL_TXDONE
;
187 mipsnet_update_irq(s
);
190 /* Read-only registers */
193 case MIPSNET_RX_DATA_COUNT
:
194 case MIPSNET_INTERRUPT_INFO
:
195 case MIPSNET_RX_DATA_BUFFER
:
201 static void mipsnet_save(QEMUFile
*f
, void *opaque
)
203 MIPSnetState
*s
= opaque
;
205 qemu_put_be32s(f
, &s
->busy
);
206 qemu_put_be32s(f
, &s
->rx_count
);
207 qemu_put_be32s(f
, &s
->rx_read
);
208 qemu_put_be32s(f
, &s
->tx_count
);
209 qemu_put_be32s(f
, &s
->tx_written
);
210 qemu_put_be32s(f
, &s
->intctl
);
211 qemu_put_buffer(f
, s
->rx_buffer
, MAX_ETH_FRAME_SIZE
);
212 qemu_put_buffer(f
, s
->tx_buffer
, MAX_ETH_FRAME_SIZE
);
215 static int mipsnet_load(QEMUFile
*f
, void *opaque
, int version_id
)
217 MIPSnetState
*s
= opaque
;
222 qemu_get_be32s(f
, &s
->busy
);
223 qemu_get_be32s(f
, &s
->rx_count
);
224 qemu_get_be32s(f
, &s
->rx_read
);
225 qemu_get_be32s(f
, &s
->tx_count
);
226 qemu_get_be32s(f
, &s
->tx_written
);
227 qemu_get_be32s(f
, &s
->intctl
);
228 qemu_get_buffer(f
, s
->rx_buffer
, MAX_ETH_FRAME_SIZE
);
229 qemu_get_buffer(f
, s
->tx_buffer
, MAX_ETH_FRAME_SIZE
);
234 void mipsnet_init (int base
, qemu_irq irq
, NICInfo
*nd
)
238 qemu_check_nic_model(nd
, "mipsnet");
240 s
= qemu_mallocz(sizeof(MIPSnetState
));
242 register_ioport_write(base
, 36, 1, mipsnet_ioport_write
, s
);
243 register_ioport_read(base
, 36, 1, mipsnet_ioport_read
, s
);
244 register_ioport_write(base
, 36, 2, mipsnet_ioport_write
, s
);
245 register_ioport_read(base
, 36, 2, mipsnet_ioport_read
, s
);
246 register_ioport_write(base
, 36, 4, mipsnet_ioport_write
, s
);
247 register_ioport_read(base
, 36, 4, mipsnet_ioport_read
, s
);
250 if (nd
&& nd
->vlan
) {
251 s
->vc
= qemu_new_vlan_client(nd
->vlan
, nd
->model
, nd
->name
,
252 mipsnet_receive
, mipsnet_can_receive
, s
);
257 qemu_format_nic_info_str(s
->vc
, nd
->macaddr
);
260 register_savevm("mipsnet", 0, 0, mipsnet_save
, mipsnet_load
, s
);