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target-ppc: use the new fp functions
[qemu/mini2440/sniper_sniper_test.git] / target-ppc / op_helper.c
blob4368df8e4e02e7086a0c21a5c15c062055c19765
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22 #include "helper.h"
23
24 #include "helper_regs.h"
25
26 //#define DEBUG_OP
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
29
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
32
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
34 {
35 #if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37 #endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
41 }
42
43 void helper_raise_exception (uint32_t exception)
44 {
45 helper_raise_exception_err(exception, 0);
46 }
47
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
51 {
52 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
60 }
61
62 void helper_store_cr (target_ulong val, uint32_t mask)
63 {
64 int i, sh;
65
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
67 if (mask & (1 << sh))
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
69 }
70 }
71
72 /*****************************************************************************/
73 /* SPR accesses */
74 void helper_load_dump_spr (uint32_t sprn)
75 {
76 if (loglevel != 0) {
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
80 }
81
82 void helper_store_dump_spr (uint32_t sprn)
83 {
84 if (loglevel != 0) {
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
87 }
88 }
89
90 target_ulong helper_load_tbl (void)
91 {
92 return cpu_ppc_load_tbl(env);
93 }
94
95 target_ulong helper_load_tbu (void)
96 {
97 return cpu_ppc_load_tbu(env);
98 }
99
100 target_ulong helper_load_atbl (void)
101 {
102 return cpu_ppc_load_atbl(env);
103 }
104
105 target_ulong helper_load_atbu (void)
106 {
107 return cpu_ppc_load_atbu(env);
108 }
109
110 target_ulong helper_load_601_rtcl (void)
111 {
112 return cpu_ppc601_load_rtcl(env);
113 }
114
115 target_ulong helper_load_601_rtcu (void)
116 {
117 return cpu_ppc601_load_rtcu(env);
118 }
119
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
123 {
124 ppc_store_asr(env, val);
125 }
126 #endif
127
128 void helper_store_sdr1 (target_ulong val)
129 {
130 ppc_store_sdr1(env, val);
131 }
132
133 void helper_store_tbl (target_ulong val)
134 {
135 cpu_ppc_store_tbl(env, val);
136 }
137
138 void helper_store_tbu (target_ulong val)
139 {
140 cpu_ppc_store_tbu(env, val);
141 }
142
143 void helper_store_atbl (target_ulong val)
144 {
145 cpu_ppc_store_atbl(env, val);
146 }
147
148 void helper_store_atbu (target_ulong val)
149 {
150 cpu_ppc_store_atbu(env, val);
151 }
152
153 void helper_store_601_rtcl (target_ulong val)
154 {
155 cpu_ppc601_store_rtcl(env, val);
156 }
157
158 void helper_store_601_rtcu (target_ulong val)
159 {
160 cpu_ppc601_store_rtcu(env, val);
161 }
162
163 target_ulong helper_load_decr (void)
164 {
165 return cpu_ppc_load_decr(env);
166 }
167
168 void helper_store_decr (target_ulong val)
169 {
170 cpu_ppc_store_decr(env, val);
171 }
172
173 void helper_store_hid0_601 (target_ulong val)
174 {
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
188 }
189 env->spr[SPR_HID0] = (uint32_t)val;
190 }
191
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
193 {
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199 }
200
201 target_ulong helper_load_40x_pit (void)
202 {
203 return load_40x_pit(env);
204 }
205
206 void helper_store_40x_pit (target_ulong val)
207 {
208 store_40x_pit(env, val);
209 }
210
211 void helper_store_40x_dbcr0 (target_ulong val)
212 {
213 store_40x_dbcr0(env, val);
214 }
215
216 void helper_store_40x_sler (target_ulong val)
217 {
218 store_40x_sler(env, val);
219 }
220
221 void helper_store_booke_tcr (target_ulong val)
222 {
223 store_booke_tcr(env, val);
224 }
225
226 void helper_store_booke_tsr (target_ulong val)
227 {
228 store_booke_tsr(env, val);
229 }
230
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
232 {
233 ppc_store_ibatu(env, nr, val);
234 }
235
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
237 {
238 ppc_store_ibatl(env, nr, val);
239 }
240
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
242 {
243 ppc_store_dbatu(env, nr, val);
244 }
245
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
247 {
248 ppc_store_dbatl(env, nr, val);
249 }
250
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
252 {
253 ppc_store_ibatl_601(env, nr, val);
254 }
255
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
257 {
258 ppc_store_ibatu_601(env, nr, val);
259 }
260 #endif
261
262 /*****************************************************************************/
263 /* Memory load and stores */
264
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
266 {
267 #if defined(TARGET_PPC64)
268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
270 else
271 #endif
272 return addr + arg;
273 }
274
275 void helper_lmw (target_ulong addr, uint32_t reg)
276 {
277 for (; reg < 32; reg++) {
278 if (msr_le)
279 env->gpr[reg] = bswap32(ldl(addr));
280 else
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
283 }
284 }
285
286 void helper_stmw (target_ulong addr, uint32_t reg)
287 {
288 for (; reg < 32; reg++) {
289 if (msr_le)
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
291 else
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
294 }
295 }
296
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298 {
299 int sh;
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
310 }
311 }
312 }
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319 {
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330 }
331
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333 {
334 int sh;
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
339 }
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
344 }
345 }
346
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
348 {
349 addr &= ~(dcache_line_size - 1);
350 int i;
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
352 stl(addr + i , 0);
353 }
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
356 }
357
358 void helper_dcbz(target_ulong addr)
359 {
360 do_dcbz(addr, env->dcache_line_size);
361 }
362
363 void helper_dcbz_970(target_ulong addr)
364 {
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
366 do_dcbz(addr, 32);
367 else
368 do_dcbz(addr, env->dcache_line_size);
369 }
370
371 void helper_icbi(target_ulong addr)
372 {
373 uint32_t tmp;
374
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
380 */
381 tmp = ldl(addr);
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
383 }
384
385 // XXX: to be tested
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
387 {
388 int i, c, d;
389 d = 24;
390 for (i = 0; i < xer_bc; i++) {
391 c = ldub(addr);
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
396 }
397 if (unlikely(c == xer_cmp))
398 break;
399 if (likely(d != 0)) {
400 d -= 8;
401 } else {
402 d = 24;
403 reg++;
404 reg = reg & 0x1F;
405 }
406 }
407 return i;
408 }
409
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
413
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
416 {
417 uint64_t tl, th;
418
419 muls64(&tl, &th, arg1, arg2);
420 return th;
421 }
422
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
425 {
426 uint64_t tl, th;
427
428 mulu64(&tl, &th, arg1, arg2);
429 return th;
430 }
431
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
433 {
434 int64_t th;
435 uint64_t tl;
436
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
441 } else {
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
443 }
444 return (int64_t)tl;
445 }
446 #endif
447
448 target_ulong helper_cntlzw (target_ulong t)
449 {
450 return clz32(t);
451 }
452
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
455 {
456 return clz64(t);
457 }
458 #endif
459
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
462 {
463 int32_t ret;
464
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
467 shift &= 0x1f;
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
471 } else {
472 env->xer |= (1 << XER_CA);
473 }
474 } else {
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
477 }
478 } else {
479 ret = (int32_t)value >> 31;
480 if (ret) {
481 env->xer |= (1 << XER_CA);
482 } else {
483 env->xer &= ~(1 << XER_CA);
484 }
485 }
486 return (target_long)ret;
487 }
488
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
491 {
492 int64_t ret;
493
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
496 shift &= 0x3f;
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
500 } else {
501 env->xer |= (1 << XER_CA);
502 }
503 } else {
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
506 }
507 } else {
508 ret = (int64_t)value >> 63;
509 if (ret) {
510 env->xer |= (1 << XER_CA);
511 } else {
512 env->xer &= ~(1 << XER_CA);
513 }
514 }
515 return ret;
516 }
517 #endif
518
519 target_ulong helper_popcntb (target_ulong val)
520 {
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
524 return val;
525 }
526
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
529 {
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
533 return val;
534 }
535 #endif
536
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
540 {
541 CPU_FloatU f;
542 CPU_DoubleU d;
543 f.l = arg;
544 d.d = float32_to_float64(f.f, &env->fp_status);
545 return d.ll;
546 }
547
548 uint32_t helper_float64_to_float32(uint64_t arg)
549 {
550 CPU_FloatU f;
551 CPU_DoubleU d;
552 d.ll = arg;
553 f.f = float64_to_float32(d.d, &env->fp_status);
554 return f.l;
555 }
556
557 static always_inline int isden (float64 d)
558 {
559 CPU_DoubleU u;
560
561 u.d = d;
562
563 return ((u.ll >> 52) & 0x7FF) == 0;
564 }
565
566
567 #ifdef CONFIG_SOFTFLOAT
568 static always_inline int isfinite (float64 d)
569 {
570 CPU_DoubleU u;
571
572 u.d = d;
573
574 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
575 }
576
577 static always_inline int isnormal (float64 d)
578 {
579 CPU_DoubleU u;
580
581 u.d = d;
582
583 uint32_t exp = (u.ll >> 52) & 0x7FF;
584 return ((0 < exp) && (exp < 0x7FF));
585 }
586 #endif
587
588 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
589 {
590 CPU_DoubleU farg;
591 int isneg;
592 int ret;
593 farg.ll = arg;
594 isneg = float64_is_neg(farg.d);
595 if (unlikely(float64_is_nan(farg.d))) {
596 if (float64_is_signaling_nan(farg.d)) {
597 /* Signaling NaN: flags are undefined */
598 ret = 0x00;
599 } else {
600 /* Quiet NaN */
601 ret = 0x11;
602 }
603 } else if (unlikely(float64_is_infinity(farg.d))) {
604 /* +/- infinity */
605 if (isneg)
606 ret = 0x09;
607 else
608 ret = 0x05;
609 } else {
610 if (float64_is_zero(farg.d)) {
611 /* +/- zero */
612 if (isneg)
613 ret = 0x12;
614 else
615 ret = 0x02;
616 } else {
617 if (isden(farg.d)) {
618 /* Denormalized numbers */
619 ret = 0x10;
620 } else {
621 /* Normalized numbers */
622 ret = 0x00;
623 }
624 if (isneg) {
625 ret |= 0x08;
626 } else {
627 ret |= 0x04;
628 }
629 }
630 }
631 if (set_fprf) {
632 /* We update FPSCR_FPRF */
633 env->fpscr &= ~(0x1F << FPSCR_FPRF);
634 env->fpscr |= ret << FPSCR_FPRF;
635 }
636 /* We just need fpcc to update Rc1 */
637 return ret & 0xF;
638 }
639
640 /* Floating-point invalid operations exception */
641 static always_inline uint64_t fload_invalid_op_excp (int op)
642 {
643 uint64_t ret = 0;
644 int ve;
645
646 ve = fpscr_ve;
647 switch (op) {
648 case POWERPC_EXCP_FP_VXSNAN:
649 env->fpscr |= 1 << FPSCR_VXSNAN;
650 break;
651 case POWERPC_EXCP_FP_VXSOFT:
652 env->fpscr |= 1 << FPSCR_VXSOFT;
653 break;
654 case POWERPC_EXCP_FP_VXISI:
655 /* Magnitude subtraction of infinities */
656 env->fpscr |= 1 << FPSCR_VXISI;
657 goto update_arith;
658 case POWERPC_EXCP_FP_VXIDI:
659 /* Division of infinity by infinity */
660 env->fpscr |= 1 << FPSCR_VXIDI;
661 goto update_arith;
662 case POWERPC_EXCP_FP_VXZDZ:
663 /* Division of zero by zero */
664 env->fpscr |= 1 << FPSCR_VXZDZ;
665 goto update_arith;
666 case POWERPC_EXCP_FP_VXIMZ:
667 /* Multiplication of zero by infinity */
668 env->fpscr |= 1 << FPSCR_VXIMZ;
669 goto update_arith;
670 case POWERPC_EXCP_FP_VXVC:
671 /* Ordered comparison of NaN */
672 env->fpscr |= 1 << FPSCR_VXVC;
673 env->fpscr &= ~(0xF << FPSCR_FPCC);
674 env->fpscr |= 0x11 << FPSCR_FPCC;
675 /* We must update the target FPR before raising the exception */
676 if (ve != 0) {
677 env->exception_index = POWERPC_EXCP_PROGRAM;
678 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
679 /* Update the floating-point enabled exception summary */
680 env->fpscr |= 1 << FPSCR_FEX;
681 /* Exception is differed */
682 ve = 0;
683 }
684 break;
685 case POWERPC_EXCP_FP_VXSQRT:
686 /* Square root of a negative number */
687 env->fpscr |= 1 << FPSCR_VXSQRT;
688 update_arith:
689 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
690 if (ve == 0) {
691 /* Set the result to quiet NaN */
692 ret = 0xFFF8000000000000ULL;
693 env->fpscr &= ~(0xF << FPSCR_FPCC);
694 env->fpscr |= 0x11 << FPSCR_FPCC;
695 }
696 break;
697 case POWERPC_EXCP_FP_VXCVI:
698 /* Invalid conversion */
699 env->fpscr |= 1 << FPSCR_VXCVI;
700 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
701 if (ve == 0) {
702 /* Set the result to quiet NaN */
703 ret = 0xFFF8000000000000ULL;
704 env->fpscr &= ~(0xF << FPSCR_FPCC);
705 env->fpscr |= 0x11 << FPSCR_FPCC;
706 }
707 break;
708 }
709 /* Update the floating-point invalid operation summary */
710 env->fpscr |= 1 << FPSCR_VX;
711 /* Update the floating-point exception summary */
712 env->fpscr |= 1 << FPSCR_FX;
713 if (ve != 0) {
714 /* Update the floating-point enabled exception summary */
715 env->fpscr |= 1 << FPSCR_FEX;
716 if (msr_fe0 != 0 || msr_fe1 != 0)
717 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
718 }
719 return ret;
720 }
721
722 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
723 {
724 env->fpscr |= 1 << FPSCR_ZX;
725 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
726 /* Update the floating-point exception summary */
727 env->fpscr |= 1 << FPSCR_FX;
728 if (fpscr_ze != 0) {
729 /* Update the floating-point enabled exception summary */
730 env->fpscr |= 1 << FPSCR_FEX;
731 if (msr_fe0 != 0 || msr_fe1 != 0) {
732 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
733 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
734 }
735 } else {
736 /* Set the result to infinity */
737 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
738 arg1 |= 0x7FFULL << 52;
739 }
740 return arg1;
741 }
742
743 static always_inline void float_overflow_excp (void)
744 {
745 env->fpscr |= 1 << FPSCR_OX;
746 /* Update the floating-point exception summary */
747 env->fpscr |= 1 << FPSCR_FX;
748 if (fpscr_oe != 0) {
749 /* XXX: should adjust the result */
750 /* Update the floating-point enabled exception summary */
751 env->fpscr |= 1 << FPSCR_FEX;
752 /* We must update the target FPR before raising the exception */
753 env->exception_index = POWERPC_EXCP_PROGRAM;
754 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
755 } else {
756 env->fpscr |= 1 << FPSCR_XX;
757 env->fpscr |= 1 << FPSCR_FI;
758 }
759 }
760
761 static always_inline void float_underflow_excp (void)
762 {
763 env->fpscr |= 1 << FPSCR_UX;
764 /* Update the floating-point exception summary */
765 env->fpscr |= 1 << FPSCR_FX;
766 if (fpscr_ue != 0) {
767 /* XXX: should adjust the result */
768 /* Update the floating-point enabled exception summary */
769 env->fpscr |= 1 << FPSCR_FEX;
770 /* We must update the target FPR before raising the exception */
771 env->exception_index = POWERPC_EXCP_PROGRAM;
772 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
773 }
774 }
775
776 static always_inline void float_inexact_excp (void)
777 {
778 env->fpscr |= 1 << FPSCR_XX;
779 /* Update the floating-point exception summary */
780 env->fpscr |= 1 << FPSCR_FX;
781 if (fpscr_xe != 0) {
782 /* Update the floating-point enabled exception summary */
783 env->fpscr |= 1 << FPSCR_FEX;
784 /* We must update the target FPR before raising the exception */
785 env->exception_index = POWERPC_EXCP_PROGRAM;
786 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
787 }
788 }
789
790 static always_inline void fpscr_set_rounding_mode (void)
791 {
792 int rnd_type;
793
794 /* Set rounding mode */
795 switch (fpscr_rn) {
796 case 0:
797 /* Best approximation (round to nearest) */
798 rnd_type = float_round_nearest_even;
799 break;
800 case 1:
801 /* Smaller magnitude (round toward zero) */
802 rnd_type = float_round_to_zero;
803 break;
804 case 2:
805 /* Round toward +infinite */
806 rnd_type = float_round_up;
807 break;
808 default:
809 case 3:
810 /* Round toward -infinite */
811 rnd_type = float_round_down;
812 break;
813 }
814 set_float_rounding_mode(rnd_type, &env->fp_status);
815 }
816
817 void helper_fpscr_clrbit (uint32_t bit)
818 {
819 int prev;
820
821 prev = (env->fpscr >> bit) & 1;
822 env->fpscr &= ~(1 << bit);
823 if (prev == 1) {
824 switch (bit) {
825 case FPSCR_RN1:
826 case FPSCR_RN:
827 fpscr_set_rounding_mode();
828 break;
829 default:
830 break;
831 }
832 }
833 }
834
835 void helper_fpscr_setbit (uint32_t bit)
836 {
837 int prev;
838
839 prev = (env->fpscr >> bit) & 1;
840 env->fpscr |= 1 << bit;
841 if (prev == 0) {
842 switch (bit) {
843 case FPSCR_VX:
844 env->fpscr |= 1 << FPSCR_FX;
845 if (fpscr_ve)
846 goto raise_ve;
847 case FPSCR_OX:
848 env->fpscr |= 1 << FPSCR_FX;
849 if (fpscr_oe)
850 goto raise_oe;
851 break;
852 case FPSCR_UX:
853 env->fpscr |= 1 << FPSCR_FX;
854 if (fpscr_ue)
855 goto raise_ue;
856 break;
857 case FPSCR_ZX:
858 env->fpscr |= 1 << FPSCR_FX;
859 if (fpscr_ze)
860 goto raise_ze;
861 break;
862 case FPSCR_XX:
863 env->fpscr |= 1 << FPSCR_FX;
864 if (fpscr_xe)
865 goto raise_xe;
866 break;
867 case FPSCR_VXSNAN:
868 case FPSCR_VXISI:
869 case FPSCR_VXIDI:
870 case FPSCR_VXZDZ:
871 case FPSCR_VXIMZ:
872 case FPSCR_VXVC:
873 case FPSCR_VXSOFT:
874 case FPSCR_VXSQRT:
875 case FPSCR_VXCVI:
876 env->fpscr |= 1 << FPSCR_VX;
877 env->fpscr |= 1 << FPSCR_FX;
878 if (fpscr_ve != 0)
879 goto raise_ve;
880 break;
881 case FPSCR_VE:
882 if (fpscr_vx != 0) {
883 raise_ve:
884 env->error_code = POWERPC_EXCP_FP;
885 if (fpscr_vxsnan)
886 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
887 if (fpscr_vxisi)
888 env->error_code |= POWERPC_EXCP_FP_VXISI;
889 if (fpscr_vxidi)
890 env->error_code |= POWERPC_EXCP_FP_VXIDI;
891 if (fpscr_vxzdz)
892 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
893 if (fpscr_vximz)
894 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
895 if (fpscr_vxvc)
896 env->error_code |= POWERPC_EXCP_FP_VXVC;
897 if (fpscr_vxsoft)
898 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
899 if (fpscr_vxsqrt)
900 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
901 if (fpscr_vxcvi)
902 env->error_code |= POWERPC_EXCP_FP_VXCVI;
903 goto raise_excp;
904 }
905 break;
906 case FPSCR_OE:
907 if (fpscr_ox != 0) {
908 raise_oe:
909 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
910 goto raise_excp;
911 }
912 break;
913 case FPSCR_UE:
914 if (fpscr_ux != 0) {
915 raise_ue:
916 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
917 goto raise_excp;
918 }
919 break;
920 case FPSCR_ZE:
921 if (fpscr_zx != 0) {
922 raise_ze:
923 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
924 goto raise_excp;
925 }
926 break;
927 case FPSCR_XE:
928 if (fpscr_xx != 0) {
929 raise_xe:
930 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
931 goto raise_excp;
932 }
933 break;
934 case FPSCR_RN1:
935 case FPSCR_RN:
936 fpscr_set_rounding_mode();
937 break;
938 default:
939 break;
940 raise_excp:
941 /* Update the floating-point enabled exception summary */
942 env->fpscr |= 1 << FPSCR_FEX;
943 /* We have to update Rc1 before raising the exception */
944 env->exception_index = POWERPC_EXCP_PROGRAM;
945 break;
946 }
947 }
948 }
949
950 void helper_store_fpscr (uint64_t arg, uint32_t mask)
951 {
952 /*
953 * We use only the 32 LSB of the incoming fpr
954 */
955 uint32_t prev, new;
956 int i;
957
958 prev = env->fpscr;
959 new = (uint32_t)arg;
960 new &= ~0x60000000;
961 new |= prev & 0x60000000;
962 for (i = 0; i < 8; i++) {
963 if (mask & (1 << i)) {
964 env->fpscr &= ~(0xF << (4 * i));
965 env->fpscr |= new & (0xF << (4 * i));
966 }
967 }
968 /* Update VX and FEX */
969 if (fpscr_ix != 0)
970 env->fpscr |= 1 << FPSCR_VX;
971 else
972 env->fpscr &= ~(1 << FPSCR_VX);
973 if ((fpscr_ex & fpscr_eex) != 0) {
974 env->fpscr |= 1 << FPSCR_FEX;
975 env->exception_index = POWERPC_EXCP_PROGRAM;
976 /* XXX: we should compute it properly */
977 env->error_code = POWERPC_EXCP_FP;
978 }
979 else
980 env->fpscr &= ~(1 << FPSCR_FEX);
981 fpscr_set_rounding_mode();
982 }
983
984 void helper_float_check_status (void)
985 {
986 #ifdef CONFIG_SOFTFLOAT
987 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
988 (env->error_code & POWERPC_EXCP_FP)) {
989 /* Differred floating-point exception after target FPR update */
990 if (msr_fe0 != 0 || msr_fe1 != 0)
991 helper_raise_exception_err(env->exception_index, env->error_code);
992 } else {
993 int status = get_float_exception_flags(&env->fp_status);
994 if (status & float_flag_overflow) {
995 float_overflow_excp();
996 } else if (status & float_flag_underflow) {
997 float_underflow_excp();
998 } else if (status & float_flag_inexact) {
999 float_inexact_excp();
1000 }
1001 }
1002 #else
1003 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1004 (env->error_code & POWERPC_EXCP_FP)) {
1005 /* Differred floating-point exception after target FPR update */
1006 if (msr_fe0 != 0 || msr_fe1 != 0)
1007 helper_raise_exception_err(env->exception_index, env->error_code);
1008 }
1009 #endif
1010 }
1011
1012 #ifdef CONFIG_SOFTFLOAT
1013 void helper_reset_fpstatus (void)
1014 {
1015 set_float_exception_flags(0, &env->fp_status);
1016 }
1017 #endif
1018
1019 /* fadd - fadd. */
1020 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1021 {
1022 CPU_DoubleU farg1, farg2;
1023
1024 farg1.ll = arg1;
1025 farg2.ll = arg2;
1026 #if USE_PRECISE_EMULATION
1027 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1028 float64_is_signaling_nan(farg2.d))) {
1029 /* sNaN addition */
1030 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1031 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1032 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
1033 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1034 } else {
1035 /* Magnitude subtraction of infinities */
1036 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1037 }
1038 #else
1039 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1040 #endif
1041 return farg1.ll;
1042 }
1043
1044 /* fsub - fsub. */
1045 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1046 {
1047 CPU_DoubleU farg1, farg2;
1048
1049 farg1.ll = arg1;
1050 farg2.ll = arg2;
1051 #if USE_PRECISE_EMULATION
1052 {
1053 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1054 float64_is_signaling_nan(farg2.d))) {
1055 /* sNaN subtraction */
1056 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1057 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1058 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
1059 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1060 } else {
1061 /* Magnitude subtraction of infinities */
1062 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1063 }
1064 }
1065 #else
1066 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1067 #endif
1068 return farg1.ll;
1069 }
1070
1071 /* fmul - fmul. */
1072 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1073 {
1074 CPU_DoubleU farg1, farg2;
1075
1076 farg1.ll = arg1;
1077 farg2.ll = arg2;
1078 #if USE_PRECISE_EMULATION
1079 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1080 float64_is_signaling_nan(farg2.d))) {
1081 /* sNaN multiplication */
1082 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1083 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1084 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1085 /* Multiplication of zero by infinity */
1086 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1087 } else {
1088 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1089 }
1090 #else
1091 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1092 #endif
1093 return farg1.ll;
1094 }
1095
1096 /* fdiv - fdiv. */
1097 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1098 {
1099 CPU_DoubleU farg1, farg2;
1100
1101 farg1.ll = arg1;
1102 farg2.ll = arg2;
1103 #if USE_PRECISE_EMULATION
1104 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1105 float64_is_signaling_nan(farg2.d))) {
1106 /* sNaN division */
1107 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1108 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
1109 /* Division of infinity by infinity */
1110 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1111 } else if (unlikely(!float64_is_nan(farg1.d) && float64_is_zero(farg2.d))) {
1112 if (float64_is_zero(farg1.d)) {
1113 /* Division of zero by zero */
1114 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1115 } else {
1116 /* Division by zero */
1117 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1118 }
1119 } else {
1120 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1121 }
1122 #else
1123 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1124 #endif
1125 return farg1.ll;
1126 }
1127
1128 /* fabs */
1129 uint64_t helper_fabs (uint64_t arg)
1130 {
1131 CPU_DoubleU farg;
1132
1133 farg.ll = arg;
1134 farg.d = float64_abs(farg.d);
1135 return farg.ll;
1136 }
1137
1138 /* fnabs */
1139 uint64_t helper_fnabs (uint64_t arg)
1140 {
1141 CPU_DoubleU farg;
1142
1143 farg.ll = arg;
1144 farg.d = float64_abs(farg.d);
1145 farg.d = float64_chs(farg.d);
1146 return farg.ll;
1147 }
1148
1149 /* fneg */
1150 uint64_t helper_fneg (uint64_t arg)
1151 {
1152 CPU_DoubleU farg;
1153
1154 farg.ll = arg;
1155 farg.d = float64_chs(farg.d);
1156 return farg.ll;
1157 }
1158
1159 /* fctiw - fctiw. */
1160 uint64_t helper_fctiw (uint64_t arg)
1161 {
1162 CPU_DoubleU farg;
1163 farg.ll = arg;
1164
1165 if (unlikely(float64_is_signaling_nan(farg.d))) {
1166 /* sNaN conversion */
1167 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1168 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1169 /* qNan / infinity conversion */
1170 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1171 } else {
1172 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1173 #if USE_PRECISE_EMULATION
1174 /* XXX: higher bits are not supposed to be significant.
1175 * to make tests easier, return the same as a real PowerPC 750
1176 */
1177 farg.ll |= 0xFFF80000ULL << 32;
1178 #endif
1179 }
1180 return farg.ll;
1181 }
1182
1183 /* fctiwz - fctiwz. */
1184 uint64_t helper_fctiwz (uint64_t arg)
1185 {
1186 CPU_DoubleU farg;
1187 farg.ll = arg;
1188
1189 if (unlikely(float64_is_signaling_nan(farg.d))) {
1190 /* sNaN conversion */
1191 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1192 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1193 /* qNan / infinity conversion */
1194 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1195 } else {
1196 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1197 #if USE_PRECISE_EMULATION
1198 /* XXX: higher bits are not supposed to be significant.
1199 * to make tests easier, return the same as a real PowerPC 750
1200 */
1201 farg.ll |= 0xFFF80000ULL << 32;
1202 #endif
1203 }
1204 return farg.ll;
1205 }
1206
1207 #if defined(TARGET_PPC64)
1208 /* fcfid - fcfid. */
1209 uint64_t helper_fcfid (uint64_t arg)
1210 {
1211 CPU_DoubleU farg;
1212 farg.d = int64_to_float64(arg, &env->fp_status);
1213 return farg.ll;
1214 }
1215
1216 /* fctid - fctid. */
1217 uint64_t helper_fctid (uint64_t arg)
1218 {
1219 CPU_DoubleU farg;
1220 farg.ll = arg;
1221
1222 if (unlikely(float64_is_signaling_nan(farg.d))) {
1223 /* sNaN conversion */
1224 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1225 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1226 /* qNan / infinity conversion */
1227 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1228 } else {
1229 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1230 }
1231 return farg.ll;
1232 }
1233
1234 /* fctidz - fctidz. */
1235 uint64_t helper_fctidz (uint64_t arg)
1236 {
1237 CPU_DoubleU farg;
1238 farg.ll = arg;
1239
1240 if (unlikely(float64_is_signaling_nan(farg.d))) {
1241 /* sNaN conversion */
1242 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1243 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1244 /* qNan / infinity conversion */
1245 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1246 } else {
1247 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1248 }
1249 return farg.ll;
1250 }
1251
1252 #endif
1253
1254 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1255 {
1256 CPU_DoubleU farg;
1257 farg.ll = arg;
1258
1259 if (unlikely(float64_is_signaling_nan(farg.d))) {
1260 /* sNaN round */
1261 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1262 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1263 /* qNan / infinity round */
1264 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1265 } else {
1266 set_float_rounding_mode(rounding_mode, &env->fp_status);
1267 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1268 /* Restore rounding mode from FPSCR */
1269 fpscr_set_rounding_mode();
1270 }
1271 return farg.ll;
1272 }
1273
1274 uint64_t helper_frin (uint64_t arg)
1275 {
1276 return do_fri(arg, float_round_nearest_even);
1277 }
1278
1279 uint64_t helper_friz (uint64_t arg)
1280 {
1281 return do_fri(arg, float_round_to_zero);
1282 }
1283
1284 uint64_t helper_frip (uint64_t arg)
1285 {
1286 return do_fri(arg, float_round_up);
1287 }
1288
1289 uint64_t helper_frim (uint64_t arg)
1290 {
1291 return do_fri(arg, float_round_down);
1292 }
1293
1294 /* fmadd - fmadd. */
1295 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1296 {
1297 CPU_DoubleU farg1, farg2, farg3;
1298
1299 farg1.ll = arg1;
1300 farg2.ll = arg2;
1301 farg3.ll = arg3;
1302 #if USE_PRECISE_EMULATION
1303 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1304 float64_is_signaling_nan(farg2.d) ||
1305 float64_is_signaling_nan(farg3.d))) {
1306 /* sNaN operation */
1307 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1308 } else {
1309 #ifdef FLOAT128
1310 /* This is the way the PowerPC specification defines it */
1311 float128 ft0_128, ft1_128;
1312
1313 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1314 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1315 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1316 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1317 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1318 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1319 #else
1320 /* This is OK on x86 hosts */
1321 farg1.d = (farg1.d * farg2.d) + farg3.d;
1322 #endif
1323 }
1324 #else
1325 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1326 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1327 #endif
1328 return farg1.ll;
1329 }
1330
1331 /* fmsub - fmsub. */
1332 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1333 {
1334 CPU_DoubleU farg1, farg2, farg3;
1335
1336 farg1.ll = arg1;
1337 farg2.ll = arg2;
1338 farg3.ll = arg3;
1339 #if USE_PRECISE_EMULATION
1340 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1341 float64_is_signaling_nan(farg2.d) ||
1342 float64_is_signaling_nan(farg3.d))) {
1343 /* sNaN operation */
1344 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1345 } else {
1346 #ifdef FLOAT128
1347 /* This is the way the PowerPC specification defines it */
1348 float128 ft0_128, ft1_128;
1349
1350 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1351 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1352 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1353 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1354 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1355 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1356 #else
1357 /* This is OK on x86 hosts */
1358 farg1.d = (farg1.d * farg2.d) - farg3.d;
1359 #endif
1360 }
1361 #else
1362 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1363 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1364 #endif
1365 return farg1.ll;
1366 }
1367
1368 /* fnmadd - fnmadd. */
1369 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1370 {
1371 CPU_DoubleU farg1, farg2, farg3;
1372
1373 farg1.ll = arg1;
1374 farg2.ll = arg2;
1375 farg3.ll = arg3;
1376
1377 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1378 float64_is_signaling_nan(farg2.d) ||
1379 float64_is_signaling_nan(farg3.d))) {
1380 /* sNaN operation */
1381 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1382 } else {
1383 #if USE_PRECISE_EMULATION
1384 #ifdef FLOAT128
1385 /* This is the way the PowerPC specification defines it */
1386 float128 ft0_128, ft1_128;
1387
1388 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1389 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1390 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1391 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1392 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1393 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1394 #else
1395 /* This is OK on x86 hosts */
1396 farg1.d = (farg1.d * farg2.d) + farg3.d;
1397 #endif
1398 #else
1399 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1400 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1401 #endif
1402 if (likely(!float64_is_nan(farg1.d)))
1403 farg1.d = float64_chs(farg1.d);
1404 }
1405 return farg1.ll;
1406 }
1407
1408 /* fnmsub - fnmsub. */
1409 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1410 {
1411 CPU_DoubleU farg1, farg2, farg3;
1412
1413 farg1.ll = arg1;
1414 farg2.ll = arg2;
1415 farg3.ll = arg3;
1416
1417 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1418 float64_is_signaling_nan(farg2.d) ||
1419 float64_is_signaling_nan(farg3.d))) {
1420 /* sNaN operation */
1421 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1422 } else {
1423 #if USE_PRECISE_EMULATION
1424 #ifdef FLOAT128
1425 /* This is the way the PowerPC specification defines it */
1426 float128 ft0_128, ft1_128;
1427
1428 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1429 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1430 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1431 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1432 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1433 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1434 #else
1435 /* This is OK on x86 hosts */
1436 farg1.d = (farg1.d * farg2.d) - farg3.d;
1437 #endif
1438 #else
1439 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1440 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1441 #endif
1442 if (likely(!float64_is_nan(farg1.d)))
1443 farg1.d = float64_chs(farg1.d);
1444 }
1445 return farg1.ll;
1446 }
1447
1448 /* frsp - frsp. */
1449 uint64_t helper_frsp (uint64_t arg)
1450 {
1451 CPU_DoubleU farg;
1452 float32 f32;
1453 farg.ll = arg;
1454
1455 #if USE_PRECISE_EMULATION
1456 if (unlikely(float64_is_signaling_nan(farg.d))) {
1457 /* sNaN square root */
1458 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1459 } else {
1460 f32 = float64_to_float32(farg.d, &env->fp_status);
1461 farg.d = float32_to_float64(f32, &env->fp_status);
1462 }
1463 #else
1464 f32 = float64_to_float32(farg.d, &env->fp_status);
1465 farg.d = float32_to_float64(f32, &env->fp_status);
1466 #endif
1467 return farg.ll;
1468 }
1469
1470 /* fsqrt - fsqrt. */
1471 uint64_t helper_fsqrt (uint64_t arg)
1472 {
1473 CPU_DoubleU farg;
1474 farg.ll = arg;
1475
1476 if (unlikely(float64_is_signaling_nan(farg.d))) {
1477 /* sNaN square root */
1478 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1479 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1480 /* Square root of a negative nonzero number */
1481 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1482 } else {
1483 farg.d = float64_sqrt(farg.d, &env->fp_status);
1484 }
1485 return farg.ll;
1486 }
1487
1488 /* fre - fre. */
1489 uint64_t helper_fre (uint64_t arg)
1490 {
1491 CPU_DoubleU fone, farg;
1492 fone.ll = 0x3FF0000000000000ULL;
1493 farg.ll = arg;
1494
1495 if (unlikely(float64_is_signaling_nan(farg.d))) {
1496 /* sNaN reciprocal */
1497 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1498 } else if (unlikely(float64_is_zero(farg.d))) {
1499 /* Zero reciprocal */
1500 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1501 } else if (likely(isnormal(farg.d))) {
1502 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1503 } else {
1504 if (farg.ll == 0x8000000000000000ULL) {
1505 farg.ll = 0xFFF0000000000000ULL;
1506 } else if (farg.ll == 0x0000000000000000ULL) {
1507 farg.ll = 0x7FF0000000000000ULL;
1508 } else if (float64_is_nan(farg.d)) {
1509 farg.ll = 0x7FF8000000000000ULL;
1510 } else if (float64_is_neg(farg.d)) {
1511 farg.ll = 0x8000000000000000ULL;
1512 } else {
1513 farg.ll = 0x0000000000000000ULL;
1514 }
1515 }
1516 return farg.d;
1517 }
1518
1519 /* fres - fres. */
1520 uint64_t helper_fres (uint64_t arg)
1521 {
1522 CPU_DoubleU fone, farg;
1523 fone.ll = 0x3FF0000000000000ULL;
1524 farg.ll = arg;
1525
1526 if (unlikely(float64_is_signaling_nan(farg.d))) {
1527 /* sNaN reciprocal */
1528 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1529 } else if (unlikely(float64_is_zero(farg.d))) {
1530 /* Zero reciprocal */
1531 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1532 } else if (likely(isnormal(farg.d))) {
1533 #if USE_PRECISE_EMULATION
1534 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1535 farg.d = float64_to_float32(farg.d, &env->fp_status);
1536 #else
1537 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1538 #endif
1539 } else {
1540 if (farg.ll == 0x8000000000000000ULL) {
1541 farg.ll = 0xFFF0000000000000ULL;
1542 } else if (farg.ll == 0x0000000000000000ULL) {
1543 farg.ll = 0x7FF0000000000000ULL;
1544 } else if (float64_is_nan(farg.d)) {
1545 farg.ll = 0x7FF8000000000000ULL;
1546 } else if (float64_is_neg(farg.d)) {
1547 farg.ll = 0x8000000000000000ULL;
1548 } else {
1549 farg.ll = 0x0000000000000000ULL;
1550 }
1551 }
1552 return farg.ll;
1553 }
1554
1555 /* frsqrte - frsqrte. */
1556 uint64_t helper_frsqrte (uint64_t arg)
1557 {
1558 CPU_DoubleU fone, farg;
1559 fone.ll = 0x3FF0000000000000ULL;
1560 farg.ll = arg;
1561
1562 if (unlikely(float64_is_signaling_nan(farg.d))) {
1563 /* sNaN reciprocal square root */
1564 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1565 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1566 /* Reciprocal square root of a negative nonzero number */
1567 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1568 } else if (likely(isnormal(farg.d))) {
1569 farg.d = float64_sqrt(farg.d, &env->fp_status);
1570 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1571 } else {
1572 if (farg.ll == 0x8000000000000000ULL) {
1573 farg.ll = 0xFFF0000000000000ULL;
1574 } else if (farg.ll == 0x0000000000000000ULL) {
1575 farg.ll = 0x7FF0000000000000ULL;
1576 } else if (float64_is_nan(farg.d)) {
1577 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1578 } else if (float64_is_neg(farg.d)) {
1579 farg.ll = 0x7FF8000000000000ULL;
1580 } else {
1581 farg.ll = 0x0000000000000000ULL;
1582 }
1583 }
1584 return farg.ll;
1585 }
1586
1587 /* fsel - fsel. */
1588 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1589 {
1590 CPU_DoubleU farg1;
1591
1592 farg1.ll = arg1;
1593
1594 if (!float64_is_neg(farg1.d) || float64_is_zero(farg1.d))
1595 return arg2;
1596 else
1597 return arg3;
1598 }
1599
1600 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1601 {
1602 CPU_DoubleU farg1, farg2;
1603 uint32_t ret = 0;
1604 farg1.ll = arg1;
1605 farg2.ll = arg2;
1606
1607 if (unlikely(float64_is_nan(farg1.d) ||
1608 float64_is_nan(farg2.d))) {
1609 ret = 0x01UL;
1610 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1611 ret = 0x08UL;
1612 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1613 ret = 0x04UL;
1614 } else {
1615 ret = 0x02UL;
1616 }
1617
1618 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1619 env->fpscr |= ret << FPSCR_FPRF;
1620 env->crf[crfD] = ret;
1621 if (unlikely(ret == 0x01UL
1622 && (float64_is_signaling_nan(farg1.d) ||
1623 float64_is_signaling_nan(farg2.d)))) {
1624 /* sNaN comparison */
1625 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1626 }
1627 }
1628
1629 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1630 {
1631 CPU_DoubleU farg1, farg2;
1632 uint32_t ret = 0;
1633 farg1.ll = arg1;
1634 farg2.ll = arg2;
1635
1636 if (unlikely(float64_is_nan(farg1.d) ||
1637 float64_is_nan(farg2.d))) {
1638 ret = 0x01UL;
1639 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1640 ret = 0x08UL;
1641 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1642 ret = 0x04UL;
1643 } else {
1644 ret = 0x02UL;
1645 }
1646
1647 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1648 env->fpscr |= ret << FPSCR_FPRF;
1649 env->crf[crfD] = ret;
1650 if (unlikely (ret == 0x01UL)) {
1651 if (float64_is_signaling_nan(farg1.d) ||
1652 float64_is_signaling_nan(farg2.d)) {
1653 /* sNaN comparison */
1654 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1655 POWERPC_EXCP_FP_VXVC);
1656 } else {
1657 /* qNaN comparison */
1658 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1659 }
1660 }
1661 }
1662
1663 #if !defined (CONFIG_USER_ONLY)
1664 void helper_store_msr (target_ulong val)
1665 {
1666 val = hreg_store_msr(env, val, 0);
1667 if (val != 0) {
1668 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1669 helper_raise_exception(val);
1670 }
1671 }
1672
1673 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1674 target_ulong msrm, int keep_msrh)
1675 {
1676 #if defined(TARGET_PPC64)
1677 if (msr & (1ULL << MSR_SF)) {
1678 nip = (uint64_t)nip;
1679 msr &= (uint64_t)msrm;
1680 } else {
1681 nip = (uint32_t)nip;
1682 msr = (uint32_t)(msr & msrm);
1683 if (keep_msrh)
1684 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1685 }
1686 #else
1687 nip = (uint32_t)nip;
1688 msr &= (uint32_t)msrm;
1689 #endif
1690 /* XXX: beware: this is false if VLE is supported */
1691 env->nip = nip & ~((target_ulong)0x00000003);
1692 hreg_store_msr(env, msr, 1);
1693 #if defined (DEBUG_OP)
1694 cpu_dump_rfi(env->nip, env->msr);
1695 #endif
1696 /* No need to raise an exception here,
1697 * as rfi is always the last insn of a TB
1698 */
1699 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1700 }
1701
1702 void helper_rfi (void)
1703 {
1704 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1705 ~((target_ulong)0xFFFF0000), 1);
1706 }
1707
1708 #if defined(TARGET_PPC64)
1709 void helper_rfid (void)
1710 {
1711 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1712 ~((target_ulong)0xFFFF0000), 0);
1713 }
1714
1715 void helper_hrfid (void)
1716 {
1717 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1718 ~((target_ulong)0xFFFF0000), 0);
1719 }
1720 #endif
1721 #endif
1722
1723 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1724 {
1725 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1726 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1727 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1728 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1729 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1730 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1731 }
1732 }
1733
1734 #if defined(TARGET_PPC64)
1735 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1736 {
1737 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1738 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1739 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1740 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1741 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1742 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1743 }
1744 #endif
1745
1746 /*****************************************************************************/
1747 /* PowerPC 601 specific instructions (POWER bridge) */
1748
1749 target_ulong helper_clcs (uint32_t arg)
1750 {
1751 switch (arg) {
1752 case 0x0CUL:
1753 /* Instruction cache line size */
1754 return env->icache_line_size;
1755 break;
1756 case 0x0DUL:
1757 /* Data cache line size */
1758 return env->dcache_line_size;
1759 break;
1760 case 0x0EUL:
1761 /* Minimum cache line size */
1762 return (env->icache_line_size < env->dcache_line_size) ?
1763 env->icache_line_size : env->dcache_line_size;
1764 break;
1765 case 0x0FUL:
1766 /* Maximum cache line size */
1767 return (env->icache_line_size > env->dcache_line_size) ?
1768 env->icache_line_size : env->dcache_line_size;
1769 break;
1770 default:
1771 /* Undefined */
1772 return 0;
1773 break;
1774 }
1775 }
1776
1777 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1778 {
1779 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1780
1781 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1782 (int32_t)arg2 == 0) {
1783 env->spr[SPR_MQ] = 0;
1784 return INT32_MIN;
1785 } else {
1786 env->spr[SPR_MQ] = tmp % arg2;
1787 return tmp / (int32_t)arg2;
1788 }
1789 }
1790
1791 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1792 {
1793 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1794
1795 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1796 (int32_t)arg2 == 0) {
1797 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1798 env->spr[SPR_MQ] = 0;
1799 return INT32_MIN;
1800 } else {
1801 env->spr[SPR_MQ] = tmp % arg2;
1802 tmp /= (int32_t)arg2;
1803 if ((int32_t)tmp != tmp) {
1804 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1805 } else {
1806 env->xer &= ~(1 << XER_OV);
1807 }
1808 return tmp;
1809 }
1810 }
1811
1812 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1813 {
1814 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1815 (int32_t)arg2 == 0) {
1816 env->spr[SPR_MQ] = 0;
1817 return INT32_MIN;
1818 } else {
1819 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1820 return (int32_t)arg1 / (int32_t)arg2;
1821 }
1822 }
1823
1824 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1825 {
1826 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1827 (int32_t)arg2 == 0) {
1828 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1829 env->spr[SPR_MQ] = 0;
1830 return INT32_MIN;
1831 } else {
1832 env->xer &= ~(1 << XER_OV);
1833 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1834 return (int32_t)arg1 / (int32_t)arg2;
1835 }
1836 }
1837
1838 #if !defined (CONFIG_USER_ONLY)
1839 target_ulong helper_rac (target_ulong addr)
1840 {
1841 mmu_ctx_t ctx;
1842 int nb_BATs;
1843 target_ulong ret = 0;
1844
1845 /* We don't have to generate many instances of this instruction,
1846 * as rac is supervisor only.
1847 */
1848 /* XXX: FIX THIS: Pretend we have no BAT */
1849 nb_BATs = env->nb_BATs;
1850 env->nb_BATs = 0;
1851 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1852 ret = ctx.raddr;
1853 env->nb_BATs = nb_BATs;
1854 return ret;
1855 }
1856
1857 void helper_rfsvc (void)
1858 {
1859 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1860 }
1861 #endif
1862
1863 /*****************************************************************************/
1864 /* 602 specific instructions */
1865 /* mfrom is the most crazy instruction ever seen, imho ! */
1866 /* Real implementation uses a ROM table. Do the same */
1867 /* Extremly decomposed:
1868 * -arg / 256
1869 * return 256 * log10(10 + 1.0) + 0.5
1870 */
1871 #if !defined (CONFIG_USER_ONLY)
1872 target_ulong helper_602_mfrom (target_ulong arg)
1873 {
1874 if (likely(arg < 602)) {
1875 #include "mfrom_table.c"
1876 return mfrom_ROM_table[arg];
1877 } else {
1878 return 0;
1879 }
1880 }
1881 #endif
1882
1883 /*****************************************************************************/
1884 /* Embedded PowerPC specific helpers */
1885
1886 /* XXX: to be improved to check access rights when in user-mode */
1887 target_ulong helper_load_dcr (target_ulong dcrn)
1888 {
1889 target_ulong val = 0;
1890
1891 if (unlikely(env->dcr_env == NULL)) {
1892 if (loglevel != 0) {
1893 fprintf(logfile, "No DCR environment\n");
1894 }
1895 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1896 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1897 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1898 if (loglevel != 0) {
1899 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1900 }
1901 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1902 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1903 }
1904 return val;
1905 }
1906
1907 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1908 {
1909 if (unlikely(env->dcr_env == NULL)) {
1910 if (loglevel != 0) {
1911 fprintf(logfile, "No DCR environment\n");
1912 }
1913 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1914 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1915 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1916 if (loglevel != 0) {
1917 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1918 }
1919 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1920 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1921 }
1922 }
1923
1924 #if !defined(CONFIG_USER_ONLY)
1925 void helper_40x_rfci (void)
1926 {
1927 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1928 ~((target_ulong)0xFFFF0000), 0);
1929 }
1930
1931 void helper_rfci (void)
1932 {
1933 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1934 ~((target_ulong)0x3FFF0000), 0);
1935 }
1936
1937 void helper_rfdi (void)
1938 {
1939 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1940 ~((target_ulong)0x3FFF0000), 0);
1941 }
1942
1943 void helper_rfmci (void)
1944 {
1945 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1946 ~((target_ulong)0x3FFF0000), 0);
1947 }
1948 #endif
1949
1950 /* 440 specific */
1951 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1952 {
1953 target_ulong mask;
1954 int i;
1955
1956 i = 1;
1957 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1958 if ((high & mask) == 0) {
1959 if (update_Rc) {
1960 env->crf[0] = 0x4;
1961 }
1962 goto done;
1963 }
1964 i++;
1965 }
1966 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1967 if ((low & mask) == 0) {
1968 if (update_Rc) {
1969 env->crf[0] = 0x8;
1970 }
1971 goto done;
1972 }
1973 i++;
1974 }
1975 if (update_Rc) {
1976 env->crf[0] = 0x2;
1977 }
1978 done:
1979 env->xer = (env->xer & ~0x7F) | i;
1980 if (update_Rc) {
1981 env->crf[0] |= xer_so;
1982 }
1983 return i;
1984 }
1985
1986 /*****************************************************************************/
1987 /* SPE extension helpers */
1988 /* Use a table to make this quicker */
1989 static uint8_t hbrev[16] = {
1990 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1991 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1992 };
1993
1994 static always_inline uint8_t byte_reverse (uint8_t val)
1995 {
1996 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1997 }
1998
1999 static always_inline uint32_t word_reverse (uint32_t val)
2000 {
2001 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2002 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2003 }
2004
2005 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2006 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2007 {
2008 uint32_t a, b, d, mask;
2009
2010 mask = UINT32_MAX >> (32 - MASKBITS);
2011 a = arg1 & mask;
2012 b = arg2 & mask;
2013 d = word_reverse(1 + word_reverse(a | ~b));
2014 return (arg1 & ~mask) | (d & b);
2015 }
2016
2017 uint32_t helper_cntlsw32 (uint32_t val)
2018 {
2019 if (val & 0x80000000)
2020 return clz32(~val);
2021 else
2022 return clz32(val);
2023 }
2024
2025 uint32_t helper_cntlzw32 (uint32_t val)
2026 {
2027 return clz32(val);
2028 }
2029
2030 /* Single-precision floating-point conversions */
2031 static always_inline uint32_t efscfsi (uint32_t val)
2032 {
2033 CPU_FloatU u;
2034
2035 u.f = int32_to_float32(val, &env->spe_status);
2036
2037 return u.l;
2038 }
2039
2040 static always_inline uint32_t efscfui (uint32_t val)
2041 {
2042 CPU_FloatU u;
2043
2044 u.f = uint32_to_float32(val, &env->spe_status);
2045
2046 return u.l;
2047 }
2048
2049 static always_inline int32_t efsctsi (uint32_t val)
2050 {
2051 CPU_FloatU u;
2052
2053 u.l = val;
2054 /* NaN are not treated the same way IEEE 754 does */
2055 if (unlikely(float32_is_nan(u.f)))
2056 return 0;
2057
2058 return float32_to_int32(u.f, &env->spe_status);
2059 }
2060
2061 static always_inline uint32_t efsctui (uint32_t val)
2062 {
2063 CPU_FloatU u;
2064
2065 u.l = val;
2066 /* NaN are not treated the same way IEEE 754 does */
2067 if (unlikely(float32_is_nan(u.f)))
2068 return 0;
2069
2070 return float32_to_uint32(u.f, &env->spe_status);
2071 }
2072
2073 static always_inline uint32_t efsctsiz (uint32_t val)
2074 {
2075 CPU_FloatU u;
2076
2077 u.l = val;
2078 /* NaN are not treated the same way IEEE 754 does */
2079 if (unlikely(float32_is_nan(u.f)))
2080 return 0;
2081
2082 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2083 }
2084
2085 static always_inline uint32_t efsctuiz (uint32_t val)
2086 {
2087 CPU_FloatU u;
2088
2089 u.l = val;
2090 /* NaN are not treated the same way IEEE 754 does */
2091 if (unlikely(float32_is_nan(u.f)))
2092 return 0;
2093
2094 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2095 }
2096
2097 static always_inline uint32_t efscfsf (uint32_t val)
2098 {
2099 CPU_FloatU u;
2100 float32 tmp;
2101
2102 u.f = int32_to_float32(val, &env->spe_status);
2103 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2104 u.f = float32_div(u.f, tmp, &env->spe_status);
2105
2106 return u.l;
2107 }
2108
2109 static always_inline uint32_t efscfuf (uint32_t val)
2110 {
2111 CPU_FloatU u;
2112 float32 tmp;
2113
2114 u.f = uint32_to_float32(val, &env->spe_status);
2115 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2116 u.f = float32_div(u.f, tmp, &env->spe_status);
2117
2118 return u.l;
2119 }
2120
2121 static always_inline uint32_t efsctsf (uint32_t val)
2122 {
2123 CPU_FloatU u;
2124 float32 tmp;
2125
2126 u.l = val;
2127 /* NaN are not treated the same way IEEE 754 does */
2128 if (unlikely(float32_is_nan(u.f)))
2129 return 0;
2130 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2131 u.f = float32_mul(u.f, tmp, &env->spe_status);
2132
2133 return float32_to_int32(u.f, &env->spe_status);
2134 }
2135
2136 static always_inline uint32_t efsctuf (uint32_t val)
2137 {
2138 CPU_FloatU u;
2139 float32 tmp;
2140
2141 u.l = val;
2142 /* NaN are not treated the same way IEEE 754 does */
2143 if (unlikely(float32_is_nan(u.f)))
2144 return 0;
2145 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2146 u.f = float32_mul(u.f, tmp, &env->spe_status);
2147
2148 return float32_to_uint32(u.f, &env->spe_status);
2149 }
2150
2151 #define HELPER_SPE_SINGLE_CONV(name) \
2152 uint32_t helper_e##name (uint32_t val) \
2153 { \
2154 return e##name(val); \
2155 }
2156 /* efscfsi */
2157 HELPER_SPE_SINGLE_CONV(fscfsi);
2158 /* efscfui */
2159 HELPER_SPE_SINGLE_CONV(fscfui);
2160 /* efscfuf */
2161 HELPER_SPE_SINGLE_CONV(fscfuf);
2162 /* efscfsf */
2163 HELPER_SPE_SINGLE_CONV(fscfsf);
2164 /* efsctsi */
2165 HELPER_SPE_SINGLE_CONV(fsctsi);
2166 /* efsctui */
2167 HELPER_SPE_SINGLE_CONV(fsctui);
2168 /* efsctsiz */
2169 HELPER_SPE_SINGLE_CONV(fsctsiz);
2170 /* efsctuiz */
2171 HELPER_SPE_SINGLE_CONV(fsctuiz);
2172 /* efsctsf */
2173 HELPER_SPE_SINGLE_CONV(fsctsf);
2174 /* efsctuf */
2175 HELPER_SPE_SINGLE_CONV(fsctuf);
2176
2177 #define HELPER_SPE_VECTOR_CONV(name) \
2178 uint64_t helper_ev##name (uint64_t val) \
2179 { \
2180 return ((uint64_t)e##name(val >> 32) << 32) | \
2181 (uint64_t)e##name(val); \
2182 }
2183 /* evfscfsi */
2184 HELPER_SPE_VECTOR_CONV(fscfsi);
2185 /* evfscfui */
2186 HELPER_SPE_VECTOR_CONV(fscfui);
2187 /* evfscfuf */
2188 HELPER_SPE_VECTOR_CONV(fscfuf);
2189 /* evfscfsf */
2190 HELPER_SPE_VECTOR_CONV(fscfsf);
2191 /* evfsctsi */
2192 HELPER_SPE_VECTOR_CONV(fsctsi);
2193 /* evfsctui */
2194 HELPER_SPE_VECTOR_CONV(fsctui);
2195 /* evfsctsiz */
2196 HELPER_SPE_VECTOR_CONV(fsctsiz);
2197 /* evfsctuiz */
2198 HELPER_SPE_VECTOR_CONV(fsctuiz);
2199 /* evfsctsf */
2200 HELPER_SPE_VECTOR_CONV(fsctsf);
2201 /* evfsctuf */
2202 HELPER_SPE_VECTOR_CONV(fsctuf);
2203
2204 /* Single-precision floating-point arithmetic */
2205 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2206 {
2207 CPU_FloatU u1, u2;
2208 u1.l = op1;
2209 u2.l = op2;
2210 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2211 return u1.l;
2212 }
2213
2214 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2215 {
2216 CPU_FloatU u1, u2;
2217 u1.l = op1;
2218 u2.l = op2;
2219 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2220 return u1.l;
2221 }
2222
2223 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2224 {
2225 CPU_FloatU u1, u2;
2226 u1.l = op1;
2227 u2.l = op2;
2228 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2229 return u1.l;
2230 }
2231
2232 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2233 {
2234 CPU_FloatU u1, u2;
2235 u1.l = op1;
2236 u2.l = op2;
2237 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2238 return u1.l;
2239 }
2240
2241 #define HELPER_SPE_SINGLE_ARITH(name) \
2242 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2243 { \
2244 return e##name(op1, op2); \
2245 }
2246 /* efsadd */
2247 HELPER_SPE_SINGLE_ARITH(fsadd);
2248 /* efssub */
2249 HELPER_SPE_SINGLE_ARITH(fssub);
2250 /* efsmul */
2251 HELPER_SPE_SINGLE_ARITH(fsmul);
2252 /* efsdiv */
2253 HELPER_SPE_SINGLE_ARITH(fsdiv);
2254
2255 #define HELPER_SPE_VECTOR_ARITH(name) \
2256 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2257 { \
2258 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2259 (uint64_t)e##name(op1, op2); \
2260 }
2261 /* evfsadd */
2262 HELPER_SPE_VECTOR_ARITH(fsadd);
2263 /* evfssub */
2264 HELPER_SPE_VECTOR_ARITH(fssub);
2265 /* evfsmul */
2266 HELPER_SPE_VECTOR_ARITH(fsmul);
2267 /* evfsdiv */
2268 HELPER_SPE_VECTOR_ARITH(fsdiv);
2269
2270 /* Single-precision floating-point comparisons */
2271 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2272 {
2273 CPU_FloatU u1, u2;
2274 u1.l = op1;
2275 u2.l = op2;
2276 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2277 }
2278
2279 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2280 {
2281 CPU_FloatU u1, u2;
2282 u1.l = op1;
2283 u2.l = op2;
2284 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2285 }
2286
2287 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2288 {
2289 CPU_FloatU u1, u2;
2290 u1.l = op1;
2291 u2.l = op2;
2292 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2293 }
2294
2295 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2296 {
2297 /* XXX: TODO: test special values (NaN, infinites, ...) */
2298 return efststlt(op1, op2);
2299 }
2300
2301 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2302 {
2303 /* XXX: TODO: test special values (NaN, infinites, ...) */
2304 return efststgt(op1, op2);
2305 }
2306
2307 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2308 {
2309 /* XXX: TODO: test special values (NaN, infinites, ...) */
2310 return efststeq(op1, op2);
2311 }
2312
2313 #define HELPER_SINGLE_SPE_CMP(name) \
2314 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2315 { \
2316 return e##name(op1, op2) << 2; \
2317 }
2318 /* efststlt */
2319 HELPER_SINGLE_SPE_CMP(fststlt);
2320 /* efststgt */
2321 HELPER_SINGLE_SPE_CMP(fststgt);
2322 /* efststeq */
2323 HELPER_SINGLE_SPE_CMP(fststeq);
2324 /* efscmplt */
2325 HELPER_SINGLE_SPE_CMP(fscmplt);
2326 /* efscmpgt */
2327 HELPER_SINGLE_SPE_CMP(fscmpgt);
2328 /* efscmpeq */
2329 HELPER_SINGLE_SPE_CMP(fscmpeq);
2330
2331 static always_inline uint32_t evcmp_merge (int t0, int t1)
2332 {
2333 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2334 }
2335
2336 #define HELPER_VECTOR_SPE_CMP(name) \
2337 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2338 { \
2339 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2340 }
2341 /* evfststlt */
2342 HELPER_VECTOR_SPE_CMP(fststlt);
2343 /* evfststgt */
2344 HELPER_VECTOR_SPE_CMP(fststgt);
2345 /* evfststeq */
2346 HELPER_VECTOR_SPE_CMP(fststeq);
2347 /* evfscmplt */
2348 HELPER_VECTOR_SPE_CMP(fscmplt);
2349 /* evfscmpgt */
2350 HELPER_VECTOR_SPE_CMP(fscmpgt);
2351 /* evfscmpeq */
2352 HELPER_VECTOR_SPE_CMP(fscmpeq);
2353
2354 /* Double-precision floating-point conversion */
2355 uint64_t helper_efdcfsi (uint32_t val)
2356 {
2357 CPU_DoubleU u;
2358
2359 u.d = int32_to_float64(val, &env->spe_status);
2360
2361 return u.ll;
2362 }
2363
2364 uint64_t helper_efdcfsid (uint64_t val)
2365 {
2366 CPU_DoubleU u;
2367
2368 u.d = int64_to_float64(val, &env->spe_status);
2369
2370 return u.ll;
2371 }
2372
2373 uint64_t helper_efdcfui (uint32_t val)
2374 {
2375 CPU_DoubleU u;
2376
2377 u.d = uint32_to_float64(val, &env->spe_status);
2378
2379 return u.ll;
2380 }
2381
2382 uint64_t helper_efdcfuid (uint64_t val)
2383 {
2384 CPU_DoubleU u;
2385
2386 u.d = uint64_to_float64(val, &env->spe_status);
2387
2388 return u.ll;
2389 }
2390
2391 uint32_t helper_efdctsi (uint64_t val)
2392 {
2393 CPU_DoubleU u;
2394
2395 u.ll = val;
2396 /* NaN are not treated the same way IEEE 754 does */
2397 if (unlikely(float64_is_nan(u.d)))
2398 return 0;
2399
2400 return float64_to_int32(u.d, &env->spe_status);
2401 }
2402
2403 uint32_t helper_efdctui (uint64_t val)
2404 {
2405 CPU_DoubleU u;
2406
2407 u.ll = val;
2408 /* NaN are not treated the same way IEEE 754 does */
2409 if (unlikely(float64_is_nan(u.d)))
2410 return 0;
2411
2412 return float64_to_uint32(u.d, &env->spe_status);
2413 }
2414
2415 uint32_t helper_efdctsiz (uint64_t val)
2416 {
2417 CPU_DoubleU u;
2418
2419 u.ll = val;
2420 /* NaN are not treated the same way IEEE 754 does */
2421 if (unlikely(float64_is_nan(u.d)))
2422 return 0;
2423
2424 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2425 }
2426
2427 uint64_t helper_efdctsidz (uint64_t val)
2428 {
2429 CPU_DoubleU u;
2430
2431 u.ll = val;
2432 /* NaN are not treated the same way IEEE 754 does */
2433 if (unlikely(float64_is_nan(u.d)))
2434 return 0;
2435
2436 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2437 }
2438
2439 uint32_t helper_efdctuiz (uint64_t val)
2440 {
2441 CPU_DoubleU u;
2442
2443 u.ll = val;
2444 /* NaN are not treated the same way IEEE 754 does */
2445 if (unlikely(float64_is_nan(u.d)))
2446 return 0;
2447
2448 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2449 }
2450
2451 uint64_t helper_efdctuidz (uint64_t val)
2452 {
2453 CPU_DoubleU u;
2454
2455 u.ll = val;
2456 /* NaN are not treated the same way IEEE 754 does */
2457 if (unlikely(float64_is_nan(u.d)))
2458 return 0;
2459
2460 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2461 }
2462
2463 uint64_t helper_efdcfsf (uint32_t val)
2464 {
2465 CPU_DoubleU u;
2466 float64 tmp;
2467
2468 u.d = int32_to_float64(val, &env->spe_status);
2469 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2470 u.d = float64_div(u.d, tmp, &env->spe_status);
2471
2472 return u.ll;
2473 }
2474
2475 uint64_t helper_efdcfuf (uint32_t val)
2476 {
2477 CPU_DoubleU u;
2478 float64 tmp;
2479
2480 u.d = uint32_to_float64(val, &env->spe_status);
2481 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2482 u.d = float64_div(u.d, tmp, &env->spe_status);
2483
2484 return u.ll;
2485 }
2486
2487 uint32_t helper_efdctsf (uint64_t val)
2488 {
2489 CPU_DoubleU u;
2490 float64 tmp;
2491
2492 u.ll = val;
2493 /* NaN are not treated the same way IEEE 754 does */
2494 if (unlikely(float64_is_nan(u.d)))
2495 return 0;
2496 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2497 u.d = float64_mul(u.d, tmp, &env->spe_status);
2498
2499 return float64_to_int32(u.d, &env->spe_status);
2500 }
2501
2502 uint32_t helper_efdctuf (uint64_t val)
2503 {
2504 CPU_DoubleU u;
2505 float64 tmp;
2506
2507 u.ll = val;
2508 /* NaN are not treated the same way IEEE 754 does */
2509 if (unlikely(float64_is_nan(u.d)))
2510 return 0;
2511 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2512 u.d = float64_mul(u.d, tmp, &env->spe_status);
2513
2514 return float64_to_uint32(u.d, &env->spe_status);
2515 }
2516
2517 uint32_t helper_efscfd (uint64_t val)
2518 {
2519 CPU_DoubleU u1;
2520 CPU_FloatU u2;
2521
2522 u1.ll = val;
2523 u2.f = float64_to_float32(u1.d, &env->spe_status);
2524
2525 return u2.l;
2526 }
2527
2528 uint64_t helper_efdcfs (uint32_t val)
2529 {
2530 CPU_DoubleU u2;
2531 CPU_FloatU u1;
2532
2533 u1.l = val;
2534 u2.d = float32_to_float64(u1.f, &env->spe_status);
2535
2536 return u2.ll;
2537 }
2538
2539 /* Double precision fixed-point arithmetic */
2540 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2541 {
2542 CPU_DoubleU u1, u2;
2543 u1.ll = op1;
2544 u2.ll = op2;
2545 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2546 return u1.ll;
2547 }
2548
2549 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2550 {
2551 CPU_DoubleU u1, u2;
2552 u1.ll = op1;
2553 u2.ll = op2;
2554 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2555 return u1.ll;
2556 }
2557
2558 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2559 {
2560 CPU_DoubleU u1, u2;
2561 u1.ll = op1;
2562 u2.ll = op2;
2563 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2564 return u1.ll;
2565 }
2566
2567 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2568 {
2569 CPU_DoubleU u1, u2;
2570 u1.ll = op1;
2571 u2.ll = op2;
2572 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2573 return u1.ll;
2574 }
2575
2576 /* Double precision floating point helpers */
2577 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2578 {
2579 CPU_DoubleU u1, u2;
2580 u1.ll = op1;
2581 u2.ll = op2;
2582 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2583 }
2584
2585 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2586 {
2587 CPU_DoubleU u1, u2;
2588 u1.ll = op1;
2589 u2.ll = op2;
2590 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2591 }
2592
2593 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2594 {
2595 CPU_DoubleU u1, u2;
2596 u1.ll = op1;
2597 u2.ll = op2;
2598 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2599 }
2600
2601 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2602 {
2603 /* XXX: TODO: test special values (NaN, infinites, ...) */
2604 return helper_efdtstlt(op1, op2);
2605 }
2606
2607 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2608 {
2609 /* XXX: TODO: test special values (NaN, infinites, ...) */
2610 return helper_efdtstgt(op1, op2);
2611 }
2612
2613 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2614 {
2615 /* XXX: TODO: test special values (NaN, infinites, ...) */
2616 return helper_efdtsteq(op1, op2);
2617 }
2618
2619 /*****************************************************************************/
2620 /* Softmmu support */
2621 #if !defined (CONFIG_USER_ONLY)
2622
2623 #define MMUSUFFIX _mmu
2624
2625 #define SHIFT 0
2626 #include "softmmu_template.h"
2627
2628 #define SHIFT 1
2629 #include "softmmu_template.h"
2630
2631 #define SHIFT 2
2632 #include "softmmu_template.h"
2633
2634 #define SHIFT 3
2635 #include "softmmu_template.h"
2636
2637 /* try to fill the TLB and return an exception if error. If retaddr is
2638 NULL, it means that the function was called in C code (i.e. not
2639 from generated code or from helper.c) */
2640 /* XXX: fix it to restore all registers */
2641 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2642 {
2643 TranslationBlock *tb;
2644 CPUState *saved_env;
2645 unsigned long pc;
2646 int ret;
2647
2648 /* XXX: hack to restore env in all cases, even if not called from
2649 generated code */
2650 saved_env = env;
2651 env = cpu_single_env;
2652 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2653 if (unlikely(ret != 0)) {
2654 if (likely(retaddr)) {
2655 /* now we have a real cpu fault */
2656 pc = (unsigned long)retaddr;
2657 tb = tb_find_pc(pc);
2658 if (likely(tb)) {
2659 /* the PC is inside the translated code. It means that we have
2660 a virtual CPU fault */
2661 cpu_restore_state(tb, env, pc, NULL);
2662 }
2663 }
2664 helper_raise_exception_err(env->exception_index, env->error_code);
2665 }
2666 env = saved_env;
2667 }
2668
2669 /* Segment registers load and store */
2670 target_ulong helper_load_sr (target_ulong sr_num)
2671 {
2672 return env->sr[sr_num];
2673 }
2674
2675 void helper_store_sr (target_ulong sr_num, target_ulong val)
2676 {
2677 ppc_store_sr(env, sr_num, val);
2678 }
2679
2680 /* SLB management */
2681 #if defined(TARGET_PPC64)
2682 target_ulong helper_load_slb (target_ulong slb_nr)
2683 {
2684 return ppc_load_slb(env, slb_nr);
2685 }
2686
2687 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2688 {
2689 ppc_store_slb(env, slb_nr, rs);
2690 }
2691
2692 void helper_slbia (void)
2693 {
2694 ppc_slb_invalidate_all(env);
2695 }
2696
2697 void helper_slbie (target_ulong addr)
2698 {
2699 ppc_slb_invalidate_one(env, addr);
2700 }
2701
2702 #endif /* defined(TARGET_PPC64) */
2703
2704 /* TLB management */
2705 void helper_tlbia (void)
2706 {
2707 ppc_tlb_invalidate_all(env);
2708 }
2709
2710 void helper_tlbie (target_ulong addr)
2711 {
2712 ppc_tlb_invalidate_one(env, addr);
2713 }
2714
2715 /* Software driven TLBs management */
2716 /* PowerPC 602/603 software TLB load instructions helpers */
2717 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2718 {
2719 target_ulong RPN, CMP, EPN;
2720 int way;
2721
2722 RPN = env->spr[SPR_RPA];
2723 if (is_code) {
2724 CMP = env->spr[SPR_ICMP];
2725 EPN = env->spr[SPR_IMISS];
2726 } else {
2727 CMP = env->spr[SPR_DCMP];
2728 EPN = env->spr[SPR_DMISS];
2729 }
2730 way = (env->spr[SPR_SRR1] >> 17) & 1;
2731 #if defined (DEBUG_SOFTWARE_TLB)
2732 if (loglevel != 0) {
2733 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2734 " PTE1 " ADDRX " way %d\n",
2735 __func__, new_EPN, EPN, CMP, RPN, way);
2736 }
2737 #endif
2738 /* Store this TLB */
2739 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2740 way, is_code, CMP, RPN);
2741 }
2742
2743 void helper_6xx_tlbd (target_ulong EPN)
2744 {
2745 do_6xx_tlb(EPN, 0);
2746 }
2747
2748 void helper_6xx_tlbi (target_ulong EPN)
2749 {
2750 do_6xx_tlb(EPN, 1);
2751 }
2752
2753 /* PowerPC 74xx software TLB load instructions helpers */
2754 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2755 {
2756 target_ulong RPN, CMP, EPN;
2757 int way;
2758
2759 RPN = env->spr[SPR_PTELO];
2760 CMP = env->spr[SPR_PTEHI];
2761 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2762 way = env->spr[SPR_TLBMISS] & 0x3;
2763 #if defined (DEBUG_SOFTWARE_TLB)
2764 if (loglevel != 0) {
2765 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2766 " PTE1 " ADDRX " way %d\n",
2767 __func__, new_EPN, EPN, CMP, RPN, way);
2768 }
2769 #endif
2770 /* Store this TLB */
2771 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2772 way, is_code, CMP, RPN);
2773 }
2774
2775 void helper_74xx_tlbd (target_ulong EPN)
2776 {
2777 do_74xx_tlb(EPN, 0);
2778 }
2779
2780 void helper_74xx_tlbi (target_ulong EPN)
2781 {
2782 do_74xx_tlb(EPN, 1);
2783 }
2784
2785 static always_inline target_ulong booke_tlb_to_page_size (int size)
2786 {
2787 return 1024 << (2 * size);
2788 }
2789
2790 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2791 {
2792 int size;
2793
2794 switch (page_size) {
2795 case 0x00000400UL:
2796 size = 0x0;
2797 break;
2798 case 0x00001000UL:
2799 size = 0x1;
2800 break;
2801 case 0x00004000UL:
2802 size = 0x2;
2803 break;
2804 case 0x00010000UL:
2805 size = 0x3;
2806 break;
2807 case 0x00040000UL:
2808 size = 0x4;
2809 break;
2810 case 0x00100000UL:
2811 size = 0x5;
2812 break;
2813 case 0x00400000UL:
2814 size = 0x6;
2815 break;
2816 case 0x01000000UL:
2817 size = 0x7;
2818 break;
2819 case 0x04000000UL:
2820 size = 0x8;
2821 break;
2822 case 0x10000000UL:
2823 size = 0x9;
2824 break;
2825 case 0x40000000UL:
2826 size = 0xA;
2827 break;
2828 #if defined (TARGET_PPC64)
2829 case 0x000100000000ULL:
2830 size = 0xB;
2831 break;
2832 case 0x000400000000ULL:
2833 size = 0xC;
2834 break;
2835 case 0x001000000000ULL:
2836 size = 0xD;
2837 break;
2838 case 0x004000000000ULL:
2839 size = 0xE;
2840 break;
2841 case 0x010000000000ULL:
2842 size = 0xF;
2843 break;
2844 #endif
2845 default:
2846 size = -1;
2847 break;
2848 }
2849
2850 return size;
2851 }
2852
2853 /* Helpers for 4xx TLB management */
2854 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2855 {
2856 ppcemb_tlb_t *tlb;
2857 target_ulong ret;
2858 int size;
2859
2860 entry &= 0x3F;
2861 tlb = &env->tlb[entry].tlbe;
2862 ret = tlb->EPN;
2863 if (tlb->prot & PAGE_VALID)
2864 ret |= 0x400;
2865 size = booke_page_size_to_tlb(tlb->size);
2866 if (size < 0 || size > 0x7)
2867 size = 1;
2868 ret |= size << 7;
2869 env->spr[SPR_40x_PID] = tlb->PID;
2870 return ret;
2871 }
2872
2873 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2874 {
2875 ppcemb_tlb_t *tlb;
2876 target_ulong ret;
2877
2878 entry &= 0x3F;
2879 tlb = &env->tlb[entry].tlbe;
2880 ret = tlb->RPN;
2881 if (tlb->prot & PAGE_EXEC)
2882 ret |= 0x200;
2883 if (tlb->prot & PAGE_WRITE)
2884 ret |= 0x100;
2885 return ret;
2886 }
2887
2888 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2889 {
2890 ppcemb_tlb_t *tlb;
2891 target_ulong page, end;
2892
2893 #if defined (DEBUG_SOFTWARE_TLB)
2894 if (loglevel != 0) {
2895 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2896 }
2897 #endif
2898 entry &= 0x3F;
2899 tlb = &env->tlb[entry].tlbe;
2900 /* Invalidate previous TLB (if it's valid) */
2901 if (tlb->prot & PAGE_VALID) {
2902 end = tlb->EPN + tlb->size;
2903 #if defined (DEBUG_SOFTWARE_TLB)
2904 if (loglevel != 0) {
2905 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2906 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2907 }
2908 #endif
2909 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2910 tlb_flush_page(env, page);
2911 }
2912 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2913 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2914 * If this ever occurs, one should use the ppcemb target instead
2915 * of the ppc or ppc64 one
2916 */
2917 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2918 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2919 "are not supported (%d)\n",
2920 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2921 }
2922 tlb->EPN = val & ~(tlb->size - 1);
2923 if (val & 0x40)
2924 tlb->prot |= PAGE_VALID;
2925 else
2926 tlb->prot &= ~PAGE_VALID;
2927 if (val & 0x20) {
2928 /* XXX: TO BE FIXED */
2929 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2930 }
2931 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2932 tlb->attr = val & 0xFF;
2933 #if defined (DEBUG_SOFTWARE_TLB)
2934 if (loglevel != 0) {
2935 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2936 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2937 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2938 tlb->prot & PAGE_READ ? 'r' : '-',
2939 tlb->prot & PAGE_WRITE ? 'w' : '-',
2940 tlb->prot & PAGE_EXEC ? 'x' : '-',
2941 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2942 }
2943 #endif
2944 /* Invalidate new TLB (if valid) */
2945 if (tlb->prot & PAGE_VALID) {
2946 end = tlb->EPN + tlb->size;
2947 #if defined (DEBUG_SOFTWARE_TLB)
2948 if (loglevel != 0) {
2949 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2950 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2951 }
2952 #endif
2953 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2954 tlb_flush_page(env, page);
2955 }
2956 }
2957
2958 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2959 {
2960 ppcemb_tlb_t *tlb;
2961
2962 #if defined (DEBUG_SOFTWARE_TLB)
2963 if (loglevel != 0) {
2964 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2965 }
2966 #endif
2967 entry &= 0x3F;
2968 tlb = &env->tlb[entry].tlbe;
2969 tlb->RPN = val & 0xFFFFFC00;
2970 tlb->prot = PAGE_READ;
2971 if (val & 0x200)
2972 tlb->prot |= PAGE_EXEC;
2973 if (val & 0x100)
2974 tlb->prot |= PAGE_WRITE;
2975 #if defined (DEBUG_SOFTWARE_TLB)
2976 if (loglevel != 0) {
2977 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2978 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2979 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2980 tlb->prot & PAGE_READ ? 'r' : '-',
2981 tlb->prot & PAGE_WRITE ? 'w' : '-',
2982 tlb->prot & PAGE_EXEC ? 'x' : '-',
2983 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2984 }
2985 #endif
2986 }
2987
2988 target_ulong helper_4xx_tlbsx (target_ulong address)
2989 {
2990 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
2991 }
2992
2993 /* PowerPC 440 TLB management */
2994 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
2995 {
2996 ppcemb_tlb_t *tlb;
2997 target_ulong EPN, RPN, size;
2998 int do_flush_tlbs;
2999
3000 #if defined (DEBUG_SOFTWARE_TLB)
3001 if (loglevel != 0) {
3002 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3003 __func__, word, (int)entry, value);
3004 }
3005 #endif
3006 do_flush_tlbs = 0;
3007 entry &= 0x3F;
3008 tlb = &env->tlb[entry].tlbe;
3009 switch (word) {
3010 default:
3011 /* Just here to please gcc */
3012 case 0:
3013 EPN = value & 0xFFFFFC00;
3014 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3015 do_flush_tlbs = 1;
3016 tlb->EPN = EPN;
3017 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3018 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3019 do_flush_tlbs = 1;
3020 tlb->size = size;
3021 tlb->attr &= ~0x1;
3022 tlb->attr |= (value >> 8) & 1;
3023 if (value & 0x200) {
3024 tlb->prot |= PAGE_VALID;
3025 } else {
3026 if (tlb->prot & PAGE_VALID) {
3027 tlb->prot &= ~PAGE_VALID;
3028 do_flush_tlbs = 1;
3029 }
3030 }
3031 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3032 if (do_flush_tlbs)
3033 tlb_flush(env, 1);
3034 break;
3035 case 1:
3036 RPN = value & 0xFFFFFC0F;
3037 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3038 tlb_flush(env, 1);
3039 tlb->RPN = RPN;
3040 break;
3041 case 2:
3042 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3043 tlb->prot = tlb->prot & PAGE_VALID;
3044 if (value & 0x1)
3045 tlb->prot |= PAGE_READ << 4;
3046 if (value & 0x2)
3047 tlb->prot |= PAGE_WRITE << 4;
3048 if (value & 0x4)
3049 tlb->prot |= PAGE_EXEC << 4;
3050 if (value & 0x8)
3051 tlb->prot |= PAGE_READ;
3052 if (value & 0x10)
3053 tlb->prot |= PAGE_WRITE;
3054 if (value & 0x20)
3055 tlb->prot |= PAGE_EXEC;
3056 break;
3057 }
3058 }
3059
3060 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3061 {
3062 ppcemb_tlb_t *tlb;
3063 target_ulong ret;
3064 int size;
3065
3066 entry &= 0x3F;
3067 tlb = &env->tlb[entry].tlbe;
3068 switch (word) {
3069 default:
3070 /* Just here to please gcc */
3071 case 0:
3072 ret = tlb->EPN;
3073 size = booke_page_size_to_tlb(tlb->size);
3074 if (size < 0 || size > 0xF)
3075 size = 1;
3076 ret |= size << 4;
3077 if (tlb->attr & 0x1)
3078 ret |= 0x100;
3079 if (tlb->prot & PAGE_VALID)
3080 ret |= 0x200;
3081 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3082 env->spr[SPR_440_MMUCR] |= tlb->PID;
3083 break;
3084 case 1:
3085 ret = tlb->RPN;
3086 break;
3087 case 2:
3088 ret = tlb->attr & ~0x1;
3089 if (tlb->prot & (PAGE_READ << 4))
3090 ret |= 0x1;
3091 if (tlb->prot & (PAGE_WRITE << 4))
3092 ret |= 0x2;
3093 if (tlb->prot & (PAGE_EXEC << 4))
3094 ret |= 0x4;
3095 if (tlb->prot & PAGE_READ)
3096 ret |= 0x8;
3097 if (tlb->prot & PAGE_WRITE)
3098 ret |= 0x10;
3099 if (tlb->prot & PAGE_EXEC)
3100 ret |= 0x20;
3101 break;
3102 }
3103 return ret;
3104 }
3105
3106 target_ulong helper_440_tlbsx (target_ulong address)
3107 {
3108 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3109 }
3110
3111 #endif /* !CONFIG_USER_ONLY */