target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  41 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  42
  43 #define ARMV7M_EXCP_RESET   1
  44 #define ARMV7M_EXCP_NMI     2
  45 #define ARMV7M_EXCP_HARD    3
  46 #define ARMV7M_EXCP_MEM     4
  47 #define ARMV7M_EXCP_BUS     5
  48 #define ARMV7M_EXCP_USAGE   6
  49 #define ARMV7M_EXCP_SVC     11
  50 #define ARMV7M_EXCP_DEBUG   12
  51 #define ARMV7M_EXCP_PENDSV  14
  52 #define ARMV7M_EXCP_SYSTICK 15
  53
  54 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  55                             int srcreg, int operand, uint32_t value);
  56 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  57                                int dstreg, int operand);
  58
  59 struct arm_boot_info;
  60
  61 #define NB_MMU_MODES 2
  62
  63 /* We currently assume float and double are IEEE single and double
  64    precision respectively.
  65    Doing runtime conversions is tricky because VFP registers may contain
  66    integer values (eg. as the result of a FTOSI instruction).
  67    s<2n> maps to the least significant half of d<n>
  68    s<2n+1> maps to the most significant half of d<n>
  69  */
  70
  71 typedef struct CPUARMState {
  72     /* Regs for current mode.  */
  73     uint32_t regs[16];
  74     /* Frequently accessed CPSR bits are stored separately for efficiently.
  75        This contains all the other bits.  Use cpsr_{read,write} to access
  76        the whole CPSR.  */
  77     uint32_t uncached_cpsr;
  78     uint32_t spsr;
  79
  80     /* Banked registers.  */
  81     uint32_t banked_spsr[6];
  82     uint32_t banked_r13[6];
  83     uint32_t banked_r14[6];
  84
  85     /* These hold r8-r12.  */
  86     uint32_t usr_regs[5];
  87     uint32_t fiq_regs[5];
  88
  89     /* cpsr flag cache for faster execution */
  90     uint32_t CF; /* 0 or 1 */
  91     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  92     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
  93     uint32_t ZF; /* Z set if zero.  */
  94     uint32_t QF; /* 0 or 1 */
  95     uint32_t GE; /* cpsr[19:16] */
  96     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
  97     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
  98
  99     /* System control coprocessor (cp15) */
 100     struct {
 101         uint32_t c0_cpuid;
 102         uint32_t c0_cachetype;
 103         uint32_t c0_c1[8]; /* Feature registers.  */
 104         uint32_t c0_c2[8]; /* Instruction set registers.  */
 105         uint32_t c1_sys; /* System control register.  */
 106         uint32_t c1_coproc; /* Coprocessor access register.  */
 107         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 108         uint32_t c2_base0; /* MMU translation table base 0.  */
 109         uint32_t c2_base1; /* MMU translation table base 1.  */
 110         uint32_t c2_mask; /* MMU translation table base mask.  */
 111         uint32_t c2_data; /* MPU data cachable bits.  */
 112         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 113         uint32_t c3; /* MMU domain access control register
 114                         MPU write buffer control.  */
 115         uint32_t c5_insn; /* Fault status registers.  */
 116         uint32_t c5_data;
 117         uint32_t c6_region[8]; /* MPU base/size registers.  */
 118         uint32_t c6_insn; /* Fault address registers.  */
 119         uint32_t c6_data;
 120         uint32_t c9_insn; /* Cache lockdown registers.  */
 121         uint32_t c9_data;
 122         uint32_t c13_fcse; /* FCSE PID.  */
 123         uint32_t c13_context; /* Context ID.  */
 124         uint32_t c13_tls1; /* User RW Thread register.  */
 125         uint32_t c13_tls2; /* User RO Thread register.  */
 126         uint32_t c13_tls3; /* Privileged Thread register.  */
 127         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 128         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 129         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 130         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 131         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 132     } cp15;
 133
 134     struct {
 135         uint32_t other_sp;
 136         uint32_t vecbase;
 137         uint32_t basepri;
 138         uint32_t control;
 139         int current_sp;
 140         int exception;
 141         int pending_exception;
 142         void *nvic;
 143     } v7m;
 144
 145     /* Coprocessor IO used by peripherals */
 146     struct {
 147         ARMReadCPFunc *cp_read;
 148         ARMWriteCPFunc *cp_write;
 149         void *opaque;
 150     } cp[15];
 151
 152     /* Internal CPU feature flags.  */
 153     uint32_t features;
 154
 155     /* Callback for vectored interrupt controller.  */
 156     int (*get_irq_vector)(struct CPUARMState *);
 157     void *irq_opaque;
 158
 159     /* VFP coprocessor state.  */
 160     struct {
 161         float64 regs[32];
 162
 163         uint32_t xregs[16];
 164         /* We store these fpcsr fields separately for convenience.  */
 165         int vec_len;
 166         int vec_stride;
 167
 168         /* scratch space when Tn are not sufficient.  */
 169         uint32_t scratch[8];
 170
 171         float_status fp_status;
 172     } vfp;
 173 #if defined(CONFIG_USER_ONLY)
 174     struct mmon_state *mmon_entry;
 175 #else
 176     uint32_t mmon_addr;
 177 #endif
 178
 179     /* iwMMXt coprocessor state.  */
 180     struct {
 181         uint64_t regs[16];
 182         uint64_t val;
 183
 184         uint32_t cregs[16];
 185     } iwmmxt;
 186
 187 #if defined(CONFIG_USER_ONLY)
 188     /* For usermode syscall translation.  */
 189     int eabi;
 190 #endif
 191
 192     CPU_COMMON
 193
 194     /* These fields after the common ones so they are preserved on reset.  */
 195     struct arm_boot_info *boot_info;
 196 } CPUARMState;
 197
 198 CPUARMState *cpu_arm_init(const char *cpu_model);
 199 void arm_translate_init(void);
 200 int cpu_arm_exec(CPUARMState *s);
 201 void cpu_arm_close(CPUARMState *s);
 202 void do_interrupt(CPUARMState *);
 203 void switch_mode(CPUARMState *, int);
 204 uint32_t do_arm_semihosting(CPUARMState *env);
 205
 206 /* you can call this signal handler from your SIGBUS and SIGSEGV
 207    signal handlers to inform the virtual CPU of exceptions. non zero
 208    is returned if the signal was handled by the virtual CPU.  */
 209 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 210                            void *puc);
 211
 212 void cpu_lock(void);
 213 void cpu_unlock(void);
 214 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 215 {
 216   env->cp15.c13_tls2 = newtls;
 217 }
 218
 219 #define CPSR_M (0x1f)
 220 #define CPSR_T (1 << 5)
 221 #define CPSR_F (1 << 6)
 222 #define CPSR_I (1 << 7)
 223 #define CPSR_A (1 << 8)
 224 #define CPSR_E (1 << 9)
 225 #define CPSR_IT_2_7 (0xfc00)
 226 #define CPSR_GE (0xf << 16)
 227 #define CPSR_RESERVED (0xf << 20)
 228 #define CPSR_J (1 << 24)
 229 #define CPSR_IT_0_1 (3 << 25)
 230 #define CPSR_Q (1 << 27)
 231 #define CPSR_V (1 << 28)
 232 #define CPSR_C (1 << 29)
 233 #define CPSR_Z (1 << 30)
 234 #define CPSR_N (1 << 31)
 235 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 236
 237 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 238 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 239 /* Bits writable in user mode.  */
 240 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 241 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 242 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 243
 244 /* Return the current CPSR value.  */
 245 uint32_t cpsr_read(CPUARMState *env);
 246 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 247 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 248
 249 /* Return the current xPSR value.  */
 250 static inline uint32_t xpsr_read(CPUARMState *env)
 251 {
 252     int ZF;
 253     ZF = (env->ZF == 0);
 254     return (env->NF & 0x80000000) | (ZF << 30)
 255         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 256         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 257         | ((env->condexec_bits & 0xfc) << 8)
 258         | env->v7m.exception;
 259 }
 260
 261 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 262 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 263 {
 264     if (mask & CPSR_NZCV) {
 265         env->ZF = (~val) & CPSR_Z;
 266         env->NF = val;
 267         env->CF = (val >> 29) & 1;
 268         env->VF = (val << 3) & 0x80000000;
 269     }
 270     if (mask & CPSR_Q)
 271         env->QF = ((val & CPSR_Q) != 0);
 272     if (mask & (1 << 24))
 273         env->thumb = ((val & (1 << 24)) != 0);
 274     if (mask & CPSR_IT_0_1) {
 275         env->condexec_bits &= ~3;
 276         env->condexec_bits |= (val >> 25) & 3;
 277     }
 278     if (mask & CPSR_IT_2_7) {
 279         env->condexec_bits &= 3;
 280         env->condexec_bits |= (val >> 8) & 0xfc;
 281     }
 282     if (mask & 0x1ff) {
 283         env->v7m.exception = val & 0x1ff;
 284     }
 285 }
 286
 287 enum arm_cpu_mode {
 288   ARM_CPU_MODE_USR = 0x10,
 289   ARM_CPU_MODE_FIQ = 0x11,
 290   ARM_CPU_MODE_IRQ = 0x12,
 291   ARM_CPU_MODE_SVC = 0x13,
 292   ARM_CPU_MODE_ABT = 0x17,
 293   ARM_CPU_MODE_UND = 0x1b,
 294   ARM_CPU_MODE_SYS = 0x1f
 295 };
 296
 297 /* VFP system registers.  */
 298 #define ARM_VFP_FPSID   0
 299 #define ARM_VFP_FPSCR   1
 300 #define ARM_VFP_MVFR1   6
 301 #define ARM_VFP_MVFR0   7
 302 #define ARM_VFP_FPEXC   8
 303 #define ARM_VFP_FPINST  9
 304 #define ARM_VFP_FPINST2 10
 305
 306 /* iwMMXt coprocessor control registers.  */
 307 #define ARM_IWMMXT_wCID         0
 308 #define ARM_IWMMXT_wCon         1
 309 #define ARM_IWMMXT_wCSSF        2
 310 #define ARM_IWMMXT_wCASF        3
 311 #define ARM_IWMMXT_wCGR0        8
 312 #define ARM_IWMMXT_wCGR1        9
 313 #define ARM_IWMMXT_wCGR2        10
 314 #define ARM_IWMMXT_wCGR3        11
 315
 316 enum arm_features {
 317     ARM_FEATURE_VFP,
 318     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 319     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 320     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 321     ARM_FEATURE_V6,
 322     ARM_FEATURE_V6K,
 323     ARM_FEATURE_V7,
 324     ARM_FEATURE_THUMB2,
 325     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 326     ARM_FEATURE_VFP3,
 327     ARM_FEATURE_NEON,
 328     ARM_FEATURE_DIV,
 329     ARM_FEATURE_M, /* Microcontroller profile.  */
 330     ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
 331 };
 332
 333 static inline int arm_feature(CPUARMState *env, int feature)
 334 {
 335     return (env->features & (1u << feature)) != 0;
 336 }
 337
 338 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 339
 340 /* Interface between CPU and Interrupt controller.  */
 341 void armv7m_nvic_set_pending(void *opaque, int irq);
 342 int armv7m_nvic_acknowledge_irq(void *opaque);
 343 void armv7m_nvic_complete_irq(void *opaque, int irq);
 344
 345 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 346                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 347                        void *opaque);
 348
 349 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 350    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 351    conventional cores (ie. Application or Realtime profile).  */
 352
 353 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 354 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 355
 356 #define ARM_CPUID_ARM1026     0x4106a262
 357 #define ARM_CPUID_ARM926      0x41069265
 358 #define ARM_CPUID_ARM946      0x41059461
 359 #define ARM_CPUID_TI915T      0x54029152
 360 #define ARM_CPUID_TI925T      0x54029252
 361 #define ARM_CPUID_PXA250      0x69052100
 362 #define ARM_CPUID_PXA255      0x69052d00
 363 #define ARM_CPUID_PXA260      0x69052903
 364 #define ARM_CPUID_PXA261      0x69052d05
 365 #define ARM_CPUID_PXA262      0x69052d06
 366 #define ARM_CPUID_PXA270      0x69054110
 367 #define ARM_CPUID_PXA270_A0   0x69054110
 368 #define ARM_CPUID_PXA270_A1   0x69054111
 369 #define ARM_CPUID_PXA270_B0   0x69054112
 370 #define ARM_CPUID_PXA270_B1   0x69054113
 371 #define ARM_CPUID_PXA270_C0   0x69054114
 372 #define ARM_CPUID_PXA270_C5   0x69054117
 373 #define ARM_CPUID_ARM1136     0x4117b363
 374 #define ARM_CPUID_ARM1136_R2  0x4107b362
 375 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 376 #define ARM_CPUID_CORTEXA8    0x410fc080
 377 #define ARM_CPUID_CORTEXM3    0x410fc231
 378 #define ARM_CPUID_ANY         0xffffffff
 379
 380 #if defined(CONFIG_USER_ONLY)
 381 #define TARGET_PAGE_BITS 12
 382 #else
 383 /* The ARM MMU allows 1k pages.  */
 384 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 385    architecture revisions.  Maybe a configure option to disable them.  */
 386 #define TARGET_PAGE_BITS 10
 387 #endif
 388
 389 #define CPUState CPUARMState
 390 #define cpu_init cpu_arm_init
 391 #define cpu_exec cpu_arm_exec
 392 #define cpu_gen_code cpu_arm_gen_code
 393 #define cpu_signal_handler cpu_arm_signal_handler
 394 #define cpu_list arm_cpu_list
 395
 396 #define CPU_SAVE_VERSION 1
 397
 398 /* MMU modes definitions */
 399 #define MMU_MODE0_SUFFIX _kernel
 400 #define MMU_MODE1_SUFFIX _user
 401 #define MMU_USER_IDX 1
 402 static inline int cpu_mmu_index (CPUState *env)
 403 {
 404     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 405 }
 406
 407 #if defined(CONFIG_USER_ONLY)
 408 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 409 {
 410     if (newsp)
 411         env->regs[13] = newsp;
 412     env->regs[0] = 0;
 413 }
 414 #endif
 415
 416 #define CPU_PC_FROM_TB(env, tb) env->regs[15] = tb->pc
 417
 418 #include "cpu-all.h"
 419
 420 #endif