Handle link status in qemu_sendv_packet() (Mark McLoughlin)
[qemu/mini2440/sniper_sniper_test.git] / ppc-dis.c
blobdc640227840a8a9cf12b66f08499c4e72efa5189
1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20 #include "dis-asm.h"
22 /* ppc.h -- Header file for PowerPC opcode table
23 Copyright 1994 Free Software Foundation, Inc.
24 Written by Ian Lance Taylor, Cygnus Support
26 This file is part of GDB, GAS, and the GNU binutils.
28 GDB, GAS, and the GNU binutils are free software; you can redistribute
29 them and/or modify them under the terms of the GNU General Public
30 License as published by the Free Software Foundation; either version
31 1, or (at your option) any later version.
33 GDB, GAS, and the GNU binutils are distributed in the hope that they
34 will be useful, but WITHOUT ANY WARRANTY; without even the implied
35 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
36 the GNU General Public License for more details.
38 You should have received a copy of the GNU General Public License
39 along with this file; see the file COPYING. If not, write to the Free
40 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
42 /* The opcode table is an array of struct powerpc_opcode. */
44 struct powerpc_opcode
46 /* The opcode name. */
47 const char *name;
49 /* The opcode itself. Those bits which will be filled in with
50 operands are zeroes. */
51 uint32_t opcode;
53 /* The opcode mask. This is used by the disassembler. This is a
54 mask containing ones indicating those bits which must match the
55 opcode field, and zeroes indicating those bits which need not
56 match (and are presumably filled in by operands). */
57 uint32_t mask;
59 /* One bit flags for the opcode. These are used to indicate which
60 specific processors support the instructions. The defined values
61 are listed below. */
62 uint32_t flags;
64 /* An array of operand codes. Each code is an index into the
65 operand table. They appear in the order which the operands must
66 appear in assembly code, and are terminated by a zero. */
67 unsigned char operands[8];
70 /* The table itself is sorted by major opcode number, and is otherwise
71 in the order in which the disassembler should consider
72 instructions. */
73 extern const struct powerpc_opcode powerpc_opcodes[];
74 extern const int powerpc_num_opcodes;
76 /* Values defined for the flags field of a struct powerpc_opcode. */
78 /* Opcode is defined for the PowerPC architecture. */
79 #define PPC_OPCODE_PPC (01)
81 /* Opcode is defined for the POWER (RS/6000) architecture. */
82 #define PPC_OPCODE_POWER (02)
84 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
85 #define PPC_OPCODE_POWER2 (04)
87 /* Opcode is only defined on 32 bit architectures. */
88 #define PPC_OPCODE_32 (010)
90 /* Opcode is only defined on 64 bit architectures. */
91 #define PPC_OPCODE_64 (020)
93 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
94 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
95 but it also supports many additional POWER instructions. */
96 #define PPC_OPCODE_601 (040)
98 /* A macro to extract the major opcode from an instruction. */
99 #define PPC_OP(i) (((i) >> 26) & 0x3f)
101 /* The operands table is an array of struct powerpc_operand. */
103 struct powerpc_operand
105 /* The number of bits in the operand. */
106 int bits;
108 /* How far the operand is left shifted in the instruction. */
109 int shift;
111 /* Insertion function. This is used by the assembler. To insert an
112 operand value into an instruction, check this field.
114 If it is NULL, execute
115 i |= (op & ((1 << o->bits) - 1)) << o->shift;
116 (i is the instruction which we are filling in, o is a pointer to
117 this structure, and op is the opcode value; this assumes twos
118 complement arithmetic).
120 If this field is not NULL, then simply call it with the
121 instruction and the operand value. It will return the new value
122 of the instruction. If the ERRMSG argument is not NULL, then if
123 the operand value is illegal, *ERRMSG will be set to a warning
124 string (the operand will be inserted in any case). If the
125 operand value is legal, *ERRMSG will be unchanged (most operands
126 can accept any value). */
127 unsigned long (*insert)(uint32_t instruction, int32_t op,
128 const char **errmsg);
130 /* Extraction function. This is used by the disassembler. To
131 extract this operand type from an instruction, check this field.
133 If it is NULL, compute
134 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
135 if ((o->flags & PPC_OPERAND_SIGNED) != 0
136 && (op & (1 << (o->bits - 1))) != 0)
137 op -= 1 << o->bits;
138 (i is the instruction, o is a pointer to this structure, and op
139 is the result; this assumes twos complement arithmetic).
141 If this field is not NULL, then simply call it with the
142 instruction value. It will return the value of the operand. If
143 the INVALID argument is not NULL, *INVALID will be set to
144 non-zero if this operand type can not actually be extracted from
145 this operand (i.e., the instruction does not match). If the
146 operand is valid, *INVALID will not be changed. */
147 long (*extract) (uint32_t instruction, int *invalid);
149 /* One bit syntax flags. */
150 uint32_t flags;
153 /* Elements in the table are retrieved by indexing with values from
154 the operands field of the powerpc_opcodes table. */
156 extern const struct powerpc_operand powerpc_operands[];
158 /* Values defined for the flags field of a struct powerpc_operand. */
160 /* This operand takes signed values. */
161 #define PPC_OPERAND_SIGNED (01)
163 /* This operand takes signed values, but also accepts a full positive
164 range of values when running in 32 bit mode. That is, if bits is
165 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
166 this flag is ignored. */
167 #define PPC_OPERAND_SIGNOPT (02)
169 /* This operand does not actually exist in the assembler input. This
170 is used to support extended mnemonics such as mr, for which two
171 operands fields are identical. The assembler should call the
172 insert function with any op value. The disassembler should call
173 the extract function, ignore the return value, and check the value
174 placed in the valid argument. */
175 #define PPC_OPERAND_FAKE (04)
177 /* The next operand should be wrapped in parentheses rather than
178 separated from this one by a comma. This is used for the load and
179 store instructions which want their operands to look like
180 reg,displacement(reg)
182 #define PPC_OPERAND_PARENS (010)
184 /* This operand may use the symbolic names for the CR fields, which
186 lt 0 gt 1 eq 2 so 3 un 3
187 cr0 0 cr1 1 cr2 2 cr3 3
188 cr4 4 cr5 5 cr6 6 cr7 7
189 These may be combined arithmetically, as in cr2*4+gt. These are
190 only supported on the PowerPC, not the POWER. */
191 #define PPC_OPERAND_CR (020)
193 /* This operand names a register. The disassembler uses this to print
194 register names with a leading 'r'. */
195 #define PPC_OPERAND_GPR (040)
197 /* This operand names a floating point register. The disassembler
198 prints these with a leading 'f'. */
199 #define PPC_OPERAND_FPR (0100)
201 /* This operand is a relative branch displacement. The disassembler
202 prints these symbolically if possible. */
203 #define PPC_OPERAND_RELATIVE (0200)
205 /* This operand is an absolute branch address. The disassembler
206 prints these symbolically if possible. */
207 #define PPC_OPERAND_ABSOLUTE (0400)
209 /* This operand is optional, and is zero if omitted. This is used for
210 the optional BF and L fields in the comparison instructions. The
211 assembler must count the number of operands remaining on the line,
212 and the number of operands remaining for the opcode, and decide
213 whether this operand is present or not. The disassembler should
214 print this operand out only if it is not zero. */
215 #define PPC_OPERAND_OPTIONAL (01000)
217 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
218 is omitted, then for the next operand use this operand value plus
219 1, ignoring the next operand field for the opcode. This wretched
220 hack is needed because the Power rotate instructions can take
221 either 4 or 5 operands. The disassembler should print this operand
222 out regardless of the PPC_OPERAND_OPTIONAL field. */
223 #define PPC_OPERAND_NEXT (02000)
225 /* This operand should be regarded as a negative number for the
226 purposes of overflow checking (i.e., the normal most negative
227 number is disallowed and one more than the normal most positive
228 number is allowed). This flag will only be set for a signed
229 operand. */
230 #define PPC_OPERAND_NEGATIVE (04000)
232 /* The POWER and PowerPC assemblers use a few macros. We keep them
233 with the operands table for simplicity. The macro table is an
234 array of struct powerpc_macro. */
236 struct powerpc_macro
238 /* The macro name. */
239 const char *name;
241 /* The number of operands the macro takes. */
242 unsigned int operands;
244 /* One bit flags for the opcode. These are used to indicate which
245 specific processors support the instructions. The values are the
246 same as those for the struct powerpc_opcode flags field. */
247 uint32_t flags;
249 /* A format string to turn the macro into a normal instruction.
250 Each %N in the string is replaced with operand number N (zero
251 based). */
252 const char *format;
255 extern const struct powerpc_macro powerpc_macros[];
256 extern const int powerpc_num_macros;
258 /* ppc-opc.c -- PowerPC opcode list
259 Copyright 1994 Free Software Foundation, Inc.
260 Written by Ian Lance Taylor, Cygnus Support
262 This file is part of GDB, GAS, and the GNU binutils.
264 GDB, GAS, and the GNU binutils are free software; you can redistribute
265 them and/or modify them under the terms of the GNU General Public
266 License as published by the Free Software Foundation; either version
267 2, or (at your option) any later version.
269 GDB, GAS, and the GNU binutils are distributed in the hope that they
270 will be useful, but WITHOUT ANY WARRANTY; without even the implied
271 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
272 the GNU General Public License for more details.
274 You should have received a copy of the GNU General Public License
275 along with this file; see the file COPYING. If not, write to the Free
276 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
277 02110-1301, USA. */
279 /* This file holds the PowerPC opcode table. The opcode table
280 includes almost all of the extended instruction mnemonics. This
281 permits the disassembler to use them, and simplifies the assembler
282 logic, at the cost of increasing the table size. The table is
283 strictly constant data, so the compiler should be able to put it in
284 the .text section.
286 This file also holds the operand table. All knowledge about
287 inserting operands into instructions and vice-versa is kept in this
288 file. */
290 /* Local insertion and extraction functions. */
292 static unsigned long insert_bat (uint32_t, int32_t, const char **);
293 static long extract_bat(uint32_t, int *);
294 static unsigned long insert_bba(uint32_t, int32_t, const char **);
295 static long extract_bba(uint32_t, int *);
296 static unsigned long insert_bd(uint32_t, int32_t, const char **);
297 static long extract_bd(uint32_t, int *);
298 static unsigned long insert_bdm(uint32_t, int32_t, const char **);
299 static long extract_bdm(uint32_t, int *);
300 static unsigned long insert_bdp(uint32_t, int32_t, const char **);
301 static long extract_bdp(uint32_t, int *);
302 static unsigned long insert_bo(uint32_t, int32_t, const char **);
303 static long extract_bo(uint32_t, int *);
304 static unsigned long insert_boe(uint32_t, int32_t, const char **);
305 static long extract_boe(uint32_t, int *);
306 static unsigned long insert_ds(uint32_t, int32_t, const char **);
307 static long extract_ds(uint32_t, int *);
308 static unsigned long insert_li(uint32_t, int32_t, const char **);
309 static long extract_li(uint32_t, int *);
310 static unsigned long insert_mbe(uint32_t, int32_t, const char **);
311 static long extract_mbe(uint32_t, int *);
312 static unsigned long insert_mb6(uint32_t, int32_t, const char **);
313 static long extract_mb6(uint32_t, int *);
314 static unsigned long insert_nb(uint32_t, int32_t, const char **);
315 static long extract_nb(uint32_t, int *);
316 static unsigned long insert_nsi(uint32_t, int32_t, const char **);
317 static long extract_nsi(uint32_t, int *);
318 static unsigned long insert_ral(uint32_t, int32_t, const char **);
319 static unsigned long insert_ram(uint32_t, int32_t, const char **);
320 static unsigned long insert_ras(uint32_t, int32_t, const char **);
321 static unsigned long insert_rbs(uint32_t, int32_t, const char **);
322 static long extract_rbs(uint32_t, int *);
323 static unsigned long insert_sh6(uint32_t, int32_t, const char **);
324 static long extract_sh6(uint32_t, int *);
325 static unsigned long insert_spr(uint32_t, int32_t, const char **);
326 static long extract_spr(uint32_t, int *);
327 static unsigned long insert_tbr(uint32_t, int32_t, const char **);
328 static long extract_tbr(uint32_t, int *);
330 /* The operands table.
332 The fields are bits, shift, signed, insert, extract, flags. */
334 const struct powerpc_operand powerpc_operands[] =
336 /* The zero index is used to indicate the end of the list of
337 operands. */
338 #define UNUSED (0)
339 { 0, 0, 0, 0, 0 },
341 /* The BA field in an XL form instruction. */
342 #define BA (1)
343 #define BA_MASK (0x1f << 16)
344 { 5, 16, 0, 0, PPC_OPERAND_CR },
346 /* The BA field in an XL form instruction when it must be the same
347 as the BT field in the same instruction. */
348 #define BAT (2)
349 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
351 /* The BB field in an XL form instruction. */
352 #define BB (3)
353 #define BB_MASK (0x1f << 11)
354 { 5, 11, 0, 0, PPC_OPERAND_CR },
356 /* The BB field in an XL form instruction when it must be the same
357 as the BA field in the same instruction. */
358 #define BBA (4)
359 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
361 /* The BD field in a B form instruction. The lower two bits are
362 forced to zero. */
363 #define BD (5)
364 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
366 /* The BD field in a B form instruction when absolute addressing is
367 used. */
368 #define BDA (6)
369 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
371 /* The BD field in a B form instruction when the - modifier is used.
372 This sets the y bit of the BO field appropriately. */
373 #define BDM (7)
374 { 16, 0, insert_bdm, extract_bdm,
375 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
377 /* The BD field in a B form instruction when the - modifier is used
378 and absolute address is used. */
379 #define BDMA (8)
380 { 16, 0, insert_bdm, extract_bdm,
381 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
383 /* The BD field in a B form instruction when the + modifier is used.
384 This sets the y bit of the BO field appropriately. */
385 #define BDP (9)
386 { 16, 0, insert_bdp, extract_bdp,
387 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
389 /* The BD field in a B form instruction when the + modifier is used
390 and absolute addressing is used. */
391 #define BDPA (10)
392 { 16, 0, insert_bdp, extract_bdp,
393 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
395 /* The BF field in an X or XL form instruction. */
396 #define BF (11)
397 { 3, 23, 0, 0, PPC_OPERAND_CR },
399 /* An optional BF field. This is used for comparison instructions,
400 in which an omitted BF field is taken as zero. */
401 #define OBF (12)
402 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
404 /* The BFA field in an X or XL form instruction. */
405 #define BFA (13)
406 { 3, 18, 0, 0, PPC_OPERAND_CR },
408 /* The BI field in a B form or XL form instruction. */
409 #define BI (14)
410 #define BI_MASK (0x1f << 16)
411 { 5, 16, 0, 0, PPC_OPERAND_CR },
413 /* The BO field in a B form instruction. Certain values are
414 illegal. */
415 #define BO (15)
416 #define BO_MASK (0x1f << 21)
417 { 5, 21, insert_bo, extract_bo, 0 },
419 /* The BO field in a B form instruction when the + or - modifier is
420 used. This is like the BO field, but it must be even. */
421 #define BOE (16)
422 { 5, 21, insert_boe, extract_boe, 0 },
424 /* The BT field in an X or XL form instruction. */
425 #define BT (17)
426 { 5, 21, 0, 0, PPC_OPERAND_CR },
428 /* The condition register number portion of the BI field in a B form
429 or XL form instruction. This is used for the extended
430 conditional branch mnemonics, which set the lower two bits of the
431 BI field. This field is optional. */
432 #define CR (18)
433 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
435 /* The D field in a D form instruction. This is a displacement off
436 a register, and implies that the next operand is a register in
437 parentheses. */
438 #define D (19)
439 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
441 /* The DS field in a DS form instruction. This is like D, but the
442 lower two bits are forced to zero. */
443 #define DS (20)
444 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
446 /* The FL1 field in a POWER SC form instruction. */
447 #define FL1 (21)
448 { 4, 12, 0, 0, 0 },
450 /* The FL2 field in a POWER SC form instruction. */
451 #define FL2 (22)
452 { 3, 2, 0, 0, 0 },
454 /* The FLM field in an XFL form instruction. */
455 #define FLM (23)
456 { 8, 17, 0, 0, 0 },
458 /* The FRA field in an X or A form instruction. */
459 #define FRA (24)
460 #define FRA_MASK (0x1f << 16)
461 { 5, 16, 0, 0, PPC_OPERAND_FPR },
463 /* The FRB field in an X or A form instruction. */
464 #define FRB (25)
465 #define FRB_MASK (0x1f << 11)
466 { 5, 11, 0, 0, PPC_OPERAND_FPR },
468 /* The FRC field in an A form instruction. */
469 #define FRC (26)
470 #define FRC_MASK (0x1f << 6)
471 { 5, 6, 0, 0, PPC_OPERAND_FPR },
473 /* The FRS field in an X form instruction or the FRT field in a D, X
474 or A form instruction. */
475 #define FRS (27)
476 #define FRT (FRS)
477 { 5, 21, 0, 0, PPC_OPERAND_FPR },
479 /* The FXM field in an XFX instruction. */
480 #define FXM (28)
481 #define FXM_MASK (0xff << 12)
482 { 8, 12, 0, 0, 0 },
484 /* The L field in a D or X form instruction. */
485 #define L (29)
486 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
488 /* The LEV field in a POWER SC form instruction. */
489 #define LEV (30)
490 { 7, 5, 0, 0, 0 },
492 /* The LI field in an I form instruction. The lower two bits are
493 forced to zero. */
494 #define LI (31)
495 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
497 /* The LI field in an I form instruction when used as an absolute
498 address. */
499 #define LIA (32)
500 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
502 /* The MB field in an M form instruction. */
503 #define MB (33)
504 #define MB_MASK (0x1f << 6)
505 { 5, 6, 0, 0, 0 },
507 /* The ME field in an M form instruction. */
508 #define ME (34)
509 #define ME_MASK (0x1f << 1)
510 { 5, 1, 0, 0, 0 },
512 /* The MB and ME fields in an M form instruction expressed a single
513 operand which is a bitmask indicating which bits to select. This
514 is a two operand form using PPC_OPERAND_NEXT. See the
515 description in opcode/ppc.h for what this means. */
516 #define MBE (35)
517 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
518 { 32, 0, insert_mbe, extract_mbe, 0 },
520 /* The MB or ME field in an MD or MDS form instruction. The high
521 bit is wrapped to the low end. */
522 #define MB6 (37)
523 #define ME6 (MB6)
524 #define MB6_MASK (0x3f << 5)
525 { 6, 5, insert_mb6, extract_mb6, 0 },
527 /* The NB field in an X form instruction. The value 32 is stored as
528 0. */
529 #define NB (38)
530 { 6, 11, insert_nb, extract_nb, 0 },
532 /* The NSI field in a D form instruction. This is the same as the
533 SI field, only negated. */
534 #define NSI (39)
535 { 16, 0, insert_nsi, extract_nsi,
536 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
538 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
539 #define RA (40)
540 #define RA_MASK (0x1f << 16)
541 { 5, 16, 0, 0, PPC_OPERAND_GPR },
543 /* The RA field in a D or X form instruction which is an updating
544 load, which means that the RA field may not be zero and may not
545 equal the RT field. */
546 #define RAL (41)
547 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
549 /* The RA field in an lmw instruction, which has special value
550 restrictions. */
551 #define RAM (42)
552 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
554 /* The RA field in a D or X form instruction which is an updating
555 store or an updating floating point load, which means that the RA
556 field may not be zero. */
557 #define RAS (43)
558 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
560 /* The RB field in an X, XO, M, or MDS form instruction. */
561 #define RB (44)
562 #define RB_MASK (0x1f << 11)
563 { 5, 11, 0, 0, PPC_OPERAND_GPR },
565 /* The RB field in an X form instruction when it must be the same as
566 the RS field in the instruction. This is used for extended
567 mnemonics like mr. */
568 #define RBS (45)
569 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
571 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
572 instruction or the RT field in a D, DS, X, XFX or XO form
573 instruction. */
574 #define RS (46)
575 #define RT (RS)
576 #define RT_MASK (0x1f << 21)
577 { 5, 21, 0, 0, PPC_OPERAND_GPR },
579 /* The SH field in an X or M form instruction. */
580 #define SH (47)
581 #define SH_MASK (0x1f << 11)
582 { 5, 11, 0, 0, 0 },
584 /* The SH field in an MD form instruction. This is split. */
585 #define SH6 (48)
586 #define SH6_MASK ((0x1f << 11) | (1 << 1))
587 { 6, 1, insert_sh6, extract_sh6, 0 },
589 /* The SI field in a D form instruction. */
590 #define SI (49)
591 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
593 /* The SI field in a D form instruction when we accept a wide range
594 of positive values. */
595 #define SISIGNOPT (50)
596 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
598 /* The SPR field in an XFX form instruction. This is flipped--the
599 lower 5 bits are stored in the upper 5 and vice- versa. */
600 #define SPR (51)
601 #define SPR_MASK (0x3ff << 11)
602 { 10, 11, insert_spr, extract_spr, 0 },
604 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
605 #define SPRBAT (52)
606 #define SPRBAT_MASK (0x3 << 17)
607 { 2, 17, 0, 0, 0 },
609 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
610 #define SPRG (53)
611 #define SPRG_MASK (0x3 << 16)
612 { 2, 16, 0, 0, 0 },
614 /* The SR field in an X form instruction. */
615 #define SR (54)
616 { 4, 16, 0, 0, 0 },
618 /* The SV field in a POWER SC form instruction. */
619 #define SV (55)
620 { 14, 2, 0, 0, 0 },
622 /* The TBR field in an XFX form instruction. This is like the SPR
623 field, but it is optional. */
624 #define TBR (56)
625 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
627 /* The TO field in a D or X form instruction. */
628 #define TO (57)
629 #define TO_MASK (0x1f << 21)
630 { 5, 21, 0, 0, 0 },
632 /* The U field in an X form instruction. */
633 #define U (58)
634 { 4, 12, 0, 0, 0 },
636 /* The UI field in a D form instruction. */
637 #define UI (59)
638 { 16, 0, 0, 0, 0 },
641 /* The functions used to insert and extract complicated operands. */
643 /* The BA field in an XL form instruction when it must be the same as
644 the BT field in the same instruction. This operand is marked FAKE.
645 The insertion function just copies the BT field into the BA field,
646 and the extraction function just checks that the fields are the
647 same. */
649 /*ARGSUSED*/
650 static unsigned long
651 insert_bat (insn, value, errmsg)
652 uint32_t insn;
653 int32_t value;
654 const char **errmsg;
656 return insn | (((insn >> 21) & 0x1f) << 16);
659 static long
660 extract_bat (insn, invalid)
661 uint32_t insn;
662 int *invalid;
664 if (invalid != (int *) NULL
665 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
666 *invalid = 1;
667 return 0;
670 /* The BB field in an XL form instruction when it must be the same as
671 the BA field in the same instruction. This operand is marked FAKE.
672 The insertion function just copies the BA field into the BB field,
673 and the extraction function just checks that the fields are the
674 same. */
676 /*ARGSUSED*/
677 static unsigned long
678 insert_bba (insn, value, errmsg)
679 uint32_t insn;
680 int32_t value;
681 const char **errmsg;
683 return insn | (((insn >> 16) & 0x1f) << 11);
686 static long
687 extract_bba (insn, invalid)
688 uint32_t insn;
689 int *invalid;
691 if (invalid != (int *) NULL
692 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
693 *invalid = 1;
694 return 0;
697 /* The BD field in a B form instruction. The lower two bits are
698 forced to zero. */
700 /*ARGSUSED*/
701 static unsigned long
702 insert_bd (insn, value, errmsg)
703 uint32_t insn;
704 int32_t value;
705 const char **errmsg;
707 return insn | (value & 0xfffc);
710 /*ARGSUSED*/
711 static long
712 extract_bd (insn, invalid)
713 uint32_t insn;
714 int *invalid;
716 if ((insn & 0x8000) != 0)
717 return (insn & 0xfffc) - 0x10000;
718 else
719 return insn & 0xfffc;
722 /* The BD field in a B form instruction when the - modifier is used.
723 This modifier means that the branch is not expected to be taken.
724 We must set the y bit of the BO field to 1 if the offset is
725 negative. When extracting, we require that the y bit be 1 and that
726 the offset be positive, since if the y bit is 0 we just want to
727 print the normal form of the instruction. */
729 /*ARGSUSED*/
730 static unsigned long
731 insert_bdm (insn, value, errmsg)
732 uint32_t insn;
733 int32_t value;
734 const char **errmsg;
736 if ((value & 0x8000) != 0)
737 insn |= 1 << 21;
738 return insn | (value & 0xfffc);
741 static long
742 extract_bdm (insn, invalid)
743 uint32_t insn;
744 int *invalid;
746 if (invalid != (int *) NULL
747 && ((insn & (1 << 21)) == 0
748 || (insn & (1 << 15)) == 0))
749 *invalid = 1;
750 if ((insn & 0x8000) != 0)
751 return (insn & 0xfffc) - 0x10000;
752 else
753 return insn & 0xfffc;
756 /* The BD field in a B form instruction when the + modifier is used.
757 This is like BDM, above, except that the branch is expected to be
758 taken. */
760 /*ARGSUSED*/
761 static unsigned long
762 insert_bdp (insn, value, errmsg)
763 uint32_t insn;
764 int32_t value;
765 const char **errmsg;
767 if ((value & 0x8000) == 0)
768 insn |= 1 << 21;
769 return insn | (value & 0xfffc);
772 static long
773 extract_bdp (insn, invalid)
774 uint32_t insn;
775 int *invalid;
777 if (invalid != (int *) NULL
778 && ((insn & (1 << 21)) == 0
779 || (insn & (1 << 15)) != 0))
780 *invalid = 1;
781 if ((insn & 0x8000) != 0)
782 return (insn & 0xfffc) - 0x10000;
783 else
784 return insn & 0xfffc;
787 /* Check for legal values of a BO field. */
789 static int
790 valid_bo (int32_t value)
792 /* Certain encodings have bits that are required to be zero. These
793 are (z must be zero, y may be anything):
794 001zy
795 011zy
796 1z00y
797 1z01y
798 1z1zz
800 switch (value & 0x14)
802 default:
803 case 0:
804 return 1;
805 case 0x4:
806 return (value & 0x2) == 0;
807 case 0x10:
808 return (value & 0x8) == 0;
809 case 0x14:
810 return value == 0x14;
814 /* The BO field in a B form instruction. Warn about attempts to set
815 the field to an illegal value. */
817 static unsigned long
818 insert_bo (insn, value, errmsg)
819 uint32_t insn;
820 int32_t value;
821 const char **errmsg;
823 if (errmsg != (const char **) NULL
824 && ! valid_bo (value))
825 *errmsg = "invalid conditional option";
826 return insn | ((value & 0x1f) << 21);
829 static long
830 extract_bo (insn, invalid)
831 uint32_t insn;
832 int *invalid;
834 int32_t value;
836 value = (insn >> 21) & 0x1f;
837 if (invalid != (int *) NULL
838 && ! valid_bo (value))
839 *invalid = 1;
840 return value;
843 /* The BO field in a B form instruction when the + or - modifier is
844 used. This is like the BO field, but it must be even. When
845 extracting it, we force it to be even. */
847 static unsigned long
848 insert_boe (insn, value, errmsg)
849 uint32_t insn;
850 int32_t value;
851 const char **errmsg;
853 if (errmsg != (const char **) NULL)
855 if (! valid_bo (value))
856 *errmsg = "invalid conditional option";
857 else if ((value & 1) != 0)
858 *errmsg = "attempt to set y bit when using + or - modifier";
860 return insn | ((value & 0x1f) << 21);
863 static long
864 extract_boe (insn, invalid)
865 uint32_t insn;
866 int *invalid;
868 int32_t value;
870 value = (insn >> 21) & 0x1f;
871 if (invalid != (int *) NULL
872 && ! valid_bo (value))
873 *invalid = 1;
874 return value & 0x1e;
877 /* The DS field in a DS form instruction. This is like D, but the
878 lower two bits are forced to zero. */
880 /*ARGSUSED*/
881 static unsigned long
882 insert_ds (insn, value, errmsg)
883 uint32_t insn;
884 int32_t value;
885 const char **errmsg;
887 return insn | (value & 0xfffc);
890 /*ARGSUSED*/
891 static long
892 extract_ds (insn, invalid)
893 uint32_t insn;
894 int *invalid;
896 if ((insn & 0x8000) != 0)
897 return (insn & 0xfffc) - 0x10000;
898 else
899 return insn & 0xfffc;
902 /* The LI field in an I form instruction. The lower two bits are
903 forced to zero. */
905 /*ARGSUSED*/
906 static unsigned long
907 insert_li (insn, value, errmsg)
908 uint32_t insn;
909 int32_t value;
910 const char **errmsg;
912 return insn | (value & 0x3fffffc);
915 /*ARGSUSED*/
916 static long
917 extract_li (insn, invalid)
918 uint32_t insn;
919 int *invalid;
921 if ((insn & 0x2000000) != 0)
922 return (insn & 0x3fffffc) - 0x4000000;
923 else
924 return insn & 0x3fffffc;
927 /* The MB and ME fields in an M form instruction expressed as a single
928 operand which is itself a bitmask. The extraction function always
929 marks it as invalid, since we never want to recognize an
930 instruction which uses a field of this type. */
932 static unsigned long
933 insert_mbe (insn, value, errmsg)
934 uint32_t insn;
935 int32_t value;
936 const char **errmsg;
938 uint32_t uval;
939 int mb, me;
941 uval = value;
943 if (uval == 0)
945 if (errmsg != (const char **) NULL)
946 *errmsg = "illegal bitmask";
947 return insn;
950 me = 31;
951 while ((uval & 1) == 0)
953 uval >>= 1;
954 --me;
957 mb = me;
958 uval >>= 1;
959 while ((uval & 1) != 0)
961 uval >>= 1;
962 --mb;
965 if (uval != 0)
967 if (errmsg != (const char **) NULL)
968 *errmsg = "illegal bitmask";
971 return insn | (mb << 6) | (me << 1);
974 static long
975 extract_mbe (insn, invalid)
976 uint32_t insn;
977 int *invalid;
979 long ret;
980 int mb, me;
981 int i;
983 if (invalid != (int *) NULL)
984 *invalid = 1;
986 ret = 0;
987 mb = (insn >> 6) & 0x1f;
988 me = (insn >> 1) & 0x1f;
989 for (i = mb; i < me; i++)
990 ret |= 1 << (31 - i);
991 return ret;
994 /* The MB or ME field in an MD or MDS form instruction. The high bit
995 is wrapped to the low end. */
997 /*ARGSUSED*/
998 static unsigned long
999 insert_mb6 (insn, value, errmsg)
1000 uint32_t insn;
1001 int32_t value;
1002 const char **errmsg;
1004 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1007 /*ARGSUSED*/
1008 static long
1009 extract_mb6 (insn, invalid)
1010 uint32_t insn;
1011 int *invalid;
1013 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1016 /* The NB field in an X form instruction. The value 32 is stored as
1017 0. */
1019 static unsigned long
1020 insert_nb (insn, value, errmsg)
1021 uint32_t insn;
1022 int32_t value;
1023 const char **errmsg;
1025 if (value < 0 || value > 32)
1026 *errmsg = "value out of range";
1027 if (value == 32)
1028 value = 0;
1029 return insn | ((value & 0x1f) << 11);
1032 /*ARGSUSED*/
1033 static long
1034 extract_nb (insn, invalid)
1035 uint32_t insn;
1036 int *invalid;
1038 long ret;
1040 ret = (insn >> 11) & 0x1f;
1041 if (ret == 0)
1042 ret = 32;
1043 return ret;
1046 /* The NSI field in a D form instruction. This is the same as the SI
1047 field, only negated. The extraction function always marks it as
1048 invalid, since we never want to recognize an instruction which uses
1049 a field of this type. */
1051 /*ARGSUSED*/
1052 static unsigned long
1053 insert_nsi (insn, value, errmsg)
1054 uint32_t insn;
1055 int32_t value;
1056 const char **errmsg;
1058 return insn | ((- value) & 0xffff);
1061 static long
1062 extract_nsi (insn, invalid)
1063 uint32_t insn;
1064 int *invalid;
1066 if (invalid != (int *) NULL)
1067 *invalid = 1;
1068 if ((insn & 0x8000) != 0)
1069 return - ((insn & 0xffff) - 0x10000);
1070 else
1071 return - (insn & 0xffff);
1074 /* The RA field in a D or X form instruction which is an updating
1075 load, which means that the RA field may not be zero and may not
1076 equal the RT field. */
1078 static unsigned long
1079 insert_ral (insn, value, errmsg)
1080 uint32_t insn;
1081 int32_t value;
1082 const char **errmsg;
1084 if (value == 0
1085 || value == ((insn >> 21) & 0x1f))
1086 *errmsg = "invalid register operand when updating";
1087 return insn | ((value & 0x1f) << 16);
1090 /* The RA field in an lmw instruction, which has special value
1091 restrictions. */
1093 static unsigned long
1094 insert_ram (insn, value, errmsg)
1095 uint32_t insn;
1096 int32_t value;
1097 const char **errmsg;
1099 if (value >= ((insn >> 21) & 0x1f))
1100 *errmsg = "index register in load range";
1101 return insn | ((value & 0x1f) << 16);
1104 /* The RA field in a D or X form instruction which is an updating
1105 store or an updating floating point load, which means that the RA
1106 field may not be zero. */
1108 static unsigned long
1109 insert_ras (insn, value, errmsg)
1110 uint32_t insn;
1111 int32_t value;
1112 const char **errmsg;
1114 if (value == 0)
1115 *errmsg = "invalid register operand when updating";
1116 return insn | ((value & 0x1f) << 16);
1119 /* The RB field in an X form instruction when it must be the same as
1120 the RS field in the instruction. This is used for extended
1121 mnemonics like mr. This operand is marked FAKE. The insertion
1122 function just copies the BT field into the BA field, and the
1123 extraction function just checks that the fields are the same. */
1125 /*ARGSUSED*/
1126 static unsigned long
1127 insert_rbs (insn, value, errmsg)
1128 uint32_t insn;
1129 int32_t value;
1130 const char **errmsg;
1132 return insn | (((insn >> 21) & 0x1f) << 11);
1135 static long
1136 extract_rbs (insn, invalid)
1137 uint32_t insn;
1138 int *invalid;
1140 if (invalid != (int *) NULL
1141 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1142 *invalid = 1;
1143 return 0;
1146 /* The SH field in an MD form instruction. This is split. */
1148 /*ARGSUSED*/
1149 static unsigned long
1150 insert_sh6 (insn, value, errmsg)
1151 uint32_t insn;
1152 int32_t value;
1153 const char **errmsg;
1155 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1158 /*ARGSUSED*/
1159 static long
1160 extract_sh6 (insn, invalid)
1161 uint32_t insn;
1162 int *invalid;
1164 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1167 /* The SPR field in an XFX form instruction. This is flipped--the
1168 lower 5 bits are stored in the upper 5 and vice- versa. */
1170 static unsigned long
1171 insert_spr (insn, value, errmsg)
1172 uint32_t insn;
1173 int32_t value;
1174 const char **errmsg;
1176 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1179 static long
1180 extract_spr (insn, invalid)
1181 uint32_t insn;
1182 int *invalid;
1184 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1187 /* The TBR field in an XFX instruction. This is just like SPR, but it
1188 is optional. When TBR is omitted, it must be inserted as 268 (the
1189 magic number of the TB register). These functions treat 0
1190 (indicating an omitted optional operand) as 268. This means that
1191 ``mftb 4,0'' is not handled correctly. This does not matter very
1192 much, since the architecture manual does not define mftb as
1193 accepting any values other than 268 or 269. */
1195 #define TB (268)
1197 static unsigned long
1198 insert_tbr (insn, value, errmsg)
1199 uint32_t insn;
1200 int32_t value;
1201 const char **errmsg;
1203 if (value == 0)
1204 value = TB;
1205 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1208 static long
1209 extract_tbr (insn, invalid)
1210 uint32_t insn;
1211 int *invalid;
1213 long ret;
1215 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1216 if (ret == TB)
1217 ret = 0;
1218 return ret;
1221 /* Macros used to form opcodes. */
1223 /* The main opcode. */
1224 #define OP(x) (((x) & 0x3f) << 26)
1225 #define OP_MASK OP (0x3f)
1227 /* The main opcode combined with a trap code in the TO field of a D
1228 form instruction. Used for extended mnemonics for the trap
1229 instructions. */
1230 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
1231 #define OPTO_MASK (OP_MASK | TO_MASK)
1233 /* The main opcode combined with a comparison size bit in the L field
1234 of a D form or X form instruction. Used for extended mnemonics for
1235 the comparison instructions. */
1236 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
1237 #define OPL_MASK OPL (0x3f,1)
1239 /* An A form instruction. */
1240 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
1241 #define A_MASK A (0x3f, 0x1f, 1)
1243 /* An A_MASK with the FRB field fixed. */
1244 #define AFRB_MASK (A_MASK | FRB_MASK)
1246 /* An A_MASK with the FRC field fixed. */
1247 #define AFRC_MASK (A_MASK | FRC_MASK)
1249 /* An A_MASK with the FRA and FRC fields fixed. */
1250 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1252 /* A B form instruction. */
1253 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
1254 #define B_MASK B (0x3f, 1, 1)
1256 /* A B form instruction setting the BO field. */
1257 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
1258 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1260 /* A BBO_MASK with the y bit of the BO field removed. This permits
1261 matching a conditional branch regardless of the setting of the y
1262 bit. */
1263 #define Y_MASK (1 << 21)
1264 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1266 /* A B form instruction setting the BO field and the condition bits of
1267 the BI field. */
1268 #define BBOCB(op, bo, cb, aa, lk) \
1269 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
1270 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1272 /* A BBOCB_MASK with the y bit of the BO field removed. */
1273 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1275 /* A BBOYCB_MASK in which the BI field is fixed. */
1276 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1278 /* The main opcode mask with the RA field clear. */
1279 #define DRA_MASK (OP_MASK | RA_MASK)
1281 /* A DS form instruction. */
1282 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1283 #define DS_MASK DSO (0x3f, 3)
1285 /* An M form instruction. */
1286 #define M(op, rc) (OP (op) | ((rc) & 1))
1287 #define M_MASK M (0x3f, 1)
1289 /* An M form instruction with the ME field specified. */
1290 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
1292 /* An M_MASK with the MB and ME fields fixed. */
1293 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1295 /* An M_MASK with the SH and ME fields fixed. */
1296 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1298 /* An MD form instruction. */
1299 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
1300 #define MD_MASK MD (0x3f, 0x7, 1)
1302 /* An MD_MASK with the MB field fixed. */
1303 #define MDMB_MASK (MD_MASK | MB6_MASK)
1305 /* An MD_MASK with the SH field fixed. */
1306 #define MDSH_MASK (MD_MASK | SH6_MASK)
1308 /* An MDS form instruction. */
1309 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
1310 #define MDS_MASK MDS (0x3f, 0xf, 1)
1312 /* An MDS_MASK with the MB field fixed. */
1313 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1315 /* An SC form instruction. */
1316 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
1317 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
1319 /* An X form instruction. */
1320 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1322 /* An X form instruction with the RC bit specified. */
1323 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1325 /* The mask for an X form instruction. */
1326 #define X_MASK XRC (0x3f, 0x3ff, 1)
1328 /* An X_MASK with the RA field fixed. */
1329 #define XRA_MASK (X_MASK | RA_MASK)
1331 /* An X_MASK with the RB field fixed. */
1332 #define XRB_MASK (X_MASK | RB_MASK)
1334 /* An X_MASK with the RT field fixed. */
1335 #define XRT_MASK (X_MASK | RT_MASK)
1337 /* An X_MASK with the RA and RB fields fixed. */
1338 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1340 /* An X_MASK with the RT and RA fields fixed. */
1341 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1343 /* An X form comparison instruction. */
1344 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
1346 /* The mask for an X form comparison instruction. */
1347 #define XCMP_MASK (X_MASK | (1 << 22))
1349 /* The mask for an X form comparison instruction with the L field
1350 fixed. */
1351 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1353 /* An X form trap instruction with the TO field specified. */
1354 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1355 #define XTO_MASK (X_MASK | TO_MASK)
1357 /* An XFL form instruction. */
1358 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1359 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1361 /* An XL form instruction with the LK field set to 0. */
1362 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1364 /* An XL form instruction which uses the LK field. */
1365 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1367 /* The mask for an XL form instruction. */
1368 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1370 /* An XL form instruction which explicitly sets the BO field. */
1371 #define XLO(op, bo, xop, lk) \
1372 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1373 #define XLO_MASK (XL_MASK | BO_MASK)
1375 /* An XL form instruction which explicitly sets the y bit of the BO
1376 field. */
1377 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1378 #define XLYLK_MASK (XL_MASK | Y_MASK)
1380 /* An XL form instruction which sets the BO field and the condition
1381 bits of the BI field. */
1382 #define XLOCB(op, bo, cb, xop, lk) \
1383 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1384 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1386 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1387 #define XLBB_MASK (XL_MASK | BB_MASK)
1388 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1389 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1391 /* An XL_MASK with the BO and BB fields fixed. */
1392 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1394 /* An XL_MASK with the BO, BI and BB fields fixed. */
1395 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1397 /* An XO form instruction. */
1398 #define XO(op, xop, oe, rc) \
1399 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1400 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1402 /* An XO_MASK with the RB field fixed. */
1403 #define XORB_MASK (XO_MASK | RB_MASK)
1405 /* An XS form instruction. */
1406 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1407 #define XS_MASK XS (0x3f, 0x1ff, 1)
1409 /* A mask for the FXM version of an XFX form instruction. */
1410 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1412 /* An XFX form instruction with the FXM field filled in. */
1413 #define XFXM(op, xop, fxm) \
1414 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1416 /* An XFX form instruction with the SPR field filled in. */
1417 #define XSPR(op, xop, spr) \
1418 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1419 #define XSPR_MASK (X_MASK | SPR_MASK)
1421 /* An XFX form instruction with the SPR field filled in except for the
1422 SPRBAT field. */
1423 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1425 /* An XFX form instruction with the SPR field filled in except for the
1426 SPRG field. */
1427 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1429 /* The BO encodings used in extended conditional branch mnemonics. */
1430 #define BODNZF (0x0)
1431 #define BODNZFP (0x1)
1432 #define BODZF (0x2)
1433 #define BODZFP (0x3)
1434 #define BOF (0x4)
1435 #define BOFP (0x5)
1436 #define BODNZT (0x8)
1437 #define BODNZTP (0x9)
1438 #define BODZT (0xa)
1439 #define BODZTP (0xb)
1440 #define BOT (0xc)
1441 #define BOTP (0xd)
1442 #define BODNZ (0x10)
1443 #define BODNZP (0x11)
1444 #define BODZ (0x12)
1445 #define BODZP (0x13)
1446 #define BOU (0x14)
1448 /* The BI condition bit encodings used in extended conditional branch
1449 mnemonics. */
1450 #define CBLT (0)
1451 #define CBGT (1)
1452 #define CBEQ (2)
1453 #define CBSO (3)
1455 /* The TO encodings used in extended trap mnemonics. */
1456 #define TOLGT (0x1)
1457 #define TOLLT (0x2)
1458 #define TOEQ (0x4)
1459 #define TOLGE (0x5)
1460 #define TOLNL (0x5)
1461 #define TOLLE (0x6)
1462 #define TOLNG (0x6)
1463 #define TOGT (0x8)
1464 #define TOGE (0xc)
1465 #define TONL (0xc)
1466 #define TOLT (0x10)
1467 #define TOLE (0x14)
1468 #define TONG (0x14)
1469 #define TONE (0x18)
1470 #define TOU (0x1f)
1472 /* Smaller names for the flags so each entry in the opcodes table will
1473 fit on a single line. */
1474 #undef PPC
1475 #define PPC PPC_OPCODE_PPC
1476 #define POWER PPC_OPCODE_POWER
1477 #define POWER2 PPC_OPCODE_POWER2
1478 #define B32 PPC_OPCODE_32
1479 #define B64 PPC_OPCODE_64
1480 #define M601 PPC_OPCODE_601
1482 /* The opcode table.
1484 The format of the opcode table is:
1486 NAME OPCODE MASK FLAGS { OPERANDS }
1488 NAME is the name of the instruction.
1489 OPCODE is the instruction opcode.
1490 MASK is the opcode mask; this is used to tell the disassembler
1491 which bits in the actual opcode must match OPCODE.
1492 FLAGS are flags indicated what processors support the instruction.
1493 OPERANDS is the list of operands.
1495 The disassembler reads the table in order and prints the first
1496 instruction which matches, so this table is sorted to put more
1497 specific instructions before more general instructions. It is also
1498 sorted by major opcode. */
1500 const struct powerpc_opcode powerpc_opcodes[] = {
1501 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1502 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1503 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1504 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1505 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1506 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1507 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1508 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1509 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1510 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1511 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1512 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1513 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1514 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1515 { "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1517 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1518 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1519 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1520 { "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1521 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1522 { "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1523 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1524 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1525 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1526 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1527 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1528 { "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1529 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1530 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1531 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1532 { "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1533 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1534 { "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1535 { "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1536 { "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1537 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1538 { "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1539 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1540 { "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1541 { "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1542 { "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1543 { "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1544 { "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1545 { "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1546 { "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1548 { "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1549 { "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1551 { "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1552 { "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1554 { "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
1556 { "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1557 { "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1558 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1559 { "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1561 { "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1562 { "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1563 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1564 { "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1566 { "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1567 { "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1568 { "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1570 { "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1571 { "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1572 { "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1574 { "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1575 { "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1576 { "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1577 { "cal", OP(14), OP_MASK, POWER, { RT, D, RA } },
1578 { "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1579 { "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1581 { "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
1582 { "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
1583 { "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
1584 { "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
1585 { "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1587 { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1588 { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1589 { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
1590 { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
1591 { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1592 { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1593 { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
1594 { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
1595 { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1596 { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1597 { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
1598 { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
1599 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1600 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1601 { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
1602 { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
1603 { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1604 { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1605 { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1606 { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1607 { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1608 { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1609 { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1610 { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1611 { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1612 { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1613 { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1614 { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1615 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1616 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1617 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1618 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1619 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1620 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1621 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1622 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1623 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1624 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1625 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1626 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1627 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1628 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1629 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1630 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1631 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1632 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1633 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1634 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1635 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1636 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1637 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1638 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1639 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1640 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1641 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1642 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1643 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1644 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1645 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1646 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1647 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1648 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1649 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1650 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1651 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1652 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1653 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1654 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1655 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1656 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1657 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1658 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1659 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1660 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1661 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1662 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1663 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1664 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1665 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1666 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1667 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1668 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1669 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1670 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1671 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1672 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1673 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1674 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1675 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1676 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1677 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1678 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1679 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1680 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1681 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1682 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1683 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1684 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1685 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1686 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1687 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1688 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1689 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1690 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1691 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1692 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1693 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1694 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1695 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1696 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1697 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1698 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1699 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1700 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1701 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1702 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1703 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1704 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1705 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1706 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1707 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1708 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1709 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1710 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1711 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1712 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1713 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1714 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1715 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1716 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1717 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1718 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1719 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1720 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1721 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1722 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1723 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1724 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1725 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1726 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1727 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1728 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1729 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1730 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1731 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1732 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1733 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1734 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1735 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1736 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1737 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1738 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1739 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1740 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1741 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1742 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1743 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1744 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1745 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1746 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1747 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1748 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1749 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1750 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1751 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1752 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1753 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1754 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1755 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1756 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1757 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1758 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1759 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1760 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1761 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1762 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1763 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1764 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1765 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1766 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1767 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1768 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1769 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1770 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1771 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1772 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1773 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1774 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1775 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1776 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1777 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1778 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1779 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1780 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1781 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1782 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1783 { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1784 { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1785 { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1786 { "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1787 { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1788 { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1789 { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1790 { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1791 { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1792 { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1793 { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1794 { "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1795 { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1796 { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1797 { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1798 { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1799 { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1800 { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1801 { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1802 { "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1803 { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1804 { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1805 { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1806 { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1807 { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1808 { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1809 { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1810 { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1811 { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1812 { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1813 { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1814 { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1815 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1816 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1817 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1818 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1819 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1820 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1821 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1822 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1823 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1824 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1825 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1826 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1827 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1828 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1829 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1830 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1831 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1832 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1833 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1834 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1835 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1836 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1837 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1838 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1839 { "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1840 { "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1841 { "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1842 { "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1843 { "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1844 { "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1845 { "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1846 { "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1847 { "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1848 { "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1849 { "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1850 { "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1852 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1853 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1854 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1855 { "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1856 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1858 { "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1859 { "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1860 { "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1861 { "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1863 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1865 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1866 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1867 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1868 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1869 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1870 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1871 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1872 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1873 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1874 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1875 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1876 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1877 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1878 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1879 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1880 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1881 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1882 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1883 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1884 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1885 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1886 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1887 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1888 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1889 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1890 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1891 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1892 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1893 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1894 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1895 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1896 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1897 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1898 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1899 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1900 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1901 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1902 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1903 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1904 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1905 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1906 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1907 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1908 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1909 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1910 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1911 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1912 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1913 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1914 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1915 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1916 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1917 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1918 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1919 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1920 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1921 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1922 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1923 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1924 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1925 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1926 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1927 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1928 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1929 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1930 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1931 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1932 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1933 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1934 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1935 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1936 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1937 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1938 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1939 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1940 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1941 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1942 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1943 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1944 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1945 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1946 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1947 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1948 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1949 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1950 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1951 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1952 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1953 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1954 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1955 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1956 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1957 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1958 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1959 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1960 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1961 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1962 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1963 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1964 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1965 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1966 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1967 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1968 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1969 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1970 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1971 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1972 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1973 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1974 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1975 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1976 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1977 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1978 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1979 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1980 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1981 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1982 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1983 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1984 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1985 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1986 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1987 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1988 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1989 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1990 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1991 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1992 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1993 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1994 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1995 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1996 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1997 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1998 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1999 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
2000 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
2001 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
2002 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
2003 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
2004 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
2005 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
2006 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
2007 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
2008 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
2009 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
2010 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
2011 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
2012 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
2013 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
2014 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
2015 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
2016 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
2017 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
2018 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
2019 { "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
2020 { "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
2022 { "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
2023 { "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
2025 { "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
2026 { "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
2028 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2030 { "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
2032 { "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
2033 { "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
2035 { "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
2036 { "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
2038 { "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
2040 { "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
2042 { "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
2043 { "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
2045 { "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
2047 { "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
2048 { "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
2050 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
2051 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
2052 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2053 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2054 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2055 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2056 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2057 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2058 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2059 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2060 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2061 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2062 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2063 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2064 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2065 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2066 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2067 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2068 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2069 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2070 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2071 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2072 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2073 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2074 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2075 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2076 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2077 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2078 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2079 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2080 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2081 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2082 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2083 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2084 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2085 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2086 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2087 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2088 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2089 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2090 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2091 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2092 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2093 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2094 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2095 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2096 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2097 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2098 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2099 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2100 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2101 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2102 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2103 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2104 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2105 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2106 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2107 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2108 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2109 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2110 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2111 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2112 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2113 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2114 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2115 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2116 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2117 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2118 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2119 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2120 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2121 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2122 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2123 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2124 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
2125 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
2126 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
2127 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
2128 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
2129 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
2130 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
2131 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
2132 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
2133 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
2134 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
2135 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
2136 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
2137 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
2138 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
2139 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
2140 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
2141 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
2142 { "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
2143 { "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
2145 { "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2146 { "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2148 { "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2149 { "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2151 { "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
2152 { "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
2153 { "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2154 { "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2155 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
2156 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
2157 { "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2158 { "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2160 { "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
2161 { "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
2163 { "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
2164 { "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
2165 { "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
2166 { "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
2167 { "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
2168 { "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
2170 { "nop", OP(24), 0xffffffff, PPC, { 0 } },
2171 { "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
2172 { "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
2174 { "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
2175 { "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
2177 { "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
2178 { "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
2180 { "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
2181 { "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
2183 { "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
2184 { "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
2186 { "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
2187 { "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
2189 { "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
2190 { "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
2191 { "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2192 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
2193 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
2194 { "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2196 { "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
2197 { "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
2199 { "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2200 { "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2202 { "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2203 { "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2205 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
2206 { "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
2207 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
2208 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
2210 { "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
2211 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
2213 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
2214 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
2215 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
2216 { "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
2218 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
2219 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
2220 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
2221 { "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
2222 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
2223 { "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
2224 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
2225 { "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
2226 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
2227 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
2228 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
2229 { "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
2230 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
2231 { "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
2232 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
2233 { "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
2234 { "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
2235 { "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
2236 { "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
2237 { "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
2238 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
2239 { "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
2240 { "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
2241 { "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
2242 { "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
2243 { "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
2244 { "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
2245 { "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
2246 { "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
2247 { "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
2248 { "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
2250 { "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
2251 { "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
2252 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2253 { "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
2254 { "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
2255 { "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
2256 { "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
2257 { "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
2258 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2259 { "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
2260 { "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
2261 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2263 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2264 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2266 { "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
2267 { "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
2268 { "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
2269 { "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
2270 { "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
2271 { "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
2272 { "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
2273 { "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
2275 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2276 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2278 { "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
2280 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2282 { "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
2284 { "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
2285 { "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
2287 { "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
2288 { "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
2289 { "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
2290 { "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
2292 { "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
2293 { "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
2294 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
2295 { "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
2297 { "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
2298 { "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
2300 { "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2301 { "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2303 { "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
2304 { "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
2306 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
2307 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
2308 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
2309 { "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
2311 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2312 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2313 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2314 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2315 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2316 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2317 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2318 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2320 { "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
2322 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2324 { "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
2325 { "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
2327 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
2328 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
2330 { "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2331 { "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2333 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
2334 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
2335 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
2336 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
2337 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
2338 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
2339 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
2340 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
2341 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
2342 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
2343 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
2344 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
2345 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
2346 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
2347 { "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2349 { "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2350 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2352 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2353 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2355 { "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
2357 { "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2359 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2361 { "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2363 { "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
2364 { "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
2365 { "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
2366 { "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
2368 { "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2369 { "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2370 { "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2371 { "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2373 { "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2375 { "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
2377 { "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2378 { "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2379 { "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2380 { "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2382 { "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
2383 { "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
2384 { "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
2385 { "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
2386 { "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
2387 { "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
2388 { "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
2389 { "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
2391 { "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
2392 { "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
2393 { "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } },
2394 { "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } },
2395 { "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } },
2396 { "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } },
2397 { "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
2398 { "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
2400 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
2401 { "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
2403 { "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
2405 { "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
2407 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2409 { "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
2410 { "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
2412 { "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
2413 { "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
2415 { "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
2416 { "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
2418 { "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
2420 { "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
2421 { "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
2423 { "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
2424 { "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
2426 { "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
2427 { "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
2428 { "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } },
2429 { "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } },
2430 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } },
2431 { "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } },
2432 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } },
2433 { "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } },
2435 { "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } },
2436 { "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } },
2437 { "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } },
2438 { "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } },
2439 { "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } },
2440 { "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } },
2441 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } },
2442 { "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } },
2444 { "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
2446 { "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
2448 { "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
2450 { "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
2451 { "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
2453 { "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
2454 { "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
2456 { "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
2457 { "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
2458 { "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } },
2459 { "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } },
2460 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } },
2461 { "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } },
2462 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } },
2463 { "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } },
2465 { "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2466 { "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2467 { "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2468 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2470 { "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } },
2471 { "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } },
2472 { "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } },
2473 { "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } },
2474 { "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } },
2475 { "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } },
2476 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } },
2477 { "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } },
2479 { "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } },
2480 { "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } },
2481 { "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } },
2482 { "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } },
2483 { "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } },
2484 { "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } },
2485 { "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } },
2486 { "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } },
2488 { "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } },
2489 { "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } },
2491 { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2493 { "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
2495 { "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
2496 { "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
2498 { "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2499 { "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2500 { "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2501 { "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2503 { "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
2504 { "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
2505 { "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } },
2506 { "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } },
2507 { "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } },
2508 { "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } },
2509 { "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
2510 { "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
2512 { "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
2513 { "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
2515 { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2517 { "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2519 { "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
2521 { "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2522 { "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2524 { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2525 { "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } },
2527 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2529 { "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
2531 { "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2532 { "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2534 { "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
2536 { "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2537 { "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2538 { "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2539 { "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2541 { "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
2542 { "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
2543 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
2544 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
2545 { "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
2546 { "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
2547 { "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
2548 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2549 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
2550 { "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
2551 { "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
2552 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2553 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
2554 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
2555 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
2556 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2557 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
2558 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2559 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2560 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2561 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2562 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2563 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2564 { "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2566 { "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2568 { "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2570 { "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
2572 { "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2573 { "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2574 { "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2575 { "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2577 { "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2578 { "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2579 { "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2580 { "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2582 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2584 { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2585 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2587 { "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
2589 { "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
2591 { "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2593 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2595 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2597 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2599 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2601 { "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2602 { "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2604 { "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2605 { "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2607 { "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } },
2609 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2611 { "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
2613 { "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2614 { "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2615 { "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2616 { "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2618 { "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
2620 { "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2621 { "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2622 { "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2623 { "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2625 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2626 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2627 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2628 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2630 { "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } },
2631 { "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
2632 { "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
2633 { "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
2634 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2635 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
2636 { "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
2637 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
2638 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
2639 { "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
2640 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2641 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
2642 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
2643 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
2644 { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2645 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
2646 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2647 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2648 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2649 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2650 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2651 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2652 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2653 { "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2655 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2657 { "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2658 { "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2660 { "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2661 { "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2662 { "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2663 { "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2665 { "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2666 { "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2667 { "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2668 { "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2670 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2671 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2672 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2673 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2675 { "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } },
2677 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2679 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
2681 { "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } },
2683 { "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2684 { "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2686 { "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2687 { "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2689 { "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2691 { "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2692 { "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2693 { "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2694 { "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2696 { "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
2697 { "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
2699 { "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2700 { "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2702 { "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
2703 { "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
2705 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2707 { "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2709 { "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2711 { "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2712 { "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2714 { "sync", X(31,598), 0xffffffff, PPC, { 0 } },
2715 { "dcs", X(31,598), 0xffffffff, POWER, { 0 } },
2717 { "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2719 { "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2721 { "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
2723 { "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2725 { "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
2727 { "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2728 { "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2730 { "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2731 { "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2733 { "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2735 { "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
2736 { "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
2738 { "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
2739 { "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
2741 { "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2743 { "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
2744 { "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
2746 { "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2747 { "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2749 { "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2751 { "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
2752 { "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
2754 { "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
2755 { "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
2757 { "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2759 { "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
2760 { "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
2762 { "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2764 { "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2765 { "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2766 { "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2767 { "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2769 { "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2770 { "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2772 { "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2774 { "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2775 { "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2776 { "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2777 { "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2779 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2781 { "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2783 { "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
2784 { "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
2786 { "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
2787 { "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
2789 { "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
2790 { "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
2791 { "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
2792 { "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
2794 { "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
2795 { "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
2797 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2798 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2800 { "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
2802 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2804 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2806 { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2807 { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2809 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2810 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2812 { "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
2813 { "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
2815 { "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
2816 { "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
2818 { "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
2820 { "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
2822 { "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
2823 { "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
2825 { "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
2826 { "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
2828 { "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
2830 { "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
2832 { "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
2834 { "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
2836 { "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
2838 { "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
2840 { "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
2842 { "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
2844 { "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
2845 { "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
2847 { "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
2848 { "stm", OP(47), OP_MASK, POWER, { RS, D, RA } },
2850 { "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
2852 { "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2854 { "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
2856 { "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2858 { "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
2860 { "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2862 { "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
2864 { "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2866 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
2868 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
2870 { "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
2872 { "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
2874 { "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
2876 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2877 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2879 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2880 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2882 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2883 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2885 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2886 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2888 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2889 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2891 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2892 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2894 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2895 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2897 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2898 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2900 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2901 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2903 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2904 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2906 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
2908 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
2910 { "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
2912 { "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
2914 { "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2916 { "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2917 { "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2919 { "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
2920 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
2921 { "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
2922 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
2924 { "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
2925 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
2926 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
2927 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
2929 { "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2930 { "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2931 { "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2932 { "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2934 { "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2935 { "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2936 { "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2937 { "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2939 { "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2940 { "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2941 { "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2942 { "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2944 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2945 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2947 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2948 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2950 { "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2951 { "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2952 { "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2953 { "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2955 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2956 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2958 { "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2959 { "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2960 { "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2961 { "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2963 { "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2964 { "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2965 { "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2966 { "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2968 { "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2969 { "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2970 { "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2971 { "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2973 { "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2974 { "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2975 { "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2976 { "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2978 { "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2980 { "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } },
2981 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } },
2983 { "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2984 { "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2986 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2988 { "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } },
2989 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } },
2991 { "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2992 { "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2994 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2995 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2997 { "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2998 { "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
3000 { "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
3001 { "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
3003 { "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } },
3004 { "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } },
3006 { "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } },
3007 { "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } },
3009 { "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } },
3010 { "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } },
3012 { "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } },
3013 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } },
3015 { "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } },
3016 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } },
3020 const int powerpc_num_opcodes =
3021 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3023 /* The macro table. This is only used by the assembler. */
3025 const struct powerpc_macro powerpc_macros[] = {
3026 { "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" },
3027 { "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" },
3028 { "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3029 { "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3030 { "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
3031 { "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3032 { "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" },
3033 { "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" },
3034 { "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" },
3035 { "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" },
3036 { "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" },
3037 { "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" },
3038 { "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" },
3039 { "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" },
3040 { "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" },
3041 { "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" },
3043 { "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" },
3044 { "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" },
3045 { "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3046 { "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3047 { "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
3048 { "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
3049 { "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3050 { "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3051 { "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" },
3052 { "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" },
3053 { "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" },
3054 { "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" },
3055 { "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" },
3056 { "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" },
3057 { "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" },
3058 { "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" },
3059 { "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" },
3060 { "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" },
3061 { "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" },
3062 { "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" },
3063 { "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3064 { "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3068 const int powerpc_num_macros =
3069 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
3071 static int
3072 print_insn_powerpc (disassemble_info *info, uint32_t insn, unsigned memaddr,
3073 int dialect);
3075 /* Print a big endian PowerPC instruction. For convenience, also
3076 disassemble instructions supported by the Motorola PowerPC 601. */
3078 int print_insn_ppc (bfd_vma pc, disassemble_info *info)
3080 uint32_t opc;
3081 bfd_byte buf[4];
3083 (*info->read_memory_func)(pc, buf, 4, info);
3084 if (info->endian == BFD_ENDIAN_BIG)
3085 opc = bfd_getb32(buf);
3086 else
3087 opc = bfd_getl32(buf);
3088 if (info->mach == bfd_mach_ppc64) {
3089 return print_insn_powerpc (info, opc, pc,
3090 PPC | B64);
3091 } else {
3092 return print_insn_powerpc (info, opc, pc,
3093 PPC | B32 | M601);
3097 /* Print a PowerPC or POWER instruction. */
3099 static int
3100 print_insn_powerpc (disassemble_info *info, uint32_t insn, unsigned memaddr,
3101 int dialect)
3103 const struct powerpc_opcode *opcode;
3104 const struct powerpc_opcode *opcode_end;
3105 uint32_t op;
3107 /* Get the major opcode of the instruction. */
3108 op = PPC_OP (insn);
3110 /* Find the first match in the opcode table. We could speed this up
3111 a bit by doing a binary search on the major opcode. */
3112 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
3113 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
3115 uint32_t table_op;
3116 const unsigned char *opindex;
3117 const struct powerpc_operand *operand;
3118 int invalid;
3119 int need_comma;
3120 int need_paren;
3122 table_op = PPC_OP (opcode->opcode);
3123 if (op < table_op)
3124 break;
3125 if (op > table_op)
3126 continue;
3128 if ((insn & opcode->mask) != opcode->opcode
3129 || (opcode->flags & dialect) == 0)
3130 continue;
3132 /* Make two passes over the operands. First see if any of them
3133 have extraction functions, and, if they do, make sure the
3134 instruction is valid. */
3135 invalid = 0;
3136 for (opindex = opcode->operands; *opindex != 0; opindex++)
3138 operand = powerpc_operands + *opindex;
3139 if (operand->extract)
3140 (*operand->extract) (insn, &invalid);
3142 if (invalid)
3143 continue;
3145 /* The instruction is valid. */
3146 (*info->fprintf_func)(info->stream, "%s", opcode->name);
3147 if (opcode->operands[0] != 0)
3148 (*info->fprintf_func)(info->stream, "\t");
3150 /* Now extract and print the operands. */
3151 need_comma = 0;
3152 need_paren = 0;
3153 for (opindex = opcode->operands; *opindex != 0; opindex++)
3155 int32_t value;
3157 operand = powerpc_operands + *opindex;
3159 /* Operands that are marked FAKE are simply ignored. We
3160 already made sure that the extract function considered
3161 the instruction to be valid. */
3162 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
3163 continue;
3165 /* Extract the value from the instruction. */
3166 if (operand->extract)
3167 value = (*operand->extract) (insn, (int *) 0);
3168 else
3170 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
3171 if ((operand->flags & PPC_OPERAND_SIGNED) != 0
3172 && (value & (1 << (operand->bits - 1))) != 0)
3173 value -= 1 << operand->bits;
3176 /* If the operand is optional, and the value is zero, don't
3177 print anything. */
3178 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
3179 && (operand->flags & PPC_OPERAND_NEXT) == 0
3180 && value == 0)
3181 continue;
3183 if (need_comma)
3185 (*info->fprintf_func)(info->stream, ",");
3186 need_comma = 0;
3189 /* Print the operand as directed by the flags. */
3190 if ((operand->flags & PPC_OPERAND_GPR) != 0)
3191 (*info->fprintf_func)(info->stream, "r%d", value);
3192 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
3193 (*info->fprintf_func)(info->stream, "f%d", value);
3194 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
3195 (*info->fprintf_func)(info->stream, "%08X", memaddr + value);
3196 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
3197 (*info->fprintf_func)(info->stream, "%08X", value & 0xffffffff);
3198 else if ((operand->flags & PPC_OPERAND_CR) == 0
3199 || (dialect & PPC_OPCODE_PPC) == 0)
3200 (*info->fprintf_func)(info->stream, "%d", value);
3201 else
3203 if (operand->bits == 3)
3204 (*info->fprintf_func)(info->stream, "cr%d", value);
3205 else
3207 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
3208 int cr;
3209 int cc;
3211 cr = value >> 2;
3212 if (cr != 0)
3213 (*info->fprintf_func)(info->stream, "4*cr%d", cr);
3214 cc = value & 3;
3215 if (cc != 0)
3217 if (cr != 0)
3218 (*info->fprintf_func)(info->stream, "+");
3219 (*info->fprintf_func)(info->stream, "%s", cbnames[cc]);
3224 if (need_paren)
3226 (*info->fprintf_func)(info->stream, ")");
3227 need_paren = 0;
3230 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
3231 need_comma = 1;
3232 else
3234 (*info->fprintf_func)(info->stream, "(");
3235 need_paren = 1;
3239 /* We have found and printed an instruction; return. */
3240 return 4;
3243 /* We could not find a match. */
3244 (*info->fprintf_func)(info->stream, ".long 0x%x", insn);
3246 return 4;