2 * QEMU ETRAX Interrupt Controller.
4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 /* Active interrupt lines. */
38 /* Active lines, gated through the mask. */
39 uint32_t r_masked_vect
;
44 static uint32_t pic_readb (void *opaque
, target_phys_addr_t addr
)
48 static uint32_t pic_readw (void *opaque
, target_phys_addr_t addr
)
53 static uint32_t pic_readl (void *opaque
, target_phys_addr_t addr
)
55 struct fs_pic_state_t
*fs
= opaque
;
67 rval
= fs
->r_masked_vect
;
76 cpu_abort(fs
->env
, "invalid PIC register.\n");
80 D(printf("%s %x=%x\n", __func__
, addr
, rval
));
85 pic_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
90 pic_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
95 pic_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
97 struct fs_pic_state_t
*fs
= opaque
;
98 D(printf("%s addr=%x val=%x\n", __func__
, addr
, value
));
108 fs
->r_masked_vect
= value
;
117 cpu_abort(fs
->env
, "invalid PIC register.\n");
122 static CPUReadMemoryFunc
*pic_read
[] = {
128 static CPUWriteMemoryFunc
*pic_write
[] = {
142 static void irq_handler(void *opaque
, int irq
, int level
)
144 struct fs_pic_state_t
*fs
= (void *)opaque
;
145 CPUState
*env
= fs
->env
;
149 D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n",
150 __func__
, irq
, level
,
151 fs
->rw_mask
, fs
->r_vect
, fs
->r_masked_vect
));
154 fs
->r_vect
&= ~(1 << irq
);
155 fs
->r_vect
|= (!!level
<< irq
);
156 fs
->r_masked_vect
= fs
->r_vect
& fs
->rw_mask
;
158 /* The ETRAX interrupt controller signals interrupts to teh core
159 through an interrupt request wire and an irq vector bus. If
160 multiple interrupts are simultaneously active it chooses vector
161 0x30 and lets the sw choose the priorities. */
162 if (fs
->r_masked_vect
) {
163 uint32_t mv
= fs
->r_masked_vect
;
164 for (i
= 0; i
< 31; i
++) {
167 /* Check for multiple interrupts. */
175 env
->interrupt_vector
= vector
;
176 D(printf("%s vector=%x\n", __func__
, vector
));
177 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
180 env
->interrupt_vector
= 0;
181 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
182 D(printf("%s reset irqs\n", __func__
));
186 static void nmi_handler(void *opaque
, int irq
, int level
)
188 struct fs_pic_state_t
*fs
= (void *)opaque
;
189 CPUState
*env
= fs
->env
;
199 cpu_interrupt(env
, CPU_INTERRUPT_NMI
);
201 cpu_reset_interrupt(env
, CPU_INTERRUPT_NMI
);
204 static void guru_handler(void *opaque
, int irq
, int level
)
206 struct fs_pic_state_t
*fs
= (void *)opaque
;
207 CPUState
*env
= fs
->env
;
208 cpu_abort(env
, "%s unsupported exception\n", __func__
);
213 struct etraxfs_pic
*etraxfs_pic_init(CPUState
*env
, target_phys_addr_t base
)
215 struct fs_pic_state_t
*fs
= NULL
;
216 struct etraxfs_pic
*pic
= NULL
;
219 pic
= qemu_mallocz(sizeof *pic
);
220 pic
->internal
= fs
= qemu_mallocz(sizeof *fs
);
225 pic
->irq
= qemu_allocate_irqs(irq_handler
, fs
, 30);
226 pic
->nmi
= qemu_allocate_irqs(nmi_handler
, fs
, 2);
227 pic
->guru
= qemu_allocate_irqs(guru_handler
, fs
, 1);
229 intr_vect_regs
= cpu_register_io_memory(0, pic_read
, pic_write
, fs
);
230 cpu_register_physical_memory(base
, 0x14, intr_vect_regs
);