hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 /* PCI includes legacy ISA access.  */
   5 #include "isa.h"
   6
   7 /* PCI bus */
   8
   9 extern target_phys_addr_t pci_mem_base;
  10
  11 #define PCI_VENDOR_ID_LSI_LOGIC          0x1000
  12 #define PCI_DEVICE_ID_LSI_53C895A        0x0012
  13
  14 #define PCI_VENDOR_ID_DEC                0x1011
  15
  16 #define PCI_VENDOR_ID_CIRRUS             0x1013
  17
  18 #define PCI_VENDOR_ID_IBM                0x1014
  19
  20 #define PCI_VENDOR_ID_AMD                0x1022
  21 #define PCI_DEVICE_ID_AMD_LANCE          0x2000
  22
  23 #define PCI_VENDOR_ID_HITACHI            0x1054
  24
  25 #define PCI_VENDOR_ID_MOTOROLA           0x1057
  26 #define PCI_DEVICE_ID_MOTOROLA_MPC106    0x0002
  27 #define PCI_DEVICE_ID_MOTOROLA_RAVEN     0x4801
  28
  29 #define PCI_VENDOR_ID_APPLE              0x106b
  30 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP    0x0020
  31
  32 #define PCI_VENDOR_ID_SUN                0x108e
  33 #define PCI_DEVICE_ID_SUN_EBUS           0x1000
  34 #define PCI_DEVICE_ID_SUN_SIMBA          0x5000
  35 #define PCI_DEVICE_ID_SUN_SABRE          0xa000
  36
  37 #define PCI_VENDOR_ID_CMD                0x1095
  38 #define PCI_DEVICE_ID_CMD_646            0x0646
  39
  40 #define PCI_VENDOR_ID_REALTEK            0x10ec
  41 #define PCI_DEVICE_ID_REALTEK_8139       0x8139
  42
  43 #define PCI_VENDOR_ID_XILINX             0x10ee
  44
  45 #define PCI_VENDOR_ID_MARVELL            0x11ab
  46
  47 #define PCI_VENDOR_ID_ENSONIQ            0x1274
  48 #define PCI_DEVICE_ID_ENSONIQ_ES1370     0x5000
  49
  50 #define PCI_VENDOR_ID_VMWARE             0x15ad
  51 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  52 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  53 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  54 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  55 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  56
  57 #define PCI_VENDOR_ID_INTEL              0x8086
  58 #define PCI_DEVICE_ID_INTEL_82441        0x1237
  59 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
  60 #define PCI_DEVICE_ID_INTEL_82371SB_0    0x7000
  61 #define PCI_DEVICE_ID_INTEL_82371SB_1    0x7010
  62 #define PCI_DEVICE_ID_INTEL_82371SB_2    0x7020
  63 #define PCI_DEVICE_ID_INTEL_82371AB_0    0x7110
  64 #define PCI_DEVICE_ID_INTEL_82371AB      0x7111
  65 #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
  66 #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
  67
  68 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  69 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  70 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  71 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  72
  73 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  74 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  75 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  76 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  77
  78 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  79                                 uint32_t address, uint32_t data, int len);
  80 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  81                                    uint32_t address, int len);
  82 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  83                                 uint32_t addr, uint32_t size, int type);
  84
  85 #define PCI_ADDRESS_SPACE_MEM           0x00
  86 #define PCI_ADDRESS_SPACE_IO            0x01
  87 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  88
  89 typedef struct PCIIORegion {
  90     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  91     uint32_t size;
  92     uint8_t type;
  93     PCIMapIORegionFunc *map_func;
  94 } PCIIORegion;
  95
  96 #define PCI_ROM_SLOT 6
  97 #define PCI_NUM_REGIONS 7
  98
  99 #define PCI_DEVICES_MAX 64
 100
 101 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 102 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 103 #define PCI_COMMAND             0x04    /* 16 bits */
 104 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 105 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 106 #define PCI_REVISION            0x08
 107 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 108 #define PCI_SUBVENDOR_ID        0x2c    /* 16 bits */
 109 #define PCI_SUBDEVICE_ID        0x2e    /* 16 bits */
 110 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 111 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 112 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 113 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 114
 115 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 116 #define PCI_STATUS_RESERVED1    0x007
 117 #define PCI_STATUS_INT_STATUS   0x008
 118 #define PCI_STATUS_CAPABILITIES 0x010
 119 #define PCI_STATUS_66MHZ        0x020
 120 #define PCI_STATUS_RESERVED2    0x040
 121 #define PCI_STATUS_FAST_BACK    0x080
 122 #define PCI_STATUS_DEVSEL       0x600
 123
 124 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 125                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 126                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 127
 128 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 129
 130 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 131 #define PCI_COMMAND_RESERVED    0xf800
 132
 133 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 134
 135 struct PCIDevice {
 136     /* PCI config space */
 137     uint8_t config[256];
 138
 139     /* the following fields are read only */
 140     PCIBus *bus;
 141     int devfn;
 142     char name[64];
 143     PCIIORegion io_regions[PCI_NUM_REGIONS];
 144
 145     /* do not access the following fields */
 146     PCIConfigReadFunc *config_read;
 147     PCIConfigWriteFunc *config_write;
 148     /* ??? This is a PC-specific hack, and should be removed.  */
 149     int irq_index;
 150
 151     /* IRQ objects for the INTA-INTD pins.  */
 152     qemu_irq *irq;
 153
 154     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 155     int irq_state[4];
 156 };
 157
 158 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 159                                int instance_size, int devfn,
 160                                PCIConfigReadFunc *config_read,
 161                                PCIConfigWriteFunc *config_write);
 162
 163 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 164                             uint32_t size, int type,
 165                             PCIMapIORegionFunc *map_func);
 166
 167 uint32_t pci_default_read_config(PCIDevice *d,
 168                                  uint32_t address, int len);
 169 void pci_default_write_config(PCIDevice *d,
 170                               uint32_t address, uint32_t val, int len);
 171 void pci_device_save(PCIDevice *s, QEMUFile *f);
 172 int pci_device_load(PCIDevice *s, QEMUFile *f);
 173
 174 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 175 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 176 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 177                          qemu_irq *pic, int devfn_min, int nirq);
 178
 179 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 180                   const char *default_model);
 181 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 182 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 183 int pci_bus_num(PCIBus *s);
 184 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 185
 186 void pci_info(void);
 187 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 188                         pci_map_irq_fn map_irq, const char *name);
 189
 190 static inline void
 191 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 192 {
 193     cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
 194 }
 195
 196 static inline void
 197 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 198 {
 199     cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
 200 }
 201
 202 /* lsi53c895a.c */
 203 #define LSI_MAX_DEVS 7
 204 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
 205 void *lsi_scsi_init(PCIBus *bus, int devfn);
 206
 207 /* vmware_vga.c */
 208 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
 209                      unsigned long vga_ram_offset, int vga_ram_size);
 210
 211 /* usb-uhci.c */
 212 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 213 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 214
 215 /* usb-ohci.c */
 216 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 217
 218 /* eepro100.c */
 219
 220 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 221 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 222 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 223
 224 /* ne2000.c */
 225
 226 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 227
 228 /* rtl8139.c */
 229
 230 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 231
 232 /* e1000.c */
 233 void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
 234
 235 /* pcnet.c */
 236 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 237
 238 /* prep_pci.c */
 239 PCIBus *pci_prep_init(qemu_irq *pic);
 240
 241 /* apb_pci.c */
 242 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 243                      target_phys_addr_t mem_base,
 244                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 245
 246 /* sh_pci.c */
 247 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 248                             qemu_irq *pic, int devfn_min, int nirq);
 249
 250 #endif