2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
62 static const int tcg_target_reg_alloc_order
[] = {
78 static const int tcg_target_call_iarg_regs
[6] = {
87 static const int tcg_target_call_oarg_regs
[2] = {
92 static inline int check_fit_tl(tcg_target_long val
, unsigned int bits
)
94 return (val
<< ((sizeof(tcg_target_long
) * 8 - bits
))
95 >> (sizeof(tcg_target_long
) * 8 - bits
)) == val
;
98 static inline int check_fit_i32(uint32_t val
, unsigned int bits
)
100 return ((val
<< (32 - bits
)) >> (32 - bits
)) == val
;
103 static void patch_reloc(uint8_t *code_ptr
, int type
,
104 tcg_target_long value
, tcg_target_long addend
)
109 if (value
!= (uint32_t)value
)
111 *(uint32_t *)code_ptr
= value
;
113 case R_SPARC_WDISP22
:
114 value
-= (long)code_ptr
;
116 if (!check_fit_tl(value
, 22))
118 *(uint32_t *)code_ptr
= ((*(uint32_t *)code_ptr
) & ~0x3fffff) | value
;
125 /* maximum number of register used for input function arguments */
126 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
131 /* parse target specific constraints */
132 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
139 case 'L': /* qemu_ld/st constraint */
140 ct
->ct
|= TCG_CT_REG
;
141 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
143 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_O0
);
144 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_O1
);
145 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_O2
);
148 ct
->ct
|= TCG_CT_CONST_S11
;
151 ct
->ct
|= TCG_CT_CONST_S13
;
161 /* test if a constant matches the constraint */
162 static inline int tcg_target_const_match(tcg_target_long val
,
163 const TCGArgConstraint
*arg_ct
)
168 if (ct
& TCG_CT_CONST
)
170 else if ((ct
& TCG_CT_CONST_S11
) && check_fit_tl(val
, 11))
172 else if ((ct
& TCG_CT_CONST_S13
) && check_fit_tl(val
, 13))
178 #define INSN_OP(x) ((x) << 30)
179 #define INSN_OP2(x) ((x) << 22)
180 #define INSN_OP3(x) ((x) << 19)
181 #define INSN_OPF(x) ((x) << 5)
182 #define INSN_RD(x) ((x) << 25)
183 #define INSN_RS1(x) ((x) << 14)
184 #define INSN_RS2(x) (x)
185 #define INSN_ASI(x) ((x) << 5)
187 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
188 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
190 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
207 #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
209 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
210 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
211 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
212 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
213 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
214 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
215 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
216 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
217 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
218 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
219 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
220 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
221 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
222 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
223 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
225 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
226 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
227 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
229 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
230 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
231 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
233 #define WRY (INSN_OP(2) | INSN_OP3(0x30))
234 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
235 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
236 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
237 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
238 #define CALL INSN_OP(1)
239 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
240 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
241 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
242 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
243 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
244 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
245 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
246 #define STB (INSN_OP(3) | INSN_OP3(0x05))
247 #define STH (INSN_OP(3) | INSN_OP3(0x06))
248 #define STW (INSN_OP(3) | INSN_OP3(0x04))
249 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
250 #define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
251 #define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
252 #define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
253 #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
254 #define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
255 #define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
256 #define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
257 #define STBA (INSN_OP(3) | INSN_OP3(0x15))
258 #define STHA (INSN_OP(3) | INSN_OP3(0x16))
259 #define STWA (INSN_OP(3) | INSN_OP3(0x14))
260 #define STXA (INSN_OP(3) | INSN_OP3(0x1e))
262 #ifndef ASI_PRIMARY_LITTLE
263 #define ASI_PRIMARY_LITTLE 0x88
266 static inline void tcg_out_arith(TCGContext
*s
, int rd
, int rs1
, int rs2
,
269 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
273 static inline void tcg_out_arithi(TCGContext
*s
, int rd
, int rs1
,
274 uint32_t offset
, int op
)
276 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
280 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
282 tcg_out_arith(s
, ret
, arg
, TCG_REG_G0
, ARITH_OR
);
285 static inline void tcg_out_sethi(TCGContext
*s
, int ret
, uint32_t arg
)
287 tcg_out32(s
, SETHI
| INSN_RD(ret
) | ((arg
& 0xfffffc00) >> 10));
290 static inline void tcg_out_movi_imm13(TCGContext
*s
, int ret
, uint32_t arg
)
292 tcg_out_arithi(s
, ret
, TCG_REG_G0
, arg
, ARITH_OR
);
295 static inline void tcg_out_movi_imm32(TCGContext
*s
, int ret
, uint32_t arg
)
297 if (check_fit_tl(arg
, 12))
298 tcg_out_movi_imm13(s
, ret
, arg
);
300 tcg_out_sethi(s
, ret
, arg
);
302 tcg_out_arithi(s
, ret
, ret
, arg
& 0x3ff, ARITH_OR
);
306 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
307 int ret
, tcg_target_long arg
)
309 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
310 if (!check_fit_tl(arg
, 32) && (arg
& ~0xffffffffULL
) != 0) {
311 tcg_out_movi_imm32(s
, TCG_REG_I4
, arg
>> 32);
312 tcg_out_arithi(s
, TCG_REG_I4
, TCG_REG_I4
, 32, SHIFT_SLLX
);
313 tcg_out_movi_imm32(s
, ret
, arg
);
314 tcg_out_arith(s
, ret
, ret
, TCG_REG_I4
, ARITH_OR
);
315 } else if (check_fit_tl(arg
, 12))
316 tcg_out_movi_imm13(s
, ret
, arg
);
318 tcg_out_sethi(s
, ret
, arg
);
320 tcg_out_arithi(s
, ret
, ret
, arg
& 0x3ff, ARITH_OR
);
323 tcg_out_movi_imm32(s
, ret
, arg
);
327 static inline void tcg_out_ld_raw(TCGContext
*s
, int ret
,
330 tcg_out_sethi(s
, ret
, arg
);
331 tcg_out32(s
, LDUW
| INSN_RD(ret
) | INSN_RS1(ret
) |
332 INSN_IMM13(arg
& 0x3ff));
335 static inline void tcg_out_ld_ptr(TCGContext
*s
, int ret
,
338 if (!check_fit_tl(arg
, 10))
339 tcg_out_movi(s
, TCG_TYPE_PTR
, ret
, arg
& ~0x3ffULL
);
340 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
341 tcg_out32(s
, LDX
| INSN_RD(ret
) | INSN_RS1(ret
) |
342 INSN_IMM13(arg
& 0x3ff));
344 tcg_out32(s
, LDUW
| INSN_RD(ret
) | INSN_RS1(ret
) |
345 INSN_IMM13(arg
& 0x3ff));
349 static inline void tcg_out_ldst(TCGContext
*s
, int ret
, int addr
, int offset
, int op
)
351 if (check_fit_tl(offset
, 13))
352 tcg_out32(s
, op
| INSN_RD(ret
) | INSN_RS1(addr
) |
355 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I5
, offset
);
356 tcg_out32(s
, op
| INSN_RD(ret
) | INSN_RS1(TCG_REG_I5
) |
361 static inline void tcg_out_ldst_asi(TCGContext
*s
, int ret
, int addr
,
362 int offset
, int op
, int asi
)
364 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I5
, offset
);
365 tcg_out32(s
, op
| INSN_RD(ret
) | INSN_RS1(TCG_REG_I5
) |
366 INSN_ASI(asi
) | INSN_RS2(addr
));
369 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int ret
,
370 int arg1
, tcg_target_long arg2
)
372 if (type
== TCG_TYPE_I32
)
373 tcg_out_ldst(s
, ret
, arg1
, arg2
, LDUW
);
375 tcg_out_ldst(s
, ret
, arg1
, arg2
, LDX
);
378 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
379 int arg1
, tcg_target_long arg2
)
381 if (type
== TCG_TYPE_I32
)
382 tcg_out_ldst(s
, arg
, arg1
, arg2
, STW
);
384 tcg_out_ldst(s
, arg
, arg1
, arg2
, STX
);
387 static inline void tcg_out_sety(TCGContext
*s
, tcg_target_long val
)
389 if (val
== 0 || val
== -1)
390 tcg_out32(s
, WRY
| INSN_IMM13(val
));
392 fprintf(stderr
, "unimplemented sety %ld\n", (long)val
);
395 static inline void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
398 if (check_fit_tl(val
, 13))
399 tcg_out_arithi(s
, reg
, reg
, val
, ARITH_ADD
);
401 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I5
, val
);
402 tcg_out_arith(s
, reg
, reg
, TCG_REG_I5
, ARITH_ADD
);
407 static inline void tcg_out_andi(TCGContext
*s
, int reg
, tcg_target_long val
)
410 if (check_fit_tl(val
, 13))
411 tcg_out_arithi(s
, reg
, reg
, val
, ARITH_AND
);
413 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_I5
, val
);
414 tcg_out_arith(s
, reg
, reg
, TCG_REG_I5
, ARITH_AND
);
419 static inline void tcg_out_nop(TCGContext
*s
)
421 tcg_out_sethi(s
, TCG_REG_G0
, 0);
424 static void tcg_out_branch(TCGContext
*s
, int opc
, int label_index
)
427 TCGLabel
*l
= &s
->labels
[label_index
];
430 val
= l
->u
.value
- (tcg_target_long
)s
->code_ptr
;
431 tcg_out32(s
, (INSN_OP(0) | INSN_COND(opc
, 0) | INSN_OP2(0x2)
432 | INSN_OFF22(l
->u
.value
- (unsigned long)s
->code_ptr
)));
434 tcg_out_reloc(s
, s
->code_ptr
, R_SPARC_WDISP22
, label_index
, 0);
435 tcg_out32(s
, (INSN_OP(0) | INSN_COND(opc
, 0) | INSN_OP2(0x2) | 0));
439 static const uint8_t tcg_cond_to_bcond
[10] = {
440 [TCG_COND_EQ
] = COND_E
,
441 [TCG_COND_NE
] = COND_NE
,
442 [TCG_COND_LT
] = COND_L
,
443 [TCG_COND_GE
] = COND_GE
,
444 [TCG_COND_LE
] = COND_LE
,
445 [TCG_COND_GT
] = COND_G
,
446 [TCG_COND_LTU
] = COND_CS
,
447 [TCG_COND_GEU
] = COND_CC
,
448 [TCG_COND_LEU
] = COND_LEU
,
449 [TCG_COND_GTU
] = COND_GU
,
452 static void tcg_out_brcond(TCGContext
*s
, int cond
,
453 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
456 if (const_arg2
&& arg2
== 0)
457 /* orcc %g0, r, %g0 */
458 tcg_out_arith(s
, TCG_REG_G0
, TCG_REG_G0
, arg1
, ARITH_ORCC
);
460 /* subcc r1, r2, %g0 */
461 tcg_out_arith(s
, TCG_REG_G0
, arg1
, arg2
, ARITH_SUBCC
);
462 tcg_out_branch(s
, tcg_cond_to_bcond
[cond
], label_index
);
466 /* Generate global QEMU prologue and epilogue code */
467 void tcg_target_qemu_prologue(TCGContext
*s
)
469 tcg_out32(s
, SAVE
| INSN_RD(TCG_REG_O6
) | INSN_RS1(TCG_REG_O6
) |
470 INSN_IMM13(-TCG_TARGET_STACK_MINFRAME
));
471 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I0
) |
472 INSN_RS2(TCG_REG_G0
));
476 #if defined(CONFIG_SOFTMMU)
478 #include "../../softmmu_defs.h"
480 static const void * const qemu_ld_helpers
[4] = {
487 static const void * const qemu_st_helpers
[4] = {
495 #if TARGET_LONG_BITS == 32
496 #define TARGET_LD_OP LDUW
498 #define TARGET_LD_OP LDX
501 #if TARGET_PHYS_ADDR_BITS == 32
502 #define TARGET_ADDEND_LD_OP LDUW
504 #define TARGET_ADDEND_LD_OP LDX
508 #define HOST_LD_OP LDX
509 #define HOST_ST_OP STX
510 #define HOST_SLL_OP SHIFT_SLLX
511 #define HOST_SRA_OP SHIFT_SRAX
513 #define HOST_LD_OP LDUW
514 #define HOST_ST_OP STW
515 #define HOST_SLL_OP SHIFT_SLL
516 #define HOST_SRA_OP SHIFT_SRA
519 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
,
522 int addr_reg
, data_reg
, arg0
, arg1
, arg2
, mem_index
, s_bits
;
523 #if defined(CONFIG_SOFTMMU)
524 uint32_t *label1_ptr
, *label2_ptr
;
536 #if defined(CONFIG_SOFTMMU)
537 /* srl addr_reg, x, arg1 */
538 tcg_out_arithi(s
, arg1
, addr_reg
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
,
540 /* and addr_reg, x, arg0 */
541 tcg_out_arithi(s
, arg0
, addr_reg
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1),
544 /* and arg1, x, arg1 */
545 tcg_out_andi(s
, arg1
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
547 /* add arg1, x, arg1 */
548 tcg_out_addi(s
, arg1
, offsetof(CPUState
,
549 tlb_table
[mem_index
][0].addr_read
));
551 /* add env, arg1, arg1 */
552 tcg_out_arith(s
, arg1
, TCG_AREG0
, arg1
, ARITH_ADD
);
554 /* ld [arg1], arg2 */
555 tcg_out32(s
, TARGET_LD_OP
| INSN_RD(arg2
) | INSN_RS1(arg1
) |
556 INSN_RS2(TCG_REG_G0
));
558 /* subcc arg0, arg2, %g0 */
559 tcg_out_arith(s
, TCG_REG_G0
, arg0
, arg2
, ARITH_SUBCC
);
563 label1_ptr
= (uint32_t *)s
->code_ptr
;
566 /* mov (delay slot) */
567 tcg_out_mov(s
, arg0
, addr_reg
);
570 tcg_out_movi(s
, TCG_TYPE_I32
, arg1
, mem_index
);
572 /* XXX: move that code at the end of the TB */
573 /* qemu_ld_helper[s_bits](arg0, arg1) */
574 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)qemu_ld_helpers
[s_bits
]
575 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
577 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
580 tcg_out_ldst(s
, TCG_AREG0
, TCG_REG_CALL_STACK
,
581 TCG_TARGET_CALL_STACK_OFFSET
- sizeof(long), HOST_ST_OP
);
582 tcg_out_ldst(s
, TCG_AREG0
, TCG_REG_CALL_STACK
,
583 TCG_TARGET_CALL_STACK_OFFSET
- sizeof(long), HOST_LD_OP
);
585 /* data_reg = sign_extend(arg0) */
588 /* sll arg0, 24/56, data_reg */
589 tcg_out_arithi(s
, data_reg
, arg0
, (int)sizeof(tcg_target_long
) * 8 - 8,
591 /* sra data_reg, 24/56, data_reg */
592 tcg_out_arithi(s
, data_reg
, data_reg
,
593 (int)sizeof(tcg_target_long
) * 8 - 8, HOST_SRA_OP
);
596 /* sll arg0, 16/48, data_reg */
597 tcg_out_arithi(s
, data_reg
, arg0
,
598 (int)sizeof(tcg_target_long
) * 8 - 16, HOST_SLL_OP
);
599 /* sra data_reg, 16/48, data_reg */
600 tcg_out_arithi(s
, data_reg
, data_reg
,
601 (int)sizeof(tcg_target_long
) * 8 - 16, HOST_SRA_OP
);
604 /* sll arg0, 32, data_reg */
605 tcg_out_arithi(s
, data_reg
, arg0
, 32, HOST_SLL_OP
);
606 /* sra data_reg, 32, data_reg */
607 tcg_out_arithi(s
, data_reg
, data_reg
, 32, HOST_SRA_OP
);
615 tcg_out_mov(s
, data_reg
, arg0
);
621 label2_ptr
= (uint32_t *)s
->code_ptr
;
624 /* nop (delay slot */
628 *label1_ptr
= (INSN_OP(0) | INSN_COND(COND_E
, 0) | INSN_OP2(0x2) |
629 INSN_OFF22((unsigned long)s
->code_ptr
-
630 (unsigned long)label1_ptr
));
632 /* ld [arg1 + x], arg1 */
633 tcg_out_ldst(s
, arg1
, arg1
, offsetof(CPUTLBEntry
, addend
) -
634 offsetof(CPUTLBEntry
, addr_read
), TARGET_ADDEND_LD_OP
);
636 #if TARGET_LONG_BITS == 32
637 /* and addr_reg, x, arg0 */
638 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_I5
, 0xffffffff);
639 tcg_out_arith(s
, arg0
, addr_reg
, TCG_REG_I5
, ARITH_AND
);
640 /* add arg0, arg1, arg0 */
641 tcg_out_arith(s
, arg0
, arg0
, arg1
, ARITH_ADD
);
643 /* add addr_reg, arg1, arg0 */
644 tcg_out_arith(s
, arg0
, addr_reg
, arg1
, ARITH_ADD
);
653 /* ldub [arg0], data_reg */
654 tcg_out_ldst(s
, data_reg
, arg0
, 0, LDUB
);
657 /* ldsb [arg0], data_reg */
658 tcg_out_ldst(s
, data_reg
, arg0
, 0, LDSB
);
661 #ifdef TARGET_WORDS_BIGENDIAN
662 /* lduh [arg0], data_reg */
663 tcg_out_ldst(s
, data_reg
, arg0
, 0, LDUH
);
665 /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
666 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, LDUHA
, ASI_PRIMARY_LITTLE
);
670 #ifdef TARGET_WORDS_BIGENDIAN
671 /* ldsh [arg0], data_reg */
672 tcg_out_ldst(s
, data_reg
, arg0
, 0, LDSH
);
674 /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
675 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, LDSHA
, ASI_PRIMARY_LITTLE
);
679 #ifdef TARGET_WORDS_BIGENDIAN
680 /* lduw [arg0], data_reg */
681 tcg_out_ldst(s
, data_reg
, arg0
, 0, LDUW
);
683 /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
684 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, LDUWA
, ASI_PRIMARY_LITTLE
);
688 #ifdef TARGET_WORDS_BIGENDIAN
689 /* ldsw [arg0], data_reg */
690 tcg_out_ldst(s
, data_reg
, arg0
, 0, LDSW
);
692 /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
693 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, LDSWA
, ASI_PRIMARY_LITTLE
);
697 #ifdef TARGET_WORDS_BIGENDIAN
698 /* ldx [arg0], data_reg */
699 tcg_out_ldst(s
, data_reg
, arg0
, 0, LDX
);
701 /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
702 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, LDXA
, ASI_PRIMARY_LITTLE
);
709 #if defined(CONFIG_SOFTMMU)
711 *label2_ptr
= (INSN_OP(0) | INSN_COND(COND_A
, 0) | INSN_OP2(0x2) |
712 INSN_OFF22((unsigned long)s
->code_ptr
-
713 (unsigned long)label2_ptr
));
717 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
,
720 int addr_reg
, data_reg
, arg0
, arg1
, arg2
, mem_index
, s_bits
;
721 #if defined(CONFIG_SOFTMMU)
722 uint32_t *label1_ptr
, *label2_ptr
;
735 #if defined(CONFIG_SOFTMMU)
736 /* srl addr_reg, x, arg1 */
737 tcg_out_arithi(s
, arg1
, addr_reg
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
,
740 /* and addr_reg, x, arg0 */
741 tcg_out_arithi(s
, arg0
, addr_reg
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1),
744 /* and arg1, x, arg1 */
745 tcg_out_andi(s
, arg1
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
747 /* add arg1, x, arg1 */
748 tcg_out_addi(s
, arg1
, offsetof(CPUState
,
749 tlb_table
[mem_index
][0].addr_write
));
751 /* add env, arg1, arg1 */
752 tcg_out_arith(s
, arg1
, TCG_AREG0
, arg1
, ARITH_ADD
);
754 /* ld [arg1], arg2 */
755 tcg_out32(s
, TARGET_LD_OP
| INSN_RD(arg2
) | INSN_RS1(arg1
) |
756 INSN_RS2(TCG_REG_G0
));
758 /* subcc arg0, arg2, %g0 */
759 tcg_out_arith(s
, TCG_REG_G0
, arg0
, arg2
, ARITH_SUBCC
);
763 label1_ptr
= (uint32_t *)s
->code_ptr
;
766 /* mov (delay slot) */
767 tcg_out_mov(s
, arg0
, addr_reg
);
770 tcg_out_mov(s
, arg1
, data_reg
);
773 tcg_out_movi(s
, TCG_TYPE_I32
, arg2
, mem_index
);
775 /* XXX: move that code at the end of the TB */
776 /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
777 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)qemu_st_helpers
[s_bits
]
778 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
780 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
783 tcg_out_ldst(s
, TCG_AREG0
, TCG_REG_CALL_STACK
,
784 TCG_TARGET_CALL_STACK_OFFSET
- sizeof(long), HOST_ST_OP
);
785 tcg_out_ldst(s
, TCG_AREG0
, TCG_REG_CALL_STACK
,
786 TCG_TARGET_CALL_STACK_OFFSET
- sizeof(long), HOST_LD_OP
);
790 label2_ptr
= (uint32_t *)s
->code_ptr
;
793 /* nop (delay slot) */
797 *label1_ptr
= (INSN_OP(0) | INSN_COND(COND_E
, 0) | INSN_OP2(0x2) |
798 INSN_OFF22((unsigned long)s
->code_ptr
-
799 (unsigned long)label1_ptr
));
801 /* ld [arg1 + x], arg1 */
802 tcg_out_ldst(s
, arg1
, arg1
, offsetof(CPUTLBEntry
, addend
) -
803 offsetof(CPUTLBEntry
, addr_write
), TARGET_ADDEND_LD_OP
);
805 #if TARGET_LONG_BITS == 32
806 /* and addr_reg, x, arg0 */
807 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_I5
, 0xffffffff);
808 tcg_out_arith(s
, arg0
, addr_reg
, TCG_REG_I5
, ARITH_AND
);
809 /* add arg0, arg1, arg0 */
810 tcg_out_arith(s
, arg0
, arg0
, arg1
, ARITH_ADD
);
812 /* add addr_reg, arg1, arg0 */
813 tcg_out_arith(s
, arg0
, addr_reg
, arg1
, ARITH_ADD
);
822 /* stb data_reg, [arg0] */
823 tcg_out_ldst(s
, data_reg
, arg0
, 0, STB
);
826 #ifdef TARGET_WORDS_BIGENDIAN
827 /* sth data_reg, [arg0] */
828 tcg_out_ldst(s
, data_reg
, arg0
, 0, STH
);
830 /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
831 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, STHA
, ASI_PRIMARY_LITTLE
);
835 #ifdef TARGET_WORDS_BIGENDIAN
836 /* stw data_reg, [arg0] */
837 tcg_out_ldst(s
, data_reg
, arg0
, 0, STW
);
839 /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
840 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, STWA
, ASI_PRIMARY_LITTLE
);
844 #ifdef TARGET_WORDS_BIGENDIAN
845 /* stx data_reg, [arg0] */
846 tcg_out_ldst(s
, data_reg
, arg0
, 0, STX
);
848 /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
849 tcg_out_ldst_asi(s
, data_reg
, arg0
, 0, STXA
, ASI_PRIMARY_LITTLE
);
856 #if defined(CONFIG_SOFTMMU)
858 *label2_ptr
= (INSN_OP(0) | INSN_COND(COND_A
, 0) | INSN_OP2(0x2) |
859 INSN_OFF22((unsigned long)s
->code_ptr
-
860 (unsigned long)label2_ptr
));
864 static inline void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
865 const int *const_args
)
870 case INDEX_op_exit_tb
:
871 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I0
, args
[0]);
872 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I7
) |
874 tcg_out32(s
, RESTORE
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_G0
) |
875 INSN_RS2(TCG_REG_G0
));
877 case INDEX_op_goto_tb
:
878 if (s
->tb_jmp_offset
) {
879 /* direct jump method */
880 tcg_out_sethi(s
, TCG_REG_I5
, args
[0] & 0xffffe000);
881 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I5
) |
882 INSN_IMM13((args
[0] & 0x1fff)));
883 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
885 /* indirect jump method */
886 tcg_out_ld_ptr(s
, TCG_REG_I5
, (tcg_target_long
)(s
->tb_next
+ args
[0]));
887 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I5
) |
888 INSN_RS2(TCG_REG_G0
));
891 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
895 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)args
[0]
896 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
899 tcg_out_ld_ptr(s
, TCG_REG_I5
,
900 (tcg_target_long
)(s
->tb_next
+ args
[0]));
901 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_O7
) | INSN_RS1(TCG_REG_I5
) |
902 INSN_RS2(TCG_REG_G0
));
904 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
907 tcg_out_ldst(s
, TCG_AREG0
, TCG_REG_CALL_STACK
,
908 TCG_TARGET_CALL_STACK_OFFSET
- sizeof(long), HOST_ST_OP
);
909 tcg_out_ldst(s
, TCG_AREG0
, TCG_REG_CALL_STACK
,
910 TCG_TARGET_CALL_STACK_OFFSET
- sizeof(long), HOST_LD_OP
);
914 tcg_out_branch(s
, COND_A
, args
[0]);
917 case INDEX_op_movi_i32
:
918 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], (uint32_t)args
[1]);
921 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
922 #define OP_32_64(x) \
923 glue(glue(case INDEX_op_, x), _i32:) \
924 glue(glue(case INDEX_op_, x), _i64:)
926 #define OP_32_64(x) \
927 glue(glue(case INDEX_op_, x), _i32:)
930 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUB
);
933 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSB
);
936 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUH
);
939 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSH
);
941 case INDEX_op_ld_i32
:
942 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
943 case INDEX_op_ld32u_i64
:
945 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUW
);
948 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STB
);
951 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STH
);
953 case INDEX_op_st_i32
:
954 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
955 case INDEX_op_st32_i64
:
957 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STW
);
974 case INDEX_op_shl_i32
:
977 case INDEX_op_shr_i32
:
980 case INDEX_op_sar_i32
:
983 case INDEX_op_mul_i32
:
986 case INDEX_op_div2_i32
:
987 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
995 case INDEX_op_divu2_i32
:
996 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
1005 case INDEX_op_brcond_i32
:
1006 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1010 case INDEX_op_qemu_ld8u
:
1011 tcg_out_qemu_ld(s
, args
, 0);
1013 case INDEX_op_qemu_ld8s
:
1014 tcg_out_qemu_ld(s
, args
, 0 | 4);
1016 case INDEX_op_qemu_ld16u
:
1017 tcg_out_qemu_ld(s
, args
, 1);
1019 case INDEX_op_qemu_ld16s
:
1020 tcg_out_qemu_ld(s
, args
, 1 | 4);
1022 case INDEX_op_qemu_ld32u
:
1023 tcg_out_qemu_ld(s
, args
, 2);
1025 case INDEX_op_qemu_ld32s
:
1026 tcg_out_qemu_ld(s
, args
, 2 | 4);
1028 case INDEX_op_qemu_st8
:
1029 tcg_out_qemu_st(s
, args
, 0);
1031 case INDEX_op_qemu_st16
:
1032 tcg_out_qemu_st(s
, args
, 1);
1034 case INDEX_op_qemu_st32
:
1035 tcg_out_qemu_st(s
, args
, 2);
1038 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1039 case INDEX_op_movi_i64
:
1040 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
1042 case INDEX_op_ld32s_i64
:
1043 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSW
);
1045 case INDEX_op_ld_i64
:
1046 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDX
);
1048 case INDEX_op_st_i64
:
1049 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STX
);
1051 case INDEX_op_shl_i64
:
1054 case INDEX_op_shr_i64
:
1057 case INDEX_op_sar_i64
:
1060 case INDEX_op_mul_i64
:
1063 case INDEX_op_div2_i64
:
1066 case INDEX_op_divu2_i64
:
1070 case INDEX_op_brcond_i64
:
1071 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1074 case INDEX_op_qemu_ld64
:
1075 tcg_out_qemu_ld(s
, args
, 3);
1077 case INDEX_op_qemu_st64
:
1078 tcg_out_qemu_st(s
, args
, 3);
1083 if (const_args
[2]) {
1084 tcg_out_arithi(s
, args
[0], args
[1], args
[2], c
);
1086 tcg_out_arith(s
, args
[0], args
[1], args
[2], c
);
1091 fprintf(stderr
, "unknown opcode 0x%x\n", opc
);
1096 static const TCGTargetOpDef sparc_op_defs
[] = {
1097 { INDEX_op_exit_tb
, { } },
1098 { INDEX_op_goto_tb
, { } },
1099 { INDEX_op_call
, { "ri" } },
1100 { INDEX_op_jmp
, { "ri" } },
1101 { INDEX_op_br
, { } },
1103 { INDEX_op_mov_i32
, { "r", "r" } },
1104 { INDEX_op_movi_i32
, { "r" } },
1105 { INDEX_op_ld8u_i32
, { "r", "r" } },
1106 { INDEX_op_ld8s_i32
, { "r", "r" } },
1107 { INDEX_op_ld16u_i32
, { "r", "r" } },
1108 { INDEX_op_ld16s_i32
, { "r", "r" } },
1109 { INDEX_op_ld_i32
, { "r", "r" } },
1110 { INDEX_op_st8_i32
, { "r", "r" } },
1111 { INDEX_op_st16_i32
, { "r", "r" } },
1112 { INDEX_op_st_i32
, { "r", "r" } },
1114 { INDEX_op_add_i32
, { "r", "r", "rJ" } },
1115 { INDEX_op_mul_i32
, { "r", "r", "rJ" } },
1116 { INDEX_op_div2_i32
, { "r", "r", "0", "1", "r" } },
1117 { INDEX_op_divu2_i32
, { "r", "r", "0", "1", "r" } },
1118 { INDEX_op_sub_i32
, { "r", "r", "rJ" } },
1119 { INDEX_op_and_i32
, { "r", "r", "rJ" } },
1120 { INDEX_op_or_i32
, { "r", "r", "rJ" } },
1121 { INDEX_op_xor_i32
, { "r", "r", "rJ" } },
1123 { INDEX_op_shl_i32
, { "r", "r", "rJ" } },
1124 { INDEX_op_shr_i32
, { "r", "r", "rJ" } },
1125 { INDEX_op_sar_i32
, { "r", "r", "rJ" } },
1127 { INDEX_op_brcond_i32
, { "r", "ri" } },
1129 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1130 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1131 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1132 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1133 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1134 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1136 { INDEX_op_qemu_st8
, { "L", "L" } },
1137 { INDEX_op_qemu_st16
, { "L", "L" } },
1138 { INDEX_op_qemu_st32
, { "L", "L" } },
1140 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1141 { INDEX_op_mov_i64
, { "r", "r" } },
1142 { INDEX_op_movi_i64
, { "r" } },
1143 { INDEX_op_ld8u_i64
, { "r", "r" } },
1144 { INDEX_op_ld8s_i64
, { "r", "r" } },
1145 { INDEX_op_ld16u_i64
, { "r", "r" } },
1146 { INDEX_op_ld16s_i64
, { "r", "r" } },
1147 { INDEX_op_ld32u_i64
, { "r", "r" } },
1148 { INDEX_op_ld32s_i64
, { "r", "r" } },
1149 { INDEX_op_ld_i64
, { "r", "r" } },
1150 { INDEX_op_st8_i64
, { "r", "r" } },
1151 { INDEX_op_st16_i64
, { "r", "r" } },
1152 { INDEX_op_st32_i64
, { "r", "r" } },
1153 { INDEX_op_st_i64
, { "r", "r" } },
1154 { INDEX_op_qemu_ld64
, { "L", "L" } },
1155 { INDEX_op_qemu_st64
, { "L", "L" } },
1157 { INDEX_op_add_i64
, { "r", "r", "rJ" } },
1158 { INDEX_op_mul_i64
, { "r", "r", "rJ" } },
1159 { INDEX_op_div2_i64
, { "r", "r", "0", "1", "r" } },
1160 { INDEX_op_divu2_i64
, { "r", "r", "0", "1", "r" } },
1161 { INDEX_op_sub_i64
, { "r", "r", "rJ" } },
1162 { INDEX_op_and_i64
, { "r", "r", "rJ" } },
1163 { INDEX_op_or_i64
, { "r", "r", "rJ" } },
1164 { INDEX_op_xor_i64
, { "r", "r", "rJ" } },
1166 { INDEX_op_shl_i64
, { "r", "r", "rJ" } },
1167 { INDEX_op_shr_i64
, { "r", "r", "rJ" } },
1168 { INDEX_op_sar_i64
, { "r", "r", "rJ" } },
1170 { INDEX_op_brcond_i64
, { "r", "ri" } },
1175 void tcg_target_init(TCGContext
*s
)
1177 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1178 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1179 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
1181 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1197 tcg_regset_clear(s
->reserved_regs
);
1198 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_G0
);
1199 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1200 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I4
); // for internal use
1202 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I5
); // for internal use
1203 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I6
);
1204 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I7
);
1205 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_O6
);
1206 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_O7
);
1207 tcg_add_target_add_op_defs(sparc_op_defs
);