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[MISC] Updated maintainer
[qemu/mini2440/sniper_sniper_test.git] / hw / s3c2410.c
blobb5f9275dc8e2693a37add901bb98a6dde874f787
1 /*
2 * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
3 *
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
6 * With: Michel Pollet <buserror@gmail.com>
7 *
8 * This code is licenced under the GNU GPL v2.
9 */
10
11 #include "s3c.h"
12 #include "qemu-timer.h"
13 #include "qemu-char.h"
14 #include "hw.h"
15 #include "console.h"
16 #include "devices.h"
17 #include "arm-misc.h"
18 #include "i2c.h"
19 #include "pxa.h"
20 #include "sysemu.h"
21
22 /* Interrupt controller */
23 struct s3c_pic_state_s {
24 target_phys_addr_t base;
25 qemu_irq *parent_pic;
26 qemu_irq *irqs;
27
28 uint32_t srcpnd;
29 uint32_t intpnd;
30 uint32_t intmsk;
31 uint32_t intmod;
32 uint32_t priority;
33 int intoffset;
34 uint32_t subsrcpnd;
35 uint32_t intsubmsk;
36 };
37
38 static void s3c_pic_update(struct s3c_pic_state_s *s)
39 {
40 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ],
41 s->srcpnd & s->intmod);
42 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ],
43 s->intpnd & ~s->intmsk & ~s->intmod);
44 }
45
46 /*
47 * Performs interrupt arbitration and notifies the CPU.
48 *
49 * Since it's a complex logic which cannot be relied on by the OS
50 * anyway - first because real hardware doesn't do it accurately,
51 * second because it only matters when interrupts occur at the
52 * same time which normally can't be predicted - we use a simpler
53 * version for non-debug runs.
54 */
55 #ifdef DEBUG
56 static const uint32_t s3c_arbmsk[6] = {
57 0x0000000f,
58 0x000003f0,
59 0x0000fc00,
60 0x003f0000,
61 0x0fc00000,
62 0xf0000000,
63 };
64
65 # define S3C_ARB_SEL(i) ((s->priority >> (7 + (i << 1))) & 3)
66 # define S3C_ARB_MODE(i) ((s->priority >> i) & 1)
67 # define S3C_ARB_SEL_SET(i, v) \
68 s->priority &= ~(3 << (7 + (i << 1))); \
69 s->priority |= v << (7 + (i << 1));
70
71 static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
72 {
73 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
74 int offset, i, arb;
75 if (s->intpnd || !pnd) {
76 s3c_pic_update(s);
77 return;
78 }
79
80 if (pnd & s3c_arbmsk[0]) {
81 offset = 0;
82 arb = 0;
83 } else if (pnd & 0x0ffffff0) {
84 i = S3C_ARB_SEL(6);
85 i ^= i << 1;
86 if (!(pnd & s3c_arbmsk[1 + (i & 3)]))
87 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
88 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
89 i ++;
90
91 if (S3C_ARB_MODE(6))
92 S3C_ARB_SEL_SET(6, ((i + 1) & 3));
93 offset = (i & 3) * 6 + 4;
94 if (pnd & (1 << offset))
95 goto known_offset;
96 else if (!(pnd & (0x1f << offset))) {
97 offset += 5;
98 goto known_offset;
99 }
100 offset ++;
101 arb = (i & 3) + 1;
102 } else {
103 arb = 5;
104 offset = 28;
105 }
106
107 pnd >>= offset;
108 i = S3C_ARB_SEL(arb);
109 i ^= i << 1;
110 if (!(pnd & (1 << (i & 3))))
111 if (!(pnd & (1 << (++ i & 3))))
112 if (!(pnd & (1 << (++ i & 3))))
113 i ++;
114
115 if (S3C_ARB_MODE(arb))
116 S3C_ARB_SEL_SET(arb, ((i + 1) & 3));
117 offset += i & 3;
118 known_offset:
119 s->intoffset = offset;
120 s->intpnd = 1 << offset;
121 s3c_pic_update(s);
122 }
123 #else
124 inline static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
125 {
126 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
127 if (pnd && !s->intpnd)
128 s->intpnd = 1 << (s->intoffset = ffs(pnd) - 1);
129 s3c_pic_update(s);
130 }
131 #endif
132
133 static const int s3c_sub_src_map[] = {
134 [S3C_PICS_RXD0 & 31] = S3C_PIC_UART0,
135 [S3C_PICS_TXD0 & 31] = S3C_PIC_UART0,
136 [S3C_PICS_ERR0 & 31] = S3C_PIC_UART0,
137 [S3C_PICS_RXD1 & 31] = S3C_PIC_UART1,
138 [S3C_PICS_TXD1 & 31] = S3C_PIC_UART1,
139 [S3C_PICS_ERR1 & 31] = S3C_PIC_UART1,
140 [S3C_PICS_RXD2 & 31] = S3C_PIC_UART2,
141 [S3C_PICS_TXD2 & 31] = S3C_PIC_UART2,
142 [S3C_PICS_ERR2 & 31] = S3C_PIC_UART2,
143 [S3C_PICS_TC & 31] = S3C_PIC_ADC,
144 [S3C_PICS_ADC & 31] = S3C_PIC_ADC,
145 };
146
147 static void s3c_pic_subupdate(struct s3c_pic_state_s *s)
148 {
149 int next;
150 const int *sub = &s3c_sub_src_map[-1];
151 uint32_t pnd = s->subsrcpnd & ~s->intsubmsk;
152 while ((next = ffs(pnd))) {
153 sub += next;
154 pnd >>= next;
155 s->srcpnd |= 1 << *sub;
156 }
157 s3c_pic_arbitrate(s);
158 }
159
160 static void s3c_pic_set_irq(void *opaque, int irq, int req)
161 {
162 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
163 uint32_t mask;
164 /* This interrupt controller doesn't clear any request signals
165 * or register bits automatically. */
166 if (!req)
167 return;
168
169 if (irq & 32) {
170 irq &= 31;
171 s->subsrcpnd |= 1 << irq;
172 if (s->intsubmsk & (1 << irq))
173 return;
174 else
175 irq = s3c_sub_src_map[irq];
176 }
177 s->srcpnd |= (mask = 1 << irq);
178
179 /* A FIQ */
180 if (s->intmod & mask)
181 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_FIQ]);
182 else if (!s->intpnd && !(s->intmsk & mask)) {
183 #ifdef DEBUG
184 s3c_pic_arbitrate(s);
185 #else
186 s->intpnd = mask;
187 s->intoffset = irq;
188 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_IRQ]);
189 #endif
190 }
191 }
192
193 static void s3c_pic_reset(struct s3c_pic_state_s *s)
194 {
195 s->srcpnd = 0;
196 s->intpnd = 0;
197 s->intmsk = 0xffffffff;
198 s->intmod = 0;
199 s->priority = 0x7f;
200 s->intoffset = 0;
201 s->subsrcpnd = 0;
202 s->intsubmsk = 0x7ff;
203 s3c_pic_update(s);
204 }
205
206 #define S3C_SRCPND 0x00 /* Source Pending register */
207 #define S3C_INTMOD 0x04 /* Source Mode register */
208 #define S3C_INTMSK 0x08 /* Interrupt Mask register */
209 #define S3C_PRIORITY 0x0c /* Priority register */
210 #define S3C_INTPND 0x10 /* Interrupt Pending register */
211 #define S3C_INTOFFSET 0x14 /* Interrupt Offset register */
212 #define S3C_SUBSRCPND 0x18 /* Sub Source Pending register */
213 #define S3C_INTSUBMSK 0x1c /* Interrupt Sub Mask register */
214
215 static uint32_t s3c_pic_read(void *opaque, target_phys_addr_t addr)
216 {
217 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
218
219 switch (addr) {
220 case S3C_SRCPND:
221 return s->srcpnd;
222 case S3C_INTPND:
223 return s->intpnd;
224 case S3C_INTMSK:
225 return s->intmsk;
226 case S3C_INTMOD:
227 return s->intmod;
228 case S3C_PRIORITY:
229 return s->priority;
230 case S3C_INTOFFSET:
231 return s->intoffset;
232 case S3C_SUBSRCPND:
233 return s->subsrcpnd;
234 case S3C_INTSUBMSK:
235 return s->intsubmsk;
236 default:
237 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
238 break;
239 }
240 return 0;
241 }
242
243 static void s3c_pic_write(void *opaque, target_phys_addr_t addr,
244 uint32_t value)
245 {
246 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
247
248 switch (addr) {
249 case S3C_SRCPND:
250 s->srcpnd &= ~value;
251 if (value & s->intmod)
252 s3c_pic_update(s);
253 break;
254 case S3C_INTPND:
255 if (s->intpnd & value) {
256 s->intpnd = 0;
257 s->intoffset = 0;
258 s3c_pic_arbitrate(s);
259 }
260 break;
261 case S3C_INTMSK:
262 s->intmsk = value;
263 if (s->intpnd & value) {
264 s->intpnd = 0;
265 s->intoffset = 0;
266 }
267 s3c_pic_arbitrate(s);
268 break;
269 case S3C_INTMOD:
270 s->intmod = value;
271 break;
272 case S3C_PRIORITY:
273 s->priority = value;
274 break;
275 case S3C_SUBSRCPND:
276 s->subsrcpnd &= ~value;
277 break;
278 case S3C_INTSUBMSK:
279 s->intsubmsk = value;
280 s3c_pic_subupdate(s);
281 break;
282 default:
283 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
284 }
285 }
286
287 static CPUReadMemoryFunc *s3c_pic_readfn[] = {
288 s3c_pic_read,
289 s3c_pic_read,
290 s3c_pic_read,
291 };
292
293 static CPUWriteMemoryFunc *s3c_pic_writefn[] = {
294 s3c_pic_write,
295 s3c_pic_write,
296 s3c_pic_write,
297 };
298
299 static void s3c_pic_save(QEMUFile *f, void *opaque)
300 {
301 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
302 qemu_put_be32s(f, &s->srcpnd);
303 qemu_put_be32s(f, &s->intpnd);
304 qemu_put_be32s(f, &s->intmsk);
305 qemu_put_be32s(f, &s->intmod);
306 qemu_put_be32s(f, &s->priority);
307 qemu_put_be32s(f, &s->subsrcpnd);
308 qemu_put_be32s(f, &s->intsubmsk);
309 qemu_put_be32(f, s->intoffset);
310 }
311
312 static int s3c_pic_load(QEMUFile *f, void *opaque, int version_id)
313 {
314 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
315 qemu_get_be32s(f, &s->srcpnd);
316 qemu_get_be32s(f, &s->intpnd);
317 qemu_get_be32s(f, &s->intmsk);
318 qemu_get_be32s(f, &s->intmod);
319 qemu_get_be32s(f, &s->priority);
320 qemu_get_be32s(f, &s->subsrcpnd);
321 qemu_get_be32s(f, &s->intsubmsk);
322 s->intoffset = qemu_get_be32(f);
323 s3c_pic_update(s);
324 return 0;
325 }
326
327 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
328 qemu_irq *arm_pic)
329 {
330 int iomemtype;
331 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *)
332 qemu_mallocz(sizeof(struct s3c_pic_state_s));
333
334 s->base = base;
335 s->parent_pic = arm_pic;
336 s->irqs = qemu_allocate_irqs(s3c_pic_set_irq, s, S3C_PIC_MAX);
337
338 s3c_pic_reset(s);
339
340 iomemtype = cpu_register_io_memory(0, s3c_pic_readfn,
341 s3c_pic_writefn, s);
342 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
343
344 register_savevm("s3c24xx_pic", 0, 0, s3c_pic_save, s3c_pic_load, s);
345
346 return s;
347 }
348
349 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s)
350 {
351 return s->irqs;
352 }
353
354 /* Memory controller */
355 #define S3C_BWSCON 0x00 /* Bus Width & Wait Control register */
356 #define S3C_BANKCON0 0x04 /* Bank 0 Control register */
357 #define S3C_BANKCON1 0x08 /* Bank 1 Control register */
358 #define S3C_BANKCON2 0x0c /* Bank 2 Control register */
359 #define S3C_BANKCON3 0x10 /* Bank 3 Control register */
360 #define S3C_BANKCON4 0x14 /* Bank 4 Control register */
361 #define S3C_BANKCON5 0x18 /* Bank 5 Control register */
362 #define S3C_BANKCON6 0x1c /* Bank 6 Control register */
363 #define S3C_BANKCON7 0x20 /* Bank 7 Control register */
364 #define S3C_REFRESH 0x24 /* SDRAM Refresh Control register */
365 #define S3C_BANKSIZE 0x28 /* Flexible Bank Size register */
366 #define S3C_MRSRB6 0x2c /* Bank 6 Mode Set register */
367 #define S3C_MRSRB7 0x30 /* Bank 6 Mode Set register */
368
369 static void s3c_mc_reset(struct s3c_state_s *s)
370 {
371 s->mc_regs[S3C_BWSCON >> 2] = 0x0000000;
372 s->mc_regs[S3C_BANKCON0 >> 2] = 0x0700;
373 s->mc_regs[S3C_BANKCON1 >> 2] = 0x0700;
374 s->mc_regs[S3C_BANKCON2 >> 2] = 0x0700;
375 s->mc_regs[S3C_BANKCON3 >> 2] = 0x0700;
376 s->mc_regs[S3C_BANKCON4 >> 2] = 0x0700;
377 s->mc_regs[S3C_BANKCON5 >> 2] = 0x0700;
378 s->mc_regs[S3C_BANKCON6 >> 2] = 0x18008;
379 s->mc_regs[S3C_BANKCON7 >> 2] = 0x18008;
380 s->mc_regs[S3C_REFRESH >> 2] = 0xac0000;
381 s->mc_regs[S3C_BANKSIZE >> 2] = 0x2;
382 s->mc_regs[S3C_MRSRB6 >> 2] = 0x00;
383 s->mc_regs[S3C_MRSRB7 >> 2] = 0x00;
384 }
385
386 static uint32_t s3c_mc_read(void *opaque, target_phys_addr_t addr)
387 {
388 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
389
390 switch (addr >> 2) {
391 case S3C_BWSCON ... S3C_MRSRB7:
392 return s->mc_regs[addr >> 2];
393 default:
394 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
395 break;
396 }
397 return 0;
398 }
399
400 static void s3c_mc_write(void *opaque, target_phys_addr_t addr,
401 uint32_t value)
402 {
403 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
404
405 switch (addr >> 2) {
406 case S3C_BWSCON ... S3C_MRSRB7:
407 s->mc_regs[addr >> 2] = value;
408 break;
409 default:
410 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
411 }
412 }
413
414 static CPUReadMemoryFunc *s3c_mc_readfn[] = {
415 s3c_mc_read,
416 s3c_mc_read,
417 s3c_mc_read,
418 };
419
420 static CPUWriteMemoryFunc *s3c_mc_writefn[] = {
421 s3c_mc_write,
422 s3c_mc_write,
423 s3c_mc_write,
424 };
425
426 static void s3c_mc_save(QEMUFile *f, void *opaque)
427 {
428 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
429 int i;
430 for (i = 0; i < 13; i ++)
431 qemu_put_be32s(f, &s->mc_regs[i]);
432 }
433
434 static int s3c_mc_load(QEMUFile *f, void *opaque, int version_id)
435 {
436 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
437 int i;
438 for (i = 0; i < 13; i ++)
439 qemu_get_be32s(f, &s->mc_regs[i]);
440 return 0;
441 }
442
443 /* Clock & power management */
444 #define S3C_LOCKTIME 0x00 /* PLL Lock Time Count register */
445 #define S3C_MPLLCON 0x04 /* MPLL Configuration register */
446 #define S3C_UPLLCON 0x08 /* UPLL Configuration register */
447 #define S3C_CLKCON 0x0c /* Clock Generator Control register */
448 #define S3C_CLKSLOW 0x10 /* Slow Clock Control register */
449 #define S3C_CLKDIVN 0x14 /* Clock Divider Control register */
450
451 #define S3C2440_CAMDIVN 0x18 /* Camera Clock Divider register */
452
453 static void s3c_clkpwr_reset(struct s3c_state_s *s)
454 {
455 s->clkpwr_regs[S3C_LOCKTIME >> 2] = 0x00ffffff;
456 s->clkpwr_regs[S3C_MPLLCON >> 2] = 0x0005c080;
457 s->clkpwr_regs[S3C_UPLLCON >> 2] = 0x00028080;
458 s->clkpwr_regs[S3C_CLKCON >> 2] = 0x0007fff0;
459 s->clkpwr_regs[S3C_CLKSLOW >> 2] = 0x00000004;
460 s->clkpwr_regs[S3C_CLKDIVN >> 2] = 0x00000000;
461 s->clkpwr_regs[S3C2440_CAMDIVN >> 2] = 0x00000000;
462 }
463
464 static uint32_t s3c_clkpwr_read(void *opaque, target_phys_addr_t addr)
465 {
466 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
467
468 switch (addr) {
469 case S3C_LOCKTIME ... S3C_CLKDIVN:
470 return s->clkpwr_regs[addr >> 2];
471 case S3C2440_CAMDIVN:
472 if (s->cpu_id == S3C_CPU_2440)
473 return s->clkpwr_regs[addr >> 2];
474 default:
475 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
476 break;
477 }
478 return 0;
479 }
480
481 static void s3c_clkpwr_write(void *opaque, target_phys_addr_t addr,
482 uint32_t value)
483 {
484 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
485
486 switch (addr) {
487 case S3C_LOCKTIME:
488 case S3C_MPLLCON:
489 case S3C_UPLLCON:
490 case S3C_CLKDIVN:
491 s->clkpwr_regs[addr >> 2] = value;
492 break;
493 case S3C_CLKCON:
494 if (value & (1 << 3)) {
495 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
496 printf("%s: processor powered off\n", __FUNCTION__);
497 s3c_gpio_setpwrstat(s->io, 2);
498 #if 0
499 cpu_reset(s->env);
500 s->env->regs[15] = 0; /* XXX */
501 #endif
502 } else
503 if (value & (1 << 2)) /* Normal IDLE mode */
504 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
505 if ((s->clkpwr_regs[addr >> 2] ^ value) & 1)
506 printf("%s: SPECIAL mode %s\n", __FUNCTION__,
507 (value & 1) ? "on" : "off");
508 s->clkpwr_regs[addr >> 2] = value;
509 break;
510 case S3C_CLKSLOW:
511 if ((s->clkpwr_regs[addr >> 2] ^ value) & (1 << 4))
512 printf("%s: SLOW mode %s\n", __FUNCTION__,
513 (value & (1 << 4)) ? "on" : "off");
514 s->clkpwr_regs[addr >> 2] = value;
515 break;
516 case S3C2440_CAMDIVN:
517 if (s->cpu_id == S3C_CPU_2440) {
518 s->clkpwr_regs[addr >> 2] = value;
519 break;
520 }
521 default:
522 printf("%s: Bad register 0x%lx (cpu %08x)\n", __FUNCTION__, /*(unsigned long)*/addr, s->cpu_id);
523 }
524 }
525
526 static CPUReadMemoryFunc *s3c_clkpwr_readfn[] = {
527 s3c_clkpwr_read,
528 s3c_clkpwr_read,
529 s3c_clkpwr_read,
530 };
531
532 static CPUWriteMemoryFunc *s3c_clkpwr_writefn[] = {
533 s3c_clkpwr_write,
534 s3c_clkpwr_write,
535 s3c_clkpwr_write,
536 };
537
538 static void s3c_clkpwr_save(QEMUFile *f, void *opaque)
539 {
540 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
541 int i;
542 for (i = 0; i < 7; i ++)
543 qemu_put_be32s(f, &s->clkpwr_regs[i]);
544 }
545
546 static int s3c_clkpwr_load(QEMUFile *f, void *opaque, int version_id)
547 {
548 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
549 int i;
550 for (i = 0; i < 7; i ++)
551 qemu_get_be32s(f, &s->clkpwr_regs[i]);
552 return 0;
553 }
554
555 /* DMA controller */
556 #define S3C_DMA_CH_N 4
557
558 struct s3c_dma_ch_state_s;
559 struct s3c_dma_state_s { /* Modelled as an interrupt controller */
560 target_phys_addr_t base;
561 qemu_irq *drqs;
562 struct s3c_dma_ch_state_s {
563 qemu_irq intr;
564 int curr_tc;
565 int req;
566 int running;
567 uint32_t con;
568 uint32_t isrc;
569 uint32_t isrcc;
570 uint32_t idst;
571 uint32_t idstc;
572 uint32_t csrc;
573 uint32_t cdst;
574 uint32_t mask;
575 } ch[S3C_DMA_CH_N];
576 };
577
578 static inline void s3c_dma_ch_run(struct s3c_dma_state_s *s,
579 struct s3c_dma_ch_state_s *ch)
580 {
581 int width, burst, t;
582 uint8_t buffer[4];
583 width = 1 << ((ch->con >> 20) & 3); /* DSZ */
584 burst = (ch->con & (1 << 28)) ? 4 : 1; /* TSZ */
585
586 while (!ch->running && ch->curr_tc > 0 && ch->req &&
587 (ch->mask & (1 << 1))) { /* ON_OFF */
588 if (width > sizeof(buffer)) {
589 printf("%s: wrong access width\n", __FUNCTION__);
590 return;
591 }
592 ch->running = 1;
593 while (ch->curr_tc --) {
594 for (t = 0; t < burst; t ++) {
595 cpu_physical_memory_read(ch->csrc, buffer, width);
596 cpu_physical_memory_write(ch->cdst, buffer, width);
597
598 if (!(ch->isrcc & 1)) /* INT */
599 ch->csrc += width;
600 if (!(ch->idstc & 1)) /* INT */
601 ch->cdst += width;
602 }
603
604 if (!(ch->con & (1 << 27)) && !ch->req) /* SERVMODE */
605 break;
606 }
607 ch->running = 0;
608
609 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
610 ch->req = 0;
611 }
612
613 if (ch->curr_tc <= 0) {
614 if (ch->con & (1 << 22)) /* RELOAD */
615 ch->mask &= ~(1 << 1); /* ON_OFF */
616 else {
617 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
618 printf("%s: auto-reload software controlled transfer\n",
619 __FUNCTION__);
620 break;
621 }
622 ch->csrc = ch->isrc; /* S_ADDR */
623 ch->cdst = ch->idst; /* D_ADDR */
624 ch->curr_tc = ch->con & 0xfffff; /* TC */
625 ch->con |= 1 << 22; /* ON_OFF */
626 }
627
628 if (ch->con & (1 << 31)) /* DMD_HS */
629 ch->req = 0;
630
631 if (ch->con & (1 << 29)) { /* INT */
632 qemu_irq_raise(ch->intr);
633 /* Give the system a chance to respond. */
634 break;
635 }
636 }
637 }
638 }
639
640 static void s3c_dma_reset(struct s3c_dma_state_s *s)
641 {
642 int i;
643 for (i = 0; i < S3C_DMA_CH_N; i ++) {
644 s->ch[i].curr_tc = 0;
645 s->ch[i].csrc = 0;
646 s->ch[i].isrc = 0;
647 s->ch[i].isrcc = 0;
648 s->ch[i].cdst = 0;
649 s->ch[i].idst = 0;
650 s->ch[i].idstc = 0;
651 s->ch[i].con = 0;
652 s->ch[i].csrc = 0;
653 s->ch[i].cdst = 0;
654 s->ch[i].mask = 0;
655 }
656 }
657
658 static void s3c_dma_dreq(void *opaque, int line, int req)
659 {
660 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
661 struct s3c_dma_ch_state_s *ch = &s->ch[line >> 4];
662
663 if (ch->con & (1 << 23)) /* SWHW_SEL */
664 if (((ch->con >> 24) & 7) == (line & 7)) { /* HWSRCSEL */
665 ch->req = req;
666 s3c_dma_ch_run(s, ch);
667 }
668 }
669
670 #define S3C_DISRC 0x00 /* DMA Initial Source register */
671 #define S3C_DISRCC 0x04 /* DMA Initial Source Control register */
672 #define S3C_DIDST 0x08 /* DMA Initial Destination register */
673 #define S3C_DIDSTC 0x0c /* DMA Initial Destination Control register */
674 #define S3C_DCON 0x10 /* DMA Control register */
675 #define S3C_DSTAT 0x14 /* DMA Count register */
676 #define S3C_DCSRC 0x18 /* DMA Current Source register */
677 #define S3C_DCDST 0x1c /* DMA Current Destination register */
678 #define S3C_DMASKTRIG 0x20 /* DMA Mask Trigger register */
679
680 static uint32_t s3c_dma_read(void *opaque, target_phys_addr_t addr)
681 {
682 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
683 struct s3c_dma_ch_state_s *ch = 0;
684
685 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
686 ch = &s->ch[addr >> 6];
687 addr &= 0x3f;
688 }
689
690 switch (addr) {
691 case S3C_DISRC:
692 return ch->isrc;
693 case S3C_DISRCC:
694 return ch->isrcc;
695 case S3C_DIDST:
696 return ch->idst;
697 case S3C_DIDSTC:
698 return ch->idstc;
699 case S3C_DCON:
700 return ch->con;
701 case S3C_DSTAT:
702 return ch->curr_tc;
703 case S3C_DCSRC:
704 return ch->csrc;
705 case S3C_DCDST:
706 return ch->cdst;
707 case S3C_DMASKTRIG:
708 return ch->mask;
709 default:
710 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
711 break;
712 }
713 return 0;
714 }
715
716 static void s3c_dma_write(void *opaque, target_phys_addr_t addr,
717 uint32_t value)
718 {
719 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
720 struct s3c_dma_ch_state_s *ch = 0;
721
722 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
723 ch = &s->ch[addr >> 6];
724 addr &= 0x3f;
725 }
726
727 switch (addr) {
728 case S3C_DCON:
729 ch->con = value;
730 break;
731 case S3C_DISRC:
732 ch->isrc = value;
733 break;
734 case S3C_DISRCC:
735 ch->isrcc = value;
736 break;
737 case S3C_DIDST:
738 ch->idst = value;
739 break;
740 case S3C_DIDSTC:
741 ch->idstc = value;
742 break;
743 case S3C_DMASKTRIG:
744 if (~ch->mask & value & (1 << 1)) { /* ON_OFF */
745 ch->curr_tc = ch->con & 0xfffff; /* TC */
746 ch->csrc = ch->isrc; /* S_ADDR */
747 ch->cdst = ch->idst; /* D_ADDR */
748 }
749
750 ch->mask = value;
751 if (value & (1 << 2)) { /* STOP */
752 ch->mask &= ~(3 << 1); /* ON_OFF */
753 } else if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
754 ch->req = value & 1; /* SW_TRIG */
755 s3c_dma_ch_run(s, ch);
756 }
757 break;
758 default:
759 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
760 }
761 }
762
763 static CPUReadMemoryFunc *s3c_dma_readfn[] = {
764 s3c_dma_read,
765 s3c_dma_read,
766 s3c_dma_read,
767 };
768
769 static CPUWriteMemoryFunc *s3c_dma_writefn[] = {
770 s3c_dma_write,
771 s3c_dma_write,
772 s3c_dma_write,
773 };
774
775 static void s3c_dma_save(QEMUFile *f, void *opaque)
776 {
777 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
778 int i;
779 for (i = 0; i < S3C_DMA_CH_N; i ++) {
780 qemu_put_be32(f, s->ch[i].curr_tc);
781 qemu_put_be32(f, s->ch[i].req);
782 qemu_put_be32s(f, &s->ch[i].con);
783 qemu_put_be32s(f, &s->ch[i].isrc);
784 qemu_put_be32s(f, &s->ch[i].isrcc);
785 qemu_put_be32s(f, &s->ch[i].idst);
786 qemu_put_be32s(f, &s->ch[i].idstc);
787 qemu_put_be32s(f, &s->ch[i].csrc);
788 qemu_put_be32s(f, &s->ch[i].cdst);
789 qemu_put_be32s(f, &s->ch[i].mask);
790 }
791 }
792
793 static int s3c_dma_load(QEMUFile *f, void *opaque, int version_id)
794 {
795 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
796 int i;
797 for (i = 0; i < S3C_DMA_CH_N; i ++) {
798 s->ch[i].curr_tc = qemu_get_be32(f);
799 s->ch[i].req = qemu_get_be32(f);
800 qemu_get_be32s(f, &s->ch[i].con);
801 qemu_get_be32s(f, &s->ch[i].isrc);
802 qemu_get_be32s(f, &s->ch[i].isrcc);
803 qemu_get_be32s(f, &s->ch[i].idst);
804 qemu_get_be32s(f, &s->ch[i].idstc);
805 qemu_get_be32s(f, &s->ch[i].csrc);
806 qemu_get_be32s(f, &s->ch[i].cdst);
807 qemu_get_be32s(f, &s->ch[i].mask);
808 }
809 return 0;
810 }
811
812 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic)
813 {
814 int iomemtype;
815 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *)
816 qemu_mallocz(sizeof(struct s3c_dma_state_s));
817
818 s->base = base;
819 s->ch[0].intr = pic[0];
820 s->ch[1].intr = pic[1];
821 s->ch[2].intr = pic[2];
822 s->ch[3].intr = pic[3];
823 s->drqs = qemu_allocate_irqs(s3c_dma_dreq, s, S3C_RQ_MAX);
824
825 s3c_dma_reset(s);
826
827 iomemtype = cpu_register_io_memory(0, s3c_dma_readfn,
828 s3c_dma_writefn, s);
829 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
830
831 register_savevm("s3c24xx_dma", 0, 0, s3c_dma_save, s3c_dma_load, s);
832
833 return s;
834 }
835
836 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s)
837 {
838 return s->drqs;
839 }
840
841 /* PWM timers controller */
842 struct s3c_timer_state_s;
843 struct s3c_timers_state_s {
844 target_phys_addr_t base;
845 qemu_irq *dma;
846 DisplayState *ds;
847 struct s3c_timer_state_s {
848 QEMUTimer *t;
849 struct s3c_timers_state_s *s;
850 int n;
851 int running;
852 uint32_t divider;
853 uint16_t count;
854 int64_t reload;
855 qemu_irq irq;
856 gpio_handler_t cmp_cb;
857 void *cmp_opaque;
858 } timer[5];
859
860 uint16_t compareb[4];
861 uint16_t countb[5];
862 uint32_t config[2];
863 uint32_t control;
864 };
865
866 static const int s3c_tm_bits[] = { 0, 8, 12, 16, 20 };
867
868 static uint16_t s3c_timers_get(struct s3c_timers_state_s *s, int tm)
869 {
870 uint16_t elapsed;
871 if (!s->timer[tm].running)
872 return s->timer[tm].count;
873
874 elapsed = muldiv64(qemu_get_clock(vm_clock) - s->timer[tm].reload,
875 s->timer[tm].divider, ticks_per_sec);
876 if (unlikely(elapsed > s->timer[tm].count))
877 return s->timer[tm].count;
878
879 return s->timer[tm].count - elapsed;
880 }
881
882 static void s3c_timers_stop(struct s3c_timers_state_s *s, int tm)
883 {
884 s->timer[tm].count = s3c_timers_get(s, tm);
885 s->timer[tm].running = 0;
886 }
887
888 static void s3c_timers_start(struct s3c_timers_state_s *s, int tm)
889 {
890 if (s->timer[tm].running)
891 return;
892
893 s->timer[tm].divider = S3C_PCLK_FREQ >>
894 (((s->config[1] >> (tm * 4)) & 3) + 1);
895 if (tm < 2)
896 s->timer[tm].divider /= ((s->config[0] >> 0) & 0xff) + 1;
897 else
898 s->timer[tm].divider /= ((s->config[0] >> 8) & 0xff) + 1;
899 s->timer[tm].running = 1;
900 s->timer[tm].reload = qemu_get_clock(vm_clock);
901 qemu_mod_timer(s->timer[tm].t,
902 s->timer[tm].reload + muldiv64(s->timer[tm].count,
903 ticks_per_sec, s->timer[tm].divider));
904 }
905
906 static void s3c_timers_reset(struct s3c_timers_state_s *s)
907 {
908 int i;
909 s->config[0] = 0x00000000;
910 s->config[1] = 0x00000000;
911 s->control = 0x00000000;
912
913 for (i = 0; i < 5; i ++) {
914 if (s->timer[i].running)
915 s3c_timers_stop(s, i);
916 s->countb[i] = 0x0000;
917 s->timer[i].count = 0;
918 }
919 for (i = 0; i < 4; i ++)
920 s->compareb[i] = 0x0000;
921 }
922
923 static void s3c_timers_tick(void *opaque)
924 {
925 struct s3c_timer_state_s *t = (struct s3c_timer_state_s *) opaque;
926 struct s3c_timers_state_s *s = t->s;
927 if (!t->running)
928 return;
929
930 if (((s->config[1] >> 20) & 0xf) == t->n + 1) {
931 qemu_irq_raise(s->dma[S3C_RQ_TIMER0]); /* TODO */
932 qemu_irq_raise(s->dma[S3C_RQ_TIMER1]);
933 qemu_irq_raise(s->dma[S3C_RQ_TIMER2]);
934 } else
935 qemu_irq_raise(t->irq);
936
937 t->running = 0;
938 t->count = 0;
939
940 if (s->control & (1 << ((t->n == 4) ? 22 : (s3c_tm_bits[t->n] + 3)))) {
941 /* Auto-reload */
942 t->count = s->countb[t->n];
943 s3c_timers_start(s, t->n);
944 } else
945 s->control &= ~(1 << s3c_tm_bits[t->n]);
946 }
947
948 #define S3C_TCFG0 0x00 /* Timer Configuration register 0 */
949 #define S3C_TCFG1 0x04 /* Timer Configuration register 1 */
950 #define S3C_TCON 0x08 /* Timer Control register */
951 #define S3C_TCNTB0 0x0c /* Timer 0 Count Buffer register */
952 #define S3C_TCMPB0 0x10 /* Timer 0 Compare Buffer register */
953 #define S3C_TCNTO0 0x14 /* Timer 0 Count Observation register */
954 #define S3C_TCNTB1 0x18 /* Timer 1 Count Buffer register */
955 #define S3C_TCMPB1 0x1c /* Timer 1 Compare Buffer register */
956 #define S3C_TCNTO1 0x20 /* Timer 1 Count Observation register */
957 #define S3C_TCNTB2 0x24 /* Timer 2 Count Buffer register */
958 #define S3C_TCMPB2 0x28 /* Timer 2 Compare Buffer register */
959 #define S3C_TCNTO2 0x2c /* Timer 2 Count Observation register */
960 #define S3C_TCNTB3 0x30 /* Timer 3 Count Buffer register */
961 #define S3C_TCMPB3 0x34 /* Timer 3 Compare Buffer register */
962 #define S3C_TCNTO3 0x38 /* Timer 3 Count Observation register */
963 #define S3C_TCNTB4 0x3c /* Timer 4 Count Buffer register */
964 #define S3C_TCNTO4 0x40 /* Timer 4 Count Observation register */
965
966 static uint32_t s3c_timers_read(void *opaque, target_phys_addr_t addr)
967 {
968 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
969 int tm = 0;
970
971 switch (addr) {
972 case S3C_TCFG0:
973 return s->config[0];
974 case S3C_TCFG1:
975 return s->config[1];
976 case S3C_TCON:
977 return s->control;
978 case S3C_TCMPB3: tm ++;
979 case S3C_TCMPB2: tm ++;
980 case S3C_TCMPB1: tm ++;
981 case S3C_TCMPB0:
982 return s->compareb[tm];
983 case S3C_TCNTB4: tm ++;
984 case S3C_TCNTB3: tm ++;
985 case S3C_TCNTB2: tm ++;
986 case S3C_TCNTB1: tm ++;
987 case S3C_TCNTB0:
988 return s->countb[tm];
989 case S3C_TCNTO4: tm ++;
990 case S3C_TCNTO3: tm ++;
991 case S3C_TCNTO2: tm ++;
992 case S3C_TCNTO1: tm ++;
993 case S3C_TCNTO0:
994 return s3c_timers_get(s, tm);
995 default:
996 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
997 break;
998 }
999 return 0;
1000 }
1001
1002 static void s3c_timers_write(void *opaque, target_phys_addr_t addr,
1003 uint32_t value)
1004 {
1005 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1006 int tm = 0;
1007 // s->base;
1008
1009 switch (addr) {
1010 case S3C_TCFG0:
1011 s->config[0] = value & 0x00ffffff;
1012 break;
1013 case S3C_TCFG1:
1014 s->config[1] = value & 0x00ffffff;
1015 break;
1016 case S3C_TCON:
1017 for (tm = 0; tm < 5; tm ++) {
1018 if (value & (2 << (s3c_tm_bits[tm]))) {
1019 if (s->timer[tm].running) {
1020 s3c_timers_stop(s, tm);
1021 s->timer[tm].count = s->countb[tm];
1022 s3c_timers_start(s, tm);
1023 } else
1024 s->timer[tm].count = s->countb[tm];
1025 }
1026 if (((value >> s3c_tm_bits[tm]) & 1) ^ s->timer[tm].running) {
1027 if (s->timer[tm].running)
1028 s3c_timers_stop(s, tm);
1029 else
1030 s3c_timers_start(s, tm);
1031 }
1032 }
1033
1034 s->control = value & 0x007fff1f;
1035 break;
1036 case S3C_TCMPB3: tm ++;
1037 case S3C_TCMPB2: tm ++;
1038 case S3C_TCMPB1: tm ++;
1039 case S3C_TCMPB0:
1040 s->compareb[tm] = value & 0xffff;
1041 if (s->timer[tm].cmp_cb)
1042 s->timer[tm].cmp_cb(tm, s->compareb[tm], s->timer[tm].cmp_opaque);
1043 break;
1044 case S3C_TCNTB4: tm ++;
1045 case S3C_TCNTB3: tm ++;
1046 case S3C_TCNTB2: tm ++;
1047 case S3C_TCNTB1: tm ++;
1048 case S3C_TCNTB0:
1049 s->countb[tm] = value & 0xffff;
1050 break;
1051 default:
1052 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1053 }
1054 }
1055
1056 static CPUReadMemoryFunc *s3c_timers_readfn[] = {
1057 s3c_timers_read,
1058 s3c_timers_read,
1059 s3c_timers_read,
1060 };
1061
1062 static CPUWriteMemoryFunc *s3c_timers_writefn[] = {
1063 s3c_timers_write,
1064 s3c_timers_write,
1065 s3c_timers_write,
1066 };
1067
1068 static void s3c_timers_save(QEMUFile *f, void *opaque)
1069 {
1070 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1071 int i;
1072 for (i = 0; i < 5; i ++) {
1073 qemu_put_be32(f, s->timer[i].running);
1074 qemu_put_be32s(f, &s->timer[i].divider);
1075 qemu_put_be16(f, s3c_timers_get(s, i));
1076 qemu_put_be64s(f, &s->timer[i].reload);
1077 }
1078
1079 for (i = 0; i < 4; i ++)
1080 qemu_put_be16s(f, &s->compareb[i]);
1081 for (i = 0; i < 5; i ++)
1082 qemu_put_be16s(f, &s->countb[i]);
1083 for (i = 0; i < 2; i ++)
1084 qemu_put_be32s(f, &s->config[i]);
1085 qemu_put_be32s(f, &s->control);
1086 }
1087
1088 static int s3c_timers_load(QEMUFile *f, void *opaque, int version_id)
1089 {
1090 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1091 int i, running[5];
1092 for (i = 0; i < 5; i ++) {
1093 s->timer[i].running = 0;
1094 running[i] = qemu_get_be32(f);
1095 qemu_get_be32s(f, &s->timer[i].divider);
1096 qemu_get_be16s(f, &s->timer[i].count);
1097 qemu_get_be64s(f, &s->timer[i].reload);
1098 }
1099
1100 for (i = 0; i < 4; i ++)
1101 qemu_get_be16s(f, &s->compareb[i]);
1102 for (i = 0; i < 5; i ++)
1103 qemu_get_be16s(f, &s->countb[i]);
1104 for (i = 0; i < 2; i ++)
1105 qemu_get_be32s(f, &s->config[i]);
1106 qemu_get_be32s(f, &s->control);
1107
1108 for (i = 0; i < 5; i ++)
1109 if (running[i])
1110 s3c_timers_start(s, i);
1111
1112 return 0;
1113 }
1114
1115 struct s3c_timers_state_s *s3c_timers_init(target_phys_addr_t base,
1116 qemu_irq *pic, qemu_irq *dma)
1117 {
1118 int i, iomemtype;
1119 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *)
1120 qemu_mallocz(sizeof(struct s3c_timers_state_s));
1121
1122 s->base = base;
1123 s->dma = dma;
1124
1125 s3c_timers_reset(s);
1126
1127 for (i = 0; i < 5; i ++) {
1128 s->timer[i].t = qemu_new_timer(vm_clock,
1129 s3c_timers_tick, &s->timer[i]);
1130 s->timer[i].s = s;
1131 s->timer[i].n = i;
1132 s->timer[i].cmp_cb = 0;
1133 s->timer[i].irq = pic[i];
1134 }
1135
1136 iomemtype = cpu_register_io_memory(0, s3c_timers_readfn,
1137 s3c_timers_writefn, s);
1138 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1139
1140 register_savevm("s3c24xx_timers", 0, 0,
1141 s3c_timers_save, s3c_timers_load, s);
1142
1143 return s;
1144 }
1145
1146 void s3c_timers_cmp_handler_set(void *opaque, int line,
1147 gpio_handler_t handler, void *cmp_opaque)
1148 {
1149 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1150 if (line > 4 || line < 0) {
1151 printf("%s: Bad timer number %i.\n", __FUNCTION__, line);
1152 exit(-1);
1153 }
1154 s->timer[line].cmp_cb = handler;
1155 s->timer[line].cmp_opaque = cmp_opaque;
1156 }
1157
1158 /* UART */
1159 struct s3c_uart_state_s {
1160 target_phys_addr_t base;
1161 qemu_irq *irq;
1162 qemu_irq *dma;
1163 uint8_t data;
1164 uint8_t rxfifo[16];
1165 int rxstart;
1166 int rxlen;
1167 #define UART_MAX_CHR 4
1168 int chr_num;
1169 CharDriverState *chr[UART_MAX_CHR];
1170
1171 uint8_t lcontrol;
1172 uint8_t fcontrol;
1173 uint8_t mcontrol;
1174 uint16_t control;
1175 uint16_t brdiv;
1176 uint8_t errstat;
1177 };
1178
1179 static void s3c_uart_reset(struct s3c_uart_state_s *s)
1180 {
1181 s->lcontrol = 0x00;
1182 s->fcontrol = 0x00;
1183 s->mcontrol = 0x00;
1184 s->control = 0x0000;
1185 s->errstat = 0;
1186
1187 s->rxstart = 0;
1188 s->rxlen = 0;
1189 }
1190
1191 static void s3c_uart_err(struct s3c_uart_state_s *s, int err)
1192 {
1193 s->errstat |= err;
1194 if (s->control & (1 << 6))
1195 qemu_irq_raise(s->irq[2]);
1196 }
1197
1198 inline static void s3c_uart_full(struct s3c_uart_state_s *s, int pulse)
1199 {
1200 if (s->fcontrol & 1) /* FIFOEnable */
1201 if (s->rxlen < (((s->fcontrol >> 4) & 3) + 1) * 4) {
1202 if (((s->control >> 0) & 3) != 1 || /* ReceiveMode */
1203 !s->rxlen)
1204 return;
1205 if (!(s->control & (1 << 7))) /* RxTimeOutEnable */
1206 return;
1207 /* When the Rx FIFO trigger level is not reached, the interrupt
1208 * is generated anyway, just after a small timeout instead of
1209 * immediately. */
1210 }
1211
1212 switch ((s->control >> 0) & 3) { /* ReceiveMode */
1213 case 1:
1214 if ((s->control & (1 << 8)) || pulse) /* RxInterruptType */
1215 qemu_irq_raise(s->irq[0]);
1216 break;
1217 case 2:
1218 case 3:
1219 qemu_irq_raise(s->dma[0]);
1220 break;
1221 }
1222 }
1223
1224 inline static void s3c_uart_empty(struct s3c_uart_state_s *s, int pulse)
1225 {
1226 switch ((s->control >> 2) & 3) { /* TransmitMode */
1227 case 1:
1228 if ((s->control & (1 << 9)) || pulse) /* TxInterruptType */
1229 qemu_irq_raise(s->irq[1]);
1230 break;
1231 case 2:
1232 case 3:
1233 qemu_irq_raise(s->dma[0]);
1234 break;
1235 }
1236 }
1237
1238 inline static void s3c_uart_update(struct s3c_uart_state_s *s)
1239 {
1240 s3c_uart_empty(s, 0);
1241 s3c_uart_full(s, 0);
1242 }
1243
1244 static void s3c_uart_params_update(struct s3c_uart_state_s *s)
1245 {
1246 QEMUSerialSetParams ssp;
1247 int i;
1248 if (!s->chr)
1249 return;
1250
1251 /* XXX Calculate PCLK frequency from clock manager registers */
1252 ssp.speed = (S3C_PCLK_FREQ >> 4) / (s->brdiv + 1);
1253
1254 switch ((s->lcontrol >> 3) & 7) {
1255 case 4:
1256 case 6:
1257 ssp.parity = 'O';
1258 break;
1259 case 5:
1260 case 7:
1261 ssp.parity = 'E';
1262 break;
1263 default:
1264 ssp.parity = 'N';
1265 }
1266
1267 ssp.data_bits = 5 + (s->lcontrol & 3);
1268
1269 ssp.stop_bits = (s->lcontrol & (1 << 2)) ? 2 : 1;
1270
1271 for (i = 0; i < s->chr_num; i ++)
1272 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1273 }
1274
1275 static int s3c_uart_is_empty(void *opaque)
1276 {
1277 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1278 if (s->fcontrol & 1) /* FIFOEnable */
1279 return 16 - s->rxlen;
1280 else
1281 return 1 - s->rxlen;
1282 }
1283
1284 static void s3c_uart_rx(void *opaque, const uint8_t *buf, int size)
1285 {
1286 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1287 int left;
1288 if (s->fcontrol & 1) { /* FIFOEnable */
1289 if (s->rxlen + size > 16) {
1290 size = 16 - s->rxlen;
1291 s3c_uart_err(s, 1);
1292 }
1293
1294 left = 16 - ((s->rxstart + s->rxlen) & 15);
1295 if (size > left) {
1296 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, left);
1297 memcpy(s->rxfifo, buf + left, size - left);
1298 } else
1299 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, size);
1300 s->rxlen += size;
1301 } else {
1302 if (s->rxlen + size > 1)
1303 s3c_uart_err(s, 1);
1304 s->rxlen = 1;
1305 s->data = buf[0];
1306 }
1307 s3c_uart_full(s, 1);
1308 }
1309
1310 /* S3C2410 UART doesn't seem to understand break conditions. */
1311 static void s3c_uart_event(void *opaque, int event)
1312 {
1313 }
1314
1315 #define S3C_ULCON 0x00 /* UART Line Control register */
1316 #define S3C_UCON 0x04 /* UART Control register */
1317 #define S3C_UFCON 0x08 /* UART FIFO Control register */
1318 #define S3C_UMCON 0x0c /* UART Modem Control register */
1319 #define S3C_UTRSTAT 0x10 /* UART Tx/Rx Status register */
1320 #define S3C_UERSTAT 0x14 /* UART Error Status register */
1321 #define S3C_UFSTAT 0x18 /* UART FIFO Status register */
1322 #define S3C_UMSTAT 0x1c /* UART Modem Status register */
1323 #define S3C_UTXH 0x20 /* UART Transmit Buffer register */
1324 #define S3C_URXH 0x24 /* UART Receive Buffer register */
1325 #define S3C_UBRDIV 0x28 /* UART Baud Rate Divisor register */
1326
1327 static uint32_t s3c_uart_read(void *opaque, target_phys_addr_t addr)
1328 {
1329 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1330 uint8_t ret;
1331
1332 switch (addr) {
1333 case S3C_ULCON:
1334 return s->lcontrol;
1335 case S3C_UCON:
1336 return s->control;
1337 case S3C_UFCON:
1338 return s->fcontrol;
1339 case S3C_UMCON:
1340 return s->mcontrol;
1341 case S3C_UTRSTAT:
1342 return 6 | !!s->rxlen;
1343 case S3C_UERSTAT:
1344 /* XXX: UERSTAT[3] is Reserved but Linux thinks it is BREAK */
1345 ret = s->errstat;
1346 s->errstat = 0;
1347 s3c_uart_update(s);
1348 return ret;
1349 case S3C_UFSTAT:
1350 s3c_uart_update(s);
1351 return s->rxlen ? s->rxlen | (1 << 8) : 0;
1352 case S3C_UMSTAT:
1353 s3c_uart_update(s);
1354 return 0x11;
1355 case S3C_UTXH: /* why this is called by u-boot is not clear */
1356 return 0;
1357 case S3C_URXH:
1358 s3c_uart_update(s);
1359 if (s->rxlen) {
1360 s->rxlen --;
1361 if (s->fcontrol & 1) { /* FIFOEnable */
1362 ret = s->rxfifo[s->rxstart ++];
1363 s->rxstart &= 15;
1364 } else
1365 ret = s->data;
1366 return ret;
1367 }
1368 return 0;
1369 case S3C_UBRDIV:
1370 return s->brdiv;
1371 default:
1372 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1373 break;
1374 }
1375 return 0;
1376 }
1377
1378 static void s3c_uart_write(void *opaque, target_phys_addr_t addr,
1379 uint32_t value)
1380 {
1381 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1382 uint8_t ch;
1383 int i, afc;
1384
1385 switch (addr) {
1386 case S3C_ULCON:
1387 if ((s->lcontrol ^ value) & (1 << 6))
1388 printf("%s: UART Infra-red mode %s\n", __FUNCTION__,
1389 (value & (1 << 6)) ? "on" : "off");
1390 s->lcontrol = value;
1391 s3c_uart_params_update(s);
1392 s3c_uart_update(s);
1393 break;
1394 case S3C_UCON:
1395 /* XXX: UCON[4] is Reserved but Linux thinks it is BREAK */
1396 if ((s->control ^ value) & (1 << 5))
1397 printf("%s: UART loopback test mode %s\n", __FUNCTION__,
1398 (value & (1 << 5)) ? "on" : "off");
1399 s->control = value & 0x7ef;
1400 s3c_uart_update(s);
1401 break;
1402 case S3C_UFCON:
1403 if (value & (1 << 1)) /* RxReset */
1404 s->rxlen = 0;
1405 s->fcontrol = value & 0xf1;
1406 s3c_uart_update(s);
1407 break;
1408 case S3C_UMCON:
1409 #ifdef CONFIG_S3C_MODEM /* not handled, openmoko modem.c not imported */
1410 if ((s->mcontrol ^ value) & (1 << 4)) {
1411 afc = (value >> 4) & 1;
1412 for (i = 0; i < s->chr_num; i ++)
1413 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_MODEM_HANDSHAKE, &afc);
1414 }
1415 #endif
1416 s->mcontrol = value & 0x11;
1417 s3c_uart_update(s);
1418 break;
1419 case S3C_UTXH:
1420 ch = value & 0xff;
1421 for (i = 0; i < s->chr_num; i ++)
1422 qemu_chr_write(s->chr[i], &ch, 1);
1423 s3c_uart_empty(s, 1);
1424 s3c_uart_update(s);
1425 break;
1426 case S3C_UBRDIV:
1427 s->brdiv = value & 0xffff;
1428 s3c_uart_params_update(s);
1429 s3c_uart_update(s);
1430 break;
1431 default:
1432 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1433 }
1434 }
1435
1436 static CPUReadMemoryFunc *s3c_uart_readfn[] = {
1437 s3c_uart_read,
1438 s3c_uart_read,
1439 s3c_uart_read,
1440 };
1441
1442 static CPUWriteMemoryFunc *s3c_uart_writefn[] = {
1443 s3c_uart_write,
1444 s3c_uart_write,
1445 s3c_uart_write,
1446 };
1447
1448 static void s3c_uart_save(QEMUFile *f, void *opaque)
1449 {
1450 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1451 qemu_put_8s(f, &s->data);
1452 qemu_put_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1453 qemu_put_be32(f, s->rxstart);
1454 qemu_put_be32(f, s->rxlen);
1455 qemu_put_8s(f, &s->lcontrol);
1456 qemu_put_8s(f, &s->fcontrol);
1457 qemu_put_8s(f, &s->mcontrol);
1458 qemu_put_be16s(f, &s->control);
1459 qemu_put_be16s(f, &s->brdiv);
1460 qemu_put_8s(f, &s->errstat);
1461 }
1462
1463 static int s3c_uart_load(QEMUFile *f, void *opaque, int version_id)
1464 {
1465 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1466 qemu_get_8s(f, &s->data);
1467 qemu_get_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1468 s->rxstart = qemu_get_be32(f);
1469 s->rxlen = qemu_get_be32(f);
1470 qemu_get_8s(f, &s->lcontrol);
1471 qemu_get_8s(f, &s->fcontrol);
1472 qemu_get_8s(f, &s->mcontrol);
1473 qemu_get_be16s(f, &s->control);
1474 qemu_get_be16s(f, &s->brdiv);
1475 qemu_get_8s(f, &s->errstat);
1476
1477 return 0;
1478 }
1479
1480 struct s3c_uart_state_s *s3c_uart_init(target_phys_addr_t base,
1481 qemu_irq *irqs, qemu_irq *dma)
1482 {
1483 int iomemtype;
1484 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *)
1485 qemu_mallocz(sizeof(struct s3c_uart_state_s));
1486
1487 s->base = base;
1488 s->irq = irqs;
1489 s->dma = dma;
1490
1491 s3c_uart_reset(s);
1492
1493 iomemtype = cpu_register_io_memory(0, s3c_uart_readfn,
1494 s3c_uart_writefn, s);
1495 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1496
1497 register_savevm("s3c24xx_uart", base, 0, s3c_uart_save, s3c_uart_load, s);
1498
1499 return s;
1500 }
1501
1502 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr)
1503 {
1504 if (s->chr_num >= UART_MAX_CHR)
1505 cpu_abort(cpu_single_env, "%s: Too many devices\n", __FUNCTION__);
1506 s->chr[s->chr_num ++] = chr;
1507
1508 qemu_chr_add_handlers(chr, s3c_uart_is_empty,
1509 s3c_uart_rx, s3c_uart_event, s);
1510 }
1511
1512 /* ADC & Touchscreen interface */
1513 struct s3c_adc_state_s {
1514 target_phys_addr_t base;
1515 qemu_irq irq;
1516 qemu_irq tcirq;
1517 QEMUTimer *convt;
1518 QEMUTimer *tst;
1519 int x;
1520 int y;
1521 int down;
1522 int enable;
1523 int input[8];
1524 int in_idx;
1525 int noise;
1526 int scale[6];
1527
1528 uint16_t control;
1529 uint16_t ts;
1530 uint16_t delay;
1531 int16_t xdata;
1532 int16_t ydata;
1533 };
1534
1535 static void s3c_adc_reset(struct s3c_adc_state_s *s)
1536 {
1537 s->down = 0;
1538 s->control = 0x3fc4;
1539 s->ts = 0x58;
1540 s->delay = 0xff;
1541 s->enable = 1;
1542 }
1543
1544 static void s3c_adc_start(struct s3c_adc_state_s *s)
1545 {
1546 if (!s->enable || (s->ts & 7) == 0)
1547 return;
1548 s->control &= ~(1 << 15);
1549 s->in_idx = (s->control >> 3) & 7;
1550 qemu_mod_timer(s->convt, qemu_get_clock(vm_clock) + (ticks_per_sec >> 5));
1551 }
1552
1553 static void s3c_adc_done(void *opaque)
1554 {
1555 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1556 s->xdata = s->input[s->in_idx] & 0x3ff;
1557 s->control |= 1 << 15;
1558 qemu_irq_raise(s->irq);
1559 }
1560
1561 static void s3c_adc_tick(void *opaque)
1562 {
1563 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1564 int sx, sy;
1565
1566 if (s->down) {
1567 if ((s->ts & 3) == 3 && s->enable)
1568 qemu_irq_raise(s->tcirq);
1569 else if (s->enable && ((s->ts & (1 << 2)) || (s->ts & 3))) {
1570 sx = s->x * s->scale[0] + s->y * s->scale[1] + s->scale[2];
1571 sy = s->x * s->scale[3] + s->y * s->scale[4] + s->scale[5];
1572 s->xdata = ((sx >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1573 s->ydata = ((sy >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1574 s->xdata ^= s->noise >> 1;
1575 s->ydata ^= s->noise >> 2;
1576 qemu_irq_raise(s->irq);
1577 s->noise ++;
1578 s->noise &= 7;
1579 }
1580 qemu_mod_timer(s->tst, qemu_get_clock(vm_clock) +
1581 (ticks_per_sec >> 5));
1582 }
1583 }
1584
1585 static void s3c_adc_event(void *opaque,
1586 int x, int y, int z, int buttons_state)
1587 {
1588 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1589 s->down = !!buttons_state;
1590 s->x = x;
1591 s->y = y;
1592 s3c_adc_tick(s);
1593 }
1594
1595 #define S3C_ADCCON 0x00 /* ADC Control register */
1596 #define S3C_ADCTSC 0x04 /* ADC Touchscreen Control register */
1597 #define S3C_ADCDLY 0x08 /* ADC Start or Interval Delay register */
1598 #define S3C_ADCDAT0 0x0c /* ADC Conversion Data register 0 */
1599 #define S3C_ADCDAT1 0x10 /* ADC Conversion Data register 1 */
1600
1601 static uint32_t s3c_adc_read(void *opaque, target_phys_addr_t addr)
1602 {
1603 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1604
1605 switch (addr) {
1606 case S3C_ADCCON:
1607 return s->control;
1608 case S3C_ADCTSC:
1609 return s->ts;
1610 case S3C_ADCDLY:
1611 return s->delay;
1612 case S3C_ADCDAT0:
1613 if (s->control & 2)
1614 s3c_adc_start(s);
1615 return ((!s->down) << 15) | s->xdata;
1616 case S3C_ADCDAT1:
1617 return ((!s->down) << 15) | s->ydata;
1618 default:
1619 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1620 break;
1621 }
1622 return 0;
1623 }
1624
1625 static void s3c_adc_write(void *opaque, target_phys_addr_t addr,
1626 uint32_t value)
1627 {
1628 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1629
1630 switch (addr) {
1631 case S3C_ADCCON:
1632 s->control = (s->control & 0x8000) | (value & 0x7ffe);
1633 s->enable = !(value & 4);
1634 if ((value & 1) && !(value & 2))
1635 s3c_adc_start(s);
1636 if (!s->enable)
1637 qemu_del_timer(s->convt);
1638 s3c_adc_tick(s);
1639 break;
1640
1641 case S3C_ADCTSC:
1642 s->ts = value & 0xff;
1643 break;
1644
1645 case S3C_ADCDLY:
1646 s->delay = value & 0xffff;
1647 break;
1648
1649 default:
1650 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1651 }
1652 }
1653
1654 static CPUReadMemoryFunc *s3c_adc_readfn[] = {
1655 s3c_adc_read,
1656 s3c_adc_read,
1657 s3c_adc_read,
1658 };
1659
1660 static CPUWriteMemoryFunc *s3c_adc_writefn[] = {
1661 s3c_adc_write,
1662 s3c_adc_write,
1663 s3c_adc_write,
1664 };
1665
1666 static void s3c_adc_save(QEMUFile *f, void *opaque)
1667 {
1668 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1669 int i;
1670 qemu_put_be32(f, s->enable);
1671 for (i = 0; i < 8; i ++)
1672 qemu_put_be32(f, s->input[i]);
1673 qemu_put_be32(f, s->in_idx);
1674 qemu_put_be32(f, s->noise);
1675
1676 qemu_put_be16s(f, &s->control);
1677 qemu_put_be16s(f, &s->ts);
1678 qemu_put_be16s(f, &s->delay);
1679 qemu_put_be16s(f, &s->xdata);
1680 qemu_put_be16s(f, &s->ydata);
1681 }
1682
1683 static int s3c_adc_load(QEMUFile *f, void *opaque, int version_id)
1684 {
1685 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1686 int i;
1687 s->enable = qemu_get_be32(f);
1688 for (i = 0; i < 8; i ++)
1689 s->input[i] = qemu_get_be32(f);
1690 s->in_idx = qemu_get_be32(f);
1691 s->noise = qemu_get_be32(f);
1692
1693 qemu_get_be16s(f, &s->control);
1694 qemu_get_be16s(f, &s->ts);
1695 qemu_get_be16s(f, &s->delay);
1696 qemu_get_be16s(f, &s->xdata);
1697 qemu_get_be16s(f, &s->ydata);
1698
1699 if (s->enable && (s->ts & 7) && !(s->control & (1 << 15)))
1700 s3c_adc_start(s);
1701
1702 return 0;
1703 }
1704
1705 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
1706 qemu_irq tcirq)
1707 {
1708 int iomemtype;
1709 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *)
1710 qemu_mallocz(sizeof(struct s3c_adc_state_s));
1711
1712 s->base = base;
1713 s->irq = irq;
1714 s->tcirq = tcirq;
1715 s->convt = qemu_new_timer(vm_clock, s3c_adc_done, s);
1716 s->tst = qemu_new_timer(vm_clock, s3c_adc_tick, s);
1717
1718 s3c_adc_reset(s);
1719
1720 iomemtype = cpu_register_io_memory(0, s3c_adc_readfn,
1721 s3c_adc_writefn, s);
1722 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1723
1724 /* We want absolute coordinates */
1725 qemu_add_mouse_event_handler(s3c_adc_event, s, 1,
1726 "QEMU S3C2410-driven Touchscreen");
1727
1728 register_savevm("s3c24xx_adc", 0, 0, s3c_adc_save, s3c_adc_load, s);
1729
1730 return s;
1731 }
1732
1733 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[])
1734 {
1735 memcpy(adc->scale, m, 6 * sizeof(int));
1736 }
1737
1738 /* IIC-bus serial interface */
1739 struct s3c_i2c_state_s {
1740 i2c_slave slave;
1741 i2c_bus *bus;
1742 target_phys_addr_t base;
1743 qemu_irq irq;
1744
1745 uint8_t control;
1746 uint8_t status;
1747 uint8_t data;
1748 uint8_t addy;
1749 int busy;
1750 int newstart;
1751 };
1752
1753 static void s3c_i2c_irq(struct s3c_i2c_state_s *s)
1754 {
1755 s->control |= 1 << 4;
1756 if (s->control & (1 << 5))
1757 qemu_irq_raise(s->irq);
1758 }
1759
1760 static void s3c_i2c_reset(struct s3c_i2c_state_s *s)
1761 {
1762 s->control = 0x00;
1763 s->status = 0x00;
1764 s->busy = 0;
1765 s->newstart = 0;
1766 }
1767
1768 static void s3c_i2c_event(i2c_slave *i2c, enum i2c_event event)
1769 {
1770 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1771 if (!(s->status & (1 << 4)))
1772 return;
1773
1774 switch (event) {
1775 case I2C_START_RECV:
1776 case I2C_START_SEND:
1777 s->status |= 1 << 2;
1778 s3c_i2c_irq(s);
1779 break;
1780 case I2C_FINISH:
1781 s->status &= ~6;
1782 break;
1783 case I2C_NACK:
1784 s->status |= 1 << 0;
1785 break;
1786 default:
1787 break;
1788 }
1789 }
1790
1791 static int s3c_i2c_tx(i2c_slave *i2c, uint8_t data)
1792 {
1793 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1794 if (!(s->status & (1 << 4)))
1795 return 1;
1796
1797 if ((s->status >> 6) == 0)
1798 s->data = data; /* TODO */
1799 s->status &= ~(1 << 0);
1800 s3c_i2c_irq(s);
1801
1802 return !(s->control & (1 << 7));
1803 }
1804
1805 static int s3c_i2c_rx(i2c_slave *i2c)
1806 {
1807 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1808 if (!(s->status & (1 << 4)))
1809 return 1;
1810
1811 if ((s->status >> 6) == 1) {
1812 s->status &= ~(1 << 0);
1813 s3c_i2c_irq(s);
1814 return s->data;
1815 }
1816
1817 return 0x00;
1818 }
1819
1820 static void s3c_master_work(void *opaque)
1821 {
1822 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1823 int start = 0, stop = 0, ack = 1;
1824 if (s->control & (1 << 4)) /* Interrupt pending */
1825 return;
1826 if ((s->status & 0x90) != 0x90) /* Master */
1827 return;
1828 stop = ~s->status & (1 << 5);
1829 if (s->newstart && s->status & (1 << 5)) { /* START */
1830 s->busy = 1;
1831 start = 1;
1832 }
1833 s->newstart = 0;
1834 if (!s->busy)
1835 return;
1836
1837 if (start)
1838 ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
1839 else if (stop)
1840 i2c_end_transfer(s->bus);
1841 else if (s->status & (1 << 6))
1842 ack = !i2c_send(s->bus, s->data);
1843 else {
1844 s->data = i2c_recv(s->bus);
1845
1846 if (!(s->control & (1 << 7))) /* ACK */
1847 i2c_nack(s->bus);
1848 }
1849
1850 if (!(s->status & (1 << 5))) {
1851 s->busy = 0;
1852 return;
1853 }
1854 s->status &= ~1;
1855 s->status |= !ack;
1856 if (!ack)
1857 s->busy = 0;
1858 s3c_i2c_irq(s);
1859 }
1860
1861 #define S3C_IICCON 0x00 /* IIC-Bus Control register */
1862 #define S3C_IICSTAT 0x04 /* IIC-Bus Control / Status register */
1863 #define S3C_IICADD 0x08 /* IIC-Bus Address register */
1864 #define S3C_IICDS 0x0c /* IIC-Bus Tx / Rx Data Shift register */
1865
1866 static uint32_t s3c_i2c_read(void *opaque, target_phys_addr_t addr)
1867 {
1868 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1869
1870 switch (addr) {
1871 case S3C_IICCON:
1872 return s->control;
1873 case S3C_IICSTAT:
1874 return s->status & ~(1 << 5); /* Busy signal */
1875 case S3C_IICADD:
1876 return s->addy;
1877 case S3C_IICDS:
1878 return s->data;
1879 default:
1880 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1881 break;
1882 }
1883 return 0;
1884 }
1885
1886 static void s3c_i2c_write(void *opaque, target_phys_addr_t addr,
1887 uint32_t value)
1888 {
1889 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1890
1891 switch (addr) {
1892 case S3C_IICCON:
1893 s->control = (s->control | 0xef) & value;
1894 if (s->busy)
1895 s3c_master_work(s);
1896 break;
1897
1898 case S3C_IICSTAT:
1899 s->status &= 0x0f;
1900 s->status |= value & 0xf0;
1901 if (s->status & (1 << 5))
1902 s->newstart = 1;
1903 s3c_master_work(s);
1904 break;
1905
1906 case S3C_IICADD:
1907 s->addy = value & 0x7f;
1908 i2c_set_slave_address(&s->slave, s->addy);
1909 break;
1910
1911 case S3C_IICDS:
1912 s->data = value & 0xff;
1913 break;
1914
1915 default:
1916 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1917 }
1918 }
1919
1920 static CPUReadMemoryFunc *s3c_i2c_readfn[] = {
1921 s3c_i2c_read,
1922 s3c_i2c_read,
1923 s3c_i2c_read,
1924 };
1925
1926 static CPUWriteMemoryFunc *s3c_i2c_writefn[] = {
1927 s3c_i2c_write,
1928 s3c_i2c_write,
1929 s3c_i2c_write,
1930 };
1931
1932 static void s3c_i2c_save(QEMUFile *f, void *opaque)
1933 {
1934 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1935 qemu_put_8s(f, &s->control);
1936 qemu_put_8s(f, &s->status);
1937 qemu_put_8s(f, &s->data);
1938 qemu_put_8s(f, &s->addy);
1939
1940 qemu_put_be32(f, s->busy);
1941 qemu_put_be32(f, s->newstart);
1942
1943 // i2c_bus_save(f, s->bus);
1944 i2c_slave_save(f, &s->slave);
1945 }
1946
1947 static int s3c_i2c_load(QEMUFile *f, void *opaque, int version_id)
1948 {
1949 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1950 qemu_get_8s(f, &s->control);
1951 qemu_get_8s(f, &s->status);
1952 qemu_get_8s(f, &s->data);
1953 qemu_get_8s(f, &s->addy);
1954
1955 s->busy = qemu_get_be32(f);
1956 s->newstart = qemu_get_be32(f);
1957
1958 // i2c_bus_load(f, s->bus);
1959 i2c_slave_load(f, &s->slave);
1960 return 0;
1961 }
1962
1963 struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq)
1964 {
1965 int iomemtype;
1966 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *)
1967 qemu_mallocz(sizeof(struct s3c_i2c_state_s));
1968
1969 s->base = base;
1970 s->irq = irq;
1971 s->slave.event = s3c_i2c_event;
1972 s->slave.send = s3c_i2c_tx;
1973 s->slave.recv = s3c_i2c_rx;
1974 s->bus = i2c_init_bus();
1975
1976 s3c_i2c_reset(s);
1977
1978 iomemtype = cpu_register_io_memory(0, s3c_i2c_readfn,
1979 s3c_i2c_writefn, s);
1980 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1981
1982 register_savevm("s3c24xx_i2c", 0, 0, s3c_i2c_save, s3c_i2c_load, s);
1983
1984 return s;
1985 }
1986
1987 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s)
1988 {
1989 return s->bus;
1990 }
1991
1992 /* Serial Peripheral Interface */
1993 struct s3c_spi_state_s {
1994 target_phys_addr_t base;
1995
1996 struct {
1997 qemu_irq irq;
1998 qemu_irq drq;
1999 qemu_irq miso;
2000
2001 uint8_t control;
2002 uint8_t pin;
2003 uint8_t pre;
2004
2005 int cs_pin;
2006 int clk_pin;
2007 int mosi_pin;
2008 uint8_t txbuf;
2009 uint8_t rxbuf;
2010 int bit;
2011 } chan[2];
2012
2013 uint8_t (*txrx[2])(void *opaque, uint8_t value);
2014 uint8_t (*btxrx[2])(void *opaque, uint8_t value);
2015 void *opaque[2];
2016 };
2017
2018 static void s3c_spi_update(struct s3c_spi_state_s *s)
2019 {
2020 int i;
2021 for (i = 0; i < 2; i ++) {
2022 switch ((s->chan[i].control >> 5) & 3) { /* SMOD */
2023 case 1:
2024 qemu_irq_raise(s->chan[i].irq);
2025 break;
2026 case 2:
2027 qemu_irq_raise(s->chan[i].drq);
2028 break;
2029 }
2030 }
2031 }
2032
2033 static void s3c_spi_reset(struct s3c_spi_state_s *s)
2034 {
2035 memset(s->chan, 0, sizeof(s->chan));
2036 s->chan[0].pin = 0x02;
2037 s->chan[1].pin = 0x02;
2038 s3c_spi_update(s);
2039 }
2040
2041 #define S3C_SPCON0 0x00 /* SPI channel 0 control register */
2042 #define S3C_SPSTA0 0x04 /* SPI channel 0 status register */
2043 #define S3C_SPPIN0 0x08 /* SPI channel 0 pin control register */
2044 #define S3C_SPPRE0 0x0c /* SPI channel 0 baudrate prescaler register */
2045 #define S3C_SPTDAT0 0x10 /* SPI channel 0 Tx data register */
2046 #define S3C_SPRDAT0 0x14 /* SPI channel 0 Rx data register */
2047 #define S3C_SPCON1 0x20 /* SPI channel 1 control register */
2048 #define S3C_SPSTA1 0x24 /* SPI channel 1 status register */
2049 #define S3C_SPPIN1 0x28 /* SPI channel 1 pin control register */
2050 #define S3C_SPPRE1 0x2c /* SPI channel 1 baudrate prescaler register */
2051 #define S3C_SPTDAT1 0x30 /* SPI channel 1 Tx data register */
2052 #define S3C_SPRDAT1 0x34 /* SPI channel 1 Rx data register */
2053
2054 static uint32_t s3c_spi_read(void *opaque, target_phys_addr_t addr)
2055 {
2056 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2057 int ch;
2058
2059 ch = addr >> 5;
2060
2061 switch (addr) {
2062 case S3C_SPCON0:
2063 case S3C_SPCON1:
2064 return s->chan[ch].control;
2065
2066 case S3C_SPSTA0:
2067 case S3C_SPSTA1:
2068 return 0x01;
2069
2070 case S3C_SPPIN0:
2071 case S3C_SPPIN1:
2072 return s->chan[ch].pin;
2073
2074 case S3C_SPPRE0:
2075 case S3C_SPPRE1:
2076 return s->chan[ch].pre;
2077
2078 case S3C_SPTDAT0:
2079 case S3C_SPTDAT1:
2080 return s->chan[ch + 2].txbuf;
2081
2082 case S3C_SPRDAT0:
2083 case S3C_SPRDAT1:
2084 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x19)
2085 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], 'Q');
2086 s3c_spi_update(s);
2087 return s->chan[ch].rxbuf;
2088
2089 default:
2090 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2091 break;
2092 }
2093 return 0;
2094 }
2095
2096 static void s3c_spi_write(void *opaque, target_phys_addr_t addr,
2097 uint32_t value)
2098 {
2099 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2100 int ch;
2101
2102 ch = addr >> 5;
2103
2104 switch (addr) {
2105 case S3C_SPCON0:
2106 case S3C_SPCON1:
2107 s->chan[ch].control = value & 0x7f;
2108 s3c_spi_update(s);
2109 break;
2110
2111 case S3C_SPPIN0:
2112 case S3C_SPPIN1:
2113 s->chan[ch].pin = value & 0x07;
2114 break;
2115
2116 case S3C_SPPRE0:
2117 case S3C_SPPRE1:
2118 s->chan[ch].pre = value & 0xff;
2119 break;
2120
2121 case S3C_SPTDAT0:
2122 case S3C_SPTDAT1:
2123 s->chan[ch].txbuf = value & 0xff;
2124 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x18)
2125 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], value & 0xff);
2126 s3c_spi_update(s);
2127 break;
2128
2129 default:
2130 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2131 }
2132 }
2133
2134 static CPUReadMemoryFunc *s3c_spi_readfn[] = {
2135 s3c_spi_read,
2136 s3c_spi_read,
2137 s3c_spi_read,
2138 };
2139
2140 static CPUWriteMemoryFunc *s3c_spi_writefn[] = {
2141 s3c_spi_write,
2142 s3c_spi_write,
2143 s3c_spi_write,
2144 };
2145
2146 static void s3c_spi_save(QEMUFile *f, void *opaque)
2147 {
2148 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2149 int i;
2150 for (i = 0; i < 2; i ++) {
2151 qemu_put_8s(f, &s->chan[i].control);
2152 qemu_put_8s(f, &s->chan[i].pin);
2153 qemu_put_8s(f, &s->chan[i].pre);
2154
2155 qemu_put_8s(f, &s->chan[i].txbuf);
2156 qemu_put_8s(f, &s->chan[i].rxbuf);
2157 qemu_put_be32(f, s->chan[i].cs_pin);
2158 qemu_put_be32(f, s->chan[i].clk_pin);
2159 qemu_put_be32(f, s->chan[i].mosi_pin);
2160 qemu_put_be32(f, s->chan[i].bit);
2161 }
2162 }
2163
2164 static int s3c_spi_load(QEMUFile *f, void *opaque, int version_id)
2165 {
2166 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2167 int i;
2168 for (i = 0; i < 2; i ++) {
2169 qemu_get_8s(f, &s->chan[i].control);
2170 qemu_get_8s(f, &s->chan[i].pin);
2171 qemu_get_8s(f, &s->chan[i].pre);
2172
2173 qemu_get_8s(f, &s->chan[i].txbuf);
2174 qemu_get_8s(f, &s->chan[i].rxbuf);
2175 s->chan[i].cs_pin = qemu_get_be32(f);
2176 s->chan[i].clk_pin = qemu_get_be32(f);
2177 s->chan[i].mosi_pin = qemu_get_be32(f);
2178 s->chan[i].bit = qemu_get_be32(f);
2179 }
2180
2181 return 0;
2182 }
2183
2184 static void s3c_spi_bitbang_cs(void *opaque, int line, int level)
2185 {
2186 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2187 int ch = line;
2188 if (s->chan[ch].cs_pin || level) {
2189 if (s->chan[ch].bit && s->txrx[ch] && !s->btxrx[ch]) {
2190 s->chan[ch].txbuf <<= 8 - s->chan[ch].bit;
2191 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2192 }
2193 } else if (!s->chan[ch].cs_pin || !level)
2194 s->chan[ch].bit = 0;
2195
2196 /* SSn is active low. */
2197 s->chan[ch].cs_pin = !level;
2198 }
2199
2200 static void s3c_spi_bitbang_clk(void *opaque, int line, int level)
2201 {
2202 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2203 int ch = line;
2204 if (!s->chan[ch].cs_pin)
2205 goto done;
2206
2207 /* Detect CLK rising edge */
2208 if (s->chan[ch].clk_pin || !level)
2209 goto done;
2210
2211 if (s->btxrx[ch]) {
2212 qemu_set_irq(s->chan[ch].miso,
2213 s->btxrx[ch](s->opaque[ch], s->chan[ch].mosi_pin));
2214 goto done;
2215 }
2216
2217 s->chan[ch].txbuf <<= 1;
2218 s->chan[ch].txbuf |= s->chan[ch].mosi_pin;
2219
2220 qemu_set_irq(s->chan[ch].miso, (s->chan[ch].rxbuf >> 7) & 1);
2221 s->chan[ch].rxbuf <<= 1;
2222
2223 if (++ s->chan[ch].bit == 8) {
2224 if (s->txrx[ch])
2225 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2226 s->chan[ch].bit = 0;
2227 }
2228
2229 done:
2230 s->chan[ch].clk_pin = level;
2231 }
2232
2233 static void s3c_spi_bitbang_mosi(void *opaque, int line, int level)
2234 {
2235 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2236 int ch = line;
2237 s->chan[ch].mosi_pin = level;
2238 }
2239
2240 static const struct {
2241 int cs, clk, miso, mosi;
2242 } s3c_spi_pins[2] = {
2243 { S3C_GPG(2), S3C_GPE(13), S3C_GPE(11), S3C_GPE(12) },
2244 { S3C_GPG(3), S3C_GPG(7), S3C_GPG(5), S3C_GPG(6) },
2245 };
2246
2247 static void s3c_spi_bitbang_init(struct s3c_spi_state_s *s,
2248 struct s3c_gpio_state_s *gpio)
2249 {
2250 int i;
2251 qemu_irq *cs = qemu_allocate_irqs(s3c_spi_bitbang_cs, s, 2);
2252 qemu_irq *clk = qemu_allocate_irqs(s3c_spi_bitbang_clk, s, 2);
2253 qemu_irq *mosi = qemu_allocate_irqs(s3c_spi_bitbang_mosi, s, 2);
2254
2255 for (i = 0; i < 2; i ++) {
2256 s3c_gpio_out_set(gpio, s3c_spi_pins[i].cs, cs[i]);
2257 s3c_gpio_out_set(gpio, s3c_spi_pins[i].clk, clk[i]);
2258 s->chan[i].miso = s3c_gpio_in_get(gpio)[s3c_spi_pins[i].miso];
2259 s3c_gpio_out_set(gpio, s3c_spi_pins[i].mosi, mosi[i]);
2260 }
2261 }
2262
2263 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
2264 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
2265 struct s3c_gpio_state_s *gpio)
2266 {
2267 int iomemtype;
2268 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *)
2269 qemu_mallocz(sizeof(struct s3c_spi_state_s));
2270
2271 s->base = base;
2272 s->chan[0].irq = irq0;
2273 s->chan[0].drq = drq0;
2274 s->chan[1].irq = irq1;
2275 s->chan[1].drq = drq1;
2276
2277 s3c_spi_reset(s);
2278
2279 iomemtype = cpu_register_io_memory(0, s3c_spi_readfn,
2280 s3c_spi_writefn, s);
2281 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2282
2283 s3c_spi_bitbang_init(s, gpio);
2284
2285 register_savevm("s3c24xx_spi", 0, 0, s3c_spi_save, s3c_spi_load, s);
2286
2287 return s;
2288 }
2289
2290 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
2291 uint8_t (*txrx)(void *opaque, uint8_t value),
2292 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque)
2293 {
2294 if (ch & ~1)
2295 cpu_abort(cpu_single_env, "%s: No channel %i\n", __FUNCTION__, ch);
2296 s->txrx[ch] = txrx;
2297 s->btxrx[ch] = btxrx;
2298 s->opaque[ch] = opaque;
2299 }
2300
2301 /* IIS-BUS interface */
2302 static inline void s3c_i2s_update(struct s3c_i2s_state_s *s)
2303 {
2304 s->tx_en =
2305 (s->control & (1 << 0)) && !(s->control & (1 << 3)) &&
2306 (s->mode & (1 << 7)) && (s->fcontrol & (1 << 13));
2307 s->rx_en =
2308 (s->control & (1 << 0)) && !(s->control & (1 << 2)) &&
2309 (s->mode & (1 << 6)) && (s->fcontrol & (1 << 12));
2310 s->control &= ~0xc0;
2311 /* The specs are unclear about the FIFO-ready flags logic.
2312 * Implement semantics that make most sense. */
2313 if (s->tx_en && s->tx_len)
2314 s->control |= (1 << 7);
2315 if (s->rx_en && s->rx_len)
2316 s->control |= (1 << 6);
2317
2318 qemu_set_irq(s->dma[S3C_RQ_I2SSDO], (s->control >> 5) &
2319 (s->control >> 7) & (s->fcontrol >> 15) & 1);
2320 qemu_set_irq(s->dma[S3C_RQ_I2SSDI0], (s->control >> 4) &
2321 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2322 qemu_set_irq(s->dma[S3C_RQ_I2SSDI1], (s->control >> 4) &
2323 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2324 }
2325
2326 static void s3c_i2s_reset(struct s3c_i2s_state_s *s)
2327 {
2328 s->control = 0x100;
2329 s->mode = 0x000;
2330 s->prescaler = 0x000;
2331 s->fcontrol = 0x0000;
2332 s->tx_len = 0;
2333 s->rx_len = 0;
2334 s3c_i2s_update(s);
2335 }
2336
2337 #define S3C_IISCON 0x00 /* IIS Control register */
2338 #define S3C_IISMOD 0x04 /* IIS Mode register */
2339 #define S3C_IISPSR 0x08 /* IIS Prescaler register */
2340 #define S3C_IISFCON 0x0c /* IIS FIFO Interface register */
2341 #define S3C_IISFIFO 0x10 /* IIS FIFO register */
2342
2343 static uint32_t s3c_i2s_read(void *opaque, target_phys_addr_t addr)
2344 {
2345 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2346 uint32_t ret;
2347
2348 switch (addr) {
2349 case S3C_IISCON:
2350 return s->control;
2351 case S3C_IISMOD:
2352 return s->mode;
2353 case S3C_IISPSR:
2354 return s->prescaler;
2355 case S3C_IISFCON:
2356 return s->fcontrol |
2357 (MAX(32 - s->tx_len, 0) << 6) |
2358 MIN(s->rx_len, 32);
2359 case S3C_IISFIFO:
2360 if (s->rx_len > 0) {
2361 s->rx_len --;
2362 s3c_i2s_update(s);
2363 s->cycle ^= 1;
2364 if (s->cycle) {
2365 s->buffer = (uint16_t) (ret = s->codec_in(s->opaque));
2366 return ret >> 16;
2367 } else
2368 return s->buffer;
2369 }
2370 default:
2371 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2372 break;
2373 }
2374 return 0;
2375 }
2376
2377 static void s3c_i2s_write(void *opaque, target_phys_addr_t addr,
2378 uint32_t value)
2379 {
2380 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2381
2382 switch (addr) {
2383 case S3C_IISCON:
2384 s->control = (s->control & 0x100) | (value & 0x03f);
2385 s3c_i2s_update(s);
2386 break;
2387 case S3C_IISMOD:
2388 s->mode = value & 0x1ff;
2389 s3c_i2s_update(s);
2390 break;
2391 case S3C_IISPSR:
2392 s->prescaler = value & 0x3ff;
2393 break;
2394 case S3C_IISFCON:
2395 s->fcontrol = value & 0xf000;
2396 s3c_i2s_update(s);
2397 break;
2398 case S3C_IISFIFO:
2399 if (s->tx_len && s->tx_en) {
2400 s->tx_len --;
2401 s3c_i2s_update(s);
2402 if (s->cycle)
2403 s->codec_out(s->opaque, value | ((uint32_t) s->buffer << 16));
2404 else
2405 s->buffer = (uint16_t) value;
2406 s->cycle ^= 1;
2407 }
2408 break;
2409 default:
2410 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2411 }
2412 }
2413
2414 static CPUReadMemoryFunc *s3c_i2s_readfn[] = {
2415 s3c_i2s_read,
2416 s3c_i2s_read,
2417 s3c_i2s_read,
2418 };
2419
2420 static CPUWriteMemoryFunc *s3c_i2s_writefn[] = {
2421 s3c_i2s_write,
2422 s3c_i2s_write,
2423 s3c_i2s_write,
2424 };
2425
2426 static void s3c_i2s_save(QEMUFile *f, void *opaque)
2427 {
2428 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2429 qemu_put_be16s(f, &s->control);
2430 qemu_put_be16s(f, &s->mode);
2431 qemu_put_be16s(f, &s->prescaler);
2432 qemu_put_be16s(f, &s->fcontrol);
2433
2434 qemu_put_be32(f, s->tx_en);
2435 qemu_put_be32(f, s->rx_en);
2436 qemu_put_be32(f, s->tx_len);
2437 qemu_put_be32(f, s->rx_len);
2438 qemu_put_be16(f, s->buffer);
2439 qemu_put_be32(f, s->cycle);
2440 }
2441
2442 static int s3c_i2s_load(QEMUFile *f, void *opaque, int version_id)
2443 {
2444 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2445 qemu_get_be16s(f, &s->control);
2446 qemu_get_be16s(f, &s->mode);
2447 qemu_get_be16s(f, &s->prescaler);
2448 qemu_get_be16s(f, &s->fcontrol);
2449
2450 s->tx_en = qemu_get_be32(f);
2451 s->rx_en = qemu_get_be32(f);
2452 s->tx_len = qemu_get_be32(f);
2453 s->rx_len = qemu_get_be32(f);
2454 s->buffer = qemu_get_be16(f);
2455 s->cycle = qemu_get_be32(f);
2456
2457 return 0;
2458 }
2459
2460 static void s3c_i2s_data_req(void *opaque, int tx, int rx)
2461 {
2462 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2463 s->tx_len = tx;
2464 s->rx_len = rx;
2465 s3c_i2s_update(s);
2466 }
2467
2468 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma)
2469 {
2470 int iomemtype;
2471 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *)
2472 qemu_mallocz(sizeof(struct s3c_i2s_state_s));
2473
2474 s->base = base;
2475 s->dma = dma;
2476 s->data_req = s3c_i2s_data_req;
2477
2478 s3c_i2s_reset(s);
2479
2480 iomemtype = cpu_register_io_memory(0, s3c_i2s_readfn,
2481 s3c_i2s_writefn, s);
2482 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2483
2484 register_savevm("s3c24xx_iis", 0, 0, s3c_i2s_save, s3c_i2s_load, s);
2485
2486 return s;
2487 }
2488
2489 /* Watchdog Timer */
2490 struct s3c_wdt_state_s {
2491 target_phys_addr_t base;
2492 qemu_irq irq;
2493 uint16_t control;
2494 uint16_t data;
2495 uint16_t count;
2496 QEMUTimer *tm;
2497 int64_t timestamp;
2498 };
2499
2500 static void s3c_wdt_start(struct s3c_wdt_state_s *s)
2501 {
2502 int enable = s->control & (1 << 5);
2503 int prescaler = (s->control >> 8) + 1;
2504 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2505 if (enable) {
2506 s->timestamp = qemu_get_clock(vm_clock);
2507 qemu_mod_timer(s->tm, s->timestamp + muldiv64(divider * s->count,
2508 ticks_per_sec, S3C_PCLK_FREQ));
2509 } else
2510 qemu_del_timer(s->tm);
2511 }
2512
2513 static void s3c_wdt_stop(struct s3c_wdt_state_s *s)
2514 {
2515 int prescaler = (s->control >> 8) + 1;
2516 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2517 int diff;
2518
2519 diff = muldiv64(qemu_get_clock(vm_clock) - s->timestamp, S3C_PCLK_FREQ,
2520 ticks_per_sec) / divider;
2521 s->count -= MIN(s->count, diff);
2522 s->timestamp = qemu_get_clock(vm_clock);
2523 }
2524
2525 static void s3c_wdt_reset(struct s3c_wdt_state_s *s)
2526 {
2527 s->control = 0x8021;
2528 s->data = 0x8000;
2529 s->count = 0x8000;
2530 s3c_wdt_start(s);
2531 }
2532
2533 static void s3c_wdt_timeout(void *opaque)
2534 {
2535 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2536 if (s->control & (1 << 0)) {
2537 qemu_system_reset_request();
2538 return;
2539 }
2540 if (s->control & (1 << 2))
2541 qemu_irq_raise(s->irq);
2542 s->count = s->data;
2543 s3c_wdt_start(s);
2544 }
2545
2546 #define S3C_WTCON 0x00 /* Watchdog timer control register */
2547 #define S3C_WTDAT 0x04 /* Watchdog timer data register */
2548 #define S3C_WTCNT 0x08 /* Watchdog timer count register */
2549
2550 static uint32_t s3c_wdt_read(void *opaque, target_phys_addr_t addr)
2551 {
2552 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2553
2554 switch (addr) {
2555 case S3C_WTCON:
2556 return s->control;
2557 case S3C_WTDAT:
2558 return s->data;
2559 case S3C_WTCNT:
2560 s3c_wdt_stop(s);
2561 return s->count;
2562 default:
2563 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2564 break;
2565 }
2566 return 0;
2567 }
2568
2569 static void s3c_wdt_write(void *opaque, target_phys_addr_t addr,
2570 uint32_t value)
2571 {
2572 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2573
2574 switch (addr) {
2575 case S3C_WTCON:
2576 s3c_wdt_stop(s);
2577 s->control = value;
2578 s3c_wdt_start(s);
2579 break;
2580 case S3C_WTDAT:
2581 s->data = value;
2582 break;
2583 case S3C_WTCNT:
2584 s->count = value;
2585 s3c_wdt_start(s);
2586 break;
2587 default:
2588 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2589 }
2590 }
2591
2592 static CPUReadMemoryFunc *s3c_wdt_readfn[] = {
2593 s3c_wdt_read,
2594 s3c_wdt_read,
2595 s3c_wdt_read,
2596 };
2597
2598 static CPUWriteMemoryFunc *s3c_wdt_writefn[] = {
2599 s3c_wdt_write,
2600 s3c_wdt_write,
2601 s3c_wdt_write,
2602 };
2603
2604 static void s3c_wdt_save(QEMUFile *f, void *opaque)
2605 {
2606 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2607
2608 s3c_wdt_stop(s);
2609 qemu_put_be16s(f, &s->control);
2610 qemu_put_be16s(f, &s->data);
2611 qemu_put_be16s(f, &s->count);
2612 qemu_put_be64s(f, &s->timestamp);
2613 }
2614
2615 static int s3c_wdt_load(QEMUFile *f, void *opaque, int version_id)
2616 {
2617 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2618
2619 qemu_get_be16s(f, &s->control);
2620 qemu_get_be16s(f, &s->data);
2621 qemu_get_be16s(f, &s->count);
2622 qemu_get_be64s(f, &s->timestamp);
2623 s3c_wdt_start(s);
2624
2625 return 0;
2626 }
2627
2628 struct s3c_wdt_state_s *s3c_wdt_init(target_phys_addr_t base, qemu_irq irq)
2629 {
2630 int iomemtype;
2631 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *)
2632 qemu_mallocz(sizeof(struct s3c_wdt_state_s));
2633
2634 s->base = base;
2635 s->irq = irq;
2636 s->tm = qemu_new_timer(vm_clock, s3c_wdt_timeout, s);
2637
2638 s3c_wdt_reset(s);
2639
2640 iomemtype = cpu_register_io_memory(0, s3c_wdt_readfn,
2641 s3c_wdt_writefn, s);
2642 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2643
2644 register_savevm("s3c24xx_wdt", 0, 0, s3c_wdt_save, s3c_wdt_load, s);
2645
2646 return s;
2647 }
2648
2649 /* On-chip UARTs */
2650 static struct {
2651 target_phys_addr_t base;
2652 int irq[3];
2653 int dma[1];
2654 } s3c2410_uart[] = {
2655 {
2656 0x50000000,
2657 { S3C_PICS_RXD0, S3C_PICS_TXD0, S3C_PICS_ERR0 },
2658 { S3C_RQ_UART0 },
2659 },
2660 {
2661 0x50004000,
2662 { S3C_PICS_RXD1, S3C_PICS_TXD1, S3C_PICS_ERR1 },
2663 { S3C_RQ_UART1 },
2664 },
2665 {
2666 0x50008000,
2667 { S3C_PICS_RXD2, S3C_PICS_TXD2, S3C_PICS_ERR2 },
2668 { S3C_RQ_UART2 },
2669 },
2670 { 0, { 0, 0, 0 }, { 0 } }
2671 };
2672
2673 /* General CPU reset */
2674 static void s3c2410_reset(void *opaque)
2675 {
2676 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
2677 int i;
2678 s3c_mc_reset(s);
2679 s3c_pic_reset(s->pic);
2680 s3c_dma_reset(s->dma);
2681 s3c_gpio_reset(s->io);
2682 s3c_lcd_reset(s->lcd);
2683 s3c_timers_reset(s->timers);
2684 s3c_mmci_reset(s->mmci);
2685 s3c_adc_reset(s->adc);
2686 s3c_i2c_reset(s->i2c);
2687 s3c_i2s_reset(s->i2s);
2688 s3c_rtc_reset(s->rtc);
2689 s3c_spi_reset(s->spi);
2690 s3c_udc_reset(s->udc);
2691 s3c_wdt_reset(s->wdt);
2692 s3c_clkpwr_reset(s);
2693 // s3c_nand_reset(s);
2694 s->nand->reset(s->nand);
2695 for (i = 0; s3c2410_uart[i].base; i ++)
2696 s3c_uart_reset(s->uart[i]);
2697 cpu_reset(s->env);
2698 }
2699
2700 struct s3c_state_s * g_s3c;
2701
2702 /* Initialise an S3C24XX microprocessor. */
2703 struct s3c_state_s *s3c24xx_init(
2704 uint32_t cpu_id,
2705 unsigned int sdram_size,
2706 uint32_t sram_address,
2707 SDState *mmc)
2708 {
2709 struct s3c_state_s *s;
2710 int iomemtype, i;
2711 s = (struct s3c_state_s *) qemu_mallocz(sizeof(struct s3c_state_s));
2712
2713 g_s3c = s;
2714
2715 s->cpu_id = cpu_id;
2716
2717 s->env = cpu_init("arm920t");
2718 if (!s->env) {
2719 fprintf(stderr, "Unable to initialize ARM920T\n");
2720 exit(2);
2721 }
2722 register_savevm("s3c24xx", 0, 0,
2723 cpu_save, cpu_load, s->env);
2724
2725 cpu_register_physical_memory(S3C_RAM_BASE, sdram_size,
2726 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2727
2728 /* If OM pins are 00, SRAM is mapped at 0x0 instead. */
2729 cpu_register_physical_memory(sram_address, S3C_SRAM_SIZE,
2730 qemu_ram_alloc(S3C_SRAM_SIZE) | IO_MEM_RAM);
2731
2732 s->mc_base = 0x48000000;
2733 s3c_mc_reset(s);
2734 iomemtype = cpu_register_io_memory(0, s3c_mc_readfn, s3c_mc_writefn, s);
2735 cpu_register_physical_memory(s->mc_base, 0xffffff, iomemtype);
2736 register_savevm("s3c24xx_mc", 0, 0, s3c_mc_save, s3c_mc_load, s);
2737
2738 s->pic = s3c_pic_init(0x4a000000, arm_pic_init_cpu(s->env));
2739 s->irq = s3c_pic_get(s->pic);
2740
2741 s->dma = s3c_dma_init(0x4b000000, &s->irq[S3C_PIC_DMA0]);
2742 s->drq = s3c_dma_get(s->dma);
2743
2744 s->clkpwr_base = 0x4c000000;
2745 s3c_clkpwr_reset(s);
2746 iomemtype = cpu_register_io_memory(0, s3c_clkpwr_readfn,
2747 s3c_clkpwr_writefn, s);
2748 cpu_register_physical_memory(s->clkpwr_base, 0xffffff, iomemtype);
2749 register_savevm("s3c24xx_clkpwr", 0, 0,
2750 s3c_clkpwr_save, s3c_clkpwr_load, s);
2751
2752 s->lcd = s3c_lcd_init(0x4d000000, s->irq[S3C_PIC_LCD]);
2753
2754 if (s->cpu_id == S3C_CPU_2440)
2755 s->nand = s3c2440_nand_init();
2756 else
2757 s->nand = s3c2410_nand_init();
2758
2759 for (i = 0; s3c2410_uart[i].base; i ++) {
2760 s->uart[i] = s3c_uart_init(s3c2410_uart[i].base,
2761 &s->irq[s3c2410_uart[i].irq[0]],
2762 &s->drq[s3c2410_uart[i].dma[0]]);
2763 if (serial_hds[i])
2764 s3c_uart_attach(s->uart[i], serial_hds[i]);
2765 }
2766
2767 s->timers = s3c_timers_init(0x51000000, &s->irq[S3C_PIC_TIMER0], s->drq);
2768
2769 s->udc = s3c_udc_init(0x52000000, s->irq[S3C_PIC_USBD], s->drq);
2770
2771 s->wdt = s3c_wdt_init(0x53000000, s->irq[S3C_PIC_WDT]);
2772
2773 s->i2c = s3c_i2c_init(0x54000000, s->irq[S3C_PIC_IIC]);
2774
2775 s->i2s = s3c_i2s_init(0x55000000, s->drq);
2776
2777 s->io = s3c_gpio_init(0x56000000, s->irq, s->cpu_id);
2778
2779 s->rtc = s3c_rtc_init(0x57000000, s->irq[S3C_PIC_RTC]);
2780
2781 s->adc = s3c_adc_init(0x58000000, s->irq[S3C_PICS_ADC],
2782 s->irq[S3C_PICS_TC]);
2783
2784 s->spi = s3c_spi_init(0x59000000,
2785 s->irq[S3C_PIC_SPI0], s->drq[S3C_RQ_SPI0],
2786 s->irq[S3C_PIC_SPI1], s->drq[S3C_RQ_SPI1], s->io);
2787
2788 s->mmci = s3c_mmci_init(0x5a000000, s->cpu_id, mmc,
2789 s->irq[S3C_PIC_SDI], s->drq);
2790
2791 if (usb_enabled) {
2792 usb_ohci_init_pxa(0x49000000, 3, -1, s->irq[S3C_PIC_USBH]);
2793 }
2794
2795 qemu_register_reset(s3c2410_reset, s);
2796
2797 s->nand->setwp(s->nand, 1);
2798 //s3c_nand_setwp(s, 1);
2799
2800 /* Power on reset */
2801 s3c_gpio_setpwrstat(s->io, 1);
2802 return s;
2803 }