2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licenced under the GPL.
15 #include "qemu-timer.h"
16 #include "qemu-char.h"
19 target_phys_addr_t io_base
;
22 { 0x40100000, PXA2XX_PIC_FFUART
},
23 { 0x40200000, PXA2XX_PIC_BTUART
},
24 { 0x40700000, PXA2XX_PIC_STUART
},
25 { 0x41600000, PXA25X_PIC_HWUART
},
27 }, pxa270_serial
[] = {
28 { 0x40100000, PXA2XX_PIC_FFUART
},
29 { 0x40200000, PXA2XX_PIC_BTUART
},
30 { 0x40700000, PXA2XX_PIC_STUART
},
34 typedef struct PXASSPDef
{
35 target_phys_addr_t io_base
;
40 static PXASSPDef pxa250_ssp
[] = {
41 { 0x41000000, PXA2XX_PIC_SSP
},
46 static PXASSPDef pxa255_ssp
[] = {
47 { 0x41000000, PXA2XX_PIC_SSP
},
48 { 0x41400000, PXA25X_PIC_NSSP
},
53 static PXASSPDef pxa26x_ssp
[] = {
54 { 0x41000000, PXA2XX_PIC_SSP
},
55 { 0x41400000, PXA25X_PIC_NSSP
},
56 { 0x41500000, PXA26X_PIC_ASSP
},
61 static PXASSPDef pxa27x_ssp
[] = {
62 { 0x41000000, PXA2XX_PIC_SSP
},
63 { 0x41700000, PXA27X_PIC_SSP2
},
64 { 0x41900000, PXA2XX_PIC_SSP3
},
68 #define PMCR 0x00 /* Power Manager Control register */
69 #define PSSR 0x04 /* Power Manager Sleep Status register */
70 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
71 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
72 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
73 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
74 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
75 #define PCFR 0x1c /* Power Manager General Configuration register */
76 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
77 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
78 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
79 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
80 #define RCSR 0x30 /* Reset Controller Status register */
81 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
82 #define PTSR 0x38 /* Power Manager Standby Configuration register */
83 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
84 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
85 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
86 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
87 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
88 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90 static uint32_t pxa2xx_pm_read(void *opaque
, target_phys_addr_t addr
)
92 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
99 return s
->pm_regs
[addr
>> 2];
102 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
108 static void pxa2xx_pm_write(void *opaque
, target_phys_addr_t addr
,
111 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
115 s
->pm_regs
[addr
>> 2] &= 0x15 & ~(value
& 0x2a);
116 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
119 case PSSR
: /* Read-clean registers */
122 s
->pm_regs
[addr
>> 2] &= ~value
;
125 default: /* Read-write registers */
126 if (addr
>= PMCR
&& addr
<= PCMD31
&& !(addr
& 3)) {
127 s
->pm_regs
[addr
>> 2] = value
;
131 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
136 static CPUReadMemoryFunc
*pxa2xx_pm_readfn
[] = {
142 static CPUWriteMemoryFunc
*pxa2xx_pm_writefn
[] = {
148 static void pxa2xx_pm_save(QEMUFile
*f
, void *opaque
)
150 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
153 for (i
= 0; i
< 0x40; i
++)
154 qemu_put_be32s(f
, &s
->pm_regs
[i
]);
157 static int pxa2xx_pm_load(QEMUFile
*f
, void *opaque
, int version_id
)
159 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
162 for (i
= 0; i
< 0x40; i
++)
163 qemu_get_be32s(f
, &s
->pm_regs
[i
]);
168 #define CCCR 0x00 /* Core Clock Configuration register */
169 #define CKEN 0x04 /* Clock Enable register */
170 #define OSCC 0x08 /* Oscillator Configuration register */
171 #define CCSR 0x0c /* Core Clock Status register */
173 static uint32_t pxa2xx_cm_read(void *opaque
, target_phys_addr_t addr
)
175 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
181 return s
->cm_regs
[addr
>> 2];
184 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
187 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
193 static void pxa2xx_cm_write(void *opaque
, target_phys_addr_t addr
,
196 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
201 s
->cm_regs
[addr
>> 2] = value
;
205 s
->cm_regs
[addr
>> 2] &= ~0x6c;
206 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
207 if ((value
>> 1) & 1) /* OON */
208 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
212 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
217 static CPUReadMemoryFunc
*pxa2xx_cm_readfn
[] = {
223 static CPUWriteMemoryFunc
*pxa2xx_cm_writefn
[] = {
229 static void pxa2xx_cm_save(QEMUFile
*f
, void *opaque
)
231 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
234 for (i
= 0; i
< 4; i
++)
235 qemu_put_be32s(f
, &s
->cm_regs
[i
]);
236 qemu_put_be32s(f
, &s
->clkcfg
);
237 qemu_put_be32s(f
, &s
->pmnc
);
240 static int pxa2xx_cm_load(QEMUFile
*f
, void *opaque
, int version_id
)
242 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
245 for (i
= 0; i
< 4; i
++)
246 qemu_get_be32s(f
, &s
->cm_regs
[i
]);
247 qemu_get_be32s(f
, &s
->clkcfg
);
248 qemu_get_be32s(f
, &s
->pmnc
);
253 static uint32_t pxa2xx_clkpwr_read(void *opaque
, int op2
, int reg
, int crm
)
255 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
258 case 6: /* Clock Configuration register */
261 case 7: /* Power Mode register */
265 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
271 static void pxa2xx_clkpwr_write(void *opaque
, int op2
, int reg
, int crm
,
274 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
275 static const char *pwrmode
[8] = {
276 "Normal", "Idle", "Deep-idle", "Standby",
277 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
281 case 6: /* Clock Configuration register */
282 s
->clkcfg
= value
& 0xf;
284 printf("%s: CPU frequency change attempt\n", __FUNCTION__
);
287 case 7: /* Power Mode register */
289 printf("%s: CPU voltage change attempt\n", __FUNCTION__
);
297 if (!(s
->cm_regs
[CCCR
>> 2] & (1 << 31))) { /* CPDIS */
298 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
305 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
306 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
310 s
->env
->uncached_cpsr
=
311 ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
312 s
->env
->cp15
.c1_sys
= 0;
313 s
->env
->cp15
.c1_coproc
= 0;
314 s
->env
->cp15
.c2_base0
= 0;
316 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
317 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
320 * The scratch-pad register is almost universally used
321 * for storing the return address on suspend. For the
322 * lack of a resuming bootloader, perform a jump
323 * directly to that address.
325 memset(s
->env
->regs
, 0, 4 * 15);
326 s
->env
->regs
[15] = s
->pm_regs
[PSPR
>> 2];
329 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
330 cpu_physical_memory_write(0, &buffer
, 4);
331 buffer
= s
->pm_regs
[PSPR
>> 2];
332 cpu_physical_memory_write(8, &buffer
, 4);
336 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
342 printf("%s: machine entered %s mode\n", __FUNCTION__
,
348 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
353 /* Performace Monitoring Registers */
354 #define CPPMNC 0 /* Performance Monitor Control register */
355 #define CPCCNT 1 /* Clock Counter register */
356 #define CPINTEN 4 /* Interrupt Enable register */
357 #define CPFLAG 5 /* Overflow Flag register */
358 #define CPEVTSEL 8 /* Event Selection register */
360 #define CPPMN0 0 /* Performance Count register 0 */
361 #define CPPMN1 1 /* Performance Count register 1 */
362 #define CPPMN2 2 /* Performance Count register 2 */
363 #define CPPMN3 3 /* Performance Count register 3 */
365 static uint32_t pxa2xx_perf_read(void *opaque
, int op2
, int reg
, int crm
)
367 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
374 return qemu_get_clock(vm_clock
);
383 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
389 static void pxa2xx_perf_write(void *opaque
, int op2
, int reg
, int crm
,
392 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
406 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
411 static uint32_t pxa2xx_cp14_read(void *opaque
, int op2
, int reg
, int crm
)
415 return pxa2xx_clkpwr_read(opaque
, op2
, reg
, crm
);
417 return pxa2xx_perf_read(opaque
, op2
, reg
, crm
);
428 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
434 static void pxa2xx_cp14_write(void *opaque
, int op2
, int reg
, int crm
,
439 pxa2xx_clkpwr_write(opaque
, op2
, reg
, crm
, value
);
442 pxa2xx_perf_write(opaque
, op2
, reg
, crm
, value
);
454 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
459 #define MDCNFG 0x00 /* SDRAM Configuration register */
460 #define MDREFR 0x04 /* SDRAM Refresh Control register */
461 #define MSC0 0x08 /* Static Memory Control register 0 */
462 #define MSC1 0x0c /* Static Memory Control register 1 */
463 #define MSC2 0x10 /* Static Memory Control register 2 */
464 #define MECR 0x14 /* Expansion Memory Bus Config register */
465 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
466 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
467 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
468 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
469 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
470 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
471 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
472 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
473 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
474 #define ARB_CNTL 0x48 /* Arbiter Control register */
475 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
476 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
477 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
478 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
479 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
480 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
481 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
483 static uint32_t pxa2xx_mm_read(void *opaque
, target_phys_addr_t addr
)
485 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
488 case MDCNFG
... SA1110
:
490 return s
->mm_regs
[addr
>> 2];
493 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
499 static void pxa2xx_mm_write(void *opaque
, target_phys_addr_t addr
,
502 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
505 case MDCNFG
... SA1110
:
506 if ((addr
& 3) == 0) {
507 s
->mm_regs
[addr
>> 2] = value
;
512 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
517 static CPUReadMemoryFunc
*pxa2xx_mm_readfn
[] = {
523 static CPUWriteMemoryFunc
*pxa2xx_mm_writefn
[] = {
529 static void pxa2xx_mm_save(QEMUFile
*f
, void *opaque
)
531 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
534 for (i
= 0; i
< 0x1a; i
++)
535 qemu_put_be32s(f
, &s
->mm_regs
[i
]);
538 static int pxa2xx_mm_load(QEMUFile
*f
, void *opaque
, int version_id
)
540 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
543 for (i
= 0; i
< 0x1a; i
++)
544 qemu_get_be32s(f
, &s
->mm_regs
[i
]);
549 /* Synchronous Serial Ports */
550 struct pxa2xx_ssp_s
{
563 uint32_t rx_fifo
[16];
567 uint32_t (*readfn
)(void *opaque
);
568 void (*writefn
)(void *opaque
, uint32_t value
);
572 #define SSCR0 0x00 /* SSP Control register 0 */
573 #define SSCR1 0x04 /* SSP Control register 1 */
574 #define SSSR 0x08 /* SSP Status register */
575 #define SSITR 0x0c /* SSP Interrupt Test register */
576 #define SSDR 0x10 /* SSP Data register */
577 #define SSTO 0x28 /* SSP Time-Out register */
578 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
579 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
580 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
581 #define SSTSS 0x38 /* SSP Time Slot Status register */
582 #define SSACD 0x3c /* SSP Audio Clock Divider register */
584 /* Bitfields for above registers */
585 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
586 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
587 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
588 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
589 #define SSCR0_SSE (1 << 7)
590 #define SSCR0_RIM (1 << 22)
591 #define SSCR0_TIM (1 << 23)
592 #define SSCR0_MOD (1 << 31)
593 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
594 #define SSCR1_RIE (1 << 0)
595 #define SSCR1_TIE (1 << 1)
596 #define SSCR1_LBM (1 << 2)
597 #define SSCR1_MWDS (1 << 5)
598 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
599 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
600 #define SSCR1_EFWR (1 << 14)
601 #define SSCR1_PINTE (1 << 18)
602 #define SSCR1_TINTE (1 << 19)
603 #define SSCR1_RSRE (1 << 20)
604 #define SSCR1_TSRE (1 << 21)
605 #define SSCR1_EBCEI (1 << 29)
606 #define SSITR_INT (7 << 5)
607 #define SSSR_TNF (1 << 2)
608 #define SSSR_RNE (1 << 3)
609 #define SSSR_TFS (1 << 5)
610 #define SSSR_RFS (1 << 6)
611 #define SSSR_ROR (1 << 7)
612 #define SSSR_PINT (1 << 18)
613 #define SSSR_TINT (1 << 19)
614 #define SSSR_EOC (1 << 20)
615 #define SSSR_TUR (1 << 21)
616 #define SSSR_BCE (1 << 23)
617 #define SSSR_RW 0x00bc0080
619 static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s
*s
)
623 level
|= s
->ssitr
& SSITR_INT
;
624 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
625 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
626 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
627 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
628 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
629 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
630 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
631 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
632 qemu_set_irq(s
->irq
, !!level
);
635 static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s
*s
)
637 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
638 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
639 s
->sssr
&= ~SSSR_TNF
;
641 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
642 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
645 s
->sssr
&= ~SSSR_RFS
;
646 if (0 <= SSCR1_TFT(s
->sscr
[1]))
649 s
->sssr
&= ~SSSR_TFS
;
653 s
->sssr
&= ~SSSR_RNE
;
657 pxa2xx_ssp_int_update(s
);
660 static uint32_t pxa2xx_ssp_read(void *opaque
, target_phys_addr_t addr
)
662 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
677 return s
->sssr
| s
->ssitr
;
681 if (s
->rx_level
< 1) {
682 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
686 retval
= s
->rx_fifo
[s
->rx_start
++];
688 pxa2xx_ssp_fifo_update(s
);
699 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
705 static void pxa2xx_ssp_write(void *opaque
, target_phys_addr_t addr
,
708 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
712 s
->sscr
[0] = value
& 0xc7ffffff;
713 s
->enable
= value
& SSCR0_SSE
;
714 if (value
& SSCR0_MOD
)
715 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
716 if (s
->enable
&& SSCR0_DSS(value
) < 4)
717 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
719 if (!(value
& SSCR0_SSE
)) {
724 pxa2xx_ssp_fifo_update(s
);
729 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
730 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
731 pxa2xx_ssp_fifo_update(s
);
743 s
->ssitr
= value
& SSITR_INT
;
744 pxa2xx_ssp_int_update(s
);
748 s
->sssr
&= ~(value
& SSSR_RW
);
749 pxa2xx_ssp_int_update(s
);
753 if (SSCR0_UWIRE(s
->sscr
[0])) {
754 if (s
->sscr
[1] & SSCR1_MWDS
)
759 /* Note how 32bits overflow does no harm here */
760 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
762 /* Data goes from here to the Tx FIFO and is shifted out from
763 * there directly to the slave, no need to buffer it.
767 s
->writefn(s
->opaque
, value
);
769 if (s
->rx_level
< 0x10) {
771 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] =
772 s
->readfn(s
->opaque
);
774 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = 0x0;
778 pxa2xx_ssp_fifo_update(s
);
794 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
799 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s
*port
,
800 uint32_t (*readfn
)(void *opaque
),
801 void (*writefn
)(void *opaque
, uint32_t value
), void *opaque
)
804 printf("%s: no such SSP\n", __FUNCTION__
);
808 port
->opaque
= opaque
;
809 port
->readfn
= readfn
;
810 port
->writefn
= writefn
;
813 static CPUReadMemoryFunc
*pxa2xx_ssp_readfn
[] = {
819 static CPUWriteMemoryFunc
*pxa2xx_ssp_writefn
[] = {
825 static void pxa2xx_ssp_save(QEMUFile
*f
, void *opaque
)
827 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
830 qemu_put_be32(f
, s
->enable
);
832 qemu_put_be32s(f
, &s
->sscr
[0]);
833 qemu_put_be32s(f
, &s
->sscr
[1]);
834 qemu_put_be32s(f
, &s
->sspsp
);
835 qemu_put_be32s(f
, &s
->ssto
);
836 qemu_put_be32s(f
, &s
->ssitr
);
837 qemu_put_be32s(f
, &s
->sssr
);
838 qemu_put_8s(f
, &s
->sstsa
);
839 qemu_put_8s(f
, &s
->ssrsa
);
840 qemu_put_8s(f
, &s
->ssacd
);
842 qemu_put_byte(f
, s
->rx_level
);
843 for (i
= 0; i
< s
->rx_level
; i
++)
844 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 0xf]);
847 static int pxa2xx_ssp_load(QEMUFile
*f
, void *opaque
, int version_id
)
849 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
852 s
->enable
= qemu_get_be32(f
);
854 qemu_get_be32s(f
, &s
->sscr
[0]);
855 qemu_get_be32s(f
, &s
->sscr
[1]);
856 qemu_get_be32s(f
, &s
->sspsp
);
857 qemu_get_be32s(f
, &s
->ssto
);
858 qemu_get_be32s(f
, &s
->ssitr
);
859 qemu_get_be32s(f
, &s
->sssr
);
860 qemu_get_8s(f
, &s
->sstsa
);
861 qemu_get_8s(f
, &s
->ssrsa
);
862 qemu_get_8s(f
, &s
->ssacd
);
864 s
->rx_level
= qemu_get_byte(f
);
866 for (i
= 0; i
< s
->rx_level
; i
++)
867 s
->rx_fifo
[i
] = qemu_get_byte(f
);
872 /* Real-Time Clock */
873 #define RCNR 0x00 /* RTC Counter register */
874 #define RTAR 0x04 /* RTC Alarm register */
875 #define RTSR 0x08 /* RTC Status register */
876 #define RTTR 0x0c /* RTC Timer Trim register */
877 #define RDCR 0x10 /* RTC Day Counter register */
878 #define RYCR 0x14 /* RTC Year Counter register */
879 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
880 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
881 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
882 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
883 #define SWCR 0x28 /* RTC Stopwatch Counter register */
884 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
885 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
886 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
887 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
889 static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s
*s
)
891 qemu_set_irq(s
->pic
[PXA2XX_PIC_RTCALARM
], !!(s
->rtsr
& 0x2553));
894 static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s
*s
)
896 int64_t rt
= qemu_get_clock(rt_clock
);
897 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
898 (1000 * ((s
->rttr
& 0xffff) + 1));
899 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
900 (1000 * ((s
->rttr
& 0xffff) + 1));
904 static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s
*s
)
906 int64_t rt
= qemu_get_clock(rt_clock
);
907 if (s
->rtsr
& (1 << 12))
908 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
912 static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s
*s
)
914 int64_t rt
= qemu_get_clock(rt_clock
);
915 if (s
->rtsr
& (1 << 15))
916 s
->last_swcr
+= rt
- s
->last_pi
;
920 static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s
*s
,
923 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
924 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+
925 (((s
->rtar
- s
->last_rcnr
) * 1000 *
926 ((s
->rttr
& 0xffff) + 1)) >> 15));
928 qemu_del_timer(s
->rtc_hz
);
930 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
931 qemu_mod_timer(s
->rtc_rdal1
, s
->last_hz
+
932 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
933 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
935 qemu_del_timer(s
->rtc_rdal1
);
937 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
938 qemu_mod_timer(s
->rtc_rdal2
, s
->last_hz
+
939 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
940 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
942 qemu_del_timer(s
->rtc_rdal2
);
944 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
945 qemu_mod_timer(s
->rtc_swal1
, s
->last_sw
+
946 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
948 qemu_del_timer(s
->rtc_swal1
);
950 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
951 qemu_mod_timer(s
->rtc_swal2
, s
->last_sw
+
952 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
954 qemu_del_timer(s
->rtc_swal2
);
956 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
957 qemu_mod_timer(s
->rtc_pi
, s
->last_pi
+
958 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
960 qemu_del_timer(s
->rtc_pi
);
963 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
965 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
967 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
968 pxa2xx_rtc_int_update(s
);
971 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
973 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
975 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
976 pxa2xx_rtc_int_update(s
);
979 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
981 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
983 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
984 pxa2xx_rtc_int_update(s
);
987 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
989 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
991 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
992 pxa2xx_rtc_int_update(s
);
995 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
997 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
998 s
->rtsr
|= (1 << 10);
999 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1000 pxa2xx_rtc_int_update(s
);
1003 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
1005 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1006 s
->rtsr
|= (1 << 13);
1007 pxa2xx_rtc_piupdate(s
);
1008 s
->last_rtcpicr
= 0;
1009 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1010 pxa2xx_rtc_int_update(s
);
1013 static uint32_t pxa2xx_rtc_read(void *opaque
, target_phys_addr_t addr
)
1015 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1039 return s
->last_rcnr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1040 (1000 * ((s
->rttr
& 0xffff) + 1));
1042 return s
->last_rdcr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1043 (1000 * ((s
->rttr
& 0xffff) + 1));
1045 return s
->last_rycr
;
1047 if (s
->rtsr
& (1 << 12))
1048 return s
->last_swcr
+ (qemu_get_clock(rt_clock
) - s
->last_sw
) / 10;
1050 return s
->last_swcr
;
1052 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1058 static void pxa2xx_rtc_write(void *opaque
, target_phys_addr_t addr
,
1061 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1065 if (!(s
->rttr
& (1 << 31))) {
1066 pxa2xx_rtc_hzupdate(s
);
1068 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1073 if ((s
->rtsr
^ value
) & (1 << 15))
1074 pxa2xx_rtc_piupdate(s
);
1076 if ((s
->rtsr
^ value
) & (1 << 12))
1077 pxa2xx_rtc_swupdate(s
);
1079 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1080 pxa2xx_rtc_alarm_update(s
, value
);
1082 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1083 pxa2xx_rtc_int_update(s
);
1088 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1093 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1098 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1103 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1108 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1112 pxa2xx_rtc_swupdate(s
);
1115 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1120 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1125 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1129 pxa2xx_rtc_hzupdate(s
);
1130 s
->last_rcnr
= value
;
1131 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1135 pxa2xx_rtc_hzupdate(s
);
1136 s
->last_rdcr
= value
;
1137 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1141 s
->last_rycr
= value
;
1145 pxa2xx_rtc_swupdate(s
);
1146 s
->last_swcr
= value
;
1147 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1151 pxa2xx_rtc_piupdate(s
);
1152 s
->last_rtcpicr
= value
& 0xffff;
1153 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1157 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1161 static CPUReadMemoryFunc
*pxa2xx_rtc_readfn
[] = {
1167 static CPUWriteMemoryFunc
*pxa2xx_rtc_writefn
[] = {
1173 static void pxa2xx_rtc_init(struct pxa2xx_state_s
*s
)
1181 qemu_get_timedate(&tm
, 0);
1182 wom
= ((tm
.tm_mday
- 1) / 7) + 1;
1184 s
->last_rcnr
= (uint32_t) mktime(&tm
);
1185 s
->last_rdcr
= (wom
<< 20) | ((tm
.tm_wday
+ 1) << 17) |
1186 (tm
.tm_hour
<< 12) | (tm
.tm_min
<< 6) | tm
.tm_sec
;
1187 s
->last_rycr
= ((tm
.tm_year
+ 1900) << 9) |
1188 ((tm
.tm_mon
+ 1) << 5) | tm
.tm_mday
;
1189 s
->last_swcr
= (tm
.tm_hour
<< 19) |
1190 (tm
.tm_min
<< 13) | (tm
.tm_sec
<< 7);
1191 s
->last_rtcpicr
= 0;
1192 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_get_clock(rt_clock
);
1194 s
->rtc_hz
= qemu_new_timer(rt_clock
, pxa2xx_rtc_hz_tick
, s
);
1195 s
->rtc_rdal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1196 s
->rtc_rdal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1197 s
->rtc_swal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal1_tick
, s
);
1198 s
->rtc_swal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal2_tick
, s
);
1199 s
->rtc_pi
= qemu_new_timer(rt_clock
, pxa2xx_rtc_pi_tick
, s
);
1202 static void pxa2xx_rtc_save(QEMUFile
*f
, void *opaque
)
1204 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1206 pxa2xx_rtc_hzupdate(s
);
1207 pxa2xx_rtc_piupdate(s
);
1208 pxa2xx_rtc_swupdate(s
);
1210 qemu_put_be32s(f
, &s
->rttr
);
1211 qemu_put_be32s(f
, &s
->rtsr
);
1212 qemu_put_be32s(f
, &s
->rtar
);
1213 qemu_put_be32s(f
, &s
->rdar1
);
1214 qemu_put_be32s(f
, &s
->rdar2
);
1215 qemu_put_be32s(f
, &s
->ryar1
);
1216 qemu_put_be32s(f
, &s
->ryar2
);
1217 qemu_put_be32s(f
, &s
->swar1
);
1218 qemu_put_be32s(f
, &s
->swar2
);
1219 qemu_put_be32s(f
, &s
->piar
);
1220 qemu_put_be32s(f
, &s
->last_rcnr
);
1221 qemu_put_be32s(f
, &s
->last_rdcr
);
1222 qemu_put_be32s(f
, &s
->last_rycr
);
1223 qemu_put_be32s(f
, &s
->last_swcr
);
1224 qemu_put_be32s(f
, &s
->last_rtcpicr
);
1225 qemu_put_sbe64s(f
, &s
->last_hz
);
1226 qemu_put_sbe64s(f
, &s
->last_sw
);
1227 qemu_put_sbe64s(f
, &s
->last_pi
);
1230 static int pxa2xx_rtc_load(QEMUFile
*f
, void *opaque
, int version_id
)
1232 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1234 qemu_get_be32s(f
, &s
->rttr
);
1235 qemu_get_be32s(f
, &s
->rtsr
);
1236 qemu_get_be32s(f
, &s
->rtar
);
1237 qemu_get_be32s(f
, &s
->rdar1
);
1238 qemu_get_be32s(f
, &s
->rdar2
);
1239 qemu_get_be32s(f
, &s
->ryar1
);
1240 qemu_get_be32s(f
, &s
->ryar2
);
1241 qemu_get_be32s(f
, &s
->swar1
);
1242 qemu_get_be32s(f
, &s
->swar2
);
1243 qemu_get_be32s(f
, &s
->piar
);
1244 qemu_get_be32s(f
, &s
->last_rcnr
);
1245 qemu_get_be32s(f
, &s
->last_rdcr
);
1246 qemu_get_be32s(f
, &s
->last_rycr
);
1247 qemu_get_be32s(f
, &s
->last_swcr
);
1248 qemu_get_be32s(f
, &s
->last_rtcpicr
);
1249 qemu_get_sbe64s(f
, &s
->last_hz
);
1250 qemu_get_sbe64s(f
, &s
->last_sw
);
1251 qemu_get_sbe64s(f
, &s
->last_pi
);
1253 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1259 struct pxa2xx_i2c_s
{
1270 #define IBMR 0x80 /* I2C Bus Monitor register */
1271 #define IDBR 0x88 /* I2C Data Buffer register */
1272 #define ICR 0x90 /* I2C Control register */
1273 #define ISR 0x98 /* I2C Status register */
1274 #define ISAR 0xa0 /* I2C Slave Address register */
1276 static void pxa2xx_i2c_update(struct pxa2xx_i2c_s
*s
)
1279 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1280 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1281 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1282 level
|= s
->status
& (1 << 9); /* SAD */
1283 qemu_set_irq(s
->irq
, !!level
);
1286 /* These are only stubs now. */
1287 static void pxa2xx_i2c_event(i2c_slave
*i2c
, enum i2c_event event
)
1289 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1292 case I2C_START_SEND
:
1293 s
->status
|= (1 << 9); /* set SAD */
1294 s
->status
&= ~(1 << 0); /* clear RWM */
1296 case I2C_START_RECV
:
1297 s
->status
|= (1 << 9); /* set SAD */
1298 s
->status
|= 1 << 0; /* set RWM */
1301 s
->status
|= (1 << 4); /* set SSD */
1304 s
->status
|= 1 << 1; /* set ACKNAK */
1307 pxa2xx_i2c_update(s
);
1310 static int pxa2xx_i2c_rx(i2c_slave
*i2c
)
1312 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1313 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1316 if (s
->status
& (1 << 0)) { /* RWM */
1317 s
->status
|= 1 << 6; /* set ITE */
1319 pxa2xx_i2c_update(s
);
1324 static int pxa2xx_i2c_tx(i2c_slave
*i2c
, uint8_t data
)
1326 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1327 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1330 if (!(s
->status
& (1 << 0))) { /* RWM */
1331 s
->status
|= 1 << 7; /* set IRF */
1334 pxa2xx_i2c_update(s
);
1339 static uint32_t pxa2xx_i2c_read(void *opaque
, target_phys_addr_t addr
)
1341 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1348 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1350 return s
->slave
.address
;
1354 if (s
->status
& (1 << 2))
1355 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1360 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1366 static void pxa2xx_i2c_write(void *opaque
, target_phys_addr_t addr
,
1369 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1375 s
->control
= value
& 0xfff7;
1376 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1377 /* TODO: slave mode */
1378 if (value
& (1 << 0)) { /* START condition */
1380 s
->status
|= 1 << 0; /* set RWM */
1382 s
->status
&= ~(1 << 0); /* clear RWM */
1383 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1385 if (s
->status
& (1 << 0)) { /* RWM */
1386 s
->data
= i2c_recv(s
->bus
);
1387 if (value
& (1 << 2)) /* ACKNAK */
1391 ack
= !i2c_send(s
->bus
, s
->data
);
1394 if (value
& (1 << 1)) /* STOP condition */
1395 i2c_end_transfer(s
->bus
);
1398 if (value
& (1 << 0)) /* START condition */
1399 s
->status
|= 1 << 6; /* set ITE */
1401 if (s
->status
& (1 << 0)) /* RWM */
1402 s
->status
|= 1 << 7; /* set IRF */
1404 s
->status
|= 1 << 6; /* set ITE */
1405 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1407 s
->status
|= 1 << 6; /* set ITE */
1408 s
->status
|= 1 << 10; /* set BED */
1409 s
->status
|= 1 << 1; /* set ACKNAK */
1412 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1413 if (value
& (1 << 4)) /* MA */
1414 i2c_end_transfer(s
->bus
);
1415 pxa2xx_i2c_update(s
);
1419 s
->status
&= ~(value
& 0x07f0);
1420 pxa2xx_i2c_update(s
);
1424 i2c_set_slave_address(&s
->slave
, value
& 0x7f);
1428 s
->data
= value
& 0xff;
1432 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1436 static CPUReadMemoryFunc
*pxa2xx_i2c_readfn
[] = {
1442 static CPUWriteMemoryFunc
*pxa2xx_i2c_writefn
[] = {
1448 static void pxa2xx_i2c_save(QEMUFile
*f
, void *opaque
)
1450 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1452 qemu_put_be16s(f
, &s
->control
);
1453 qemu_put_be16s(f
, &s
->status
);
1454 qemu_put_8s(f
, &s
->ibmr
);
1455 qemu_put_8s(f
, &s
->data
);
1457 i2c_slave_save(f
, &s
->slave
);
1460 static int pxa2xx_i2c_load(QEMUFile
*f
, void *opaque
, int version_id
)
1462 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1464 if (version_id
!= 1)
1467 qemu_get_be16s(f
, &s
->control
);
1468 qemu_get_be16s(f
, &s
->status
);
1469 qemu_get_8s(f
, &s
->ibmr
);
1470 qemu_get_8s(f
, &s
->data
);
1472 i2c_slave_load(f
, &s
->slave
);
1476 struct pxa2xx_i2c_s
*pxa2xx_i2c_init(target_phys_addr_t base
,
1477 qemu_irq irq
, uint32_t page_size
)
1480 /* FIXME: Should the slave device really be on a separate bus? */
1481 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*)
1482 i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s
));
1485 s
->slave
.event
= pxa2xx_i2c_event
;
1486 s
->slave
.recv
= pxa2xx_i2c_rx
;
1487 s
->slave
.send
= pxa2xx_i2c_tx
;
1488 s
->bus
= i2c_init_bus();
1490 iomemtype
= cpu_register_io_memory(0, pxa2xx_i2c_readfn
,
1491 pxa2xx_i2c_writefn
, s
);
1492 cpu_register_physical_memory(base
& ~page_size
, page_size
+ 1, iomemtype
);
1494 register_savevm("pxa2xx_i2c", base
, 1,
1495 pxa2xx_i2c_save
, pxa2xx_i2c_load
, s
);
1500 i2c_bus
*pxa2xx_i2c_bus(struct pxa2xx_i2c_s
*s
)
1505 /* PXA Inter-IC Sound Controller */
1506 static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s
*i2s
)
1512 i2s
->control
[0] = 0x00;
1513 i2s
->control
[1] = 0x00;
1518 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1519 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1520 #define SACR_DREC(val) (val & (1 << 3))
1521 #define SACR_DPRL(val) (val & (1 << 4))
1523 static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s
*i2s
)
1526 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1527 !SACR_DREC(i2s
->control
[1]);
1528 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1529 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1531 pxa2xx_dma_request(i2s
->dma
, PXA2XX_RX_RQ_I2S
, rfs
);
1532 pxa2xx_dma_request(i2s
->dma
, PXA2XX_TX_RQ_I2S
, tfs
);
1534 i2s
->status
&= 0xe0;
1535 if (i2s
->fifo_len
< 16 || !i2s
->enable
)
1536 i2s
->status
|= 1 << 0; /* TNF */
1538 i2s
->status
|= 1 << 1; /* RNE */
1540 i2s
->status
|= 1 << 2; /* BSY */
1542 i2s
->status
|= 1 << 3; /* TFS */
1544 i2s
->status
|= 1 << 4; /* RFS */
1545 if (!(i2s
->tx_len
&& i2s
->enable
))
1546 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1547 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1549 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1552 #define SACR0 0x00 /* Serial Audio Global Control register */
1553 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1554 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1555 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1556 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1557 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1558 #define SADR 0x80 /* Serial Audio Data register */
1560 static uint32_t pxa2xx_i2s_read(void *opaque
, target_phys_addr_t addr
)
1562 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1566 return s
->control
[0];
1568 return s
->control
[1];
1578 if (s
->rx_len
> 0) {
1580 pxa2xx_i2s_update(s
);
1581 return s
->codec_in(s
->opaque
);
1585 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1591 static void pxa2xx_i2s_write(void *opaque
, target_phys_addr_t addr
,
1594 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1599 if (value
& (1 << 3)) /* RST */
1600 pxa2xx_i2s_reset(s
);
1601 s
->control
[0] = value
& 0xff3d;
1602 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1603 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1604 s
->codec_out(s
->opaque
, *sample
);
1605 s
->status
&= ~(1 << 7); /* I2SOFF */
1607 if (value
& (1 << 4)) /* EFWR */
1608 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1609 s
->enable
= ((value
^ 4) & 5) == 5; /* ENB && !RST*/
1610 pxa2xx_i2s_update(s
);
1613 s
->control
[1] = value
& 0x0039;
1614 if (value
& (1 << 5)) /* ENLBF */
1615 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1616 if (value
& (1 << 4)) /* DPRL */
1618 pxa2xx_i2s_update(s
);
1621 s
->mask
= value
& 0x0078;
1622 pxa2xx_i2s_update(s
);
1625 s
->status
&= ~(value
& (3 << 5));
1626 pxa2xx_i2s_update(s
);
1629 s
->clk
= value
& 0x007f;
1632 if (s
->tx_len
&& s
->enable
) {
1634 pxa2xx_i2s_update(s
);
1635 s
->codec_out(s
->opaque
, value
);
1636 } else if (s
->fifo_len
< 16) {
1637 s
->fifo
[s
->fifo_len
++] = value
;
1638 pxa2xx_i2s_update(s
);
1642 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1646 static CPUReadMemoryFunc
*pxa2xx_i2s_readfn
[] = {
1652 static CPUWriteMemoryFunc
*pxa2xx_i2s_writefn
[] = {
1658 static void pxa2xx_i2s_save(QEMUFile
*f
, void *opaque
)
1660 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1662 qemu_put_be32s(f
, &s
->control
[0]);
1663 qemu_put_be32s(f
, &s
->control
[1]);
1664 qemu_put_be32s(f
, &s
->status
);
1665 qemu_put_be32s(f
, &s
->mask
);
1666 qemu_put_be32s(f
, &s
->clk
);
1668 qemu_put_be32(f
, s
->enable
);
1669 qemu_put_be32(f
, s
->rx_len
);
1670 qemu_put_be32(f
, s
->tx_len
);
1671 qemu_put_be32(f
, s
->fifo_len
);
1674 static int pxa2xx_i2s_load(QEMUFile
*f
, void *opaque
, int version_id
)
1676 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1678 qemu_get_be32s(f
, &s
->control
[0]);
1679 qemu_get_be32s(f
, &s
->control
[1]);
1680 qemu_get_be32s(f
, &s
->status
);
1681 qemu_get_be32s(f
, &s
->mask
);
1682 qemu_get_be32s(f
, &s
->clk
);
1684 s
->enable
= qemu_get_be32(f
);
1685 s
->rx_len
= qemu_get_be32(f
);
1686 s
->tx_len
= qemu_get_be32(f
);
1687 s
->fifo_len
= qemu_get_be32(f
);
1692 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1694 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1697 /* Signal FIFO errors */
1698 if (s
->enable
&& s
->tx_len
)
1699 s
->status
|= 1 << 5; /* TUR */
1700 if (s
->enable
&& s
->rx_len
)
1701 s
->status
|= 1 << 6; /* ROR */
1703 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1704 * handle the cases where it makes a difference. */
1705 s
->tx_len
= tx
- s
->fifo_len
;
1707 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1709 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1710 s
->codec_out(s
->opaque
, *sample
);
1711 pxa2xx_i2s_update(s
);
1714 static struct pxa2xx_i2s_s
*pxa2xx_i2s_init(target_phys_addr_t base
,
1715 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
)
1718 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*)
1719 qemu_mallocz(sizeof(struct pxa2xx_i2s_s
));
1723 s
->data_req
= pxa2xx_i2s_data_req
;
1725 pxa2xx_i2s_reset(s
);
1727 iomemtype
= cpu_register_io_memory(0, pxa2xx_i2s_readfn
,
1728 pxa2xx_i2s_writefn
, s
);
1729 cpu_register_physical_memory(base
, 0x100000, iomemtype
);
1731 register_savevm("pxa2xx_i2s", base
, 0,
1732 pxa2xx_i2s_save
, pxa2xx_i2s_load
, s
);
1737 /* PXA Fast Infra-red Communications Port */
1738 struct pxa2xx_fir_s
{
1740 struct pxa2xx_dma_state_s
*dma
;
1742 CharDriverState
*chr
;
1749 uint8_t rx_fifo
[64];
1752 static void pxa2xx_fir_reset(struct pxa2xx_fir_s
*s
)
1754 s
->control
[0] = 0x00;
1755 s
->control
[1] = 0x00;
1756 s
->control
[2] = 0x00;
1757 s
->status
[0] = 0x00;
1758 s
->status
[1] = 0x00;
1762 static inline void pxa2xx_fir_update(struct pxa2xx_fir_s
*s
)
1764 static const int tresh
[4] = { 8, 16, 32, 0 };
1766 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1767 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1768 s
->status
[0] |= 1 << 4; /* RFS */
1770 s
->status
[0] &= ~(1 << 4); /* RFS */
1771 if (s
->control
[0] & (1 << 3)) /* TXE */
1772 s
->status
[0] |= 1 << 3; /* TFS */
1774 s
->status
[0] &= ~(1 << 3); /* TFS */
1776 s
->status
[1] |= 1 << 2; /* RNE */
1778 s
->status
[1] &= ~(1 << 2); /* RNE */
1779 if (s
->control
[0] & (1 << 4)) /* RXE */
1780 s
->status
[1] |= 1 << 0; /* RSY */
1782 s
->status
[1] &= ~(1 << 0); /* RSY */
1784 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1785 (s
->status
[0] & (1 << 4)); /* RFS */
1786 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1787 (s
->status
[0] & (1 << 3)); /* TFS */
1788 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1789 (s
->status
[0] & (1 << 6)); /* EOC */
1790 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1791 (s
->status
[0] & (1 << 1)); /* TUR */
1792 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1794 pxa2xx_dma_request(s
->dma
, PXA2XX_RX_RQ_ICP
, (s
->status
[0] >> 4) & 1);
1795 pxa2xx_dma_request(s
->dma
, PXA2XX_TX_RQ_ICP
, (s
->status
[0] >> 3) & 1);
1797 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1800 #define ICCR0 0x00 /* FICP Control register 0 */
1801 #define ICCR1 0x04 /* FICP Control register 1 */
1802 #define ICCR2 0x08 /* FICP Control register 2 */
1803 #define ICDR 0x0c /* FICP Data register */
1804 #define ICSR0 0x14 /* FICP Status register 0 */
1805 #define ICSR1 0x18 /* FICP Status register 1 */
1806 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1808 static uint32_t pxa2xx_fir_read(void *opaque
, target_phys_addr_t addr
)
1810 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1815 return s
->control
[0];
1817 return s
->control
[1];
1819 return s
->control
[2];
1821 s
->status
[0] &= ~0x01;
1822 s
->status
[1] &= ~0x72;
1825 ret
= s
->rx_fifo
[s
->rx_start
++];
1827 pxa2xx_fir_update(s
);
1830 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1833 return s
->status
[0];
1835 return s
->status
[1] | (1 << 3); /* TNF */
1839 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1845 static void pxa2xx_fir_write(void *opaque
, target_phys_addr_t addr
,
1848 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1853 s
->control
[0] = value
;
1854 if (!(value
& (1 << 4))) /* RXE */
1855 s
->rx_len
= s
->rx_start
= 0;
1856 if (!(value
& (1 << 3))) /* TXE */
1858 s
->enable
= value
& 1; /* ITR */
1861 pxa2xx_fir_update(s
);
1864 s
->control
[1] = value
;
1867 s
->control
[2] = value
& 0x3f;
1868 pxa2xx_fir_update(s
);
1871 if (s
->control
[2] & (1 << 2)) /* TXP */
1875 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1876 qemu_chr_write(s
->chr
, &ch
, 1);
1879 s
->status
[0] &= ~(value
& 0x66);
1880 pxa2xx_fir_update(s
);
1885 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1889 static CPUReadMemoryFunc
*pxa2xx_fir_readfn
[] = {
1895 static CPUWriteMemoryFunc
*pxa2xx_fir_writefn
[] = {
1901 static int pxa2xx_fir_is_empty(void *opaque
)
1903 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1904 return (s
->rx_len
< 64);
1907 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1909 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1910 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1914 s
->status
[1] |= 1 << 4; /* EOF */
1915 if (s
->rx_len
>= 64) {
1916 s
->status
[1] |= 1 << 6; /* ROR */
1920 if (s
->control
[2] & (1 << 3)) /* RXP */
1921 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1923 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1926 pxa2xx_fir_update(s
);
1929 static void pxa2xx_fir_event(void *opaque
, int event
)
1933 static void pxa2xx_fir_save(QEMUFile
*f
, void *opaque
)
1935 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1938 qemu_put_be32(f
, s
->enable
);
1940 qemu_put_8s(f
, &s
->control
[0]);
1941 qemu_put_8s(f
, &s
->control
[1]);
1942 qemu_put_8s(f
, &s
->control
[2]);
1943 qemu_put_8s(f
, &s
->status
[0]);
1944 qemu_put_8s(f
, &s
->status
[1]);
1946 qemu_put_byte(f
, s
->rx_len
);
1947 for (i
= 0; i
< s
->rx_len
; i
++)
1948 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 63]);
1951 static int pxa2xx_fir_load(QEMUFile
*f
, void *opaque
, int version_id
)
1953 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1956 s
->enable
= qemu_get_be32(f
);
1958 qemu_get_8s(f
, &s
->control
[0]);
1959 qemu_get_8s(f
, &s
->control
[1]);
1960 qemu_get_8s(f
, &s
->control
[2]);
1961 qemu_get_8s(f
, &s
->status
[0]);
1962 qemu_get_8s(f
, &s
->status
[1]);
1964 s
->rx_len
= qemu_get_byte(f
);
1966 for (i
= 0; i
< s
->rx_len
; i
++)
1967 s
->rx_fifo
[i
] = qemu_get_byte(f
);
1972 static struct pxa2xx_fir_s
*pxa2xx_fir_init(target_phys_addr_t base
,
1973 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
,
1974 CharDriverState
*chr
)
1977 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*)
1978 qemu_mallocz(sizeof(struct pxa2xx_fir_s
));
1984 pxa2xx_fir_reset(s
);
1986 iomemtype
= cpu_register_io_memory(0, pxa2xx_fir_readfn
,
1987 pxa2xx_fir_writefn
, s
);
1988 cpu_register_physical_memory(base
, 0x1000, iomemtype
);
1991 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
1992 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
1994 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save
, pxa2xx_fir_load
, s
);
1999 static void pxa2xx_reset(void *opaque
, int line
, int level
)
2001 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
2003 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2005 /* TODO: reset peripherals */
2009 /* Initialise a PXA270 integrated chip (ARM based core). */
2010 struct pxa2xx_state_s
*pxa270_init(unsigned int sdram_size
,
2011 DisplayState
*ds
, const char *revision
)
2013 struct pxa2xx_state_s
*s
;
2014 struct pxa2xx_ssp_s
*ssp
;
2017 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
2019 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2020 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2024 revision
= "pxa270";
2026 s
->env
= cpu_init(revision
);
2028 fprintf(stderr
, "Unable to find CPU definition\n");
2031 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2033 /* SDRAM & Internal Memory Storage */
2034 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
,
2035 sdram_size
, qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2036 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
,
2037 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM
);
2039 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2041 s
->dma
= pxa27x_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2043 pxa27x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
],
2044 s
->pic
[PXA27X_PIC_OST_4_11
]);
2046 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 121);
2048 index
= drive_get_index(IF_SD
, 0, 0);
2050 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2053 s
->mmc
= pxa2xx_mmci_init(0x41100000, drives_table
[index
].bdrv
,
2054 s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2056 for (i
= 0; pxa270_serial
[i
].io_base
; i
++)
2058 serial_mm_init(pxa270_serial
[i
].io_base
, 2,
2059 s
->pic
[pxa270_serial
[i
].irqn
], 14857000/16,
2064 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2065 s
->dma
, serial_hds
[i
]);
2068 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
2070 s
->cm_base
= 0x41300000;
2071 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2072 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2073 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
2074 pxa2xx_cm_writefn
, s
);
2075 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2076 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2078 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2080 s
->mm_base
= 0x48000000;
2081 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2082 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2083 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2084 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
2085 pxa2xx_mm_writefn
, s
);
2086 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2087 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2089 s
->pm_base
= 0x40f00000;
2090 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
2091 pxa2xx_pm_writefn
, s
);
2092 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2093 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2095 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2096 s
->ssp
= (struct pxa2xx_ssp_s
**)
2097 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
2098 ssp
= (struct pxa2xx_ssp_s
*)
2099 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
2100 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2101 target_phys_addr_t ssp_base
;
2102 s
->ssp
[i
] = &ssp
[i
];
2103 ssp_base
= pxa27x_ssp
[i
].io_base
;
2104 ssp
[i
].irq
= s
->pic
[pxa27x_ssp
[i
].irqn
];
2106 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
2107 pxa2xx_ssp_writefn
, &ssp
[i
]);
2108 cpu_register_physical_memory(ssp_base
, 0x1000, iomemtype
);
2109 register_savevm("pxa2xx_ssp", i
, 0,
2110 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
2114 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2117 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2118 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2120 s
->rtc_base
= 0x40900000;
2121 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
2122 pxa2xx_rtc_writefn
, s
);
2123 cpu_register_physical_memory(s
->rtc_base
, 0x1000, iomemtype
);
2125 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2127 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 0xffff);
2128 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0xff);
2130 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2132 s
->kp
= pxa27x_keypad_init(0x41500000, s
->pic
[PXA2XX_PIC_KEYPAD
]);
2134 /* GPIO1 resets the processor */
2135 /* The handler can be overridden by board-specific code */
2136 pxa2xx_gpio_out_set(s
->gpio
, 1, s
->reset
);
2140 /* Initialise a PXA255 integrated chip (ARM based core). */
2141 struct pxa2xx_state_s
*pxa255_init(unsigned int sdram_size
,
2144 struct pxa2xx_state_s
*s
;
2145 struct pxa2xx_ssp_s
*ssp
;
2149 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
2151 s
->env
= cpu_init("pxa255");
2153 fprintf(stderr
, "Unable to find CPU definition\n");
2156 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2158 /* SDRAM & Internal Memory Storage */
2159 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
, sdram_size
,
2160 qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2161 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
, PXA2XX_INTERNAL_SIZE
,
2162 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE
) | IO_MEM_RAM
);
2164 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2166 s
->dma
= pxa255_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2168 pxa25x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
]);
2170 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 85);
2172 index
= drive_get_index(IF_SD
, 0, 0);
2174 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2177 s
->mmc
= pxa2xx_mmci_init(0x41100000, drives_table
[index
].bdrv
,
2178 s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2180 for (i
= 0; pxa255_serial
[i
].io_base
; i
++)
2182 serial_mm_init(pxa255_serial
[i
].io_base
, 2,
2183 s
->pic
[pxa255_serial
[i
].irqn
], 14745600/16,
2188 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2189 s
->dma
, serial_hds
[i
]);
2192 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
2194 s
->cm_base
= 0x41300000;
2195 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2196 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2197 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
2198 pxa2xx_cm_writefn
, s
);
2199 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2200 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2202 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2204 s
->mm_base
= 0x48000000;
2205 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2206 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2207 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2208 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
2209 pxa2xx_mm_writefn
, s
);
2210 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2211 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2213 s
->pm_base
= 0x40f00000;
2214 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
2215 pxa2xx_pm_writefn
, s
);
2216 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2217 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2219 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2220 s
->ssp
= (struct pxa2xx_ssp_s
**)
2221 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
2222 ssp
= (struct pxa2xx_ssp_s
*)
2223 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
2224 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2225 target_phys_addr_t ssp_base
;
2226 s
->ssp
[i
] = &ssp
[i
];
2227 ssp_base
= pxa255_ssp
[i
].io_base
;
2228 ssp
[i
].irq
= s
->pic
[pxa255_ssp
[i
].irqn
];
2230 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
2231 pxa2xx_ssp_writefn
, &ssp
[i
]);
2232 cpu_register_physical_memory(ssp_base
, 0x1000, iomemtype
);
2233 register_savevm("pxa2xx_ssp", i
, 0,
2234 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
2238 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2241 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2242 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2244 s
->rtc_base
= 0x40900000;
2245 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
2246 pxa2xx_rtc_writefn
, s
);
2247 cpu_register_physical_memory(s
->rtc_base
, 0x1000, iomemtype
);
2249 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2251 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 0xffff);
2252 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0xff);
2254 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2256 /* GPIO1 resets the processor */
2257 /* The handler can be overridden by board-specific code */
2258 pxa2xx_gpio_out_set(s
->gpio
, 1, s
->reset
);