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Fix configuration 2 register (esp_2_cfg2.diff):
[qemu/mini2440/sniper_sniper_test.git] / target-ppc / translate.c
blob95cb4826624f75903845e8eaccf66853c7c423f8
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44 //#define OPTIMIZE_FPRF_UPDATE
45
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 #if !defined(TARGET_PPC64)
53 + 10*4 + 22*5 /* SPE GPRh */
54 #endif
55 + 10*4 + 22*5 /* FPR */
56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
58 static TCGv cpu_gpr[32];
59 #if !defined(TARGET_PPC64)
60 static TCGv cpu_gprh[32];
61 #endif
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 static TCGv cpu_xer;
69 static TCGv_i32 cpu_fpscr;
70 static TCGv_i32 cpu_access_type;
71
72 /* dyngen register indexes */
73 static TCGv cpu_T[3];
74
75 #include "gen-icount.h"
76
77 void ppc_translate_init(void)
78 {
79 int i;
80 char* p;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87 #if TARGET_LONG_BITS > HOST_LONG_BITS
88 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
89 cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");
90 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
91 #else
92 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
93 cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");
94 #ifdef HOST_I386
95 /* XXX: This is a temporary workaround for i386.
96 * On i386 qemu_st32 runs out of registers.
97 * The proper fix is to remove cpu_T.
98 */
99 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
100 #else
101 cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");
102 #endif
103 #endif
104
105 p = cpu_reg_names;
106
107 for (i = 0; i < 8; i++) {
108 sprintf(p, "crf%d", i);
109 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUState, crf[i]), p);
111 p += 5;
112 }
113
114 for (i = 0; i < 32; i++) {
115 sprintf(p, "r%d", i);
116 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
117 offsetof(CPUState, gpr[i]), p);
118 p += (i < 10) ? 3 : 4;
119 #if !defined(TARGET_PPC64)
120 sprintf(p, "r%dH", i);
121 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, gprh[i]), p);
123 p += (i < 10) ? 4 : 5;
124 #endif
125
126 sprintf(p, "fp%d", i);
127 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, fpr[i]), p);
129 p += (i < 10) ? 4 : 5;
130
131 sprintf(p, "avr%dH", i);
132 #ifdef WORDS_BIGENDIAN
133 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
134 offsetof(CPUState, avr[i].u64[0]), p);
135 #else
136 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
137 offsetof(CPUState, avr[i].u64[1]), p);
138 #endif
139 p += (i < 10) ? 6 : 7;
140
141 sprintf(p, "avr%dL", i);
142 #ifdef WORDS_BIGENDIAN
143 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUState, avr[i].u64[1]), p);
145 #else
146 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
147 offsetof(CPUState, avr[i].u64[0]), p);
148 #endif
149 p += (i < 10) ? 6 : 7;
150 }
151
152 cpu_nip = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUState, nip), "nip");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUState, lr), "lr");
160
161 cpu_xer = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUState, xer), "xer");
163
164 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165 offsetof(CPUState, fpscr), "fpscr");
166
167 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168 offsetof(CPUState, access_type), "access_type");
169
170 /* register helpers */
171 #define GEN_HELPER 2
172 #include "helper.h"
173
174 done_init = 1;
175 }
176
177 #if defined(OPTIMIZE_FPRF_UPDATE)
178 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
179 static uint16_t **gen_fprf_ptr;
180 #endif
181
182 /* internal defines */
183 typedef struct DisasContext {
184 struct TranslationBlock *tb;
185 target_ulong nip;
186 uint32_t opcode;
187 uint32_t exception;
188 /* Routine used to access memory */
189 int mem_idx;
190 /* Translation flags */
191 #if !defined(CONFIG_USER_ONLY)
192 int supervisor;
193 #endif
194 #if defined(TARGET_PPC64)
195 int sf_mode;
196 #endif
197 int fpu_enabled;
198 int altivec_enabled;
199 int spe_enabled;
200 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
201 int singlestep_enabled;
202 int dcache_line_size;
203 } DisasContext;
204
205 struct opc_handler_t {
206 /* invalid bits */
207 uint32_t inval;
208 /* instruction type */
209 uint64_t type;
210 /* handler */
211 void (*handler)(DisasContext *ctx);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 const char *oname;
214 #endif
215 #if defined(DO_PPC_STATISTICS)
216 uint64_t count;
217 #endif
218 };
219
220 static always_inline void gen_reset_fpstatus (void)
221 {
222 #ifdef CONFIG_SOFTFLOAT
223 gen_op_reset_fpstatus();
224 #endif
225 }
226
227 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
228 {
229 TCGv_i32 t0 = tcg_temp_new_i32();
230
231 if (set_fprf != 0) {
232 /* This case might be optimized later */
233 #if defined(OPTIMIZE_FPRF_UPDATE)
234 *gen_fprf_ptr++ = gen_opc_ptr;
235 #endif
236 tcg_gen_movi_i32(t0, 1);
237 gen_helper_compute_fprf(t0, arg, t0);
238 if (unlikely(set_rc)) {
239 tcg_gen_mov_i32(cpu_crf[1], t0);
240 }
241 gen_helper_float_check_status();
242 } else if (unlikely(set_rc)) {
243 /* We always need to compute fpcc */
244 tcg_gen_movi_i32(t0, 0);
245 gen_helper_compute_fprf(t0, arg, t0);
246 tcg_gen_mov_i32(cpu_crf[1], t0);
247 if (set_fprf)
248 gen_helper_float_check_status();
249 }
250
251 tcg_temp_free_i32(t0);
252 }
253
254 static always_inline void gen_optimize_fprf (void)
255 {
256 #if defined(OPTIMIZE_FPRF_UPDATE)
257 uint16_t **ptr;
258
259 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
260 *ptr = INDEX_op_nop1;
261 gen_fprf_ptr = gen_fprf_buf;
262 #endif
263 }
264
265 static always_inline void gen_set_access_type(int access_type)
266 {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 }
269
270 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
271 {
272 #if defined(TARGET_PPC64)
273 if (ctx->sf_mode)
274 tcg_gen_movi_tl(cpu_nip, nip);
275 else
276 #endif
277 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
278 }
279
280 #define GEN_EXCP(ctx, excp, error) \
281 do { \
282 TCGv_i32 t0 = tcg_const_i32(excp); \
283 TCGv_i32 t1 = tcg_const_i32(error); \
284 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
285 gen_update_nip(ctx, (ctx)->nip); \
286 } \
287 gen_helper_raise_exception_err(t0, t1); \
288 tcg_temp_free_i32(t0); \
289 tcg_temp_free_i32(t1); \
290 ctx->exception = (excp); \
291 } while (0)
292
293 #define GEN_EXCP_INVAL(ctx) \
294 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
295 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
296
297 #define GEN_EXCP_PRIVOPC(ctx) \
298 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
299 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
300
301 #define GEN_EXCP_PRIVREG(ctx) \
302 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
303 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
304
305 #define GEN_EXCP_NO_FP(ctx) \
306 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
307
308 #define GEN_EXCP_NO_AP(ctx) \
309 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
310
311 #define GEN_EXCP_NO_VR(ctx) \
312 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
313
314 /* Stop translation */
315 static always_inline void GEN_STOP (DisasContext *ctx)
316 {
317 gen_update_nip(ctx, ctx->nip);
318 ctx->exception = POWERPC_EXCP_STOP;
319 }
320
321 /* No need to update nip here, as execution flow will change */
322 static always_inline void GEN_SYNC (DisasContext *ctx)
323 {
324 ctx->exception = POWERPC_EXCP_SYNC;
325 }
326
327 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
328 static void gen_##name (DisasContext *ctx); \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
330 static void gen_##name (DisasContext *ctx)
331
332 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
333 static void gen_##name (DisasContext *ctx); \
334 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
335 static void gen_##name (DisasContext *ctx)
336
337 typedef struct opcode_t {
338 unsigned char opc1, opc2, opc3;
339 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
340 unsigned char pad[5];
341 #else
342 unsigned char pad[1];
343 #endif
344 opc_handler_t handler;
345 const char *oname;
346 } opcode_t;
347
348 /*****************************************************************************/
349 /*** Instruction decoding ***/
350 #define EXTRACT_HELPER(name, shift, nb) \
351 static always_inline uint32_t name (uint32_t opcode) \
352 { \
353 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
354 }
355
356 #define EXTRACT_SHELPER(name, shift, nb) \
357 static always_inline int32_t name (uint32_t opcode) \
358 { \
359 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
360 }
361
362 /* Opcode part 1 */
363 EXTRACT_HELPER(opc1, 26, 6);
364 /* Opcode part 2 */
365 EXTRACT_HELPER(opc2, 1, 5);
366 /* Opcode part 3 */
367 EXTRACT_HELPER(opc3, 6, 5);
368 /* Update Cr0 flags */
369 EXTRACT_HELPER(Rc, 0, 1);
370 /* Destination */
371 EXTRACT_HELPER(rD, 21, 5);
372 /* Source */
373 EXTRACT_HELPER(rS, 21, 5);
374 /* First operand */
375 EXTRACT_HELPER(rA, 16, 5);
376 /* Second operand */
377 EXTRACT_HELPER(rB, 11, 5);
378 /* Third operand */
379 EXTRACT_HELPER(rC, 6, 5);
380 /*** Get CRn ***/
381 EXTRACT_HELPER(crfD, 23, 3);
382 EXTRACT_HELPER(crfS, 18, 3);
383 EXTRACT_HELPER(crbD, 21, 5);
384 EXTRACT_HELPER(crbA, 16, 5);
385 EXTRACT_HELPER(crbB, 11, 5);
386 /* SPR / TBL */
387 EXTRACT_HELPER(_SPR, 11, 10);
388 static always_inline uint32_t SPR (uint32_t opcode)
389 {
390 uint32_t sprn = _SPR(opcode);
391
392 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
393 }
394 /*** Get constants ***/
395 EXTRACT_HELPER(IMM, 12, 8);
396 /* 16 bits signed immediate value */
397 EXTRACT_SHELPER(SIMM, 0, 16);
398 /* 16 bits unsigned immediate value */
399 EXTRACT_HELPER(UIMM, 0, 16);
400 /* Bit count */
401 EXTRACT_HELPER(NB, 11, 5);
402 /* Shift count */
403 EXTRACT_HELPER(SH, 11, 5);
404 /* Mask start */
405 EXTRACT_HELPER(MB, 6, 5);
406 /* Mask end */
407 EXTRACT_HELPER(ME, 1, 5);
408 /* Trap operand */
409 EXTRACT_HELPER(TO, 21, 5);
410
411 EXTRACT_HELPER(CRM, 12, 8);
412 EXTRACT_HELPER(FM, 17, 8);
413 EXTRACT_HELPER(SR, 16, 4);
414 EXTRACT_HELPER(FPIMM, 12, 4);
415
416 /*** Jump target decoding ***/
417 /* Displacement */
418 EXTRACT_SHELPER(d, 0, 16);
419 /* Immediate address */
420 static always_inline target_ulong LI (uint32_t opcode)
421 {
422 return (opcode >> 0) & 0x03FFFFFC;
423 }
424
425 static always_inline uint32_t BD (uint32_t opcode)
426 {
427 return (opcode >> 0) & 0xFFFC;
428 }
429
430 EXTRACT_HELPER(BO, 21, 5);
431 EXTRACT_HELPER(BI, 16, 5);
432 /* Absolute/relative address */
433 EXTRACT_HELPER(AA, 1, 1);
434 /* Link */
435 EXTRACT_HELPER(LK, 0, 1);
436
437 /* Create a mask between <start> and <end> bits */
438 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
439 {
440 target_ulong ret;
441
442 #if defined(TARGET_PPC64)
443 if (likely(start == 0)) {
444 ret = UINT64_MAX << (63 - end);
445 } else if (likely(end == 63)) {
446 ret = UINT64_MAX >> start;
447 }
448 #else
449 if (likely(start == 0)) {
450 ret = UINT32_MAX << (31 - end);
451 } else if (likely(end == 31)) {
452 ret = UINT32_MAX >> start;
453 }
454 #endif
455 else {
456 ret = (((target_ulong)(-1ULL)) >> (start)) ^
457 (((target_ulong)(-1ULL) >> (end)) >> 1);
458 if (unlikely(start > end))
459 return ~ret;
460 }
461
462 return ret;
463 }
464
465 /*****************************************************************************/
466 /* PowerPC Instructions types definitions */
467 enum {
468 PPC_NONE = 0x0000000000000000ULL,
469 /* PowerPC base instructions set */
470 PPC_INSNS_BASE = 0x0000000000000001ULL,
471 /* integer operations instructions */
472 #define PPC_INTEGER PPC_INSNS_BASE
473 /* flow control instructions */
474 #define PPC_FLOW PPC_INSNS_BASE
475 /* virtual memory instructions */
476 #define PPC_MEM PPC_INSNS_BASE
477 /* ld/st with reservation instructions */
478 #define PPC_RES PPC_INSNS_BASE
479 /* spr/msr access instructions */
480 #define PPC_MISC PPC_INSNS_BASE
481 /* Deprecated instruction sets */
482 /* Original POWER instruction set */
483 PPC_POWER = 0x0000000000000002ULL,
484 /* POWER2 instruction set extension */
485 PPC_POWER2 = 0x0000000000000004ULL,
486 /* Power RTC support */
487 PPC_POWER_RTC = 0x0000000000000008ULL,
488 /* Power-to-PowerPC bridge (601) */
489 PPC_POWER_BR = 0x0000000000000010ULL,
490 /* 64 bits PowerPC instruction set */
491 PPC_64B = 0x0000000000000020ULL,
492 /* New 64 bits extensions (PowerPC 2.0x) */
493 PPC_64BX = 0x0000000000000040ULL,
494 /* 64 bits hypervisor extensions */
495 PPC_64H = 0x0000000000000080ULL,
496 /* New wait instruction (PowerPC 2.0x) */
497 PPC_WAIT = 0x0000000000000100ULL,
498 /* Time base mftb instruction */
499 PPC_MFTB = 0x0000000000000200ULL,
500
501 /* Fixed-point unit extensions */
502 /* PowerPC 602 specific */
503 PPC_602_SPEC = 0x0000000000000400ULL,
504 /* isel instruction */
505 PPC_ISEL = 0x0000000000000800ULL,
506 /* popcntb instruction */
507 PPC_POPCNTB = 0x0000000000001000ULL,
508 /* string load / store */
509 PPC_STRING = 0x0000000000002000ULL,
510
511 /* Floating-point unit extensions */
512 /* Optional floating point instructions */
513 PPC_FLOAT = 0x0000000000010000ULL,
514 /* New floating-point extensions (PowerPC 2.0x) */
515 PPC_FLOAT_EXT = 0x0000000000020000ULL,
516 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
517 PPC_FLOAT_FRES = 0x0000000000080000ULL,
518 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
519 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
520 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
521 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
522
523 /* Vector/SIMD extensions */
524 /* Altivec support */
525 PPC_ALTIVEC = 0x0000000001000000ULL,
526 /* PowerPC 2.03 SPE extension */
527 PPC_SPE = 0x0000000002000000ULL,
528 /* PowerPC 2.03 SPE floating-point extension */
529 PPC_SPEFPU = 0x0000000004000000ULL,
530
531 /* Optional memory control instructions */
532 PPC_MEM_TLBIA = 0x0000000010000000ULL,
533 PPC_MEM_TLBIE = 0x0000000020000000ULL,
534 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
535 /* sync instruction */
536 PPC_MEM_SYNC = 0x0000000080000000ULL,
537 /* eieio instruction */
538 PPC_MEM_EIEIO = 0x0000000100000000ULL,
539
540 /* Cache control instructions */
541 PPC_CACHE = 0x0000000200000000ULL,
542 /* icbi instruction */
543 PPC_CACHE_ICBI = 0x0000000400000000ULL,
544 /* dcbz instruction with fixed cache line size */
545 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
546 /* dcbz instruction with tunable cache line size */
547 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
548 /* dcba instruction */
549 PPC_CACHE_DCBA = 0x0000002000000000ULL,
550 /* Freescale cache locking instructions */
551 PPC_CACHE_LOCK = 0x0000004000000000ULL,
552
553 /* MMU related extensions */
554 /* external control instructions */
555 PPC_EXTERN = 0x0000010000000000ULL,
556 /* segment register access instructions */
557 PPC_SEGMENT = 0x0000020000000000ULL,
558 /* PowerPC 6xx TLB management instructions */
559 PPC_6xx_TLB = 0x0000040000000000ULL,
560 /* PowerPC 74xx TLB management instructions */
561 PPC_74xx_TLB = 0x0000080000000000ULL,
562 /* PowerPC 40x TLB management instructions */
563 PPC_40x_TLB = 0x0000100000000000ULL,
564 /* segment register access instructions for PowerPC 64 "bridge" */
565 PPC_SEGMENT_64B = 0x0000200000000000ULL,
566 /* SLB management */
567 PPC_SLBI = 0x0000400000000000ULL,
568
569 /* Embedded PowerPC dedicated instructions */
570 PPC_WRTEE = 0x0001000000000000ULL,
571 /* PowerPC 40x exception model */
572 PPC_40x_EXCP = 0x0002000000000000ULL,
573 /* PowerPC 405 Mac instructions */
574 PPC_405_MAC = 0x0004000000000000ULL,
575 /* PowerPC 440 specific instructions */
576 PPC_440_SPEC = 0x0008000000000000ULL,
577 /* BookE (embedded) PowerPC specification */
578 PPC_BOOKE = 0x0010000000000000ULL,
579 /* mfapidi instruction */
580 PPC_MFAPIDI = 0x0020000000000000ULL,
581 /* tlbiva instruction */
582 PPC_TLBIVA = 0x0040000000000000ULL,
583 /* tlbivax instruction */
584 PPC_TLBIVAX = 0x0080000000000000ULL,
585 /* PowerPC 4xx dedicated instructions */
586 PPC_4xx_COMMON = 0x0100000000000000ULL,
587 /* PowerPC 40x ibct instructions */
588 PPC_40x_ICBT = 0x0200000000000000ULL,
589 /* rfmci is not implemented in all BookE PowerPC */
590 PPC_RFMCI = 0x0400000000000000ULL,
591 /* rfdi instruction */
592 PPC_RFDI = 0x0800000000000000ULL,
593 /* DCR accesses */
594 PPC_DCR = 0x1000000000000000ULL,
595 /* DCR extended accesse */
596 PPC_DCRX = 0x2000000000000000ULL,
597 /* user-mode DCR access, implemented in PowerPC 460 */
598 PPC_DCRUX = 0x4000000000000000ULL,
599 };
600
601 /*****************************************************************************/
602 /* PowerPC instructions table */
603 #if HOST_LONG_BITS == 64
604 #define OPC_ALIGN 8
605 #else
606 #define OPC_ALIGN 4
607 #endif
608 #if defined(__APPLE__)
609 #define OPCODES_SECTION \
610 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
611 #else
612 #define OPCODES_SECTION \
613 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
614 #endif
615
616 #if defined(DO_PPC_STATISTICS)
617 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
618 OPCODES_SECTION opcode_t opc_##name = { \
619 .opc1 = op1, \
620 .opc2 = op2, \
621 .opc3 = op3, \
622 .pad = { 0, }, \
623 .handler = { \
624 .inval = invl, \
625 .type = _typ, \
626 .handler = &gen_##name, \
627 .oname = stringify(name), \
628 }, \
629 .oname = stringify(name), \
630 }
631 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
632 OPCODES_SECTION opcode_t opc_##name = { \
633 .opc1 = op1, \
634 .opc2 = op2, \
635 .opc3 = op3, \
636 .pad = { 0, }, \
637 .handler = { \
638 .inval = invl, \
639 .type = _typ, \
640 .handler = &gen_##name, \
641 .oname = onam, \
642 }, \
643 .oname = onam, \
644 }
645 #else
646 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
647 OPCODES_SECTION opcode_t opc_##name = { \
648 .opc1 = op1, \
649 .opc2 = op2, \
650 .opc3 = op3, \
651 .pad = { 0, }, \
652 .handler = { \
653 .inval = invl, \
654 .type = _typ, \
655 .handler = &gen_##name, \
656 }, \
657 .oname = stringify(name), \
658 }
659 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
660 OPCODES_SECTION opcode_t opc_##name = { \
661 .opc1 = op1, \
662 .opc2 = op2, \
663 .opc3 = op3, \
664 .pad = { 0, }, \
665 .handler = { \
666 .inval = invl, \
667 .type = _typ, \
668 .handler = &gen_##name, \
669 }, \
670 .oname = onam, \
671 }
672 #endif
673
674 #define GEN_OPCODE_MARK(name) \
675 OPCODES_SECTION opcode_t opc_##name = { \
676 .opc1 = 0xFF, \
677 .opc2 = 0xFF, \
678 .opc3 = 0xFF, \
679 .pad = { 0, }, \
680 .handler = { \
681 .inval = 0x00000000, \
682 .type = 0x00, \
683 .handler = NULL, \
684 }, \
685 .oname = stringify(name), \
686 }
687
688 /* Start opcode list */
689 GEN_OPCODE_MARK(start);
690
691 /* Invalid instruction */
692 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
693 {
694 GEN_EXCP_INVAL(ctx);
695 }
696
697 static opc_handler_t invalid_handler = {
698 .inval = 0xFFFFFFFF,
699 .type = PPC_NONE,
700 .handler = gen_invalid,
701 };
702
703 /*** Integer comparison ***/
704
705 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
706 {
707 int l1, l2, l3;
708
709 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
710 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
711 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
712
713 l1 = gen_new_label();
714 l2 = gen_new_label();
715 l3 = gen_new_label();
716 if (s) {
717 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
718 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
719 } else {
720 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
722 }
723 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
724 tcg_gen_br(l3);
725 gen_set_label(l1);
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
727 tcg_gen_br(l3);
728 gen_set_label(l2);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
730 gen_set_label(l3);
731 }
732
733 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
734 {
735 TCGv t0 = tcg_const_local_tl(arg1);
736 gen_op_cmp(arg0, t0, s, crf);
737 tcg_temp_free(t0);
738 }
739
740 #if defined(TARGET_PPC64)
741 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
742 {
743 TCGv t0, t1;
744 t0 = tcg_temp_local_new();
745 t1 = tcg_temp_local_new();
746 if (s) {
747 tcg_gen_ext32s_tl(t0, arg0);
748 tcg_gen_ext32s_tl(t1, arg1);
749 } else {
750 tcg_gen_ext32u_tl(t0, arg0);
751 tcg_gen_ext32u_tl(t1, arg1);
752 }
753 gen_op_cmp(t0, t1, s, crf);
754 tcg_temp_free(t1);
755 tcg_temp_free(t0);
756 }
757
758 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
759 {
760 TCGv t0 = tcg_const_local_tl(arg1);
761 gen_op_cmp32(arg0, t0, s, crf);
762 tcg_temp_free(t0);
763 }
764 #endif
765
766 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
767 {
768 #if defined(TARGET_PPC64)
769 if (!(ctx->sf_mode))
770 gen_op_cmpi32(reg, 0, 1, 0);
771 else
772 #endif
773 gen_op_cmpi(reg, 0, 1, 0);
774 }
775
776 /* cmp */
777 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
778 {
779 #if defined(TARGET_PPC64)
780 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
781 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
782 1, crfD(ctx->opcode));
783 else
784 #endif
785 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 }
788
789 /* cmpi */
790 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
791 {
792 #if defined(TARGET_PPC64)
793 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
794 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
795 1, crfD(ctx->opcode));
796 else
797 #endif
798 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 }
801
802 /* cmpl */
803 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
804 {
805 #if defined(TARGET_PPC64)
806 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
807 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
808 0, crfD(ctx->opcode));
809 else
810 #endif
811 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 }
814
815 /* cmpli */
816 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
817 {
818 #if defined(TARGET_PPC64)
819 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
820 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
821 0, crfD(ctx->opcode));
822 else
823 #endif
824 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 }
827
828 /* isel (PowerPC 2.03 specification) */
829 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
830 {
831 int l1, l2;
832 uint32_t bi = rC(ctx->opcode);
833 uint32_t mask;
834 TCGv_i32 t0;
835
836 l1 = gen_new_label();
837 l2 = gen_new_label();
838
839 mask = 1 << (3 - (bi & 0x03));
840 t0 = tcg_temp_new_i32();
841 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
842 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
843 if (rA(ctx->opcode) == 0)
844 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
845 else
846 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
847 tcg_gen_br(l2);
848 gen_set_label(l1);
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
850 gen_set_label(l2);
851 tcg_temp_free_i32(t0);
852 }
853
854 /*** Integer arithmetic ***/
855
856 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
857 {
858 int l1;
859 TCGv t0;
860
861 l1 = gen_new_label();
862 /* Start with XER OV disabled, the most likely case */
863 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
864 t0 = tcg_temp_local_new();
865 tcg_gen_xor_tl(t0, arg0, arg1);
866 #if defined(TARGET_PPC64)
867 if (!ctx->sf_mode)
868 tcg_gen_ext32s_tl(t0, t0);
869 #endif
870 if (sub)
871 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
872 else
873 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
874 tcg_gen_xor_tl(t0, arg1, arg2);
875 #if defined(TARGET_PPC64)
876 if (!ctx->sf_mode)
877 tcg_gen_ext32s_tl(t0, t0);
878 #endif
879 if (sub)
880 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
881 else
882 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
883 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
884 gen_set_label(l1);
885 tcg_temp_free(t0);
886 }
887
888 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
889 {
890 int l1 = gen_new_label();
891
892 #if defined(TARGET_PPC64)
893 if (!(ctx->sf_mode)) {
894 TCGv t0, t1;
895 t0 = tcg_temp_new();
896 t1 = tcg_temp_new();
897
898 tcg_gen_ext32u_tl(t0, arg1);
899 tcg_gen_ext32u_tl(t1, arg2);
900 if (sub) {
901 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
902 } else {
903 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
904 }
905 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
906 gen_set_label(l1);
907 tcg_temp_free(t0);
908 tcg_temp_free(t1);
909 } else
910 #endif
911 {
912 if (sub) {
913 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
914 } else {
915 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
916 }
917 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
918 gen_set_label(l1);
919 }
920 }
921
922 /* Common add function */
923 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
924 int add_ca, int compute_ca, int compute_ov)
925 {
926 TCGv t0, t1;
927
928 if ((!compute_ca && !compute_ov) ||
929 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
930 t0 = ret;
931 } else {
932 t0 = tcg_temp_local_new();
933 }
934
935 if (add_ca) {
936 t1 = tcg_temp_local_new();
937 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
938 tcg_gen_shri_tl(t1, t1, XER_CA);
939 }
940
941 if (compute_ca && compute_ov) {
942 /* Start with XER CA and OV disabled, the most likely case */
943 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
944 } else if (compute_ca) {
945 /* Start with XER CA disabled, the most likely case */
946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
947 } else if (compute_ov) {
948 /* Start with XER OV disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
950 }
951
952 tcg_gen_add_tl(t0, arg1, arg2);
953
954 if (compute_ca) {
955 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
956 }
957 if (add_ca) {
958 tcg_gen_add_tl(t0, t0, t1);
959 gen_op_arith_compute_ca(ctx, t0, t1, 0);
960 tcg_temp_free(t1);
961 }
962 if (compute_ov) {
963 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
964 }
965
966 if (unlikely(Rc(ctx->opcode) != 0))
967 gen_set_Rc0(ctx, t0);
968
969 if (!TCGV_EQUAL(t0, ret)) {
970 tcg_gen_mov_tl(ret, t0);
971 tcg_temp_free(t0);
972 }
973 }
974 /* Add functions with two operands */
975 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
976 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
977 { \
978 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
979 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
980 add_ca, compute_ca, compute_ov); \
981 }
982 /* Add functions with one operand and one immediate */
983 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
984 add_ca, compute_ca, compute_ov) \
985 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
986 { \
987 TCGv t0 = tcg_const_local_tl(const_val); \
988 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
989 cpu_gpr[rA(ctx->opcode)], t0, \
990 add_ca, compute_ca, compute_ov); \
991 tcg_temp_free(t0); \
992 }
993
994 /* add add. addo addo. */
995 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
996 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
997 /* addc addc. addco addco. */
998 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
999 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1000 /* adde adde. addeo addeo. */
1001 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1002 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1003 /* addme addme. addmeo addmeo. */
1004 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1005 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1006 /* addze addze. addzeo addzeo.*/
1007 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1008 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1009 /* addi */
1010 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1011 {
1012 target_long simm = SIMM(ctx->opcode);
1013
1014 if (rA(ctx->opcode) == 0) {
1015 /* li case */
1016 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1017 } else {
1018 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1019 }
1020 }
1021 /* addic addic.*/
1022 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1023 int compute_Rc0)
1024 {
1025 target_long simm = SIMM(ctx->opcode);
1026
1027 /* Start with XER CA and OV disabled, the most likely case */
1028 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1029
1030 if (likely(simm != 0)) {
1031 TCGv t0 = tcg_temp_local_new();
1032 tcg_gen_addi_tl(t0, arg1, simm);
1033 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1034 tcg_gen_mov_tl(ret, t0);
1035 tcg_temp_free(t0);
1036 } else {
1037 tcg_gen_mov_tl(ret, arg1);
1038 }
1039 if (compute_Rc0) {
1040 gen_set_Rc0(ctx, ret);
1041 }
1042 }
1043 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044 {
1045 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1046 }
1047 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1048 {
1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1050 }
1051 /* addis */
1052 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1053 {
1054 target_long simm = SIMM(ctx->opcode);
1055
1056 if (rA(ctx->opcode) == 0) {
1057 /* lis case */
1058 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1059 } else {
1060 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1061 }
1062 }
1063
1064 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1065 int sign, int compute_ov)
1066 {
1067 int l1 = gen_new_label();
1068 int l2 = gen_new_label();
1069 TCGv_i32 t0 = tcg_temp_local_new_i32();
1070 TCGv_i32 t1 = tcg_temp_local_new_i32();
1071
1072 tcg_gen_trunc_tl_i32(t0, arg1);
1073 tcg_gen_trunc_tl_i32(t1, arg2);
1074 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1075 if (sign) {
1076 int l3 = gen_new_label();
1077 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1079 gen_set_label(l3);
1080 tcg_gen_div_i32(t0, t0, t1);
1081 } else {
1082 tcg_gen_divu_i32(t0, t0, t1);
1083 }
1084 if (compute_ov) {
1085 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1086 }
1087 tcg_gen_br(l2);
1088 gen_set_label(l1);
1089 if (sign) {
1090 tcg_gen_sari_i32(t0, t0, 31);
1091 } else {
1092 tcg_gen_movi_i32(t0, 0);
1093 }
1094 if (compute_ov) {
1095 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1096 }
1097 gen_set_label(l2);
1098 tcg_gen_extu_i32_tl(ret, t0);
1099 tcg_temp_free_i32(t0);
1100 tcg_temp_free_i32(t1);
1101 if (unlikely(Rc(ctx->opcode) != 0))
1102 gen_set_Rc0(ctx, ret);
1103 }
1104 /* Div functions */
1105 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1106 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1107 { \
1108 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1109 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1110 sign, compute_ov); \
1111 }
1112 /* divwu divwu. divwuo divwuo. */
1113 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1114 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1115 /* divw divw. divwo divwo. */
1116 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1117 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1118 #if defined(TARGET_PPC64)
1119 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1120 int sign, int compute_ov)
1121 {
1122 int l1 = gen_new_label();
1123 int l2 = gen_new_label();
1124
1125 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1126 if (sign) {
1127 int l3 = gen_new_label();
1128 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1130 gen_set_label(l3);
1131 tcg_gen_div_i64(ret, arg1, arg2);
1132 } else {
1133 tcg_gen_divu_i64(ret, arg1, arg2);
1134 }
1135 if (compute_ov) {
1136 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1137 }
1138 tcg_gen_br(l2);
1139 gen_set_label(l1);
1140 if (sign) {
1141 tcg_gen_sari_i64(ret, arg1, 63);
1142 } else {
1143 tcg_gen_movi_i64(ret, 0);
1144 }
1145 if (compute_ov) {
1146 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1147 }
1148 gen_set_label(l2);
1149 if (unlikely(Rc(ctx->opcode) != 0))
1150 gen_set_Rc0(ctx, ret);
1151 }
1152 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1153 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1154 { \
1155 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1156 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1157 sign, compute_ov); \
1158 }
1159 /* divwu divwu. divwuo divwuo. */
1160 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1161 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1162 /* divw divw. divwo divwo. */
1163 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1164 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1165 #endif
1166
1167 /* mulhw mulhw. */
1168 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1169 {
1170 TCGv_i64 t0, t1;
1171
1172 t0 = tcg_temp_new_i64();
1173 t1 = tcg_temp_new_i64();
1174 #if defined(TARGET_PPC64)
1175 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1176 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1177 tcg_gen_mul_i64(t0, t0, t1);
1178 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1179 #else
1180 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1181 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1182 tcg_gen_mul_i64(t0, t0, t1);
1183 tcg_gen_shri_i64(t0, t0, 32);
1184 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1185 #endif
1186 tcg_temp_free_i64(t0);
1187 tcg_temp_free_i64(t1);
1188 if (unlikely(Rc(ctx->opcode) != 0))
1189 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1190 }
1191 /* mulhwu mulhwu. */
1192 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1193 {
1194 TCGv_i64 t0, t1;
1195
1196 t0 = tcg_temp_new_i64();
1197 t1 = tcg_temp_new_i64();
1198 #if defined(TARGET_PPC64)
1199 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1200 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1201 tcg_gen_mul_i64(t0, t0, t1);
1202 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1203 #else
1204 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1205 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1206 tcg_gen_mul_i64(t0, t0, t1);
1207 tcg_gen_shri_i64(t0, t0, 32);
1208 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1209 #endif
1210 tcg_temp_free_i64(t0);
1211 tcg_temp_free_i64(t1);
1212 if (unlikely(Rc(ctx->opcode) != 0))
1213 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1214 }
1215 /* mullw mullw. */
1216 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1217 {
1218 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1219 cpu_gpr[rB(ctx->opcode)]);
1220 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1221 if (unlikely(Rc(ctx->opcode) != 0))
1222 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1223 }
1224 /* mullwo mullwo. */
1225 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1226 {
1227 int l1;
1228 TCGv_i64 t0, t1;
1229
1230 t0 = tcg_temp_new_i64();
1231 t1 = tcg_temp_new_i64();
1232 l1 = gen_new_label();
1233 /* Start with XER OV disabled, the most likely case */
1234 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1235 #if defined(TARGET_PPC64)
1236 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1237 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1238 #else
1239 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1240 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1241 #endif
1242 tcg_gen_mul_i64(t0, t0, t1);
1243 #if defined(TARGET_PPC64)
1244 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1245 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1246 #else
1247 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1248 tcg_gen_ext32s_i64(t1, t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1250 #endif
1251 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1252 gen_set_label(l1);
1253 tcg_temp_free_i64(t0);
1254 tcg_temp_free_i64(t1);
1255 if (unlikely(Rc(ctx->opcode) != 0))
1256 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1257 }
1258 /* mulli */
1259 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1260 {
1261 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1262 SIMM(ctx->opcode));
1263 }
1264 #if defined(TARGET_PPC64)
1265 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1266 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1267 { \
1268 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1269 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1270 if (unlikely(Rc(ctx->opcode) != 0)) \
1271 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1272 }
1273 /* mulhd mulhd. */
1274 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1275 /* mulhdu mulhdu. */
1276 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1277 /* mulld mulld. */
1278 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1279 {
1280 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1281 cpu_gpr[rB(ctx->opcode)]);
1282 if (unlikely(Rc(ctx->opcode) != 0))
1283 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1284 }
1285 /* mulldo mulldo. */
1286 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1287 #endif
1288
1289 /* neg neg. nego nego. */
1290 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1291 {
1292 int l1 = gen_new_label();
1293 int l2 = gen_new_label();
1294 TCGv t0 = tcg_temp_local_new();
1295 #if defined(TARGET_PPC64)
1296 if (ctx->sf_mode) {
1297 tcg_gen_mov_tl(t0, arg1);
1298 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1299 } else
1300 #endif
1301 {
1302 tcg_gen_ext32s_tl(t0, arg1);
1303 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1304 }
1305 tcg_gen_neg_tl(ret, arg1);
1306 if (ov_check) {
1307 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1308 }
1309 tcg_gen_br(l2);
1310 gen_set_label(l1);
1311 tcg_gen_mov_tl(ret, t0);
1312 if (ov_check) {
1313 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1314 }
1315 gen_set_label(l2);
1316 tcg_temp_free(t0);
1317 if (unlikely(Rc(ctx->opcode) != 0))
1318 gen_set_Rc0(ctx, ret);
1319 }
1320 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1321 {
1322 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1323 }
1324 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1325 {
1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1327 }
1328
1329 /* Common subf function */
1330 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1331 int add_ca, int compute_ca, int compute_ov)
1332 {
1333 TCGv t0, t1;
1334
1335 if ((!compute_ca && !compute_ov) ||
1336 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1337 t0 = ret;
1338 } else {
1339 t0 = tcg_temp_local_new();
1340 }
1341
1342 if (add_ca) {
1343 t1 = tcg_temp_local_new();
1344 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1345 tcg_gen_shri_tl(t1, t1, XER_CA);
1346 }
1347
1348 if (compute_ca && compute_ov) {
1349 /* Start with XER CA and OV disabled, the most likely case */
1350 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1351 } else if (compute_ca) {
1352 /* Start with XER CA disabled, the most likely case */
1353 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1354 } else if (compute_ov) {
1355 /* Start with XER OV disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1357 }
1358
1359 if (add_ca) {
1360 tcg_gen_not_tl(t0, arg1);
1361 tcg_gen_add_tl(t0, t0, arg2);
1362 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1363 tcg_gen_add_tl(t0, t0, t1);
1364 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1365 tcg_temp_free(t1);
1366 } else {
1367 tcg_gen_sub_tl(t0, arg2, arg1);
1368 if (compute_ca) {
1369 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1370 }
1371 }
1372 if (compute_ov) {
1373 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1374 }
1375
1376 if (unlikely(Rc(ctx->opcode) != 0))
1377 gen_set_Rc0(ctx, t0);
1378
1379 if (!TCGV_EQUAL(t0, ret)) {
1380 tcg_gen_mov_tl(ret, t0);
1381 tcg_temp_free(t0);
1382 }
1383 }
1384 /* Sub functions with Two operands functions */
1385 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1386 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1387 { \
1388 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1389 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1390 add_ca, compute_ca, compute_ov); \
1391 }
1392 /* Sub functions with one operand and one immediate */
1393 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1394 add_ca, compute_ca, compute_ov) \
1395 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1396 { \
1397 TCGv t0 = tcg_const_local_tl(const_val); \
1398 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1399 cpu_gpr[rA(ctx->opcode)], t0, \
1400 add_ca, compute_ca, compute_ov); \
1401 tcg_temp_free(t0); \
1402 }
1403 /* subf subf. subfo subfo. */
1404 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1405 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1406 /* subfc subfc. subfco subfco. */
1407 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1408 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1409 /* subfe subfe. subfeo subfo. */
1410 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1411 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1412 /* subfme subfme. subfmeo subfmeo. */
1413 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1414 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1415 /* subfze subfze. subfzeo subfzeo.*/
1416 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1417 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1418 /* subfic */
1419 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1420 {
1421 /* Start with XER CA and OV disabled, the most likely case */
1422 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1423 TCGv t0 = tcg_temp_local_new();
1424 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1425 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1426 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1427 tcg_temp_free(t1);
1428 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1429 tcg_temp_free(t0);
1430 }
1431
1432 /*** Integer logical ***/
1433 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1434 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1435 { \
1436 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1437 cpu_gpr[rB(ctx->opcode)]); \
1438 if (unlikely(Rc(ctx->opcode) != 0)) \
1439 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1440 }
1441
1442 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1443 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1444 { \
1445 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1446 if (unlikely(Rc(ctx->opcode) != 0)) \
1447 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1448 }
1449
1450 /* and & and. */
1451 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1452 /* andc & andc. */
1453 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1454 /* andi. */
1455 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1456 {
1457 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1458 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1459 }
1460 /* andis. */
1461 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1462 {
1463 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1464 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1465 }
1466 /* cntlzw */
1467 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1468 {
1469 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1470 if (unlikely(Rc(ctx->opcode) != 0))
1471 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1472 }
1473 /* eqv & eqv. */
1474 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1475 /* extsb & extsb. */
1476 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1477 /* extsh & extsh. */
1478 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1479 /* nand & nand. */
1480 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1481 /* nor & nor. */
1482 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1483 /* or & or. */
1484 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1485 {
1486 int rs, ra, rb;
1487
1488 rs = rS(ctx->opcode);
1489 ra = rA(ctx->opcode);
1490 rb = rB(ctx->opcode);
1491 /* Optimisation for mr. ri case */
1492 if (rs != ra || rs != rb) {
1493 if (rs != rb)
1494 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1495 else
1496 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1497 if (unlikely(Rc(ctx->opcode) != 0))
1498 gen_set_Rc0(ctx, cpu_gpr[ra]);
1499 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1500 gen_set_Rc0(ctx, cpu_gpr[rs]);
1501 #if defined(TARGET_PPC64)
1502 } else {
1503 int prio = 0;
1504
1505 switch (rs) {
1506 case 1:
1507 /* Set process priority to low */
1508 prio = 2;
1509 break;
1510 case 6:
1511 /* Set process priority to medium-low */
1512 prio = 3;
1513 break;
1514 case 2:
1515 /* Set process priority to normal */
1516 prio = 4;
1517 break;
1518 #if !defined(CONFIG_USER_ONLY)
1519 case 31:
1520 if (ctx->supervisor > 0) {
1521 /* Set process priority to very low */
1522 prio = 1;
1523 }
1524 break;
1525 case 5:
1526 if (ctx->supervisor > 0) {
1527 /* Set process priority to medium-hight */
1528 prio = 5;
1529 }
1530 break;
1531 case 3:
1532 if (ctx->supervisor > 0) {
1533 /* Set process priority to high */
1534 prio = 6;
1535 }
1536 break;
1537 case 7:
1538 if (ctx->supervisor > 1) {
1539 /* Set process priority to very high */
1540 prio = 7;
1541 }
1542 break;
1543 #endif
1544 default:
1545 /* nop */
1546 break;
1547 }
1548 if (prio) {
1549 TCGv t0 = tcg_temp_new();
1550 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1551 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1552 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1553 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1554 tcg_temp_free(t0);
1555 }
1556 #endif
1557 }
1558 }
1559 /* orc & orc. */
1560 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1561 /* xor & xor. */
1562 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1563 {
1564 /* Optimisation for "set to zero" case */
1565 if (rS(ctx->opcode) != rB(ctx->opcode))
1566 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1567 else
1568 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1569 if (unlikely(Rc(ctx->opcode) != 0))
1570 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1571 }
1572 /* ori */
1573 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1574 {
1575 target_ulong uimm = UIMM(ctx->opcode);
1576
1577 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1578 /* NOP */
1579 /* XXX: should handle special NOPs for POWER series */
1580 return;
1581 }
1582 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1583 }
1584 /* oris */
1585 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1586 {
1587 target_ulong uimm = UIMM(ctx->opcode);
1588
1589 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1590 /* NOP */
1591 return;
1592 }
1593 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1594 }
1595 /* xori */
1596 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1597 {
1598 target_ulong uimm = UIMM(ctx->opcode);
1599
1600 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1601 /* NOP */
1602 return;
1603 }
1604 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1605 }
1606 /* xoris */
1607 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1608 {
1609 target_ulong uimm = UIMM(ctx->opcode);
1610
1611 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1612 /* NOP */
1613 return;
1614 }
1615 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1616 }
1617 /* popcntb : PowerPC 2.03 specification */
1618 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1619 {
1620 #if defined(TARGET_PPC64)
1621 if (ctx->sf_mode)
1622 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1623 else
1624 #endif
1625 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 }
1627
1628 #if defined(TARGET_PPC64)
1629 /* extsw & extsw. */
1630 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1631 /* cntlzd */
1632 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1633 {
1634 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1635 if (unlikely(Rc(ctx->opcode) != 0))
1636 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1637 }
1638 #endif
1639
1640 /*** Integer rotate ***/
1641 /* rlwimi & rlwimi. */
1642 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1643 {
1644 uint32_t mb, me, sh;
1645
1646 mb = MB(ctx->opcode);
1647 me = ME(ctx->opcode);
1648 sh = SH(ctx->opcode);
1649 if (likely(sh == 0 && mb == 0 && me == 31)) {
1650 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1651 } else {
1652 target_ulong mask;
1653 TCGv t1;
1654 TCGv t0 = tcg_temp_new();
1655 #if defined(TARGET_PPC64)
1656 TCGv_i32 t2 = tcg_temp_new_i32();
1657 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1658 tcg_gen_rotli_i32(t2, t2, sh);
1659 tcg_gen_extu_i32_i64(t0, t2);
1660 tcg_temp_free_i32(t2);
1661 #else
1662 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1663 #endif
1664 #if defined(TARGET_PPC64)
1665 mb += 32;
1666 me += 32;
1667 #endif
1668 mask = MASK(mb, me);
1669 t1 = tcg_temp_new();
1670 tcg_gen_andi_tl(t0, t0, mask);
1671 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1672 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1673 tcg_temp_free(t0);
1674 tcg_temp_free(t1);
1675 }
1676 if (unlikely(Rc(ctx->opcode) != 0))
1677 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1678 }
1679 /* rlwinm & rlwinm. */
1680 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1681 {
1682 uint32_t mb, me, sh;
1683
1684 sh = SH(ctx->opcode);
1685 mb = MB(ctx->opcode);
1686 me = ME(ctx->opcode);
1687
1688 if (likely(mb == 0 && me == (31 - sh))) {
1689 if (likely(sh == 0)) {
1690 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1691 } else {
1692 TCGv t0 = tcg_temp_new();
1693 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1694 tcg_gen_shli_tl(t0, t0, sh);
1695 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1696 tcg_temp_free(t0);
1697 }
1698 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1699 TCGv t0 = tcg_temp_new();
1700 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1701 tcg_gen_shri_tl(t0, t0, mb);
1702 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1703 tcg_temp_free(t0);
1704 } else {
1705 TCGv t0 = tcg_temp_new();
1706 #if defined(TARGET_PPC64)
1707 TCGv_i32 t1 = tcg_temp_new_i32();
1708 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1709 tcg_gen_rotli_i32(t1, t1, sh);
1710 tcg_gen_extu_i32_i64(t0, t1);
1711 tcg_temp_free_i32(t1);
1712 #else
1713 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1714 #endif
1715 #if defined(TARGET_PPC64)
1716 mb += 32;
1717 me += 32;
1718 #endif
1719 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1720 tcg_temp_free(t0);
1721 }
1722 if (unlikely(Rc(ctx->opcode) != 0))
1723 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1724 }
1725 /* rlwnm & rlwnm. */
1726 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1727 {
1728 uint32_t mb, me;
1729 TCGv t0;
1730 #if defined(TARGET_PPC64)
1731 TCGv_i32 t1, t2;
1732 #endif
1733
1734 mb = MB(ctx->opcode);
1735 me = ME(ctx->opcode);
1736 t0 = tcg_temp_new();
1737 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1738 #if defined(TARGET_PPC64)
1739 t1 = tcg_temp_new_i32();
1740 t2 = tcg_temp_new_i32();
1741 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1742 tcg_gen_trunc_i64_i32(t2, t0);
1743 tcg_gen_rotl_i32(t1, t1, t2);
1744 tcg_gen_extu_i32_i64(t0, t1);
1745 tcg_temp_free_i32(t1);
1746 tcg_temp_free_i32(t2);
1747 #else
1748 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1749 #endif
1750 if (unlikely(mb != 0 || me != 31)) {
1751 #if defined(TARGET_PPC64)
1752 mb += 32;
1753 me += 32;
1754 #endif
1755 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1756 } else {
1757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1758 }
1759 tcg_temp_free(t0);
1760 if (unlikely(Rc(ctx->opcode) != 0))
1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763
1764 #if defined(TARGET_PPC64)
1765 #define GEN_PPC64_R2(name, opc1, opc2) \
1766 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1767 { \
1768 gen_##name(ctx, 0); \
1769 } \
1770 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1771 PPC_64B) \
1772 { \
1773 gen_##name(ctx, 1); \
1774 }
1775 #define GEN_PPC64_R4(name, opc1, opc2) \
1776 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1777 { \
1778 gen_##name(ctx, 0, 0); \
1779 } \
1780 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1781 PPC_64B) \
1782 { \
1783 gen_##name(ctx, 0, 1); \
1784 } \
1785 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1786 PPC_64B) \
1787 { \
1788 gen_##name(ctx, 1, 0); \
1789 } \
1790 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1791 PPC_64B) \
1792 { \
1793 gen_##name(ctx, 1, 1); \
1794 }
1795
1796 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1797 uint32_t me, uint32_t sh)
1798 {
1799 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1800 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1801 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1802 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1803 } else {
1804 TCGv t0 = tcg_temp_new();
1805 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1806 if (likely(mb == 0 && me == 63)) {
1807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1808 } else {
1809 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1810 }
1811 tcg_temp_free(t0);
1812 }
1813 if (unlikely(Rc(ctx->opcode) != 0))
1814 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1815 }
1816 /* rldicl - rldicl. */
1817 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1818 {
1819 uint32_t sh, mb;
1820
1821 sh = SH(ctx->opcode) | (shn << 5);
1822 mb = MB(ctx->opcode) | (mbn << 5);
1823 gen_rldinm(ctx, mb, 63, sh);
1824 }
1825 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1826 /* rldicr - rldicr. */
1827 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1828 {
1829 uint32_t sh, me;
1830
1831 sh = SH(ctx->opcode) | (shn << 5);
1832 me = MB(ctx->opcode) | (men << 5);
1833 gen_rldinm(ctx, 0, me, sh);
1834 }
1835 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1836 /* rldic - rldic. */
1837 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1838 {
1839 uint32_t sh, mb;
1840
1841 sh = SH(ctx->opcode) | (shn << 5);
1842 mb = MB(ctx->opcode) | (mbn << 5);
1843 gen_rldinm(ctx, mb, 63 - sh, sh);
1844 }
1845 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1846
1847 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1848 uint32_t me)
1849 {
1850 TCGv t0;
1851
1852 mb = MB(ctx->opcode);
1853 me = ME(ctx->opcode);
1854 t0 = tcg_temp_new();
1855 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1856 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1857 if (unlikely(mb != 0 || me != 63)) {
1858 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1859 } else {
1860 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1861 }
1862 tcg_temp_free(t0);
1863 if (unlikely(Rc(ctx->opcode) != 0))
1864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1865 }
1866
1867 /* rldcl - rldcl. */
1868 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1869 {
1870 uint32_t mb;
1871
1872 mb = MB(ctx->opcode) | (mbn << 5);
1873 gen_rldnm(ctx, mb, 63);
1874 }
1875 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1876 /* rldcr - rldcr. */
1877 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1878 {
1879 uint32_t me;
1880
1881 me = MB(ctx->opcode) | (men << 5);
1882 gen_rldnm(ctx, 0, me);
1883 }
1884 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1885 /* rldimi - rldimi. */
1886 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1887 {
1888 uint32_t sh, mb, me;
1889
1890 sh = SH(ctx->opcode) | (shn << 5);
1891 mb = MB(ctx->opcode) | (mbn << 5);
1892 me = 63 - sh;
1893 if (unlikely(sh == 0 && mb == 0)) {
1894 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1895 } else {
1896 TCGv t0, t1;
1897 target_ulong mask;
1898
1899 t0 = tcg_temp_new();
1900 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1901 t1 = tcg_temp_new();
1902 mask = MASK(mb, me);
1903 tcg_gen_andi_tl(t0, t0, mask);
1904 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1905 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1906 tcg_temp_free(t0);
1907 tcg_temp_free(t1);
1908 }
1909 if (unlikely(Rc(ctx->opcode) != 0))
1910 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1911 }
1912 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1913 #endif
1914
1915 /*** Integer shift ***/
1916 /* slw & slw. */
1917 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1918 {
1919 TCGv t0;
1920 int l1, l2;
1921 l1 = gen_new_label();
1922 l2 = gen_new_label();
1923
1924 t0 = tcg_temp_local_new();
1925 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1926 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1927 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1928 tcg_gen_br(l2);
1929 gen_set_label(l1);
1930 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1931 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1932 gen_set_label(l2);
1933 tcg_temp_free(t0);
1934 if (unlikely(Rc(ctx->opcode) != 0))
1935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1936 }
1937 /* sraw & sraw. */
1938 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1939 {
1940 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1941 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1942 if (unlikely(Rc(ctx->opcode) != 0))
1943 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1944 }
1945 /* srawi & srawi. */
1946 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1947 {
1948 int sh = SH(ctx->opcode);
1949 if (sh != 0) {
1950 int l1, l2;
1951 TCGv t0;
1952 l1 = gen_new_label();
1953 l2 = gen_new_label();
1954 t0 = tcg_temp_local_new();
1955 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1956 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1957 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1958 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1959 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1960 tcg_gen_br(l2);
1961 gen_set_label(l1);
1962 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1963 gen_set_label(l2);
1964 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1965 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1966 tcg_temp_free(t0);
1967 } else {
1968 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1970 }
1971 if (unlikely(Rc(ctx->opcode) != 0))
1972 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1973 }
1974 /* srw & srw. */
1975 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1976 {
1977 TCGv t0, t1;
1978 int l1, l2;
1979 l1 = gen_new_label();
1980 l2 = gen_new_label();
1981
1982 t0 = tcg_temp_local_new();
1983 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1984 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1985 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1986 tcg_gen_br(l2);
1987 gen_set_label(l1);
1988 t1 = tcg_temp_new();
1989 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1990 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1991 tcg_temp_free(t1);
1992 gen_set_label(l2);
1993 tcg_temp_free(t0);
1994 if (unlikely(Rc(ctx->opcode) != 0))
1995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1996 }
1997 #if defined(TARGET_PPC64)
1998 /* sld & sld. */
1999 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2000 {
2001 TCGv t0;
2002 int l1, l2;
2003 l1 = gen_new_label();
2004 l2 = gen_new_label();
2005
2006 t0 = tcg_temp_local_new();
2007 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2008 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2009 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2010 tcg_gen_br(l2);
2011 gen_set_label(l1);
2012 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2013 gen_set_label(l2);
2014 tcg_temp_free(t0);
2015 if (unlikely(Rc(ctx->opcode) != 0))
2016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2017 }
2018 /* srad & srad. */
2019 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2020 {
2021 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2022 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2023 if (unlikely(Rc(ctx->opcode) != 0))
2024 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2025 }
2026 /* sradi & sradi. */
2027 static always_inline void gen_sradi (DisasContext *ctx, int n)
2028 {
2029 int sh = SH(ctx->opcode) + (n << 5);
2030 if (sh != 0) {
2031 int l1, l2;
2032 TCGv t0;
2033 l1 = gen_new_label();
2034 l2 = gen_new_label();
2035 t0 = tcg_temp_local_new();
2036 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2037 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2038 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2039 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2040 tcg_gen_br(l2);
2041 gen_set_label(l1);
2042 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2043 gen_set_label(l2);
2044 tcg_temp_free(t0);
2045 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2046 } else {
2047 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2048 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2049 }
2050 if (unlikely(Rc(ctx->opcode) != 0))
2051 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2052 }
2053 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2054 {
2055 gen_sradi(ctx, 0);
2056 }
2057 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2058 {
2059 gen_sradi(ctx, 1);
2060 }
2061 /* srd & srd. */
2062 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2063 {
2064 TCGv t0;
2065 int l1, l2;
2066 l1 = gen_new_label();
2067 l2 = gen_new_label();
2068
2069 t0 = tcg_temp_local_new();
2070 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2071 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2072 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2073 tcg_gen_br(l2);
2074 gen_set_label(l1);
2075 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2076 gen_set_label(l2);
2077 tcg_temp_free(t0);
2078 if (unlikely(Rc(ctx->opcode) != 0))
2079 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2080 }
2081 #endif
2082
2083 /*** Floating-Point arithmetic ***/
2084 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2085 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2086 { \
2087 if (unlikely(!ctx->fpu_enabled)) { \
2088 GEN_EXCP_NO_FP(ctx); \
2089 return; \
2090 } \
2091 gen_reset_fpstatus(); \
2092 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2093 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2094 if (isfloat) { \
2095 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2096 } \
2097 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2098 Rc(ctx->opcode) != 0); \
2099 }
2100
2101 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2102 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2103 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2104
2105 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2106 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2107 { \
2108 if (unlikely(!ctx->fpu_enabled)) { \
2109 GEN_EXCP_NO_FP(ctx); \
2110 return; \
2111 } \
2112 gen_reset_fpstatus(); \
2113 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2114 cpu_fpr[rB(ctx->opcode)]); \
2115 if (isfloat) { \
2116 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2117 } \
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2119 set_fprf, Rc(ctx->opcode) != 0); \
2120 }
2121 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2122 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2123 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2124
2125 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2126 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2127 { \
2128 if (unlikely(!ctx->fpu_enabled)) { \
2129 GEN_EXCP_NO_FP(ctx); \
2130 return; \
2131 } \
2132 gen_reset_fpstatus(); \
2133 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2134 cpu_fpr[rC(ctx->opcode)]); \
2135 if (isfloat) { \
2136 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2137 } \
2138 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2139 set_fprf, Rc(ctx->opcode) != 0); \
2140 }
2141 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2142 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2143 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144
2145 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2146 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2147 { \
2148 if (unlikely(!ctx->fpu_enabled)) { \
2149 GEN_EXCP_NO_FP(ctx); \
2150 return; \
2151 } \
2152 gen_reset_fpstatus(); \
2153 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2154 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2155 set_fprf, Rc(ctx->opcode) != 0); \
2156 }
2157
2158 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2159 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2160 { \
2161 if (unlikely(!ctx->fpu_enabled)) { \
2162 GEN_EXCP_NO_FP(ctx); \
2163 return; \
2164 } \
2165 gen_reset_fpstatus(); \
2166 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2167 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2168 set_fprf, Rc(ctx->opcode) != 0); \
2169 }
2170
2171 /* fadd - fadds */
2172 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2173 /* fdiv - fdivs */
2174 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2175 /* fmul - fmuls */
2176 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2177
2178 /* fre */
2179 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2180
2181 /* fres */
2182 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2183
2184 /* frsqrte */
2185 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2186
2187 /* frsqrtes */
2188 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2189 {
2190 if (unlikely(!ctx->fpu_enabled)) {
2191 GEN_EXCP_NO_FP(ctx);
2192 return;
2193 }
2194 gen_reset_fpstatus();
2195 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2196 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2197 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2198 }
2199
2200 /* fsel */
2201 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2202 /* fsub - fsubs */
2203 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2204 /* Optional: */
2205 /* fsqrt */
2206 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2207 {
2208 if (unlikely(!ctx->fpu_enabled)) {
2209 GEN_EXCP_NO_FP(ctx);
2210 return;
2211 }
2212 gen_reset_fpstatus();
2213 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2214 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2215 }
2216
2217 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2218 {
2219 if (unlikely(!ctx->fpu_enabled)) {
2220 GEN_EXCP_NO_FP(ctx);
2221 return;
2222 }
2223 gen_reset_fpstatus();
2224 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2225 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2226 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2227 }
2228
2229 /*** Floating-Point multiply-and-add ***/
2230 /* fmadd - fmadds */
2231 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2232 /* fmsub - fmsubs */
2233 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2234 /* fnmadd - fnmadds */
2235 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2236 /* fnmsub - fnmsubs */
2237 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2238
2239 /*** Floating-Point round & convert ***/
2240 /* fctiw */
2241 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2242 /* fctiwz */
2243 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2244 /* frsp */
2245 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2246 #if defined(TARGET_PPC64)
2247 /* fcfid */
2248 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2249 /* fctid */
2250 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2251 /* fctidz */
2252 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2253 #endif
2254
2255 /* frin */
2256 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2257 /* friz */
2258 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2259 /* frip */
2260 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2261 /* frim */
2262 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2263
2264 /*** Floating-Point compare ***/
2265 /* fcmpo */
2266 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2267 {
2268 if (unlikely(!ctx->fpu_enabled)) {
2269 GEN_EXCP_NO_FP(ctx);
2270 return;
2271 }
2272 gen_reset_fpstatus();
2273 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2274 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2275 gen_helper_float_check_status();
2276 }
2277
2278 /* fcmpu */
2279 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2280 {
2281 if (unlikely(!ctx->fpu_enabled)) {
2282 GEN_EXCP_NO_FP(ctx);
2283 return;
2284 }
2285 gen_reset_fpstatus();
2286 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2287 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2288 gen_helper_float_check_status();
2289 }
2290
2291 /*** Floating-point move ***/
2292 /* fabs */
2293 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2294 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2295
2296 /* fmr - fmr. */
2297 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2298 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2299 {
2300 if (unlikely(!ctx->fpu_enabled)) {
2301 GEN_EXCP_NO_FP(ctx);
2302 return;
2303 }
2304 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2305 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2306 }
2307
2308 /* fnabs */
2309 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2310 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2311 /* fneg */
2312 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2313 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2314
2315 /*** Floating-Point status & ctrl register ***/
2316 /* mcrfs */
2317 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2318 {
2319 int bfa;
2320
2321 if (unlikely(!ctx->fpu_enabled)) {
2322 GEN_EXCP_NO_FP(ctx);
2323 return;
2324 }
2325 gen_optimize_fprf();
2326 bfa = 4 * (7 - crfS(ctx->opcode));
2327 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2328 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2329 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2330 }
2331
2332 /* mffs */
2333 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2334 {
2335 if (unlikely(!ctx->fpu_enabled)) {
2336 GEN_EXCP_NO_FP(ctx);
2337 return;
2338 }
2339 gen_optimize_fprf();
2340 gen_reset_fpstatus();
2341 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2342 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2343 }
2344
2345 /* mtfsb0 */
2346 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2347 {
2348 uint8_t crb;
2349
2350 if (unlikely(!ctx->fpu_enabled)) {
2351 GEN_EXCP_NO_FP(ctx);
2352 return;
2353 }
2354 crb = 32 - (crbD(ctx->opcode) >> 2);
2355 gen_optimize_fprf();
2356 gen_reset_fpstatus();
2357 if (likely(crb != 30 && crb != 29))
2358 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
2359 if (unlikely(Rc(ctx->opcode) != 0)) {
2360 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2361 }
2362 }
2363
2364 /* mtfsb1 */
2365 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2366 {
2367 uint8_t crb;
2368
2369 if (unlikely(!ctx->fpu_enabled)) {
2370 GEN_EXCP_NO_FP(ctx);
2371 return;
2372 }
2373 crb = 32 - (crbD(ctx->opcode) >> 2);
2374 gen_optimize_fprf();
2375 gen_reset_fpstatus();
2376 /* XXX: we pretend we can only do IEEE floating-point computations */
2377 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2378 TCGv_i32 t0 = tcg_const_i32(crb);
2379 gen_helper_fpscr_setbit(t0);
2380 tcg_temp_free_i32(t0);
2381 }
2382 if (unlikely(Rc(ctx->opcode) != 0)) {
2383 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2384 }
2385 /* We can raise a differed exception */
2386 gen_helper_float_check_status();
2387 }
2388
2389 /* mtfsf */
2390 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2391 {
2392 TCGv_i32 t0;
2393
2394 if (unlikely(!ctx->fpu_enabled)) {
2395 GEN_EXCP_NO_FP(ctx);
2396 return;
2397 }
2398 gen_optimize_fprf();
2399 gen_reset_fpstatus();
2400 t0 = tcg_const_i32(FM(ctx->opcode));
2401 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2402 tcg_temp_free_i32(t0);
2403 if (unlikely(Rc(ctx->opcode) != 0)) {
2404 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2405 }
2406 /* We can raise a differed exception */
2407 gen_helper_float_check_status();
2408 }
2409
2410 /* mtfsfi */
2411 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2412 {
2413 int bf, sh;
2414 TCGv_i64 t0;
2415 TCGv_i32 t1;
2416
2417 if (unlikely(!ctx->fpu_enabled)) {
2418 GEN_EXCP_NO_FP(ctx);
2419 return;
2420 }
2421 bf = crbD(ctx->opcode) >> 2;
2422 sh = 7 - bf;
2423 gen_optimize_fprf();
2424 gen_reset_fpstatus();
2425 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2426 t1 = tcg_const_i32(1 << sh);
2427 gen_helper_store_fpscr(t0, t1);
2428 tcg_temp_free_i64(t0);
2429 tcg_temp_free_i32(t1);
2430 if (unlikely(Rc(ctx->opcode) != 0)) {
2431 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2432 }
2433 /* We can raise a differed exception */
2434 gen_helper_float_check_status();
2435 }
2436
2437 /*** Addressing modes ***/
2438 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2439 static always_inline void gen_addr_imm_index (TCGv EA,
2440 DisasContext *ctx,
2441 target_long maskl)
2442 {
2443 target_long simm = SIMM(ctx->opcode);
2444
2445 simm &= ~maskl;
2446 if (rA(ctx->opcode) == 0)
2447 tcg_gen_movi_tl(EA, simm);
2448 else if (likely(simm != 0))
2449 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2450 else
2451 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2452 }
2453
2454 static always_inline void gen_addr_reg_index (TCGv EA,
2455 DisasContext *ctx)
2456 {
2457 if (rA(ctx->opcode) == 0)
2458 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2459 else
2460 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2461 }
2462
2463 static always_inline void gen_addr_register (TCGv EA,
2464 DisasContext *ctx)
2465 {
2466 if (rA(ctx->opcode) == 0)
2467 tcg_gen_movi_tl(EA, 0);
2468 else
2469 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2470 }
2471
2472 #if defined(TARGET_PPC64)
2473 #define _GEN_MEM_FUNCS(name, mode) \
2474 &gen_op_##name##_##mode, \
2475 &gen_op_##name##_le_##mode, \
2476 &gen_op_##name##_64_##mode, \
2477 &gen_op_##name##_le_64_##mode
2478 #else
2479 #define _GEN_MEM_FUNCS(name, mode) \
2480 &gen_op_##name##_##mode, \
2481 &gen_op_##name##_le_##mode
2482 #endif
2483 #if defined(CONFIG_USER_ONLY)
2484 #if defined(TARGET_PPC64)
2485 #define NB_MEM_FUNCS 4
2486 #else
2487 #define NB_MEM_FUNCS 2
2488 #endif
2489 #define GEN_MEM_FUNCS(name) \
2490 _GEN_MEM_FUNCS(name, raw)
2491 #else
2492 #if defined(TARGET_PPC64)
2493 #define NB_MEM_FUNCS 12
2494 #else
2495 #define NB_MEM_FUNCS 6
2496 #endif
2497 #define GEN_MEM_FUNCS(name) \
2498 _GEN_MEM_FUNCS(name, user), \
2499 _GEN_MEM_FUNCS(name, kernel), \
2500 _GEN_MEM_FUNCS(name, hypv)
2501 #endif
2502
2503 /*** Integer load ***/
2504 #if defined(TARGET_PPC64)
2505 #define GEN_QEMU_LD_PPC64(width) \
2506 static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2507 { \
2508 if (likely(flags & 2)) \
2509 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2510 else { \
2511 TCGv addr = tcg_temp_new(); \
2512 tcg_gen_ext32u_tl(addr, t1); \
2513 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2514 tcg_temp_free(addr); \
2515 } \
2516 }
2517 GEN_QEMU_LD_PPC64(8u)
2518 GEN_QEMU_LD_PPC64(8s)
2519 GEN_QEMU_LD_PPC64(16u)
2520 GEN_QEMU_LD_PPC64(16s)
2521 GEN_QEMU_LD_PPC64(32u)
2522 GEN_QEMU_LD_PPC64(32s)
2523 GEN_QEMU_LD_PPC64(64)
2524
2525 #define GEN_QEMU_ST_PPC64(width) \
2526 static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2527 { \
2528 if (likely(flags & 2)) \
2529 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2530 else { \
2531 TCGv addr = tcg_temp_new(); \
2532 tcg_gen_ext32u_tl(addr, t1); \
2533 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2534 tcg_temp_free(addr); \
2535 } \
2536 }
2537 GEN_QEMU_ST_PPC64(8)
2538 GEN_QEMU_ST_PPC64(16)
2539 GEN_QEMU_ST_PPC64(32)
2540 GEN_QEMU_ST_PPC64(64)
2541
2542 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2543 {
2544 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
2545 }
2546
2547 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2548 {
2549 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
2550 }
2551
2552 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2553 {
2554 if (unlikely(flags & 1)) {
2555 TCGv_i32 t0;
2556 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2557 t0 = tcg_temp_new_i32();
2558 tcg_gen_trunc_tl_i32(t0, arg0);
2559 tcg_gen_bswap16_i32(t0, t0);
2560 tcg_gen_extu_i32_tl(arg0, t0);
2561 tcg_temp_free_i32(t0);
2562 } else
2563 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2564 }
2565
2566 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2567 {
2568 if (unlikely(flags & 1)) {
2569 TCGv_i32 t0;
2570 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2571 t0 = tcg_temp_new_i32();
2572 tcg_gen_trunc_tl_i32(t0, arg0);
2573 tcg_gen_bswap16_i32(t0, t0);
2574 tcg_gen_extu_i32_tl(arg0, t0);
2575 tcg_gen_ext16s_tl(arg0, arg0);
2576 tcg_temp_free_i32(t0);
2577 } else
2578 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
2579 }
2580
2581 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2582 {
2583 if (unlikely(flags & 1)) {
2584 TCGv_i32 t0;
2585 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2586 t0 = tcg_temp_new_i32();
2587 tcg_gen_trunc_tl_i32(t0, arg0);
2588 tcg_gen_bswap_i32(t0, t0);
2589 tcg_gen_extu_i32_tl(arg0, t0);
2590 tcg_temp_free_i32(t0);
2591 } else
2592 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2593 }
2594
2595 static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
2596 {
2597 if (unlikely(flags & 1)) {
2598 TCGv_i32 t0;
2599 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2600 t0 = tcg_temp_new_i32();
2601 tcg_gen_trunc_tl_i32(t0, arg0);
2602 tcg_gen_bswap_i32(t0, t0);
2603 tcg_gen_ext_i32_tl(arg0, t0);
2604 tcg_temp_free_i32(t0);
2605 } else
2606 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
2607 }
2608
2609 static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2610 {
2611 gen_qemu_ld64_ppc64(arg0, arg1, flags);
2612 if (unlikely(flags & 1))
2613 tcg_gen_bswap_i64(arg0, arg0);
2614 }
2615
2616 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2617 {
2618 gen_qemu_st8_ppc64(arg0, arg1, flags);
2619 }
2620
2621 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2622 {
2623 if (unlikely(flags & 1)) {
2624 TCGv_i32 t0;
2625 TCGv_i64 t1;
2626 t0 = tcg_temp_new_i32();
2627 tcg_gen_trunc_tl_i32(t0, arg0);
2628 tcg_gen_ext16u_i32(t0, t0);
2629 tcg_gen_bswap16_i32(t0, t0);
2630 t1 = tcg_temp_new_i64();
2631 tcg_gen_extu_i32_tl(t1, t0);
2632 tcg_temp_free_i32(t0);
2633 gen_qemu_st16_ppc64(t1, arg1, flags);
2634 tcg_temp_free_i64(t1);
2635 } else
2636 gen_qemu_st16_ppc64(arg0, arg1, flags);
2637 }
2638
2639 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2640 {
2641 if (unlikely(flags & 1)) {
2642 TCGv_i32 t0;
2643 TCGv_i64 t1;
2644 t0 = tcg_temp_new_i32();
2645 tcg_gen_trunc_tl_i32(t0, arg0);
2646 tcg_gen_bswap_i32(t0, t0);
2647 t1 = tcg_temp_new_i64();
2648 tcg_gen_extu_i32_tl(t1, t0);
2649 tcg_temp_free_i32(t0);
2650 gen_qemu_st32_ppc64(t1, arg1, flags);
2651 tcg_temp_free_i64(t1);
2652 } else
2653 gen_qemu_st32_ppc64(arg0, arg1, flags);
2654 }
2655
2656 static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2657 {
2658 if (unlikely(flags & 1)) {
2659 TCGv_i64 t0 = tcg_temp_new_i64();
2660 tcg_gen_bswap_i64(t0, arg0);
2661 gen_qemu_st64_ppc64(t0, arg1, flags);
2662 tcg_temp_free_i64(t0);
2663 } else
2664 gen_qemu_st64_ppc64(arg0, arg1, flags);
2665 }
2666
2667
2668 #else /* defined(TARGET_PPC64) */
2669 #define GEN_QEMU_LD_PPC32(width) \
2670 static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2671 { \
2672 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
2673 }
2674 GEN_QEMU_LD_PPC32(8u)
2675 GEN_QEMU_LD_PPC32(8s)
2676 GEN_QEMU_LD_PPC32(16u)
2677 GEN_QEMU_LD_PPC32(16s)
2678 GEN_QEMU_LD_PPC32(32u)
2679 GEN_QEMU_LD_PPC32(32s)
2680 static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2681 {
2682 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2683 }
2684
2685 #define GEN_QEMU_ST_PPC32(width) \
2686 static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2687 { \
2688 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
2689 }
2690 GEN_QEMU_ST_PPC32(8)
2691 GEN_QEMU_ST_PPC32(16)
2692 GEN_QEMU_ST_PPC32(32)
2693 static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2694 {
2695 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2696 }
2697
2698 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2699 {
2700 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
2701 }
2702
2703 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2704 {
2705 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
2706 }
2707
2708 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2709 {
2710 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
2711 if (unlikely(flags & 1))
2712 tcg_gen_bswap16_i32(arg0, arg0);
2713 }
2714
2715 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2716 {
2717 if (unlikely(flags & 1)) {
2718 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2719 tcg_gen_bswap16_i32(arg0, arg0);
2720 tcg_gen_ext16s_i32(arg0, arg0);
2721 } else
2722 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
2723 }
2724
2725 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2726 {
2727 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
2728 if (unlikely(flags & 1))
2729 tcg_gen_bswap_i32(arg0, arg0);
2730 }
2731
2732 static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2733 {
2734 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2735 if (unlikely(flags & 1))
2736 tcg_gen_bswap_i64(arg0, arg0);
2737 }
2738
2739 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2740 {
2741 gen_qemu_st8_ppc32(arg0, arg1, flags);
2742 }
2743
2744 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2745 {
2746 if (unlikely(flags & 1)) {
2747 TCGv_i32 temp = tcg_temp_new_i32();
2748 tcg_gen_ext16u_i32(temp, arg0);
2749 tcg_gen_bswap16_i32(temp, temp);
2750 gen_qemu_st16_ppc32(temp, arg1, flags);
2751 tcg_temp_free_i32(temp);
2752 } else
2753 gen_qemu_st16_ppc32(arg0, arg1, flags);
2754 }
2755
2756 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2757 {
2758 if (unlikely(flags & 1)) {
2759 TCGv_i32 temp = tcg_temp_new_i32();
2760 tcg_gen_bswap_i32(temp, arg0);
2761 gen_qemu_st32_ppc32(temp, arg1, flags);
2762 tcg_temp_free_i32(temp);
2763 } else
2764 gen_qemu_st32_ppc32(arg0, arg1, flags);
2765 }
2766
2767 static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2768 {
2769 if (unlikely(flags & 1)) {
2770 TCGv_i64 temp = tcg_temp_new_i64();
2771 tcg_gen_bswap_i64(temp, arg0);
2772 gen_qemu_st64_ppc32(temp, arg1, flags);
2773 tcg_temp_free_i64(temp);
2774 } else
2775 gen_qemu_st64_ppc32(arg0, arg1, flags);
2776 }
2777 #endif
2778
2779 #define GEN_LD(name, ldop, opc, type) \
2780 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2781 { \
2782 TCGv EA = tcg_temp_new(); \
2783 gen_set_access_type(ACCESS_INT); \
2784 gen_addr_imm_index(EA, ctx, 0); \
2785 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2786 tcg_temp_free(EA); \
2787 }
2788
2789 #define GEN_LDU(name, ldop, opc, type) \
2790 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2791 { \
2792 TCGv EA; \
2793 if (unlikely(rA(ctx->opcode) == 0 || \
2794 rA(ctx->opcode) == rD(ctx->opcode))) { \
2795 GEN_EXCP_INVAL(ctx); \
2796 return; \
2797 } \
2798 EA = tcg_temp_new(); \
2799 gen_set_access_type(ACCESS_INT); \
2800 if (type == PPC_64B) \
2801 gen_addr_imm_index(EA, ctx, 0x03); \
2802 else \
2803 gen_addr_imm_index(EA, ctx, 0); \
2804 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2806 tcg_temp_free(EA); \
2807 }
2808
2809 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2810 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2811 { \
2812 TCGv EA; \
2813 if (unlikely(rA(ctx->opcode) == 0 || \
2814 rA(ctx->opcode) == rD(ctx->opcode))) { \
2815 GEN_EXCP_INVAL(ctx); \
2816 return; \
2817 } \
2818 EA = tcg_temp_new(); \
2819 gen_set_access_type(ACCESS_INT); \
2820 gen_addr_reg_index(EA, ctx); \
2821 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2822 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2823 tcg_temp_free(EA); \
2824 }
2825
2826 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2827 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2828 { \
2829 TCGv EA = tcg_temp_new(); \
2830 gen_set_access_type(ACCESS_INT); \
2831 gen_addr_reg_index(EA, ctx); \
2832 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2833 tcg_temp_free(EA); \
2834 }
2835
2836 #define GEN_LDS(name, ldop, op, type) \
2837 GEN_LD(name, ldop, op | 0x20, type); \
2838 GEN_LDU(name, ldop, op | 0x21, type); \
2839 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2840 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2841
2842 /* lbz lbzu lbzux lbzx */
2843 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2844 /* lha lhau lhaux lhax */
2845 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2846 /* lhz lhzu lhzux lhzx */
2847 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2848 /* lwz lwzu lwzux lwzx */
2849 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2850 #if defined(TARGET_PPC64)
2851 /* lwaux */
2852 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2853 /* lwax */
2854 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2855 /* ldux */
2856 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2857 /* ldx */
2858 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2859 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2860 {
2861 TCGv EA;
2862 if (Rc(ctx->opcode)) {
2863 if (unlikely(rA(ctx->opcode) == 0 ||
2864 rA(ctx->opcode) == rD(ctx->opcode))) {
2865 GEN_EXCP_INVAL(ctx);
2866 return;
2867 }
2868 }
2869 EA = tcg_temp_new();
2870 gen_set_access_type(ACCESS_INT);
2871 gen_addr_imm_index(EA, ctx, 0x03);
2872 if (ctx->opcode & 0x02) {
2873 /* lwa (lwau is undefined) */
2874 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2875 } else {
2876 /* ld - ldu */
2877 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2878 }
2879 if (Rc(ctx->opcode))
2880 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2881 tcg_temp_free(EA);
2882 }
2883 /* lq */
2884 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2885 {
2886 #if defined(CONFIG_USER_ONLY)
2887 GEN_EXCP_PRIVOPC(ctx);
2888 #else
2889 int ra, rd;
2890 TCGv EA;
2891
2892 /* Restore CPU state */
2893 if (unlikely(ctx->supervisor == 0)) {
2894 GEN_EXCP_PRIVOPC(ctx);
2895 return;
2896 }
2897 ra = rA(ctx->opcode);
2898 rd = rD(ctx->opcode);
2899 if (unlikely((rd & 1) || rd == ra)) {
2900 GEN_EXCP_INVAL(ctx);
2901 return;
2902 }
2903 if (unlikely(ctx->mem_idx & 1)) {
2904 /* Little-endian mode is not handled */
2905 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2906 return;
2907 }
2908 EA = tcg_temp_new();
2909 gen_set_access_type(ACCESS_INT);
2910 gen_addr_imm_index(EA, ctx, 0x0F);
2911 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2912 tcg_gen_addi_tl(EA, EA, 8);
2913 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2914 tcg_temp_free(EA);
2915 #endif
2916 }
2917 #endif
2918
2919 /*** Integer store ***/
2920 #define GEN_ST(name, stop, opc, type) \
2921 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2922 { \
2923 TCGv EA = tcg_temp_new(); \
2924 gen_set_access_type(ACCESS_INT); \
2925 gen_addr_imm_index(EA, ctx, 0); \
2926 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2927 tcg_temp_free(EA); \
2928 }
2929
2930 #define GEN_STU(name, stop, opc, type) \
2931 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2932 { \
2933 TCGv EA; \
2934 if (unlikely(rA(ctx->opcode) == 0)) { \
2935 GEN_EXCP_INVAL(ctx); \
2936 return; \
2937 } \
2938 EA = tcg_temp_new(); \
2939 gen_set_access_type(ACCESS_INT); \
2940 if (type == PPC_64B) \
2941 gen_addr_imm_index(EA, ctx, 0x03); \
2942 else \
2943 gen_addr_imm_index(EA, ctx, 0); \
2944 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2945 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2946 tcg_temp_free(EA); \
2947 }
2948
2949 #define GEN_STUX(name, stop, opc2, opc3, type) \
2950 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2951 { \
2952 TCGv EA; \
2953 if (unlikely(rA(ctx->opcode) == 0)) { \
2954 GEN_EXCP_INVAL(ctx); \
2955 return; \
2956 } \
2957 EA = tcg_temp_new(); \
2958 gen_set_access_type(ACCESS_INT); \
2959 gen_addr_reg_index(EA, ctx); \
2960 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2961 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2962 tcg_temp_free(EA); \
2963 }
2964
2965 #define GEN_STX(name, stop, opc2, opc3, type) \
2966 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2967 { \
2968 TCGv EA = tcg_temp_new(); \
2969 gen_set_access_type(ACCESS_INT); \
2970 gen_addr_reg_index(EA, ctx); \
2971 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2972 tcg_temp_free(EA); \
2973 }
2974
2975 #define GEN_STS(name, stop, op, type) \
2976 GEN_ST(name, stop, op | 0x20, type); \
2977 GEN_STU(name, stop, op | 0x21, type); \
2978 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2979 GEN_STX(name, stop, 0x17, op | 0x00, type)
2980
2981 /* stb stbu stbux stbx */
2982 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2983 /* sth sthu sthux sthx */
2984 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2985 /* stw stwu stwux stwx */
2986 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2987 #if defined(TARGET_PPC64)
2988 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2989 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2990 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2991 {
2992 int rs;
2993 TCGv EA;
2994
2995 rs = rS(ctx->opcode);
2996 if ((ctx->opcode & 0x3) == 0x2) {
2997 #if defined(CONFIG_USER_ONLY)
2998 GEN_EXCP_PRIVOPC(ctx);
2999 #else
3000 /* stq */
3001 if (unlikely(ctx->supervisor == 0)) {
3002 GEN_EXCP_PRIVOPC(ctx);
3003 return;
3004 }
3005 if (unlikely(rs & 1)) {
3006 GEN_EXCP_INVAL(ctx);
3007 return;
3008 }
3009 if (unlikely(ctx->mem_idx & 1)) {
3010 /* Little-endian mode is not handled */
3011 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3012 return;
3013 }
3014 EA = tcg_temp_new();
3015 gen_set_access_type(ACCESS_INT);
3016 gen_addr_imm_index(EA, ctx, 0x03);
3017 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3018 tcg_gen_addi_tl(EA, EA, 8);
3019 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3020 tcg_temp_free(EA);
3021 #endif
3022 } else {
3023 /* std / stdu */
3024 if (Rc(ctx->opcode)) {
3025 if (unlikely(rA(ctx->opcode) == 0)) {
3026 GEN_EXCP_INVAL(ctx);
3027 return;
3028 }
3029 }
3030 EA = tcg_temp_new();
3031 gen_set_access_type(ACCESS_INT);
3032 gen_addr_imm_index(EA, ctx, 0x03);
3033 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3034 if (Rc(ctx->opcode))
3035 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3036 tcg_temp_free(EA);
3037 }
3038 }
3039 #endif
3040 /*** Integer load and store with byte reverse ***/
3041 /* lhbrx */
3042 void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3043 {
3044 TCGv_i32 temp = tcg_temp_new_i32();
3045 gen_qemu_ld16u(t0, t1, flags);
3046 tcg_gen_trunc_tl_i32(temp, t0);
3047 tcg_gen_bswap16_i32(temp, temp);
3048 tcg_gen_extu_i32_tl(t0, temp);
3049 tcg_temp_free_i32(temp);
3050 }
3051 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3052
3053 /* lwbrx */
3054 void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3055 {
3056 TCGv_i32 temp = tcg_temp_new_i32();
3057 gen_qemu_ld32u(t0, t1, flags);
3058 tcg_gen_trunc_tl_i32(temp, t0);
3059 tcg_gen_bswap_i32(temp, temp);
3060 tcg_gen_extu_i32_tl(t0, temp);
3061 tcg_temp_free_i32(temp);
3062 }
3063 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3064
3065 /* sthbrx */
3066 void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3067 {
3068 TCGv_i32 temp = tcg_temp_new_i32();
3069 TCGv t2 = tcg_temp_new();
3070 tcg_gen_trunc_tl_i32(temp, t0);
3071 tcg_gen_ext16u_i32(temp, temp);
3072 tcg_gen_bswap16_i32(temp, temp);
3073 tcg_gen_extu_i32_tl(t2, temp);
3074 tcg_temp_free_i32(temp);
3075 gen_qemu_st16(t2, t1, flags);
3076 tcg_temp_free(t2);
3077 }
3078 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3079
3080 /* stwbrx */
3081 void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3082 {
3083 TCGv_i32 temp = tcg_temp_new_i32();
3084 TCGv t2 = tcg_temp_new();
3085 tcg_gen_trunc_tl_i32(temp, t0);
3086 tcg_gen_bswap_i32(temp, temp);
3087 tcg_gen_extu_i32_tl(t2, temp);
3088 tcg_temp_free_i32(temp);
3089 gen_qemu_st32(t2, t1, flags);
3090 tcg_temp_free(t2);
3091 }
3092 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3093
3094 /*** Integer load and store multiple ***/
3095 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
3096 static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
3097 GEN_MEM_FUNCS(lmw),
3098 };
3099 static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
3100 GEN_MEM_FUNCS(stmw),
3101 };
3102
3103 /* lmw */
3104 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3105 {
3106 /* NIP cannot be restored if the memory exception comes from an helper */
3107 gen_update_nip(ctx, ctx->nip - 4);
3108 gen_addr_imm_index(cpu_T[0], ctx, 0);
3109 op_ldstm(lmw, rD(ctx->opcode));
3110 }
3111
3112 /* stmw */
3113 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3114 {
3115 /* NIP cannot be restored if the memory exception comes from an helper */
3116 gen_update_nip(ctx, ctx->nip - 4);
3117 gen_addr_imm_index(cpu_T[0], ctx, 0);
3118 op_ldstm(stmw, rS(ctx->opcode));
3119 }
3120
3121 /*** Integer load and store strings ***/
3122 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3123 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
3124 /* string load & stores are by definition endian-safe */
3125 #define gen_op_lswi_le_raw gen_op_lswi_raw
3126 #define gen_op_lswi_le_user gen_op_lswi_user
3127 #define gen_op_lswi_le_kernel gen_op_lswi_kernel
3128 #define gen_op_lswi_le_hypv gen_op_lswi_hypv
3129 #define gen_op_lswi_le_64_raw gen_op_lswi_raw
3130 #define gen_op_lswi_le_64_user gen_op_lswi_user
3131 #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3132 #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
3133 static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3134 GEN_MEM_FUNCS(lswi),
3135 };
3136 #define gen_op_lswx_le_raw gen_op_lswx_raw
3137 #define gen_op_lswx_le_user gen_op_lswx_user
3138 #define gen_op_lswx_le_kernel gen_op_lswx_kernel
3139 #define gen_op_lswx_le_hypv gen_op_lswx_hypv
3140 #define gen_op_lswx_le_64_raw gen_op_lswx_raw
3141 #define gen_op_lswx_le_64_user gen_op_lswx_user
3142 #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3143 #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
3144 static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3145 GEN_MEM_FUNCS(lswx),
3146 };
3147 #define gen_op_stsw_le_raw gen_op_stsw_raw
3148 #define gen_op_stsw_le_user gen_op_stsw_user
3149 #define gen_op_stsw_le_kernel gen_op_stsw_kernel
3150 #define gen_op_stsw_le_hypv gen_op_stsw_hypv
3151 #define gen_op_stsw_le_64_raw gen_op_stsw_raw
3152 #define gen_op_stsw_le_64_user gen_op_stsw_user
3153 #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3154 #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
3155 static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3156 GEN_MEM_FUNCS(stsw),
3157 };
3158
3159 /* lswi */
3160 /* PowerPC32 specification says we must generate an exception if
3161 * rA is in the range of registers to be loaded.
3162 * In an other hand, IBM says this is valid, but rA won't be loaded.
3163 * For now, I'll follow the spec...
3164 */
3165 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3166 {
3167 int nb = NB(ctx->opcode);
3168 int start = rD(ctx->opcode);
3169 int ra = rA(ctx->opcode);
3170 int nr;
3171
3172 if (nb == 0)
3173 nb = 32;
3174 nr = nb / 4;
3175 if (unlikely(((start + nr) > 32 &&
3176 start <= ra && (start + nr - 32) > ra) ||
3177 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3178 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3179 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
3180 return;
3181 }
3182 /* NIP cannot be restored if the memory exception comes from an helper */
3183 gen_update_nip(ctx, ctx->nip - 4);
3184 gen_addr_register(cpu_T[0], ctx);
3185 tcg_gen_movi_tl(cpu_T[1], nb);
3186 op_ldsts(lswi, start);
3187 }
3188
3189 /* lswx */
3190 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3191 {
3192 int ra = rA(ctx->opcode);
3193 int rb = rB(ctx->opcode);
3194
3195 /* NIP cannot be restored if the memory exception comes from an helper */
3196 gen_update_nip(ctx, ctx->nip - 4);
3197 gen_addr_reg_index(cpu_T[0], ctx);
3198 if (ra == 0) {
3199 ra = rb;
3200 }
3201 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
3202 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
3203 }
3204
3205 /* stswi */
3206 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3207 {
3208 int nb = NB(ctx->opcode);
3209
3210 /* NIP cannot be restored if the memory exception comes from an helper */
3211 gen_update_nip(ctx, ctx->nip - 4);
3212 gen_addr_register(cpu_T[0], ctx);
3213 if (nb == 0)
3214 nb = 32;
3215 tcg_gen_movi_tl(cpu_T[1], nb);
3216 op_ldsts(stsw, rS(ctx->opcode));
3217 }
3218
3219 /* stswx */
3220 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3221 {
3222 /* NIP cannot be restored if the memory exception comes from an helper */
3223 gen_update_nip(ctx, ctx->nip - 4);
3224 gen_addr_reg_index(cpu_T[0], ctx);
3225 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
3226 op_ldsts(stsw, rS(ctx->opcode));
3227 }
3228
3229 /*** Memory synchronisation ***/
3230 /* eieio */
3231 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3232 {
3233 }
3234
3235 /* isync */
3236 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3237 {
3238 GEN_STOP(ctx);
3239 }
3240
3241 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3242 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
3243 static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3244 GEN_MEM_FUNCS(lwarx),
3245 };
3246 static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3247 GEN_MEM_FUNCS(stwcx),
3248 };
3249
3250 /* lwarx */
3251 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3252 {
3253 /* NIP cannot be restored if the memory exception comes from an helper */
3254 gen_update_nip(ctx, ctx->nip - 4);
3255 gen_set_access_type(ACCESS_RES);
3256 gen_addr_reg_index(cpu_T[0], ctx);
3257 op_lwarx();
3258 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
3259 }
3260
3261 /* stwcx. */
3262 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3263 {
3264 /* NIP cannot be restored if the memory exception comes from an helper */
3265 gen_update_nip(ctx, ctx->nip - 4);
3266 gen_set_access_type(ACCESS_RES);
3267 gen_addr_reg_index(cpu_T[0], ctx);
3268 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3269 op_stwcx();
3270 }
3271
3272 #if defined(TARGET_PPC64)
3273 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3274 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
3275 static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3276 GEN_MEM_FUNCS(ldarx),
3277 };
3278 static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3279 GEN_MEM_FUNCS(stdcx),
3280 };
3281
3282 /* ldarx */
3283 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3284 {
3285 /* NIP cannot be restored if the memory exception comes from an helper */
3286 gen_update_nip(ctx, ctx->nip - 4);
3287 gen_set_access_type(ACCESS_RES);
3288 gen_addr_reg_index(cpu_T[0], ctx);
3289 op_ldarx();
3290 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
3291 }
3292
3293 /* stdcx. */
3294 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3295 {
3296 /* NIP cannot be restored if the memory exception comes from an helper */
3297 gen_update_nip(ctx, ctx->nip - 4);
3298 gen_set_access_type(ACCESS_RES);
3299 gen_addr_reg_index(cpu_T[0], ctx);
3300 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3301 op_stdcx();
3302 }
3303 #endif /* defined(TARGET_PPC64) */
3304
3305 /* sync */
3306 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3307 {
3308 }
3309
3310 /* wait */
3311 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3312 {
3313 /* Stop translation, as the CPU is supposed to sleep from now */
3314 gen_op_wait();
3315 GEN_EXCP(ctx, EXCP_HLT, 1);
3316 }
3317
3318 /*** Floating-point load ***/
3319 #define GEN_LDF(name, ldop, opc, type) \
3320 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3321 { \
3322 TCGv EA; \
3323 if (unlikely(!ctx->fpu_enabled)) { \
3324 GEN_EXCP_NO_FP(ctx); \
3325 return; \
3326 } \
3327 gen_set_access_type(ACCESS_FLOAT); \
3328 EA = tcg_temp_new(); \
3329 gen_addr_imm_index(EA, ctx, 0); \
3330 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3331 tcg_temp_free(EA); \
3332 }
3333
3334 #define GEN_LDUF(name, ldop, opc, type) \
3335 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3336 { \
3337 TCGv EA; \
3338 if (unlikely(!ctx->fpu_enabled)) { \
3339 GEN_EXCP_NO_FP(ctx); \
3340 return; \
3341 } \
3342 if (unlikely(rA(ctx->opcode) == 0)) { \
3343 GEN_EXCP_INVAL(ctx); \
3344 return; \
3345 } \
3346 gen_set_access_type(ACCESS_FLOAT); \
3347 EA = tcg_temp_new(); \
3348 gen_addr_imm_index(EA, ctx, 0); \
3349 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3350 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3351 tcg_temp_free(EA); \
3352 }
3353
3354 #define GEN_LDUXF(name, ldop, opc, type) \
3355 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3356 { \
3357 TCGv EA; \
3358 if (unlikely(!ctx->fpu_enabled)) { \
3359 GEN_EXCP_NO_FP(ctx); \
3360 return; \
3361 } \
3362 if (unlikely(rA(ctx->opcode) == 0)) { \
3363 GEN_EXCP_INVAL(ctx); \
3364 return; \
3365 } \
3366 gen_set_access_type(ACCESS_FLOAT); \
3367 EA = tcg_temp_new(); \
3368 gen_addr_reg_index(EA, ctx); \
3369 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3370 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3372 }
3373
3374 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3375 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3376 { \
3377 TCGv EA; \
3378 if (unlikely(!ctx->fpu_enabled)) { \
3379 GEN_EXCP_NO_FP(ctx); \
3380 return; \
3381 } \
3382 gen_set_access_type(ACCESS_FLOAT); \
3383 EA = tcg_temp_new(); \
3384 gen_addr_reg_index(EA, ctx); \
3385 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3386 tcg_temp_free(EA); \
3387 }
3388
3389 #define GEN_LDFS(name, ldop, op, type) \
3390 GEN_LDF(name, ldop, op | 0x20, type); \
3391 GEN_LDUF(name, ldop, op | 0x21, type); \
3392 GEN_LDUXF(name, ldop, op | 0x01, type); \
3393 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3394
3395 static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3396 {
3397 TCGv t0 = tcg_temp_new();
3398 TCGv_i32 t1 = tcg_temp_new_i32();
3399 gen_qemu_ld32u(t0, arg2, flags);
3400 tcg_gen_trunc_tl_i32(t1, t0);
3401 tcg_temp_free(t0);
3402 gen_helper_float32_to_float64(arg1, t1);
3403 tcg_temp_free_i32(t1);
3404 }
3405
3406 /* lfd lfdu lfdux lfdx */
3407 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3408 /* lfs lfsu lfsux lfsx */
3409 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3410
3411 /*** Floating-point store ***/
3412 #define GEN_STF(name, stop, opc, type) \
3413 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3414 { \
3415 TCGv EA; \
3416 if (unlikely(!ctx->fpu_enabled)) { \
3417 GEN_EXCP_NO_FP(ctx); \
3418 return; \
3419 } \
3420 gen_set_access_type(ACCESS_FLOAT); \
3421 EA = tcg_temp_new(); \
3422 gen_addr_imm_index(EA, ctx, 0); \
3423 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3424 tcg_temp_free(EA); \
3425 }
3426
3427 #define GEN_STUF(name, stop, opc, type) \
3428 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3429 { \
3430 TCGv EA; \
3431 if (unlikely(!ctx->fpu_enabled)) { \
3432 GEN_EXCP_NO_FP(ctx); \
3433 return; \
3434 } \
3435 if (unlikely(rA(ctx->opcode) == 0)) { \
3436 GEN_EXCP_INVAL(ctx); \
3437 return; \
3438 } \
3439 gen_set_access_type(ACCESS_FLOAT); \
3440 EA = tcg_temp_new(); \
3441 gen_addr_imm_index(EA, ctx, 0); \
3442 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3443 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3444 tcg_temp_free(EA); \
3445 }
3446
3447 #define GEN_STUXF(name, stop, opc, type) \
3448 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3449 { \
3450 TCGv EA; \
3451 if (unlikely(!ctx->fpu_enabled)) { \
3452 GEN_EXCP_NO_FP(ctx); \
3453 return; \
3454 } \
3455 if (unlikely(rA(ctx->opcode) == 0)) { \
3456 GEN_EXCP_INVAL(ctx); \
3457 return; \
3458 } \
3459 gen_set_access_type(ACCESS_FLOAT); \
3460 EA = tcg_temp_new(); \
3461 gen_addr_reg_index(EA, ctx); \
3462 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3463 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3464 tcg_temp_free(EA); \
3465 }
3466
3467 #define GEN_STXF(name, stop, opc2, opc3, type) \
3468 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3469 { \
3470 TCGv EA; \
3471 if (unlikely(!ctx->fpu_enabled)) { \
3472 GEN_EXCP_NO_FP(ctx); \
3473 return; \
3474 } \
3475 gen_set_access_type(ACCESS_FLOAT); \
3476 EA = tcg_temp_new(); \
3477 gen_addr_reg_index(EA, ctx); \
3478 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3479 tcg_temp_free(EA); \
3480 }
3481
3482 #define GEN_STFS(name, stop, op, type) \
3483 GEN_STF(name, stop, op | 0x20, type); \
3484 GEN_STUF(name, stop, op | 0x21, type); \
3485 GEN_STUXF(name, stop, op | 0x01, type); \
3486 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3487
3488 static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3489 {
3490 TCGv_i32 t0 = tcg_temp_new_i32();
3491 TCGv t1 = tcg_temp_new();
3492 gen_helper_float64_to_float32(t0, arg1);
3493 tcg_gen_extu_i32_tl(t1, t0);
3494 tcg_temp_free_i32(t0);
3495 gen_qemu_st32(t1, arg2, flags);
3496 tcg_temp_free(t1);
3497 }
3498
3499 /* stfd stfdu stfdux stfdx */
3500 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3501 /* stfs stfsu stfsux stfsx */
3502 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3503
3504 /* Optional: */
3505 static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3506 {
3507 TCGv t0 = tcg_temp_new();
3508 tcg_gen_trunc_i64_tl(t0, arg1),
3509 gen_qemu_st32(t0, arg2, flags);
3510 tcg_temp_free(t0);
3511 }
3512 /* stfiwx */
3513 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3514
3515 /*** Branch ***/
3516 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3517 target_ulong dest)
3518 {
3519 TranslationBlock *tb;
3520 tb = ctx->tb;
3521 #if defined(TARGET_PPC64)
3522 if (!ctx->sf_mode)
3523 dest = (uint32_t) dest;
3524 #endif
3525 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3526 likely(!ctx->singlestep_enabled)) {
3527 tcg_gen_goto_tb(n);
3528 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3529 tcg_gen_exit_tb((long)tb + n);
3530 } else {
3531 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3532 if (unlikely(ctx->singlestep_enabled)) {
3533 if ((ctx->singlestep_enabled &
3534 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3535 ctx->exception == POWERPC_EXCP_BRANCH) {
3536 target_ulong tmp = ctx->nip;
3537 ctx->nip = dest;
3538 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3539 ctx->nip = tmp;
3540 }
3541 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3542 gen_update_nip(ctx, dest);
3543 gen_helper_raise_debug();
3544 }
3545 }
3546 tcg_gen_exit_tb(0);
3547 }
3548 }
3549
3550 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3551 {
3552 #if defined(TARGET_PPC64)
3553 if (ctx->sf_mode == 0)
3554 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3555 else
3556 #endif
3557 tcg_gen_movi_tl(cpu_lr, nip);
3558 }
3559
3560 /* b ba bl bla */
3561 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3562 {
3563 target_ulong li, target;
3564
3565 ctx->exception = POWERPC_EXCP_BRANCH;
3566 /* sign extend LI */
3567 #if defined(TARGET_PPC64)
3568 if (ctx->sf_mode)
3569 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3570 else
3571 #endif
3572 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3573 if (likely(AA(ctx->opcode) == 0))
3574 target = ctx->nip + li - 4;
3575 else
3576 target = li;
3577 if (LK(ctx->opcode))
3578 gen_setlr(ctx, ctx->nip);
3579 gen_goto_tb(ctx, 0, target);
3580 }
3581
3582 #define BCOND_IM 0
3583 #define BCOND_LR 1
3584 #define BCOND_CTR 2
3585
3586 static always_inline void gen_bcond (DisasContext *ctx, int type)
3587 {
3588 uint32_t bo = BO(ctx->opcode);
3589 int l1 = gen_new_label();
3590 TCGv target;
3591
3592 ctx->exception = POWERPC_EXCP_BRANCH;
3593 if (type == BCOND_LR || type == BCOND_CTR) {
3594 target = tcg_temp_local_new();
3595 if (type == BCOND_CTR)
3596 tcg_gen_mov_tl(target, cpu_ctr);
3597 else
3598 tcg_gen_mov_tl(target, cpu_lr);
3599 }
3600 if (LK(ctx->opcode))
3601 gen_setlr(ctx, ctx->nip);
3602 l1 = gen_new_label();
3603 if ((bo & 0x4) == 0) {
3604 /* Decrement and test CTR */
3605 TCGv temp = tcg_temp_new();
3606 if (unlikely(type == BCOND_CTR)) {
3607 GEN_EXCP_INVAL(ctx);
3608 return;
3609 }
3610 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3611 #if defined(TARGET_PPC64)
3612 if (!ctx->sf_mode)
3613 tcg_gen_ext32u_tl(temp, cpu_ctr);
3614 else
3615 #endif
3616 tcg_gen_mov_tl(temp, cpu_ctr);
3617 if (bo & 0x2) {
3618 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3619 } else {
3620 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3621 }
3622 tcg_temp_free(temp);
3623 }
3624 if ((bo & 0x10) == 0) {
3625 /* Test CR */
3626 uint32_t bi = BI(ctx->opcode);
3627 uint32_t mask = 1 << (3 - (bi & 0x03));
3628 TCGv_i32 temp = tcg_temp_new_i32();
3629
3630 if (bo & 0x8) {
3631 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3632 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3633 } else {
3634 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3635 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3636 }
3637 tcg_temp_free_i32(temp);
3638 }
3639 if (type == BCOND_IM) {
3640 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3641 if (likely(AA(ctx->opcode) == 0)) {
3642 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3643 } else {
3644 gen_goto_tb(ctx, 0, li);
3645 }
3646 gen_set_label(l1);
3647 gen_goto_tb(ctx, 1, ctx->nip);
3648 } else {
3649 #if defined(TARGET_PPC64)
3650 if (!(ctx->sf_mode))
3651 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3652 else
3653 #endif
3654 tcg_gen_andi_tl(cpu_nip, target, ~3);
3655 tcg_gen_exit_tb(0);
3656 gen_set_label(l1);
3657 #if defined(TARGET_PPC64)
3658 if (!(ctx->sf_mode))
3659 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3660 else
3661 #endif
3662 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3663 tcg_gen_exit_tb(0);
3664 }
3665 }
3666
3667 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3668 {
3669 gen_bcond(ctx, BCOND_IM);
3670 }
3671
3672 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3673 {
3674 gen_bcond(ctx, BCOND_CTR);
3675 }
3676
3677 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3678 {
3679 gen_bcond(ctx, BCOND_LR);
3680 }
3681
3682 /*** Condition register logical ***/
3683 #define GEN_CRLOGIC(name, tcg_op, opc) \
3684 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3685 { \
3686 uint8_t bitmask; \
3687 int sh; \
3688 TCGv_i32 t0, t1; \
3689 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3690 t0 = tcg_temp_new_i32(); \
3691 if (sh > 0) \
3692 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3693 else if (sh < 0) \
3694 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3695 else \
3696 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3697 t1 = tcg_temp_new_i32(); \
3698 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3699 if (sh > 0) \
3700 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3701 else if (sh < 0) \
3702 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3703 else \
3704 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3705 tcg_op(t0, t0, t1); \
3706 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3707 tcg_gen_andi_i32(t0, t0, bitmask); \
3708 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3709 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3710 tcg_temp_free_i32(t0); \
3711 tcg_temp_free_i32(t1); \
3712 }
3713
3714 /* crand */
3715 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3716 /* crandc */
3717 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3718 /* creqv */
3719 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3720 /* crnand */
3721 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3722 /* crnor */
3723 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3724 /* cror */
3725 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3726 /* crorc */
3727 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3728 /* crxor */
3729 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3730 /* mcrf */
3731 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3732 {
3733 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3734 }
3735
3736 /*** System linkage ***/
3737 /* rfi (supervisor only) */
3738 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3739 {
3740 #if defined(CONFIG_USER_ONLY)
3741 GEN_EXCP_PRIVOPC(ctx);
3742 #else
3743 /* Restore CPU state */
3744 if (unlikely(!ctx->supervisor)) {
3745 GEN_EXCP_PRIVOPC(ctx);
3746 return;
3747 }
3748 gen_op_rfi();
3749 GEN_SYNC(ctx);
3750 #endif
3751 }
3752
3753 #if defined(TARGET_PPC64)
3754 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3755 {
3756 #if defined(CONFIG_USER_ONLY)
3757 GEN_EXCP_PRIVOPC(ctx);
3758 #else
3759 /* Restore CPU state */
3760 if (unlikely(!ctx->supervisor)) {
3761 GEN_EXCP_PRIVOPC(ctx);
3762 return;
3763 }
3764 gen_op_rfid();
3765 GEN_SYNC(ctx);
3766 #endif
3767 }
3768
3769 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3770 {
3771 #if defined(CONFIG_USER_ONLY)
3772 GEN_EXCP_PRIVOPC(ctx);
3773 #else
3774 /* Restore CPU state */
3775 if (unlikely(ctx->supervisor <= 1)) {
3776 GEN_EXCP_PRIVOPC(ctx);
3777 return;
3778 }
3779 gen_op_hrfid();
3780 GEN_SYNC(ctx);
3781 #endif
3782 }
3783 #endif
3784
3785 /* sc */
3786 #if defined(CONFIG_USER_ONLY)
3787 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3788 #else
3789 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3790 #endif
3791 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3792 {
3793 uint32_t lev;
3794
3795 lev = (ctx->opcode >> 5) & 0x7F;
3796 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3797 }
3798
3799 /*** Trap ***/
3800 /* tw */
3801 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3802 {
3803 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3804 /* Update the nip since this might generate a trap exception */
3805 gen_update_nip(ctx, ctx->nip);
3806 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3807 tcg_temp_free_i32(t0);
3808 }
3809
3810 /* twi */
3811 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3812 {
3813 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3814 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3815 /* Update the nip since this might generate a trap exception */
3816 gen_update_nip(ctx, ctx->nip);
3817 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3818 tcg_temp_free(t0);
3819 tcg_temp_free_i32(t1);
3820 }
3821
3822 #if defined(TARGET_PPC64)
3823 /* td */
3824 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3825 {
3826 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3827 /* Update the nip since this might generate a trap exception */
3828 gen_update_nip(ctx, ctx->nip);
3829 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3830 tcg_temp_free_i32(t0);
3831 }
3832
3833 /* tdi */
3834 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3835 {
3836 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3837 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3838 /* Update the nip since this might generate a trap exception */
3839 gen_update_nip(ctx, ctx->nip);
3840 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3841 tcg_temp_free(t0);
3842 tcg_temp_free_i32(t1);
3843 }
3844 #endif
3845
3846 /*** Processor control ***/
3847 /* mcrxr */
3848 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3849 {
3850 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3851 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3852 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3853 }
3854
3855 /* mfcr */
3856 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3857 {
3858 uint32_t crm, crn;
3859
3860 if (likely(ctx->opcode & 0x00100000)) {
3861 crm = CRM(ctx->opcode);
3862 if (likely((crm ^ (crm - 1)) == 0)) {
3863 crn = ffs(crm);
3864 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3865 }
3866 } else {
3867 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3868 }
3869 }
3870
3871 /* mfmsr */
3872 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3873 {
3874 #if defined(CONFIG_USER_ONLY)
3875 GEN_EXCP_PRIVREG(ctx);
3876 #else
3877 if (unlikely(!ctx->supervisor)) {
3878 GEN_EXCP_PRIVREG(ctx);
3879 return;
3880 }
3881 gen_op_load_msr();
3882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3883 #endif
3884 }
3885
3886 #if 1
3887 #define SPR_NOACCESS ((void *)(-1UL))
3888 #else
3889 static void spr_noaccess (void *opaque, int sprn)
3890 {
3891 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3892 printf("ERROR: try to access SPR %d !\n", sprn);
3893 }
3894 #define SPR_NOACCESS (&spr_noaccess)
3895 #endif
3896
3897 /* mfspr */
3898 static always_inline void gen_op_mfspr (DisasContext *ctx)
3899 {
3900 void (*read_cb)(void *opaque, int sprn);
3901 uint32_t sprn = SPR(ctx->opcode);
3902
3903 #if !defined(CONFIG_USER_ONLY)
3904 if (ctx->supervisor == 2)
3905 read_cb = ctx->spr_cb[sprn].hea_read;
3906 else if (ctx->supervisor)
3907 read_cb = ctx->spr_cb[sprn].oea_read;
3908 else
3909 #endif
3910 read_cb = ctx->spr_cb[sprn].uea_read;
3911 if (likely(read_cb != NULL)) {
3912 if (likely(read_cb != SPR_NOACCESS)) {
3913 (*read_cb)(ctx, sprn);
3914 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3915 } else {
3916 /* Privilege exception */
3917 /* This is a hack to avoid warnings when running Linux:
3918 * this OS breaks the PowerPC virtualisation model,
3919 * allowing userland application to read the PVR
3920 */
3921 if (sprn != SPR_PVR) {
3922 if (loglevel != 0) {
3923 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3924 ADDRX "\n", sprn, sprn, ctx->nip);
3925 }
3926 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3927 sprn, sprn, ctx->nip);
3928 }
3929 GEN_EXCP_PRIVREG(ctx);
3930 }
3931 } else {
3932 /* Not defined */
3933 if (loglevel != 0) {
3934 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3935 ADDRX "\n", sprn, sprn, ctx->nip);
3936 }
3937 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3938 sprn, sprn, ctx->nip);
3939 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3940 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3941 }
3942 }
3943
3944 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3945 {
3946 gen_op_mfspr(ctx);
3947 }
3948
3949 /* mftb */
3950 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3951 {
3952 gen_op_mfspr(ctx);
3953 }
3954
3955 /* mtcrf */
3956 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3957 {
3958 uint32_t crm, crn;
3959
3960 crm = CRM(ctx->opcode);
3961 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3962 TCGv_i32 temp = tcg_temp_new_i32();
3963 crn = ffs(crm);
3964 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3965 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3966 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3967 tcg_temp_free_i32(temp);
3968 } else {
3969 TCGv_i32 temp = tcg_const_i32(crm);
3970 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3971 tcg_temp_free_i32(temp);
3972 }
3973 }
3974
3975 /* mtmsr */
3976 #if defined(TARGET_PPC64)
3977 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3978 {
3979 #if defined(CONFIG_USER_ONLY)
3980 GEN_EXCP_PRIVREG(ctx);
3981 #else
3982 if (unlikely(!ctx->supervisor)) {
3983 GEN_EXCP_PRIVREG(ctx);
3984 return;
3985 }
3986 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3987 if (ctx->opcode & 0x00010000) {
3988 /* Special form that does not need any synchronisation */
3989 gen_op_update_riee();
3990 } else {
3991 /* XXX: we need to update nip before the store
3992 * if we enter power saving mode, we will exit the loop
3993 * directly from ppc_store_msr
3994 */
3995 gen_update_nip(ctx, ctx->nip);
3996 gen_op_store_msr();
3997 /* Must stop the translation as machine state (may have) changed */
3998 /* Note that mtmsr is not always defined as context-synchronizing */
3999 ctx->exception = POWERPC_EXCP_STOP;
4000 }
4001 #endif
4002 }
4003 #endif
4004
4005 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
4006 {
4007 #if defined(CONFIG_USER_ONLY)
4008 GEN_EXCP_PRIVREG(ctx);
4009 #else
4010 if (unlikely(!ctx->supervisor)) {
4011 GEN_EXCP_PRIVREG(ctx);
4012 return;
4013 }
4014 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4015 if (ctx->opcode & 0x00010000) {
4016 /* Special form that does not need any synchronisation */
4017 gen_op_update_riee();
4018 } else {
4019 /* XXX: we need to update nip before the store
4020 * if we enter power saving mode, we will exit the loop
4021 * directly from ppc_store_msr
4022 */
4023 gen_update_nip(ctx, ctx->nip);
4024 #if defined(TARGET_PPC64)
4025 if (!ctx->sf_mode)
4026 gen_op_store_msr_32();
4027 else
4028 #endif
4029 gen_op_store_msr();
4030 /* Must stop the translation as machine state (may have) changed */
4031 /* Note that mtmsrd is not always defined as context-synchronizing */
4032 ctx->exception = POWERPC_EXCP_STOP;
4033 }
4034 #endif
4035 }
4036
4037 /* mtspr */
4038 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4039 {
4040 void (*write_cb)(void *opaque, int sprn);
4041 uint32_t sprn = SPR(ctx->opcode);
4042
4043 #if !defined(CONFIG_USER_ONLY)
4044 if (ctx->supervisor == 2)
4045 write_cb = ctx->spr_cb[sprn].hea_write;
4046 else if (ctx->supervisor)
4047 write_cb = ctx->spr_cb[sprn].oea_write;
4048 else
4049 #endif
4050 write_cb = ctx->spr_cb[sprn].uea_write;
4051 if (likely(write_cb != NULL)) {
4052 if (likely(write_cb != SPR_NOACCESS)) {
4053 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4054 (*write_cb)(ctx, sprn);
4055 } else {
4056 /* Privilege exception */
4057 if (loglevel != 0) {
4058 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4059 ADDRX "\n", sprn, sprn, ctx->nip);
4060 }
4061 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4062 sprn, sprn, ctx->nip);
4063 GEN_EXCP_PRIVREG(ctx);
4064 }
4065 } else {
4066 /* Not defined */
4067 if (loglevel != 0) {
4068 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4069 ADDRX "\n", sprn, sprn, ctx->nip);
4070 }
4071 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4072 sprn, sprn, ctx->nip);
4073 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4074 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
4075 }
4076 }
4077
4078 /*** Cache management ***/
4079 /* dcbf */
4080 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4081 {
4082 /* XXX: specification says this is treated as a load by the MMU */
4083 TCGv t0 = tcg_temp_new();
4084 gen_set_access_type(ACCESS_CACHE);
4085 gen_addr_reg_index(t0, ctx);
4086 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4087 tcg_temp_free(t0);
4088 }
4089
4090 /* dcbi (Supervisor only) */
4091 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4092 {
4093 #if defined(CONFIG_USER_ONLY)
4094 GEN_EXCP_PRIVOPC(ctx);
4095 #else
4096 TCGv EA, val;
4097 if (unlikely(!ctx->supervisor)) {
4098 GEN_EXCP_PRIVOPC(ctx);
4099 return;
4100 }
4101 EA = tcg_temp_new();
4102 gen_set_access_type(ACCESS_CACHE);
4103 gen_addr_reg_index(EA, ctx);
4104 val = tcg_temp_new();
4105 /* XXX: specification says this should be treated as a store by the MMU */
4106 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4107 gen_qemu_st8(val, EA, ctx->mem_idx);
4108 tcg_temp_free(val);
4109 tcg_temp_free(EA);
4110 #endif
4111 }
4112
4113 /* dcdst */
4114 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4115 {
4116 /* XXX: specification say this is treated as a load by the MMU */
4117 TCGv t0 = tcg_temp_new();
4118 gen_set_access_type(ACCESS_CACHE);
4119 gen_addr_reg_index(t0, ctx);
4120 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4121 tcg_temp_free(t0);
4122 }
4123
4124 /* dcbt */
4125 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4126 {
4127 /* interpreted as no-op */
4128 /* XXX: specification say this is treated as a load by the MMU
4129 * but does not generate any exception
4130 */
4131 }
4132
4133 /* dcbtst */
4134 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4135 {
4136 /* interpreted as no-op */
4137 /* XXX: specification say this is treated as a load by the MMU
4138 * but does not generate any exception
4139 */
4140 }
4141
4142 /* dcbz */
4143 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
4144 static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
4145 /* 32 bytes cache line size */
4146 {
4147 #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
4148 #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
4149 #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
4150 #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
4151 #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
4152 #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
4153 #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
4154 #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
4155 GEN_MEM_FUNCS(dcbz_l32),
4156 },
4157 /* 64 bytes cache line size */
4158 {
4159 #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
4160 #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
4161 #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
4162 #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
4163 #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
4164 #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
4165 #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
4166 #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
4167 GEN_MEM_FUNCS(dcbz_l64),
4168 },
4169 /* 128 bytes cache line size */
4170 {
4171 #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
4172 #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
4173 #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
4174 #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
4175 #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
4176 #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
4177 #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
4178 #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
4179 GEN_MEM_FUNCS(dcbz_l128),
4180 },
4181 /* tunable cache line size */
4182 {
4183 #define gen_op_dcbz_le_raw gen_op_dcbz_raw
4184 #define gen_op_dcbz_le_user gen_op_dcbz_user
4185 #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
4186 #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
4187 #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
4188 #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
4189 #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
4190 #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
4191 GEN_MEM_FUNCS(dcbz),
4192 },
4193 };
4194
4195 static always_inline void handler_dcbz (DisasContext *ctx,
4196 int dcache_line_size)
4197 {
4198 int n;
4199
4200 switch (dcache_line_size) {
4201 case 32:
4202 n = 0;
4203 break;
4204 case 64:
4205 n = 1;
4206 break;
4207 case 128:
4208 n = 2;
4209 break;
4210 default:
4211 n = 3;
4212 break;
4213 }
4214 op_dcbz(n);
4215 }
4216
4217 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4218 {
4219 gen_addr_reg_index(cpu_T[0], ctx);
4220 handler_dcbz(ctx, ctx->dcache_line_size);
4221 gen_op_check_reservation();
4222 }
4223
4224 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4225 {
4226 gen_addr_reg_index(cpu_T[0], ctx);
4227 if (ctx->opcode & 0x00200000)
4228 handler_dcbz(ctx, ctx->dcache_line_size);
4229 else
4230 handler_dcbz(ctx, -1);
4231 gen_op_check_reservation();
4232 }
4233
4234 /* icbi */
4235 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
4236 #define gen_op_icbi_le_raw gen_op_icbi_raw
4237 #define gen_op_icbi_le_user gen_op_icbi_user
4238 #define gen_op_icbi_le_kernel gen_op_icbi_kernel
4239 #define gen_op_icbi_le_hypv gen_op_icbi_hypv
4240 #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4241 #define gen_op_icbi_le_64_user gen_op_icbi_64_user
4242 #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4243 #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4244 static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4245 GEN_MEM_FUNCS(icbi),
4246 };
4247
4248 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4249 {
4250 /* NIP cannot be restored if the memory exception comes from an helper */
4251 gen_update_nip(ctx, ctx->nip - 4);
4252 gen_addr_reg_index(cpu_T[0], ctx);
4253 op_icbi();
4254 }
4255
4256 /* Optional: */
4257 /* dcba */
4258 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4259 {
4260 /* interpreted as no-op */
4261 /* XXX: specification say this is treated as a store by the MMU
4262 * but does not generate any exception
4263 */
4264 }
4265
4266 /*** Segment register manipulation ***/
4267 /* Supervisor only: */
4268 /* mfsr */
4269 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4270 {
4271 #if defined(CONFIG_USER_ONLY)
4272 GEN_EXCP_PRIVREG(ctx);
4273 #else
4274 if (unlikely(!ctx->supervisor)) {
4275 GEN_EXCP_PRIVREG(ctx);
4276 return;
4277 }
4278 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4279 gen_op_load_sr();
4280 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4281 #endif
4282 }
4283
4284 /* mfsrin */
4285 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4286 {
4287 #if defined(CONFIG_USER_ONLY)
4288 GEN_EXCP_PRIVREG(ctx);
4289 #else
4290 if (unlikely(!ctx->supervisor)) {
4291 GEN_EXCP_PRIVREG(ctx);
4292 return;
4293 }
4294 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4295 gen_op_srli_T1(28);
4296 gen_op_load_sr();
4297 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4298 #endif
4299 }
4300
4301 /* mtsr */
4302 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4303 {
4304 #if defined(CONFIG_USER_ONLY)
4305 GEN_EXCP_PRIVREG(ctx);
4306 #else
4307 if (unlikely(!ctx->supervisor)) {
4308 GEN_EXCP_PRIVREG(ctx);
4309 return;
4310 }
4311 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4312 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4313 gen_op_store_sr();
4314 #endif
4315 }
4316
4317 /* mtsrin */
4318 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4319 {
4320 #if defined(CONFIG_USER_ONLY)
4321 GEN_EXCP_PRIVREG(ctx);
4322 #else
4323 if (unlikely(!ctx->supervisor)) {
4324 GEN_EXCP_PRIVREG(ctx);
4325 return;
4326 }
4327 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4328 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4329 gen_op_srli_T1(28);
4330 gen_op_store_sr();
4331 #endif
4332 }
4333
4334 #if defined(TARGET_PPC64)
4335 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4336 /* mfsr */
4337 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4338 {
4339 #if defined(CONFIG_USER_ONLY)
4340 GEN_EXCP_PRIVREG(ctx);
4341 #else
4342 if (unlikely(!ctx->supervisor)) {
4343 GEN_EXCP_PRIVREG(ctx);
4344 return;
4345 }
4346 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4347 gen_op_load_slb();
4348 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4349 #endif
4350 }
4351
4352 /* mfsrin */
4353 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4354 PPC_SEGMENT_64B)
4355 {
4356 #if defined(CONFIG_USER_ONLY)
4357 GEN_EXCP_PRIVREG(ctx);
4358 #else
4359 if (unlikely(!ctx->supervisor)) {
4360 GEN_EXCP_PRIVREG(ctx);
4361 return;
4362 }
4363 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4364 gen_op_srli_T1(28);
4365 gen_op_load_slb();
4366 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4367 #endif
4368 }
4369
4370 /* mtsr */
4371 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4372 {
4373 #if defined(CONFIG_USER_ONLY)
4374 GEN_EXCP_PRIVREG(ctx);
4375 #else
4376 if (unlikely(!ctx->supervisor)) {
4377 GEN_EXCP_PRIVREG(ctx);
4378 return;
4379 }
4380 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4381 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4382 gen_op_store_slb();
4383 #endif
4384 }
4385
4386 /* mtsrin */
4387 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4388 PPC_SEGMENT_64B)
4389 {
4390 #if defined(CONFIG_USER_ONLY)
4391 GEN_EXCP_PRIVREG(ctx);
4392 #else
4393 if (unlikely(!ctx->supervisor)) {
4394 GEN_EXCP_PRIVREG(ctx);
4395 return;
4396 }
4397 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4398 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4399 gen_op_srli_T1(28);
4400 gen_op_store_slb();
4401 #endif
4402 }
4403 #endif /* defined(TARGET_PPC64) */
4404
4405 /*** Lookaside buffer management ***/
4406 /* Optional & supervisor only: */
4407 /* tlbia */
4408 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4409 {
4410 #if defined(CONFIG_USER_ONLY)
4411 GEN_EXCP_PRIVOPC(ctx);
4412 #else
4413 if (unlikely(!ctx->supervisor)) {
4414 GEN_EXCP_PRIVOPC(ctx);
4415 return;
4416 }
4417 gen_op_tlbia();
4418 #endif
4419 }
4420
4421 /* tlbie */
4422 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4423 {
4424 #if defined(CONFIG_USER_ONLY)
4425 GEN_EXCP_PRIVOPC(ctx);
4426 #else
4427 if (unlikely(!ctx->supervisor)) {
4428 GEN_EXCP_PRIVOPC(ctx);
4429 return;
4430 }
4431 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4432 #if defined(TARGET_PPC64)
4433 if (ctx->sf_mode)
4434 gen_op_tlbie_64();
4435 else
4436 #endif
4437 gen_op_tlbie();
4438 #endif
4439 }
4440
4441 /* tlbsync */
4442 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4443 {
4444 #if defined(CONFIG_USER_ONLY)
4445 GEN_EXCP_PRIVOPC(ctx);
4446 #else
4447 if (unlikely(!ctx->supervisor)) {
4448 GEN_EXCP_PRIVOPC(ctx);
4449 return;
4450 }
4451 /* This has no effect: it should ensure that all previous
4452 * tlbie have completed
4453 */
4454 GEN_STOP(ctx);
4455 #endif
4456 }
4457
4458 #if defined(TARGET_PPC64)
4459 /* slbia */
4460 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4461 {
4462 #if defined(CONFIG_USER_ONLY)
4463 GEN_EXCP_PRIVOPC(ctx);
4464 #else
4465 if (unlikely(!ctx->supervisor)) {
4466 GEN_EXCP_PRIVOPC(ctx);
4467 return;
4468 }
4469 gen_op_slbia();
4470 #endif
4471 }
4472
4473 /* slbie */
4474 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4475 {
4476 #if defined(CONFIG_USER_ONLY)
4477 GEN_EXCP_PRIVOPC(ctx);
4478 #else
4479 if (unlikely(!ctx->supervisor)) {
4480 GEN_EXCP_PRIVOPC(ctx);
4481 return;
4482 }
4483 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4484 gen_op_slbie();
4485 #endif
4486 }
4487 #endif
4488
4489 /*** External control ***/
4490 /* Optional: */
4491 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4492 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4493 static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4494 GEN_MEM_FUNCS(eciwx),
4495 };
4496 static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4497 GEN_MEM_FUNCS(ecowx),
4498 };
4499
4500 /* eciwx */
4501 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4502 {
4503 /* Should check EAR[E] & alignment ! */
4504 gen_set_access_type(ACCESS_RES);
4505 gen_addr_reg_index(cpu_T[0], ctx);
4506 op_eciwx();
4507 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4508 }
4509
4510 /* ecowx */
4511 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4512 {
4513 /* Should check EAR[E] & alignment ! */
4514 gen_addr_reg_index(cpu_T[0], ctx);
4515 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4516 op_ecowx();
4517 }
4518
4519 /* PowerPC 601 specific instructions */
4520 /* abs - abs. */
4521 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4522 {
4523 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4524 gen_op_POWER_abs();
4525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4526 if (unlikely(Rc(ctx->opcode) != 0))
4527 gen_set_Rc0(ctx, cpu_T[0]);
4528 }
4529
4530 /* abso - abso. */
4531 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4532 {
4533 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4534 gen_op_POWER_abso();
4535 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4536 if (unlikely(Rc(ctx->opcode) != 0))
4537 gen_set_Rc0(ctx, cpu_T[0]);
4538 }
4539
4540 /* clcs */
4541 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4542 {
4543 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4544 gen_op_POWER_clcs();
4545 /* Rc=1 sets CR0 to an undefined state */
4546 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4547 }
4548
4549 /* div - div. */
4550 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4551 {
4552 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4553 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4554 gen_op_POWER_div();
4555 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4556 if (unlikely(Rc(ctx->opcode) != 0))
4557 gen_set_Rc0(ctx, cpu_T[0]);
4558 }
4559
4560 /* divo - divo. */
4561 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4562 {
4563 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4564 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4565 gen_op_POWER_divo();
4566 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4567 if (unlikely(Rc(ctx->opcode) != 0))
4568 gen_set_Rc0(ctx, cpu_T[0]);
4569 }
4570
4571 /* divs - divs. */
4572 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4573 {
4574 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4575 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4576 gen_op_POWER_divs();
4577 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4578 if (unlikely(Rc(ctx->opcode) != 0))
4579 gen_set_Rc0(ctx, cpu_T[0]);
4580 }
4581
4582 /* divso - divso. */
4583 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4584 {
4585 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4586 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4587 gen_op_POWER_divso();
4588 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4589 if (unlikely(Rc(ctx->opcode) != 0))
4590 gen_set_Rc0(ctx, cpu_T[0]);
4591 }
4592
4593 /* doz - doz. */
4594 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4595 {
4596 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4597 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4598 gen_op_POWER_doz();
4599 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4600 if (unlikely(Rc(ctx->opcode) != 0))
4601 gen_set_Rc0(ctx, cpu_T[0]);
4602 }
4603
4604 /* dozo - dozo. */
4605 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4606 {
4607 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4608 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4609 gen_op_POWER_dozo();
4610 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4611 if (unlikely(Rc(ctx->opcode) != 0))
4612 gen_set_Rc0(ctx, cpu_T[0]);
4613 }
4614
4615 /* dozi */
4616 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4617 {
4618 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4619 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
4620 gen_op_POWER_doz();
4621 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4622 }
4623
4624 /* As lscbx load from memory byte after byte, it's always endian safe.
4625 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4626 */
4627 #define op_POWER_lscbx(start, ra, rb) \
4628 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4629 #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4630 #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4631 #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4632 #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4633 #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4634 #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4635 #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4636 #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4637 #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4638 #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4639 #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4640 #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4641 static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4642 GEN_MEM_FUNCS(POWER_lscbx),
4643 };
4644
4645 /* lscbx - lscbx. */
4646 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4647 {
4648 int ra = rA(ctx->opcode);
4649 int rb = rB(ctx->opcode);
4650
4651 gen_addr_reg_index(cpu_T[0], ctx);
4652 if (ra == 0) {
4653 ra = rb;
4654 }
4655 /* NIP cannot be restored if the memory exception comes from an helper */
4656 gen_update_nip(ctx, ctx->nip - 4);
4657 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4658 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4659 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
4660 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4661 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4662 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
4663 if (unlikely(Rc(ctx->opcode) != 0))
4664 gen_set_Rc0(ctx, cpu_T[0]);
4665 }
4666
4667 /* maskg - maskg. */
4668 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4669 {
4670 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4671 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4672 gen_op_POWER_maskg();
4673 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4674 if (unlikely(Rc(ctx->opcode) != 0))
4675 gen_set_Rc0(ctx, cpu_T[0]);
4676 }
4677
4678 /* maskir - maskir. */
4679 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4680 {
4681 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4682 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4683 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4684 gen_op_POWER_maskir();
4685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4686 if (unlikely(Rc(ctx->opcode) != 0))
4687 gen_set_Rc0(ctx, cpu_T[0]);
4688 }
4689
4690 /* mul - mul. */
4691 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4692 {
4693 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4694 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4695 gen_op_POWER_mul();
4696 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4697 if (unlikely(Rc(ctx->opcode) != 0))
4698 gen_set_Rc0(ctx, cpu_T[0]);
4699 }
4700
4701 /* mulo - mulo. */
4702 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4703 {
4704 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4705 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4706 gen_op_POWER_mulo();
4707 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4708 if (unlikely(Rc(ctx->opcode) != 0))
4709 gen_set_Rc0(ctx, cpu_T[0]);
4710 }
4711
4712 /* nabs - nabs. */
4713 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4714 {
4715 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4716 gen_op_POWER_nabs();
4717 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4718 if (unlikely(Rc(ctx->opcode) != 0))
4719 gen_set_Rc0(ctx, cpu_T[0]);
4720 }
4721
4722 /* nabso - nabso. */
4723 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4724 {
4725 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4726 gen_op_POWER_nabso();
4727 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4728 if (unlikely(Rc(ctx->opcode) != 0))
4729 gen_set_Rc0(ctx, cpu_T[0]);
4730 }
4731
4732 /* rlmi - rlmi. */
4733 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4734 {
4735 uint32_t mb, me;
4736
4737 mb = MB(ctx->opcode);
4738 me = ME(ctx->opcode);
4739 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4740 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4741 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4742 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4744 if (unlikely(Rc(ctx->opcode) != 0))
4745 gen_set_Rc0(ctx, cpu_T[0]);
4746 }
4747
4748 /* rrib - rrib. */
4749 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4750 {
4751 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4752 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4753 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4754 gen_op_POWER_rrib();
4755 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4756 if (unlikely(Rc(ctx->opcode) != 0))
4757 gen_set_Rc0(ctx, cpu_T[0]);
4758 }
4759
4760 /* sle - sle. */
4761 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4762 {
4763 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4764 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4765 gen_op_POWER_sle();
4766 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4767 if (unlikely(Rc(ctx->opcode) != 0))
4768 gen_set_Rc0(ctx, cpu_T[0]);
4769 }
4770
4771 /* sleq - sleq. */
4772 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4773 {
4774 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4775 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4776 gen_op_POWER_sleq();
4777 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4778 if (unlikely(Rc(ctx->opcode) != 0))
4779 gen_set_Rc0(ctx, cpu_T[0]);
4780 }
4781
4782 /* sliq - sliq. */
4783 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4784 {
4785 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4786 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4787 gen_op_POWER_sle();
4788 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4789 if (unlikely(Rc(ctx->opcode) != 0))
4790 gen_set_Rc0(ctx, cpu_T[0]);
4791 }
4792
4793 /* slliq - slliq. */
4794 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4795 {
4796 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4797 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4798 gen_op_POWER_sleq();
4799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4800 if (unlikely(Rc(ctx->opcode) != 0))
4801 gen_set_Rc0(ctx, cpu_T[0]);
4802 }
4803
4804 /* sllq - sllq. */
4805 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4806 {
4807 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4808 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4809 gen_op_POWER_sllq();
4810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4811 if (unlikely(Rc(ctx->opcode) != 0))
4812 gen_set_Rc0(ctx, cpu_T[0]);
4813 }
4814
4815 /* slq - slq. */
4816 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4817 {
4818 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4819 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4820 gen_op_POWER_slq();
4821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4822 if (unlikely(Rc(ctx->opcode) != 0))
4823 gen_set_Rc0(ctx, cpu_T[0]);
4824 }
4825
4826 /* sraiq - sraiq. */
4827 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4828 {
4829 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4830 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4831 gen_op_POWER_sraq();
4832 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4833 if (unlikely(Rc(ctx->opcode) != 0))
4834 gen_set_Rc0(ctx, cpu_T[0]);
4835 }
4836
4837 /* sraq - sraq. */
4838 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4839 {
4840 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4841 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4842 gen_op_POWER_sraq();
4843 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4844 if (unlikely(Rc(ctx->opcode) != 0))
4845 gen_set_Rc0(ctx, cpu_T[0]);
4846 }
4847
4848 /* sre - sre. */
4849 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4850 {
4851 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4852 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4853 gen_op_POWER_sre();
4854 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_T[0]);
4857 }
4858
4859 /* srea - srea. */
4860 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4861 {
4862 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4863 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4864 gen_op_POWER_srea();
4865 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4866 if (unlikely(Rc(ctx->opcode) != 0))
4867 gen_set_Rc0(ctx, cpu_T[0]);
4868 }
4869
4870 /* sreq */
4871 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4872 {
4873 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4874 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4875 gen_op_POWER_sreq();
4876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4877 if (unlikely(Rc(ctx->opcode) != 0))
4878 gen_set_Rc0(ctx, cpu_T[0]);
4879 }
4880
4881 /* sriq */
4882 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4883 {
4884 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4885 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4886 gen_op_POWER_srq();
4887 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4888 if (unlikely(Rc(ctx->opcode) != 0))
4889 gen_set_Rc0(ctx, cpu_T[0]);
4890 }
4891
4892 /* srliq */
4893 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4894 {
4895 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4896 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4897 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4898 gen_op_POWER_srlq();
4899 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4900 if (unlikely(Rc(ctx->opcode) != 0))
4901 gen_set_Rc0(ctx, cpu_T[0]);
4902 }
4903
4904 /* srlq */
4905 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4906 {
4907 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4908 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4909 gen_op_POWER_srlq();
4910 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4911 if (unlikely(Rc(ctx->opcode) != 0))
4912 gen_set_Rc0(ctx, cpu_T[0]);
4913 }
4914
4915 /* srq */
4916 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4917 {
4918 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4919 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4920 gen_op_POWER_srq();
4921 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4922 if (unlikely(Rc(ctx->opcode) != 0))
4923 gen_set_Rc0(ctx, cpu_T[0]);
4924 }
4925
4926 /* PowerPC 602 specific instructions */
4927 /* dsa */
4928 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4929 {
4930 /* XXX: TODO */
4931 GEN_EXCP_INVAL(ctx);
4932 }
4933
4934 /* esa */
4935 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4936 {
4937 /* XXX: TODO */
4938 GEN_EXCP_INVAL(ctx);
4939 }
4940
4941 /* mfrom */
4942 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4943 {
4944 #if defined(CONFIG_USER_ONLY)
4945 GEN_EXCP_PRIVOPC(ctx);
4946 #else
4947 if (unlikely(!ctx->supervisor)) {
4948 GEN_EXCP_PRIVOPC(ctx);
4949 return;
4950 }
4951 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4952 gen_op_602_mfrom();
4953 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4954 #endif
4955 }
4956
4957 /* 602 - 603 - G2 TLB management */
4958 /* tlbld */
4959 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4960 {
4961 #if defined(CONFIG_USER_ONLY)
4962 GEN_EXCP_PRIVOPC(ctx);
4963 #else
4964 if (unlikely(!ctx->supervisor)) {
4965 GEN_EXCP_PRIVOPC(ctx);
4966 return;
4967 }
4968 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4969 gen_op_6xx_tlbld();
4970 #endif
4971 }
4972
4973 /* tlbli */
4974 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4975 {
4976 #if defined(CONFIG_USER_ONLY)
4977 GEN_EXCP_PRIVOPC(ctx);
4978 #else
4979 if (unlikely(!ctx->supervisor)) {
4980 GEN_EXCP_PRIVOPC(ctx);
4981 return;
4982 }
4983 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4984 gen_op_6xx_tlbli();
4985 #endif
4986 }
4987
4988 /* 74xx TLB management */
4989 /* tlbld */
4990 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4991 {
4992 #if defined(CONFIG_USER_ONLY)
4993 GEN_EXCP_PRIVOPC(ctx);
4994 #else
4995 if (unlikely(!ctx->supervisor)) {
4996 GEN_EXCP_PRIVOPC(ctx);
4997 return;
4998 }
4999 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
5000 gen_op_74xx_tlbld();
5001 #endif
5002 }
5003
5004 /* tlbli */
5005 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5006 {
5007 #if defined(CONFIG_USER_ONLY)
5008 GEN_EXCP_PRIVOPC(ctx);
5009 #else
5010 if (unlikely(!ctx->supervisor)) {
5011 GEN_EXCP_PRIVOPC(ctx);
5012 return;
5013 }
5014 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
5015 gen_op_74xx_tlbli();
5016 #endif
5017 }
5018
5019 /* POWER instructions not in PowerPC 601 */
5020 /* clf */
5021 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5022 {
5023 /* Cache line flush: implemented as no-op */
5024 }
5025
5026 /* cli */
5027 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5028 {
5029 /* Cache line invalidate: privileged and treated as no-op */
5030 #if defined(CONFIG_USER_ONLY)
5031 GEN_EXCP_PRIVOPC(ctx);
5032 #else
5033 if (unlikely(!ctx->supervisor)) {
5034 GEN_EXCP_PRIVOPC(ctx);
5035 return;
5036 }
5037 #endif
5038 }
5039
5040 /* dclst */
5041 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5042 {
5043 /* Data cache line store: treated as no-op */
5044 }
5045
5046 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5047 {
5048 #if defined(CONFIG_USER_ONLY)
5049 GEN_EXCP_PRIVOPC(ctx);
5050 #else
5051 if (unlikely(!ctx->supervisor)) {
5052 GEN_EXCP_PRIVOPC(ctx);
5053 return;
5054 }
5055 int ra = rA(ctx->opcode);
5056 int rd = rD(ctx->opcode);
5057
5058 gen_addr_reg_index(cpu_T[0], ctx);
5059 gen_op_POWER_mfsri();
5060 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
5061 if (ra != 0 && ra != rd)
5062 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
5063 #endif
5064 }
5065
5066 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5067 {
5068 #if defined(CONFIG_USER_ONLY)
5069 GEN_EXCP_PRIVOPC(ctx);
5070 #else
5071 if (unlikely(!ctx->supervisor)) {
5072 GEN_EXCP_PRIVOPC(ctx);
5073 return;
5074 }
5075 gen_addr_reg_index(cpu_T[0], ctx);
5076 gen_op_POWER_rac();
5077 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5078 #endif
5079 }
5080
5081 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5082 {
5083 #if defined(CONFIG_USER_ONLY)
5084 GEN_EXCP_PRIVOPC(ctx);
5085 #else
5086 if (unlikely(!ctx->supervisor)) {
5087 GEN_EXCP_PRIVOPC(ctx);
5088 return;
5089 }
5090 gen_op_POWER_rfsvc();
5091 GEN_SYNC(ctx);
5092 #endif
5093 }
5094
5095 /* svc is not implemented for now */
5096
5097 /* POWER2 specific instructions */
5098 /* Quad manipulation (load/store two floats at a time) */
5099
5100 /* lfq */
5101 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5102 {
5103 int rd = rD(ctx->opcode);
5104 TCGv t0 = tcg_temp_new();
5105 gen_addr_imm_index(t0, ctx, 0);
5106 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5107 tcg_gen_addi_tl(t0, t0, 8);
5108 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5109 tcg_temp_free(t0);
5110 }
5111
5112 /* lfqu */
5113 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5114 {
5115 int ra = rA(ctx->opcode);
5116 int rd = rD(ctx->opcode);
5117 TCGv t0 = tcg_temp_new();
5118 TCGv t1 = tcg_temp_new();
5119 gen_addr_imm_index(t0, ctx, 0);
5120 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5121 tcg_gen_addi_tl(t1, t0, 8);
5122 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5123 if (ra != 0)
5124 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5125 tcg_temp_free(t0);
5126 tcg_temp_free(t1);
5127 }
5128
5129 /* lfqux */
5130 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5131 {
5132 int ra = rA(ctx->opcode);
5133 int rd = rD(ctx->opcode);
5134 TCGv t0 = tcg_temp_new();
5135 TCGv t1 = tcg_temp_new();
5136 gen_addr_reg_index(t0, ctx);
5137 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5138 tcg_gen_addi_tl(t1, t0, 8);
5139 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5140 if (ra != 0)
5141 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5142 tcg_temp_free(t0);
5143 tcg_temp_free(t1);
5144 }
5145
5146 /* lfqx */
5147 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5148 {
5149 int rd = rD(ctx->opcode);
5150 TCGv t0 = tcg_temp_new();
5151 gen_addr_reg_index(t0, ctx);
5152 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5153 tcg_gen_addi_tl(t0, t0, 8);
5154 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5155 tcg_temp_free(t0);
5156 }
5157
5158 /* stfq */
5159 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5160 {
5161 int rd = rD(ctx->opcode);
5162 TCGv t0 = tcg_temp_new();
5163 gen_addr_imm_index(t0, ctx, 0);
5164 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5165 tcg_gen_addi_tl(t0, t0, 8);
5166 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5167 tcg_temp_free(t0);
5168 }
5169
5170 /* stfqu */
5171 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5172 {
5173 int ra = rA(ctx->opcode);
5174 int rd = rD(ctx->opcode);
5175 TCGv t0 = tcg_temp_new();
5176 TCGv t1 = tcg_temp_new();
5177 gen_addr_imm_index(t0, ctx, 0);
5178 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5179 tcg_gen_addi_tl(t1, t0, 8);
5180 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5181 if (ra != 0)
5182 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5183 tcg_temp_free(t0);
5184 tcg_temp_free(t1);
5185 }
5186
5187 /* stfqux */
5188 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5189 {
5190 int ra = rA(ctx->opcode);
5191 int rd = rD(ctx->opcode);
5192 TCGv t0 = tcg_temp_new();
5193 TCGv t1 = tcg_temp_new();
5194 gen_addr_reg_index(t0, ctx);
5195 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5196 tcg_gen_addi_tl(t1, t0, 8);
5197 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5198 if (ra != 0)
5199 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5200 tcg_temp_free(t0);
5201 tcg_temp_free(t1);
5202 }
5203
5204 /* stfqx */
5205 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5206 {
5207 int rd = rD(ctx->opcode);
5208 TCGv t0 = tcg_temp_new();
5209 gen_addr_reg_index(t0, ctx);
5210 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5211 tcg_gen_addi_tl(t0, t0, 8);
5212 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5213 tcg_temp_free(t0);
5214 }
5215
5216 /* BookE specific instructions */
5217 /* XXX: not implemented on 440 ? */
5218 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5219 {
5220 /* XXX: TODO */
5221 GEN_EXCP_INVAL(ctx);
5222 }
5223
5224 /* XXX: not implemented on 440 ? */
5225 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5226 {
5227 #if defined(CONFIG_USER_ONLY)
5228 GEN_EXCP_PRIVOPC(ctx);
5229 #else
5230 if (unlikely(!ctx->supervisor)) {
5231 GEN_EXCP_PRIVOPC(ctx);
5232 return;
5233 }
5234 gen_addr_reg_index(cpu_T[0], ctx);
5235 /* Use the same micro-ops as for tlbie */
5236 #if defined(TARGET_PPC64)
5237 if (ctx->sf_mode)
5238 gen_op_tlbie_64();
5239 else
5240 #endif
5241 gen_op_tlbie();
5242 #endif
5243 }
5244
5245 /* All 405 MAC instructions are translated here */
5246 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5247 int opc2, int opc3,
5248 int ra, int rb, int rt, int Rc)
5249 {
5250 TCGv t0, t1;
5251
5252 t0 = tcg_temp_local_new();
5253 t1 = tcg_temp_local_new();
5254
5255 switch (opc3 & 0x0D) {
5256 case 0x05:
5257 /* macchw - macchw. - macchwo - macchwo. */
5258 /* macchws - macchws. - macchwso - macchwso. */
5259 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5260 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5261 /* mulchw - mulchw. */
5262 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5263 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5264 tcg_gen_ext16s_tl(t1, t1);
5265 break;
5266 case 0x04:
5267 /* macchwu - macchwu. - macchwuo - macchwuo. */
5268 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5269 /* mulchwu - mulchwu. */
5270 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5271 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5272 tcg_gen_ext16u_tl(t1, t1);
5273 break;
5274 case 0x01:
5275 /* machhw - machhw. - machhwo - machhwo. */
5276 /* machhws - machhws. - machhwso - machhwso. */
5277 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5278 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5279 /* mulhhw - mulhhw. */
5280 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5281 tcg_gen_ext16s_tl(t0, t0);
5282 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5283 tcg_gen_ext16s_tl(t1, t1);
5284 break;
5285 case 0x00:
5286 /* machhwu - machhwu. - machhwuo - machhwuo. */
5287 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5288 /* mulhhwu - mulhhwu. */
5289 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5290 tcg_gen_ext16u_tl(t0, t0);
5291 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5292 tcg_gen_ext16u_tl(t1, t1);
5293 break;
5294 case 0x0D:
5295 /* maclhw - maclhw. - maclhwo - maclhwo. */
5296 /* maclhws - maclhws. - maclhwso - maclhwso. */
5297 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5298 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5299 /* mullhw - mullhw. */
5300 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5301 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5302 break;
5303 case 0x0C:
5304 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5305 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5306 /* mullhwu - mullhwu. */
5307 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5308 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5309 break;
5310 }
5311 if (opc2 & 0x04) {
5312 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5313 tcg_gen_mul_tl(t1, t0, t1);
5314 if (opc2 & 0x02) {
5315 /* nmultiply-and-accumulate (0x0E) */
5316 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5317 } else {
5318 /* multiply-and-accumulate (0x0C) */
5319 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5320 }
5321
5322 if (opc3 & 0x12) {
5323 /* Check overflow and/or saturate */
5324 int l1 = gen_new_label();
5325
5326 if (opc3 & 0x10) {
5327 /* Start with XER OV disabled, the most likely case */
5328 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5329 }
5330 if (opc3 & 0x01) {
5331 /* Signed */
5332 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5333 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5334 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5335 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5336 if (opc3 & 0x02) {
5337 /* Saturate */
5338 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5339 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5340 }
5341 } else {
5342 /* Unsigned */
5343 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5344 if (opc3 & 0x02) {
5345 /* Saturate */
5346 tcg_gen_movi_tl(t0, UINT32_MAX);
5347 }
5348 }
5349 if (opc3 & 0x10) {
5350 /* Check overflow */
5351 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5352 }
5353 gen_set_label(l1);
5354 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5355 }
5356 } else {
5357 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5358 }
5359 tcg_temp_free(t0);
5360 tcg_temp_free(t1);
5361 if (unlikely(Rc) != 0) {
5362 /* Update Rc0 */
5363 gen_set_Rc0(ctx, cpu_gpr[rt]);
5364 }
5365 }
5366
5367 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5368 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5369 { \
5370 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5371 rD(ctx->opcode), Rc(ctx->opcode)); \
5372 }
5373
5374 /* macchw - macchw. */
5375 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5376 /* macchwo - macchwo. */
5377 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5378 /* macchws - macchws. */
5379 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5380 /* macchwso - macchwso. */
5381 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5382 /* macchwsu - macchwsu. */
5383 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5384 /* macchwsuo - macchwsuo. */
5385 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5386 /* macchwu - macchwu. */
5387 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5388 /* macchwuo - macchwuo. */
5389 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5390 /* machhw - machhw. */
5391 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5392 /* machhwo - machhwo. */
5393 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5394 /* machhws - machhws. */
5395 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5396 /* machhwso - machhwso. */
5397 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5398 /* machhwsu - machhwsu. */
5399 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5400 /* machhwsuo - machhwsuo. */
5401 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5402 /* machhwu - machhwu. */
5403 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5404 /* machhwuo - machhwuo. */
5405 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5406 /* maclhw - maclhw. */
5407 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5408 /* maclhwo - maclhwo. */
5409 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5410 /* maclhws - maclhws. */
5411 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5412 /* maclhwso - maclhwso. */
5413 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5414 /* maclhwu - maclhwu. */
5415 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5416 /* maclhwuo - maclhwuo. */
5417 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5418 /* maclhwsu - maclhwsu. */
5419 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5420 /* maclhwsuo - maclhwsuo. */
5421 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5422 /* nmacchw - nmacchw. */
5423 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5424 /* nmacchwo - nmacchwo. */
5425 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5426 /* nmacchws - nmacchws. */
5427 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5428 /* nmacchwso - nmacchwso. */
5429 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5430 /* nmachhw - nmachhw. */
5431 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5432 /* nmachhwo - nmachhwo. */
5433 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5434 /* nmachhws - nmachhws. */
5435 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5436 /* nmachhwso - nmachhwso. */
5437 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5438 /* nmaclhw - nmaclhw. */
5439 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5440 /* nmaclhwo - nmaclhwo. */
5441 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5442 /* nmaclhws - nmaclhws. */
5443 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5444 /* nmaclhwso - nmaclhwso. */
5445 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5446
5447 /* mulchw - mulchw. */
5448 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5449 /* mulchwu - mulchwu. */
5450 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5451 /* mulhhw - mulhhw. */
5452 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5453 /* mulhhwu - mulhhwu. */
5454 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5455 /* mullhw - mullhw. */
5456 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5457 /* mullhwu - mullhwu. */
5458 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5459
5460 /* mfdcr */
5461 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5462 {
5463 #if defined(CONFIG_USER_ONLY)
5464 GEN_EXCP_PRIVREG(ctx);
5465 #else
5466 uint32_t dcrn = SPR(ctx->opcode);
5467
5468 if (unlikely(!ctx->supervisor)) {
5469 GEN_EXCP_PRIVREG(ctx);
5470 return;
5471 }
5472 tcg_gen_movi_tl(cpu_T[0], dcrn);
5473 gen_op_load_dcr();
5474 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5475 #endif
5476 }
5477
5478 /* mtdcr */
5479 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5480 {
5481 #if defined(CONFIG_USER_ONLY)
5482 GEN_EXCP_PRIVREG(ctx);
5483 #else
5484 uint32_t dcrn = SPR(ctx->opcode);
5485
5486 if (unlikely(!ctx->supervisor)) {
5487 GEN_EXCP_PRIVREG(ctx);
5488 return;
5489 }
5490 tcg_gen_movi_tl(cpu_T[0], dcrn);
5491 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5492 gen_op_store_dcr();
5493 #endif
5494 }
5495
5496 /* mfdcrx */
5497 /* XXX: not implemented on 440 ? */
5498 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5499 {
5500 #if defined(CONFIG_USER_ONLY)
5501 GEN_EXCP_PRIVREG(ctx);
5502 #else
5503 if (unlikely(!ctx->supervisor)) {
5504 GEN_EXCP_PRIVREG(ctx);
5505 return;
5506 }
5507 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5508 gen_op_load_dcr();
5509 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5510 /* Note: Rc update flag set leads to undefined state of Rc0 */
5511 #endif
5512 }
5513
5514 /* mtdcrx */
5515 /* XXX: not implemented on 440 ? */
5516 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5517 {
5518 #if defined(CONFIG_USER_ONLY)
5519 GEN_EXCP_PRIVREG(ctx);
5520 #else
5521 if (unlikely(!ctx->supervisor)) {
5522 GEN_EXCP_PRIVREG(ctx);
5523 return;
5524 }
5525 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5526 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5527 gen_op_store_dcr();
5528 /* Note: Rc update flag set leads to undefined state of Rc0 */
5529 #endif
5530 }
5531
5532 /* mfdcrux (PPC 460) : user-mode access to DCR */
5533 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5534 {
5535 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5536 gen_op_load_dcr();
5537 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5538 /* Note: Rc update flag set leads to undefined state of Rc0 */
5539 }
5540
5541 /* mtdcrux (PPC 460) : user-mode access to DCR */
5542 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5543 {
5544 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5545 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5546 gen_op_store_dcr();
5547 /* Note: Rc update flag set leads to undefined state of Rc0 */
5548 }
5549
5550 /* dccci */
5551 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5552 {
5553 #if defined(CONFIG_USER_ONLY)
5554 GEN_EXCP_PRIVOPC(ctx);
5555 #else
5556 if (unlikely(!ctx->supervisor)) {
5557 GEN_EXCP_PRIVOPC(ctx);
5558 return;
5559 }
5560 /* interpreted as no-op */
5561 #endif
5562 }
5563
5564 /* dcread */
5565 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5566 {
5567 #if defined(CONFIG_USER_ONLY)
5568 GEN_EXCP_PRIVOPC(ctx);
5569 #else
5570 TCGv EA, val;
5571 if (unlikely(!ctx->supervisor)) {
5572 GEN_EXCP_PRIVOPC(ctx);
5573 return;
5574 }
5575 EA = tcg_temp_new();
5576 gen_set_access_type(ACCESS_CACHE);
5577 gen_addr_reg_index(EA, ctx);
5578 val = tcg_temp_new();
5579 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5580 tcg_temp_free(val);
5581 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5582 tcg_temp_free(EA);
5583 #endif
5584 }
5585
5586 /* icbt */
5587 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5588 {
5589 /* interpreted as no-op */
5590 /* XXX: specification say this is treated as a load by the MMU
5591 * but does not generate any exception
5592 */
5593 }
5594
5595 /* iccci */
5596 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5597 {
5598 #if defined(CONFIG_USER_ONLY)
5599 GEN_EXCP_PRIVOPC(ctx);
5600 #else
5601 if (unlikely(!ctx->supervisor)) {
5602 GEN_EXCP_PRIVOPC(ctx);
5603 return;
5604 }
5605 /* interpreted as no-op */
5606 #endif
5607 }
5608
5609 /* icread */
5610 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5611 {
5612 #if defined(CONFIG_USER_ONLY)
5613 GEN_EXCP_PRIVOPC(ctx);
5614 #else
5615 if (unlikely(!ctx->supervisor)) {
5616 GEN_EXCP_PRIVOPC(ctx);
5617 return;
5618 }
5619 /* interpreted as no-op */
5620 #endif
5621 }
5622
5623 /* rfci (supervisor only) */
5624 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5625 {
5626 #if defined(CONFIG_USER_ONLY)
5627 GEN_EXCP_PRIVOPC(ctx);
5628 #else
5629 if (unlikely(!ctx->supervisor)) {
5630 GEN_EXCP_PRIVOPC(ctx);
5631 return;
5632 }
5633 /* Restore CPU state */
5634 gen_op_40x_rfci();
5635 GEN_SYNC(ctx);
5636 #endif
5637 }
5638
5639 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5640 {
5641 #if defined(CONFIG_USER_ONLY)
5642 GEN_EXCP_PRIVOPC(ctx);
5643 #else
5644 if (unlikely(!ctx->supervisor)) {
5645 GEN_EXCP_PRIVOPC(ctx);
5646 return;
5647 }
5648 /* Restore CPU state */
5649 gen_op_rfci();
5650 GEN_SYNC(ctx);
5651 #endif
5652 }
5653
5654 /* BookE specific */
5655 /* XXX: not implemented on 440 ? */
5656 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5657 {
5658 #if defined(CONFIG_USER_ONLY)
5659 GEN_EXCP_PRIVOPC(ctx);
5660 #else
5661 if (unlikely(!ctx->supervisor)) {
5662 GEN_EXCP_PRIVOPC(ctx);
5663 return;
5664 }
5665 /* Restore CPU state */
5666 gen_op_rfdi();
5667 GEN_SYNC(ctx);
5668 #endif
5669 }
5670
5671 /* XXX: not implemented on 440 ? */
5672 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5673 {
5674 #if defined(CONFIG_USER_ONLY)
5675 GEN_EXCP_PRIVOPC(ctx);
5676 #else
5677 if (unlikely(!ctx->supervisor)) {
5678 GEN_EXCP_PRIVOPC(ctx);
5679 return;
5680 }
5681 /* Restore CPU state */
5682 gen_op_rfmci();
5683 GEN_SYNC(ctx);
5684 #endif
5685 }
5686
5687 /* TLB management - PowerPC 405 implementation */
5688 /* tlbre */
5689 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5690 {
5691 #if defined(CONFIG_USER_ONLY)
5692 GEN_EXCP_PRIVOPC(ctx);
5693 #else
5694 if (unlikely(!ctx->supervisor)) {
5695 GEN_EXCP_PRIVOPC(ctx);
5696 return;
5697 }
5698 switch (rB(ctx->opcode)) {
5699 case 0:
5700 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5701 gen_op_4xx_tlbre_hi();
5702 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5703 break;
5704 case 1:
5705 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5706 gen_op_4xx_tlbre_lo();
5707 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5708 break;
5709 default:
5710 GEN_EXCP_INVAL(ctx);
5711 break;
5712 }
5713 #endif
5714 }
5715
5716 /* tlbsx - tlbsx. */
5717 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5718 {
5719 #if defined(CONFIG_USER_ONLY)
5720 GEN_EXCP_PRIVOPC(ctx);
5721 #else
5722 if (unlikely(!ctx->supervisor)) {
5723 GEN_EXCP_PRIVOPC(ctx);
5724 return;
5725 }
5726 gen_addr_reg_index(cpu_T[0], ctx);
5727 gen_op_4xx_tlbsx();
5728 if (Rc(ctx->opcode))
5729 gen_op_4xx_tlbsx_check();
5730 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5731 #endif
5732 }
5733
5734 /* tlbwe */
5735 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5736 {
5737 #if defined(CONFIG_USER_ONLY)
5738 GEN_EXCP_PRIVOPC(ctx);
5739 #else
5740 if (unlikely(!ctx->supervisor)) {
5741 GEN_EXCP_PRIVOPC(ctx);
5742 return;
5743 }
5744 switch (rB(ctx->opcode)) {
5745 case 0:
5746 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5747 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5748 gen_op_4xx_tlbwe_hi();
5749 break;
5750 case 1:
5751 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5752 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5753 gen_op_4xx_tlbwe_lo();
5754 break;
5755 default:
5756 GEN_EXCP_INVAL(ctx);
5757 break;
5758 }
5759 #endif
5760 }
5761
5762 /* TLB management - PowerPC 440 implementation */
5763 /* tlbre */
5764 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5765 {
5766 #if defined(CONFIG_USER_ONLY)
5767 GEN_EXCP_PRIVOPC(ctx);
5768 #else
5769 if (unlikely(!ctx->supervisor)) {
5770 GEN_EXCP_PRIVOPC(ctx);
5771 return;
5772 }
5773 switch (rB(ctx->opcode)) {
5774 case 0:
5775 case 1:
5776 case 2:
5777 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5778 gen_op_440_tlbre(rB(ctx->opcode));
5779 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5780 break;
5781 default:
5782 GEN_EXCP_INVAL(ctx);
5783 break;
5784 }
5785 #endif
5786 }
5787
5788 /* tlbsx - tlbsx. */
5789 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5790 {
5791 #if defined(CONFIG_USER_ONLY)
5792 GEN_EXCP_PRIVOPC(ctx);
5793 #else
5794 if (unlikely(!ctx->supervisor)) {
5795 GEN_EXCP_PRIVOPC(ctx);
5796 return;
5797 }
5798 gen_addr_reg_index(cpu_T[0], ctx);
5799 gen_op_440_tlbsx();
5800 if (Rc(ctx->opcode))
5801 gen_op_4xx_tlbsx_check();
5802 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5803 #endif
5804 }
5805
5806 /* tlbwe */
5807 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5808 {
5809 #if defined(CONFIG_USER_ONLY)
5810 GEN_EXCP_PRIVOPC(ctx);
5811 #else
5812 if (unlikely(!ctx->supervisor)) {
5813 GEN_EXCP_PRIVOPC(ctx);
5814 return;
5815 }
5816 switch (rB(ctx->opcode)) {
5817 case 0:
5818 case 1:
5819 case 2:
5820 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5821 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5822 gen_op_440_tlbwe(rB(ctx->opcode));
5823 break;
5824 default:
5825 GEN_EXCP_INVAL(ctx);
5826 break;
5827 }
5828 #endif
5829 }
5830
5831 /* wrtee */
5832 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5833 {
5834 #if defined(CONFIG_USER_ONLY)
5835 GEN_EXCP_PRIVOPC(ctx);
5836 #else
5837 if (unlikely(!ctx->supervisor)) {
5838 GEN_EXCP_PRIVOPC(ctx);
5839 return;
5840 }
5841 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
5842 gen_op_wrte();
5843 /* Stop translation to have a chance to raise an exception
5844 * if we just set msr_ee to 1
5845 */
5846 GEN_STOP(ctx);
5847 #endif
5848 }
5849
5850 /* wrteei */
5851 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5852 {
5853 #if defined(CONFIG_USER_ONLY)
5854 GEN_EXCP_PRIVOPC(ctx);
5855 #else
5856 if (unlikely(!ctx->supervisor)) {
5857 GEN_EXCP_PRIVOPC(ctx);
5858 return;
5859 }
5860 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
5861 gen_op_wrte();
5862 /* Stop translation to have a chance to raise an exception
5863 * if we just set msr_ee to 1
5864 */
5865 GEN_STOP(ctx);
5866 #endif
5867 }
5868
5869 /* PowerPC 440 specific instructions */
5870 /* dlmzb */
5871 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5872 {
5873 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5874 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
5875 gen_op_440_dlmzb();
5876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
5877 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5878 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
5879 if (Rc(ctx->opcode)) {
5880 gen_op_440_dlmzb_update_Rc();
5881 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]);
5882 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf);
5883 }
5884 }
5885
5886 /* mbar replaces eieio on 440 */
5887 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5888 {
5889 /* interpreted as no-op */
5890 }
5891
5892 /* msync replaces sync on 440 */
5893 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5894 {
5895 /* interpreted as no-op */
5896 }
5897
5898 /* icbt */
5899 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5900 {
5901 /* interpreted as no-op */
5902 /* XXX: specification say this is treated as a load by the MMU
5903 * but does not generate any exception
5904 */
5905 }
5906
5907 /*** Altivec vector extension ***/
5908 /* Altivec registers moves */
5909
5910 #define GEN_VR_LDX(name, opc2, opc3) \
5911 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5912 { \
5913 TCGv EA; \
5914 if (unlikely(!ctx->altivec_enabled)) { \
5915 GEN_EXCP_NO_VR(ctx); \
5916 return; \
5917 } \
5918 EA = tcg_temp_new(); \
5919 gen_addr_reg_index(EA, ctx); \
5920 tcg_gen_andi_tl(EA, EA, ~0xf); \
5921 if (ctx->mem_idx & 1) { \
5922 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5923 tcg_gen_addi_tl(EA, EA, 8); \
5924 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5925 } else { \
5926 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5927 tcg_gen_addi_tl(EA, EA, 8); \
5928 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5929 } \
5930 tcg_temp_free(EA); \
5931 }
5932
5933 #define GEN_VR_STX(name, opc2, opc3) \
5934 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5935 { \
5936 TCGv EA; \
5937 if (unlikely(!ctx->altivec_enabled)) { \
5938 GEN_EXCP_NO_VR(ctx); \
5939 return; \
5940 } \
5941 EA = tcg_temp_new(); \
5942 gen_addr_reg_index(EA, ctx); \
5943 tcg_gen_andi_tl(EA, EA, ~0xf); \
5944 if (ctx->mem_idx & 1) { \
5945 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5946 tcg_gen_addi_tl(EA, EA, 8); \
5947 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5948 } else { \
5949 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
5950 tcg_gen_addi_tl(EA, EA, 8); \
5951 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
5952 } \
5953 tcg_temp_free(EA); \
5954 }
5955
5956 GEN_VR_LDX(lvx, 0x07, 0x03);
5957 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5958 GEN_VR_LDX(lvxl, 0x07, 0x0B);
5959
5960 GEN_VR_STX(svx, 0x07, 0x07);
5961 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5962 GEN_VR_STX(svxl, 0x07, 0x0F);
5963
5964 /*** SPE extension ***/
5965 /* Register moves */
5966
5967 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
5968 #if defined(TARGET_PPC64)
5969 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5970 #else
5971 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
5972 #endif
5973 }
5974
5975 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
5976 #if defined(TARGET_PPC64)
5977 tcg_gen_mov_i64(cpu_gpr[reg], t);
5978 #else
5979 TCGv_i64 tmp = tcg_temp_new_i64();
5980 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
5981 tcg_gen_shri_i64(tmp, t, 32);
5982 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5983 tcg_temp_free_i64(tmp);
5984 #endif
5985 }
5986
5987 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5988 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5989 { \
5990 if (Rc(ctx->opcode)) \
5991 gen_##name1(ctx); \
5992 else \
5993 gen_##name0(ctx); \
5994 }
5995
5996 /* Handler for undefined SPE opcodes */
5997 static always_inline void gen_speundef (DisasContext *ctx)
5998 {
5999 GEN_EXCP_INVAL(ctx);
6000 }
6001
6002 /* SPE logic */
6003 #if defined(TARGET_PPC64)
6004 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6005 static always_inline void gen_##name (DisasContext *ctx) \
6006 { \
6007 if (unlikely(!ctx->spe_enabled)) { \
6008 GEN_EXCP_NO_AP(ctx); \
6009 return; \
6010 } \
6011 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6012 cpu_gpr[rB(ctx->opcode)]); \
6013 }
6014 #else
6015 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6016 static always_inline void gen_##name (DisasContext *ctx) \
6017 { \
6018 if (unlikely(!ctx->spe_enabled)) { \
6019 GEN_EXCP_NO_AP(ctx); \
6020 return; \
6021 } \
6022 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6023 cpu_gpr[rB(ctx->opcode)]); \
6024 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6025 cpu_gprh[rB(ctx->opcode)]); \
6026 }
6027 #endif
6028
6029 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6030 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6031 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6032 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6033 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6034 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6035 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6036 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6037
6038 /* SPE logic immediate */
6039 #if defined(TARGET_PPC64)
6040 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6041 static always_inline void gen_##name (DisasContext *ctx) \
6042 { \
6043 if (unlikely(!ctx->spe_enabled)) { \
6044 GEN_EXCP_NO_AP(ctx); \
6045 return; \
6046 } \
6047 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6048 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6049 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6050 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6051 tcg_opi(t0, t0, rB(ctx->opcode)); \
6052 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6053 tcg_gen_trunc_i64_i32(t1, t2); \
6054 tcg_temp_free_i64(t2); \
6055 tcg_opi(t1, t1, rB(ctx->opcode)); \
6056 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6057 tcg_temp_free_i32(t0); \
6058 tcg_temp_free_i32(t1); \
6059 }
6060 #else
6061 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6062 static always_inline void gen_##name (DisasContext *ctx) \
6063 { \
6064 if (unlikely(!ctx->spe_enabled)) { \
6065 GEN_EXCP_NO_AP(ctx); \
6066 return; \
6067 } \
6068 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6069 rB(ctx->opcode)); \
6070 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6071 rB(ctx->opcode)); \
6072 }
6073 #endif
6074 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6075 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6076 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6077 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6078
6079 /* SPE arithmetic */
6080 #if defined(TARGET_PPC64)
6081 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6082 static always_inline void gen_##name (DisasContext *ctx) \
6083 { \
6084 if (unlikely(!ctx->spe_enabled)) { \
6085 GEN_EXCP_NO_AP(ctx); \
6086 return; \
6087 } \
6088 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6089 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6090 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6091 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6092 tcg_op(t0, t0); \
6093 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6094 tcg_gen_trunc_i64_i32(t1, t2); \
6095 tcg_temp_free_i64(t2); \
6096 tcg_op(t1, t1); \
6097 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6098 tcg_temp_free_i32(t0); \
6099 tcg_temp_free_i32(t1); \
6100 }
6101 #else
6102 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6103 static always_inline void gen_##name (DisasContext *ctx) \
6104 { \
6105 if (unlikely(!ctx->spe_enabled)) { \
6106 GEN_EXCP_NO_AP(ctx); \
6107 return; \
6108 } \
6109 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6110 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6111 }
6112 #endif
6113
6114 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6115 {
6116 int l1 = gen_new_label();
6117 int l2 = gen_new_label();
6118
6119 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6120 tcg_gen_neg_i32(ret, arg1);
6121 tcg_gen_br(l2);
6122 gen_set_label(l1);
6123 tcg_gen_mov_i32(ret, arg1);
6124 gen_set_label(l2);
6125 }
6126 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6127 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6128 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6129 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6130 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6131 {
6132 tcg_gen_addi_i32(ret, arg1, 0x8000);
6133 tcg_gen_ext16u_i32(ret, ret);
6134 }
6135 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6136 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6137 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6138
6139 #if defined(TARGET_PPC64)
6140 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6141 static always_inline void gen_##name (DisasContext *ctx) \
6142 { \
6143 if (unlikely(!ctx->spe_enabled)) { \
6144 GEN_EXCP_NO_AP(ctx); \
6145 return; \
6146 } \
6147 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6148 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6149 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6150 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
6151 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6152 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6153 tcg_op(t0, t0, t2); \
6154 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6155 tcg_gen_trunc_i64_i32(t1, t3); \
6156 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6157 tcg_gen_trunc_i64_i32(t2, t3); \
6158 tcg_temp_free_i64(t3); \
6159 tcg_op(t1, t1, t2); \
6160 tcg_temp_free_i32(t2); \
6161 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6162 tcg_temp_free_i32(t0); \
6163 tcg_temp_free_i32(t1); \
6164 }
6165 #else
6166 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6167 static always_inline void gen_##name (DisasContext *ctx) \
6168 { \
6169 if (unlikely(!ctx->spe_enabled)) { \
6170 GEN_EXCP_NO_AP(ctx); \
6171 return; \
6172 } \
6173 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6174 cpu_gpr[rB(ctx->opcode)]); \
6175 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6176 cpu_gprh[rB(ctx->opcode)]); \
6177 }
6178 #endif
6179
6180 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6181 {
6182 TCGv_i32 t0;
6183 int l1, l2;
6184
6185 l1 = gen_new_label();
6186 l2 = gen_new_label();
6187 t0 = tcg_temp_local_new_i32();
6188 /* No error here: 6 bits are used */
6189 tcg_gen_andi_i32(t0, arg2, 0x3F);
6190 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6191 tcg_gen_shr_i32(ret, arg1, t0);
6192 tcg_gen_br(l2);
6193 gen_set_label(l1);
6194 tcg_gen_movi_i32(ret, 0);
6195 tcg_gen_br(l2);
6196 tcg_temp_free_i32(t0);
6197 }
6198 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6199 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6200 {
6201 TCGv_i32 t0;
6202 int l1, l2;
6203
6204 l1 = gen_new_label();
6205 l2 = gen_new_label();
6206 t0 = tcg_temp_local_new_i32();
6207 /* No error here: 6 bits are used */
6208 tcg_gen_andi_i32(t0, arg2, 0x3F);
6209 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6210 tcg_gen_sar_i32(ret, arg1, t0);
6211 tcg_gen_br(l2);
6212 gen_set_label(l1);
6213 tcg_gen_movi_i32(ret, 0);
6214 tcg_gen_br(l2);
6215 tcg_temp_free_i32(t0);
6216 }
6217 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6218 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6219 {
6220 TCGv_i32 t0;
6221 int l1, l2;
6222
6223 l1 = gen_new_label();
6224 l2 = gen_new_label();
6225 t0 = tcg_temp_local_new_i32();
6226 /* No error here: 6 bits are used */
6227 tcg_gen_andi_i32(t0, arg2, 0x3F);
6228 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6229 tcg_gen_shl_i32(ret, arg1, t0);
6230 tcg_gen_br(l2);
6231 gen_set_label(l1);
6232 tcg_gen_movi_i32(ret, 0);
6233 tcg_gen_br(l2);
6234 tcg_temp_free_i32(t0);
6235 }
6236 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6237 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6238 {
6239 TCGv_i32 t0 = tcg_temp_new_i32();
6240 tcg_gen_andi_i32(t0, arg2, 0x1F);
6241 tcg_gen_rotl_i32(ret, arg1, t0);
6242 tcg_temp_free_i32(t0);
6243 }
6244 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6245 static always_inline void gen_evmergehi (DisasContext *ctx)
6246 {
6247 if (unlikely(!ctx->spe_enabled)) {
6248 GEN_EXCP_NO_AP(ctx);
6249 return;
6250 }
6251 #if defined(TARGET_PPC64)
6252 TCGv t0 = tcg_temp_new();
6253 TCGv t1 = tcg_temp_new();
6254 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6255 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6256 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6257 tcg_temp_free(t0);
6258 tcg_temp_free(t1);
6259 #else
6260 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6261 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6262 #endif
6263 }
6264 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6265 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6266 {
6267 tcg_gen_sub_i32(ret, arg2, arg1);
6268 }
6269 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6270
6271 /* SPE arithmetic immediate */
6272 #if defined(TARGET_PPC64)
6273 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6274 static always_inline void gen_##name (DisasContext *ctx) \
6275 { \
6276 if (unlikely(!ctx->spe_enabled)) { \
6277 GEN_EXCP_NO_AP(ctx); \
6278 return; \
6279 } \
6280 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6281 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6282 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6283 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6284 tcg_op(t0, t0, rA(ctx->opcode)); \
6285 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6286 tcg_gen_trunc_i64_i32(t1, t2); \
6287 tcg_temp_free_i64(t2); \
6288 tcg_op(t1, t1, rA(ctx->opcode)); \
6289 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6290 tcg_temp_free_i32(t0); \
6291 tcg_temp_free_i32(t1); \
6292 }
6293 #else
6294 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6295 static always_inline void gen_##name (DisasContext *ctx) \
6296 { \
6297 if (unlikely(!ctx->spe_enabled)) { \
6298 GEN_EXCP_NO_AP(ctx); \
6299 return; \
6300 } \
6301 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6302 rA(ctx->opcode)); \
6303 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6304 rA(ctx->opcode)); \
6305 }
6306 #endif
6307 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6308 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6309
6310 /* SPE comparison */
6311 #if defined(TARGET_PPC64)
6312 #define GEN_SPEOP_COMP(name, tcg_cond) \
6313 static always_inline void gen_##name (DisasContext *ctx) \
6314 { \
6315 if (unlikely(!ctx->spe_enabled)) { \
6316 GEN_EXCP_NO_AP(ctx); \
6317 return; \
6318 } \
6319 int l1 = gen_new_label(); \
6320 int l2 = gen_new_label(); \
6321 int l3 = gen_new_label(); \
6322 int l4 = gen_new_label(); \
6323 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6324 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6325 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6326 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6327 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6328 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6329 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6330 tcg_gen_br(l2); \
6331 gen_set_label(l1); \
6332 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6333 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6334 gen_set_label(l2); \
6335 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6336 tcg_gen_trunc_i64_i32(t0, t2); \
6337 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6338 tcg_gen_trunc_i64_i32(t1, t2); \
6339 tcg_temp_free_i64(t2); \
6340 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6341 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6342 ~(CRF_CH | CRF_CH_AND_CL)); \
6343 tcg_gen_br(l4); \
6344 gen_set_label(l3); \
6345 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6346 CRF_CH | CRF_CH_OR_CL); \
6347 gen_set_label(l4); \
6348 tcg_temp_free_i32(t0); \
6349 tcg_temp_free_i32(t1); \
6350 }
6351 #else
6352 #define GEN_SPEOP_COMP(name, tcg_cond) \
6353 static always_inline void gen_##name (DisasContext *ctx) \
6354 { \
6355 if (unlikely(!ctx->spe_enabled)) { \
6356 GEN_EXCP_NO_AP(ctx); \
6357 return; \
6358 } \
6359 int l1 = gen_new_label(); \
6360 int l2 = gen_new_label(); \
6361 int l3 = gen_new_label(); \
6362 int l4 = gen_new_label(); \
6363 \
6364 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6365 cpu_gpr[rB(ctx->opcode)], l1); \
6366 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6367 tcg_gen_br(l2); \
6368 gen_set_label(l1); \
6369 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6370 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6371 gen_set_label(l2); \
6372 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6373 cpu_gprh[rB(ctx->opcode)], l3); \
6374 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6375 ~(CRF_CH | CRF_CH_AND_CL)); \
6376 tcg_gen_br(l4); \
6377 gen_set_label(l3); \
6378 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6379 CRF_CH | CRF_CH_OR_CL); \
6380 gen_set_label(l4); \
6381 }
6382 #endif
6383 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6384 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6385 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6386 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6387 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6388
6389 /* SPE misc */
6390 static always_inline void gen_brinc (DisasContext *ctx)
6391 {
6392 /* Note: brinc is usable even if SPE is disabled */
6393 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6394 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6395 }
6396 static always_inline void gen_evmergelo (DisasContext *ctx)
6397 {
6398 if (unlikely(!ctx->spe_enabled)) {
6399 GEN_EXCP_NO_AP(ctx);
6400 return;
6401 }
6402 #if defined(TARGET_PPC64)
6403 TCGv t0 = tcg_temp_new();
6404 TCGv t1 = tcg_temp_new();
6405 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6406 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6407 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6408 tcg_temp_free(t0);
6409 tcg_temp_free(t1);
6410 #else
6411 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6412 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6413 #endif
6414 }
6415 static always_inline void gen_evmergehilo (DisasContext *ctx)
6416 {
6417 if (unlikely(!ctx->spe_enabled)) {
6418 GEN_EXCP_NO_AP(ctx);
6419 return;
6420 }
6421 #if defined(TARGET_PPC64)
6422 TCGv t0 = tcg_temp_new();
6423 TCGv t1 = tcg_temp_new();
6424 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6425 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6426 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6427 tcg_temp_free(t0);
6428 tcg_temp_free(t1);
6429 #else
6430 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6431 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6432 #endif
6433 }
6434 static always_inline void gen_evmergelohi (DisasContext *ctx)
6435 {
6436 if (unlikely(!ctx->spe_enabled)) {
6437 GEN_EXCP_NO_AP(ctx);
6438 return;
6439 }
6440 #if defined(TARGET_PPC64)
6441 TCGv t0 = tcg_temp_new();
6442 TCGv t1 = tcg_temp_new();
6443 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6444 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6445 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6446 tcg_temp_free(t0);
6447 tcg_temp_free(t1);
6448 #else
6449 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6450 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6451 #endif
6452 }
6453 static always_inline void gen_evsplati (DisasContext *ctx)
6454 {
6455 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
6456
6457 #if defined(TARGET_PPC64)
6458 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6459 #else
6460 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6461 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6462 #endif
6463 }
6464 static always_inline void gen_evsplatfi (DisasContext *ctx)
6465 {
6466 uint64_t imm = rA(ctx->opcode) << 11;
6467
6468 #if defined(TARGET_PPC64)
6469 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6470 #else
6471 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6472 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6473 #endif
6474 }
6475
6476 static always_inline void gen_evsel (DisasContext *ctx)
6477 {
6478 int l1 = gen_new_label();
6479 int l2 = gen_new_label();
6480 int l3 = gen_new_label();
6481 int l4 = gen_new_label();
6482 TCGv_i32 t0 = tcg_temp_local_new_i32();
6483 #if defined(TARGET_PPC64)
6484 TCGv t1 = tcg_temp_local_new();
6485 TCGv t2 = tcg_temp_local_new();
6486 #endif
6487 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6488 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6489 #if defined(TARGET_PPC64)
6490 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6491 #else
6492 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6493 #endif
6494 tcg_gen_br(l2);
6495 gen_set_label(l1);
6496 #if defined(TARGET_PPC64)
6497 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6498 #else
6499 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6500 #endif
6501 gen_set_label(l2);
6502 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6503 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6504 #if defined(TARGET_PPC64)
6505 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6506 #else
6507 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6508 #endif
6509 tcg_gen_br(l4);
6510 gen_set_label(l3);
6511 #if defined(TARGET_PPC64)
6512 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6513 #else
6514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6515 #endif
6516 gen_set_label(l4);
6517 tcg_temp_free_i32(t0);
6518 #if defined(TARGET_PPC64)
6519 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6520 tcg_temp_free(t1);
6521 tcg_temp_free(t2);
6522 #endif
6523 }
6524 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6525 {
6526 gen_evsel(ctx);
6527 }
6528 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6529 {
6530 gen_evsel(ctx);
6531 }
6532 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6533 {
6534 gen_evsel(ctx);
6535 }
6536 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6537 {
6538 gen_evsel(ctx);
6539 }
6540
6541 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6542 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6543 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6544 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6545 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6546 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6547 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6548 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6549 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6550 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6551 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6552 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6553 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6554 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6555 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6556 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6557 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6558 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6559 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6560 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6561 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6562 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6563 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6564 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6565 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6566
6567 /* SPE load and stores */
6568 static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6569 {
6570 target_ulong uimm = rB(ctx->opcode);
6571
6572 if (rA(ctx->opcode) == 0)
6573 tcg_gen_movi_tl(EA, uimm << sh);
6574 else
6575 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
6576 }
6577
6578 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6579 {
6580 #if defined(TARGET_PPC64)
6581 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6582 #else
6583 TCGv_i64 t0 = tcg_temp_new_i64();
6584 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6585 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6586 tcg_gen_shri_i64(t0, t0, 32);
6587 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6588 tcg_temp_free_i64(t0);
6589 #endif
6590 }
6591
6592 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6593 {
6594 #if defined(TARGET_PPC64)
6595 TCGv t0 = tcg_temp_new();
6596 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6597 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6598 tcg_gen_addi_tl(addr, addr, 4);
6599 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6600 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6601 tcg_temp_free(t0);
6602 #else
6603 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6604 tcg_gen_addi_tl(addr, addr, 4);
6605 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6606 #endif
6607 }
6608
6609 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6610 {
6611 TCGv t0 = tcg_temp_new();
6612 #if defined(TARGET_PPC64)
6613 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6614 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6615 tcg_gen_addi_tl(addr, addr, 2);
6616 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6617 tcg_gen_shli_tl(t0, t0, 32);
6618 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6619 tcg_gen_addi_tl(addr, addr, 2);
6620 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6621 tcg_gen_shli_tl(t0, t0, 16);
6622 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6623 tcg_gen_addi_tl(addr, addr, 2);
6624 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6625 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6626 #else
6627 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6628 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6629 tcg_gen_addi_tl(addr, addr, 2);
6630 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6631 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6632 tcg_gen_addi_tl(addr, addr, 2);
6633 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6634 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6635 tcg_gen_addi_tl(addr, addr, 2);
6636 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6637 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6638 #endif
6639 tcg_temp_free(t0);
6640 }
6641
6642 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6643 {
6644 TCGv t0 = tcg_temp_new();
6645 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6646 #if defined(TARGET_PPC64)
6647 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6648 tcg_gen_shli_tl(t0, t0, 16);
6649 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6650 #else
6651 tcg_gen_shli_tl(t0, t0, 16);
6652 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6653 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6654 #endif
6655 tcg_temp_free(t0);
6656 }
6657
6658 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6659 {
6660 TCGv t0 = tcg_temp_new();
6661 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6662 #if defined(TARGET_PPC64)
6663 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6664 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6665 #else
6666 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6667 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6668 #endif
6669 tcg_temp_free(t0);
6670 }
6671
6672 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6673 {
6674 TCGv t0 = tcg_temp_new();
6675 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6676 #if defined(TARGET_PPC64)
6677 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6678 tcg_gen_ext32u_tl(t0, t0);
6679 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6680 #else
6681 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6682 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6683 #endif
6684 tcg_temp_free(t0);
6685 }
6686
6687 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6688 {
6689 TCGv t0 = tcg_temp_new();
6690 #if defined(TARGET_PPC64)
6691 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6692 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6693 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6694 tcg_gen_shli_tl(t0, t0, 16);
6695 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6696 #else
6697 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6698 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6699 tcg_gen_addi_tl(addr, addr, 2);
6700 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6701 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6702 #endif
6703 tcg_temp_free(t0);
6704 }
6705
6706 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6707 {
6708 #if defined(TARGET_PPC64)
6709 TCGv t0 = tcg_temp_new();
6710 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6711 tcg_gen_addi_tl(addr, addr, 2);
6712 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6713 tcg_gen_shli_tl(t0, t0, 32);
6714 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6715 tcg_temp_free(t0);
6716 #else
6717 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6718 tcg_gen_addi_tl(addr, addr, 2);
6719 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6720 #endif
6721 }
6722
6723 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6724 {
6725 #if defined(TARGET_PPC64)
6726 TCGv t0 = tcg_temp_new();
6727 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6728 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6729 tcg_gen_addi_tl(addr, addr, 2);
6730 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6731 tcg_gen_shli_tl(t0, t0, 32);
6732 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6733 tcg_temp_free(t0);
6734 #else
6735 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6736 tcg_gen_addi_tl(addr, addr, 2);
6737 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6738 #endif
6739 }
6740
6741 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6742 {
6743 TCGv t0 = tcg_temp_new();
6744 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6745 #if defined(TARGET_PPC64)
6746 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6747 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6748 #else
6749 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6750 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6751 #endif
6752 tcg_temp_free(t0);
6753 }
6754
6755 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6756 {
6757 TCGv t0 = tcg_temp_new();
6758 #if defined(TARGET_PPC64)
6759 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6760 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6761 tcg_gen_shli_tl(t0, t0, 32);
6762 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6763 tcg_gen_addi_tl(addr, addr, 2);
6764 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6765 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6766 tcg_gen_shli_tl(t0, t0, 16);
6767 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6768 #else
6769 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6770 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6771 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6772 tcg_gen_addi_tl(addr, addr, 2);
6773 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6774 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6775 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6776 #endif
6777 tcg_temp_free(t0);
6778 }
6779
6780 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6781 {
6782 #if defined(TARGET_PPC64)
6783 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6784 #else
6785 TCGv_i64 t0 = tcg_temp_new_i64();
6786 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6787 gen_qemu_st64(t0, addr, ctx->mem_idx);
6788 tcg_temp_free_i64(t0);
6789 #endif
6790 }
6791
6792 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6793 {
6794 #if defined(TARGET_PPC64)
6795 TCGv t0 = tcg_temp_new();
6796 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6797 gen_qemu_st32(t0, addr, ctx->mem_idx);
6798 tcg_temp_free(t0);
6799 #else
6800 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6801 #endif
6802 tcg_gen_addi_tl(addr, addr, 4);
6803 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6804 }
6805
6806 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6807 {
6808 TCGv t0 = tcg_temp_new();
6809 #if defined(TARGET_PPC64)
6810 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6811 #else
6812 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6813 #endif
6814 gen_qemu_st16(t0, addr, ctx->mem_idx);
6815 tcg_gen_addi_tl(addr, addr, 2);
6816 #if defined(TARGET_PPC64)
6817 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6818 gen_qemu_st16(t0, addr, ctx->mem_idx);
6819 #else
6820 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6821 #endif
6822 tcg_gen_addi_tl(addr, addr, 2);
6823 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6824 gen_qemu_st16(t0, addr, ctx->mem_idx);
6825 tcg_temp_free(t0);
6826 tcg_gen_addi_tl(addr, addr, 2);
6827 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6828 }
6829
6830 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
6831 {
6832 TCGv t0 = tcg_temp_new();
6833 #if defined(TARGET_PPC64)
6834 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6835 #else
6836 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6837 #endif
6838 gen_qemu_st16(t0, addr, ctx->mem_idx);
6839 tcg_gen_addi_tl(addr, addr, 2);
6840 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6841 gen_qemu_st16(t0, addr, ctx->mem_idx);
6842 tcg_temp_free(t0);
6843 }
6844
6845 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
6846 {
6847 #if defined(TARGET_PPC64)
6848 TCGv t0 = tcg_temp_new();
6849 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6850 gen_qemu_st16(t0, addr, ctx->mem_idx);
6851 tcg_temp_free(t0);
6852 #else
6853 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6854 #endif
6855 tcg_gen_addi_tl(addr, addr, 2);
6856 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6857 }
6858
6859 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
6860 {
6861 #if defined(TARGET_PPC64)
6862 TCGv t0 = tcg_temp_new();
6863 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6864 gen_qemu_st32(t0, addr, ctx->mem_idx);
6865 tcg_temp_free(t0);
6866 #else
6867 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6868 #endif
6869 }
6870
6871 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
6872 {
6873 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6874 }
6875
6876 #define GEN_SPEOP_LDST(name, opc2, sh) \
6877 GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6878 { \
6879 TCGv t0; \
6880 if (unlikely(!ctx->spe_enabled)) { \
6881 GEN_EXCP_NO_AP(ctx); \
6882 return; \
6883 } \
6884 t0 = tcg_temp_new(); \
6885 if (Rc(ctx->opcode)) { \
6886 gen_addr_spe_imm_index(t0, ctx, sh); \
6887 } else { \
6888 gen_addr_reg_index(t0, ctx); \
6889 } \
6890 gen_op_##name(ctx, t0); \
6891 tcg_temp_free(t0); \
6892 }
6893
6894 GEN_SPEOP_LDST(evldd, 0x00, 3);
6895 GEN_SPEOP_LDST(evldw, 0x01, 3);
6896 GEN_SPEOP_LDST(evldh, 0x02, 3);
6897 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
6898 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
6899 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
6900 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
6901 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
6902 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
6903 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
6904 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
6905
6906 GEN_SPEOP_LDST(evstdd, 0x10, 3);
6907 GEN_SPEOP_LDST(evstdw, 0x11, 3);
6908 GEN_SPEOP_LDST(evstdh, 0x12, 3);
6909 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
6910 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
6911 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
6912 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
6913
6914 /* Multiply and add - TODO */
6915 #if 0
6916 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6917 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6918 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6919 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6920 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6921 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6922 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6923 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6924 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6925 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6926 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6927 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6928
6929 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6930 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6931 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6932 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6933 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6934 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6935 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6936 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6937 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6938 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6939 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6940 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6941 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6942 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6943
6944 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6945 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6946 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6947 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6948 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6949 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6950
6951 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6952 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6953 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6954 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6955 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6956 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6957 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6958 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6959 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6960 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6961 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6962 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6963
6964 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6965 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6966 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6967 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6968 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6969
6970 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6971 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6972 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6973 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6974 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6975 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6976 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6977 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6978 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6979 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6980 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6981 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6982
6983 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6984 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6985 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6986 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6987 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6988 #endif
6989
6990 /*** SPE floating-point extension ***/
6991 #if defined(TARGET_PPC64)
6992 #define GEN_SPEFPUOP_CONV_32_32(name) \
6993 static always_inline void gen_##name (DisasContext *ctx) \
6994 { \
6995 TCGv_i32 t0; \
6996 TCGv t1; \
6997 t0 = tcg_temp_new_i32(); \
6998 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6999 gen_helper_##name(t0, t0); \
7000 t1 = tcg_temp_new(); \
7001 tcg_gen_extu_i32_tl(t1, t0); \
7002 tcg_temp_free_i32(t0); \
7003 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7004 0xFFFFFFFF00000000ULL); \
7005 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7006 tcg_temp_free(t1); \
7007 }
7008 #define GEN_SPEFPUOP_CONV_32_64(name) \
7009 static always_inline void gen_##name (DisasContext *ctx) \
7010 { \
7011 TCGv_i32 t0; \
7012 TCGv t1; \
7013 t0 = tcg_temp_new_i32(); \
7014 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7015 t1 = tcg_temp_new(); \
7016 tcg_gen_extu_i32_tl(t1, t0); \
7017 tcg_temp_free_i32(t0); \
7018 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7019 0xFFFFFFFF00000000ULL); \
7020 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7021 tcg_temp_free(t1); \
7022 }
7023 #define GEN_SPEFPUOP_CONV_64_32(name) \
7024 static always_inline void gen_##name (DisasContext *ctx) \
7025 { \
7026 TCGv_i32 t0 = tcg_temp_new_i32(); \
7027 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7028 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7029 tcg_temp_free_i32(t0); \
7030 }
7031 #define GEN_SPEFPUOP_CONV_64_64(name) \
7032 static always_inline void gen_##name (DisasContext *ctx) \
7033 { \
7034 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7035 }
7036 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7037 static always_inline void gen_##name (DisasContext *ctx) \
7038 { \
7039 TCGv_i32 t0, t1; \
7040 TCGv_i64 t2; \
7041 if (unlikely(!ctx->spe_enabled)) { \
7042 GEN_EXCP_NO_AP(ctx); \
7043 return; \
7044 } \
7045 t0 = tcg_temp_new_i32(); \
7046 t1 = tcg_temp_new_i32(); \
7047 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7048 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7049 gen_helper_##name(t0, t0, t1); \
7050 tcg_temp_free_i32(t1); \
7051 t2 = tcg_temp_new(); \
7052 tcg_gen_extu_i32_tl(t2, t0); \
7053 tcg_temp_free_i32(t0); \
7054 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7055 0xFFFFFFFF00000000ULL); \
7056 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7057 tcg_temp_free(t2); \
7058 }
7059 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7060 static always_inline void gen_##name (DisasContext *ctx) \
7061 { \
7062 if (unlikely(!ctx->spe_enabled)) { \
7063 GEN_EXCP_NO_AP(ctx); \
7064 return; \
7065 } \
7066 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7067 cpu_gpr[rB(ctx->opcode)]); \
7068 }
7069 #define GEN_SPEFPUOP_COMP_32(name) \
7070 static always_inline void gen_##name (DisasContext *ctx) \
7071 { \
7072 TCGv_i32 t0, t1; \
7073 if (unlikely(!ctx->spe_enabled)) { \
7074 GEN_EXCP_NO_AP(ctx); \
7075 return; \
7076 } \
7077 t0 = tcg_temp_new_i32(); \
7078 t1 = tcg_temp_new_i32(); \
7079 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7080 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7081 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7082 tcg_temp_free_i32(t0); \
7083 tcg_temp_free_i32(t1); \
7084 }
7085 #define GEN_SPEFPUOP_COMP_64(name) \
7086 static always_inline void gen_##name (DisasContext *ctx) \
7087 { \
7088 if (unlikely(!ctx->spe_enabled)) { \
7089 GEN_EXCP_NO_AP(ctx); \
7090 return; \
7091 } \
7092 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7093 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7094 }
7095 #else
7096 #define GEN_SPEFPUOP_CONV_32_32(name) \
7097 static always_inline void gen_##name (DisasContext *ctx) \
7098 { \
7099 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7100 }
7101 #define GEN_SPEFPUOP_CONV_32_64(name) \
7102 static always_inline void gen_##name (DisasContext *ctx) \
7103 { \
7104 TCGv_i64 t0 = tcg_temp_new_i64(); \
7105 gen_load_gpr64(t0, rB(ctx->opcode)); \
7106 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7107 tcg_temp_free_i64(t0); \
7108 }
7109 #define GEN_SPEFPUOP_CONV_64_32(name) \
7110 static always_inline void gen_##name (DisasContext *ctx) \
7111 { \
7112 TCGv_i64 t0 = tcg_temp_new_i64(); \
7113 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7114 gen_store_gpr64(rD(ctx->opcode), t0); \
7115 tcg_temp_free_i64(t0); \
7116 }
7117 #define GEN_SPEFPUOP_CONV_64_64(name) \
7118 static always_inline void gen_##name (DisasContext *ctx) \
7119 { \
7120 TCGv_i64 t0 = tcg_temp_new_i64(); \
7121 gen_load_gpr64(t0, rB(ctx->opcode)); \
7122 gen_helper_##name(t0, t0); \
7123 gen_store_gpr64(rD(ctx->opcode), t0); \
7124 tcg_temp_free_i64(t0); \
7125 }
7126 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7127 static always_inline void gen_##name (DisasContext *ctx) \
7128 { \
7129 if (unlikely(!ctx->spe_enabled)) { \
7130 GEN_EXCP_NO_AP(ctx); \
7131 return; \
7132 } \
7133 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7134 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7135 }
7136 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7137 static always_inline void gen_##name (DisasContext *ctx) \
7138 { \
7139 TCGv_i64 t0, t1; \
7140 if (unlikely(!ctx->spe_enabled)) { \
7141 GEN_EXCP_NO_AP(ctx); \
7142 return; \
7143 } \
7144 t0 = tcg_temp_new_i64(); \
7145 t1 = tcg_temp_new_i64(); \
7146 gen_load_gpr64(t0, rA(ctx->opcode)); \
7147 gen_load_gpr64(t1, rB(ctx->opcode)); \
7148 gen_helper_##name(t0, t0, t1); \
7149 gen_store_gpr64(rD(ctx->opcode), t0); \
7150 tcg_temp_free_i64(t0); \
7151 tcg_temp_free_i64(t1); \
7152 }
7153 #define GEN_SPEFPUOP_COMP_32(name) \
7154 static always_inline void gen_##name (DisasContext *ctx) \
7155 { \
7156 if (unlikely(!ctx->spe_enabled)) { \
7157 GEN_EXCP_NO_AP(ctx); \
7158 return; \
7159 } \
7160 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7162 }
7163 #define GEN_SPEFPUOP_COMP_64(name) \
7164 static always_inline void gen_##name (DisasContext *ctx) \
7165 { \
7166 TCGv_i64 t0, t1; \
7167 if (unlikely(!ctx->spe_enabled)) { \
7168 GEN_EXCP_NO_AP(ctx); \
7169 return; \
7170 } \
7171 t0 = tcg_temp_new_i64(); \
7172 t1 = tcg_temp_new_i64(); \
7173 gen_load_gpr64(t0, rA(ctx->opcode)); \
7174 gen_load_gpr64(t1, rB(ctx->opcode)); \
7175 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7176 tcg_temp_free_i64(t0); \
7177 tcg_temp_free_i64(t1); \
7178 }
7179 #endif
7180
7181 /* Single precision floating-point vectors operations */
7182 /* Arithmetic */
7183 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7184 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7185 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7186 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7187 static always_inline void gen_evfsabs (DisasContext *ctx)
7188 {
7189 if (unlikely(!ctx->spe_enabled)) {
7190 GEN_EXCP_NO_AP(ctx);
7191 return;
7192 }
7193 #if defined(TARGET_PPC64)
7194 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7195 #else
7196 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7197 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7198 #endif
7199 }
7200 static always_inline void gen_evfsnabs (DisasContext *ctx)
7201 {
7202 if (unlikely(!ctx->spe_enabled)) {
7203 GEN_EXCP_NO_AP(ctx);
7204 return;
7205 }
7206 #if defined(TARGET_PPC64)
7207 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7208 #else
7209 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7210 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7211 #endif
7212 }
7213 static always_inline void gen_evfsneg (DisasContext *ctx)
7214 {
7215 if (unlikely(!ctx->spe_enabled)) {
7216 GEN_EXCP_NO_AP(ctx);
7217 return;
7218 }
7219 #if defined(TARGET_PPC64)
7220 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7221 #else
7222 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7223 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7224 #endif
7225 }
7226
7227 /* Conversion */
7228 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7229 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7230 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7231 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7232 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7233 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7234 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7235 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7236 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7237 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7238
7239 /* Comparison */
7240 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7241 GEN_SPEFPUOP_COMP_64(evfscmplt);
7242 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7243 GEN_SPEFPUOP_COMP_64(evfststgt);
7244 GEN_SPEFPUOP_COMP_64(evfststlt);
7245 GEN_SPEFPUOP_COMP_64(evfststeq);
7246
7247 /* Opcodes definitions */
7248 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7249 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7250 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7251 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7252 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7253 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7254 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7255 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7256 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7257 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7258 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7259 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7260 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7261 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7262
7263 /* Single precision floating-point operations */
7264 /* Arithmetic */
7265 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7266 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7267 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7268 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7269 static always_inline void gen_efsabs (DisasContext *ctx)
7270 {
7271 if (unlikely(!ctx->spe_enabled)) {
7272 GEN_EXCP_NO_AP(ctx);
7273 return;
7274 }
7275 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7276 }
7277 static always_inline void gen_efsnabs (DisasContext *ctx)
7278 {
7279 if (unlikely(!ctx->spe_enabled)) {
7280 GEN_EXCP_NO_AP(ctx);
7281 return;
7282 }
7283 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7284 }
7285 static always_inline void gen_efsneg (DisasContext *ctx)
7286 {
7287 if (unlikely(!ctx->spe_enabled)) {
7288 GEN_EXCP_NO_AP(ctx);
7289 return;
7290 }
7291 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7292 }
7293
7294 /* Conversion */
7295 GEN_SPEFPUOP_CONV_32_32(efscfui);
7296 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7297 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7298 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7299 GEN_SPEFPUOP_CONV_32_32(efsctui);
7300 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7301 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7302 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7303 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7304 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7305 GEN_SPEFPUOP_CONV_32_64(efscfd);
7306
7307 /* Comparison */
7308 GEN_SPEFPUOP_COMP_32(efscmpgt);
7309 GEN_SPEFPUOP_COMP_32(efscmplt);
7310 GEN_SPEFPUOP_COMP_32(efscmpeq);
7311 GEN_SPEFPUOP_COMP_32(efststgt);
7312 GEN_SPEFPUOP_COMP_32(efststlt);
7313 GEN_SPEFPUOP_COMP_32(efststeq);
7314
7315 /* Opcodes definitions */
7316 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
7317 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7318 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7319 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7320 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7321 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7322 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7323 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7324 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7325 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7326 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7327 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
7328 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7329 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7330
7331 /* Double precision floating-point operations */
7332 /* Arithmetic */
7333 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7334 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7335 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7336 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7337 static always_inline void gen_efdabs (DisasContext *ctx)
7338 {
7339 if (unlikely(!ctx->spe_enabled)) {
7340 GEN_EXCP_NO_AP(ctx);
7341 return;
7342 }
7343 #if defined(TARGET_PPC64)
7344 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7345 #else
7346 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7347 #endif
7348 }
7349 static always_inline void gen_efdnabs (DisasContext *ctx)
7350 {
7351 if (unlikely(!ctx->spe_enabled)) {
7352 GEN_EXCP_NO_AP(ctx);
7353 return;
7354 }
7355 #if defined(TARGET_PPC64)
7356 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7357 #else
7358 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7359 #endif
7360 }
7361 static always_inline void gen_efdneg (DisasContext *ctx)
7362 {
7363 if (unlikely(!ctx->spe_enabled)) {
7364 GEN_EXCP_NO_AP(ctx);
7365 return;
7366 }
7367 #if defined(TARGET_PPC64)
7368 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7369 #else
7370 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7371 #endif
7372 }
7373
7374 /* Conversion */
7375 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7376 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7377 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7378 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7379 GEN_SPEFPUOP_CONV_32_64(efdctui);
7380 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7381 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7382 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7383 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7384 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7385 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7386 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7387 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7388 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7389 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7390
7391 /* Comparison */
7392 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7393 GEN_SPEFPUOP_COMP_64(efdcmplt);
7394 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7395 GEN_SPEFPUOP_COMP_64(efdtstgt);
7396 GEN_SPEFPUOP_COMP_64(efdtstlt);
7397 GEN_SPEFPUOP_COMP_64(efdtsteq);
7398
7399 /* Opcodes definitions */
7400 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7401 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7402 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7403 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7404 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7405 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7406 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7407 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7408 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7409 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7410 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7411 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7412 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7413 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7414 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7415 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
7416
7417 /* End opcode list */
7418 GEN_OPCODE_MARK(end);
7419
7420 #include "translate_init.c"
7421 #include "helper_regs.h"
7422
7423 /*****************************************************************************/
7424 /* Misc PowerPC helpers */
7425 void cpu_dump_state (CPUState *env, FILE *f,
7426 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7427 int flags)
7428 {
7429 #define RGPL 4
7430 #define RFPL 4
7431
7432 int i;
7433
7434 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
7435 env->nip, env->lr, env->ctr, env->xer);
7436 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7437 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
7438 #if !defined(NO_TIMER_DUMP)
7439 cpu_fprintf(f, "TB %08x %08x "
7440 #if !defined(CONFIG_USER_ONLY)
7441 "DECR %08x"
7442 #endif
7443 "\n",
7444 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7445 #if !defined(CONFIG_USER_ONLY)
7446 , cpu_ppc_load_decr(env)
7447 #endif
7448 );
7449 #endif
7450 for (i = 0; i < 32; i++) {
7451 if ((i & (RGPL - 1)) == 0)
7452 cpu_fprintf(f, "GPR%02d", i);
7453 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
7454 if ((i & (RGPL - 1)) == (RGPL - 1))
7455 cpu_fprintf(f, "\n");
7456 }
7457 cpu_fprintf(f, "CR ");
7458 for (i = 0; i < 8; i++)
7459 cpu_fprintf(f, "%01x", env->crf[i]);
7460 cpu_fprintf(f, " [");
7461 for (i = 0; i < 8; i++) {
7462 char a = '-';
7463 if (env->crf[i] & 0x08)
7464 a = 'L';
7465 else if (env->crf[i] & 0x04)
7466 a = 'G';
7467 else if (env->crf[i] & 0x02)
7468 a = 'E';
7469 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7470 }
7471 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
7472 for (i = 0; i < 32; i++) {
7473 if ((i & (RFPL - 1)) == 0)
7474 cpu_fprintf(f, "FPR%02d", i);
7475 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7476 if ((i & (RFPL - 1)) == (RFPL - 1))
7477 cpu_fprintf(f, "\n");
7478 }
7479 #if !defined(CONFIG_USER_ONLY)
7480 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
7481 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
7482 #endif
7483
7484 #undef RGPL
7485 #undef RFPL
7486 }
7487
7488 void cpu_dump_statistics (CPUState *env, FILE*f,
7489 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7490 int flags)
7491 {
7492 #if defined(DO_PPC_STATISTICS)
7493 opc_handler_t **t1, **t2, **t3, *handler;
7494 int op1, op2, op3;
7495
7496 t1 = env->opcodes;
7497 for (op1 = 0; op1 < 64; op1++) {
7498 handler = t1[op1];
7499 if (is_indirect_opcode(handler)) {
7500 t2 = ind_table(handler);
7501 for (op2 = 0; op2 < 32; op2++) {
7502 handler = t2[op2];
7503 if (is_indirect_opcode(handler)) {
7504 t3 = ind_table(handler);
7505 for (op3 = 0; op3 < 32; op3++) {
7506 handler = t3[op3];
7507 if (handler->count == 0)
7508 continue;
7509 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7510 "%016llx %lld\n",
7511 op1, op2, op3, op1, (op3 << 5) | op2,
7512 handler->oname,
7513 handler->count, handler->count);
7514 }
7515 } else {
7516 if (handler->count == 0)
7517 continue;
7518 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7519 "%016llx %lld\n",
7520 op1, op2, op1, op2, handler->oname,
7521 handler->count, handler->count);
7522 }
7523 }
7524 } else {
7525 if (handler->count == 0)
7526 continue;
7527 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7528 op1, op1, handler->oname,
7529 handler->count, handler->count);
7530 }
7531 }
7532 #endif
7533 }
7534
7535 /*****************************************************************************/
7536 static always_inline void gen_intermediate_code_internal (CPUState *env,
7537 TranslationBlock *tb,
7538 int search_pc)
7539 {
7540 DisasContext ctx, *ctxp = &ctx;
7541 opc_handler_t **table, *handler;
7542 target_ulong pc_start;
7543 uint16_t *gen_opc_end;
7544 int supervisor, little_endian;
7545 CPUBreakpoint *bp;
7546 int j, lj = -1;
7547 int num_insns;
7548 int max_insns;
7549
7550 pc_start = tb->pc;
7551 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7552 #if defined(OPTIMIZE_FPRF_UPDATE)
7553 gen_fprf_ptr = gen_fprf_buf;
7554 #endif
7555 ctx.nip = pc_start;
7556 ctx.tb = tb;
7557 ctx.exception = POWERPC_EXCP_NONE;
7558 ctx.spr_cb = env->spr_cb;
7559 supervisor = env->mmu_idx;
7560 #if !defined(CONFIG_USER_ONLY)
7561 ctx.supervisor = supervisor;
7562 #endif
7563 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
7564 #if defined(TARGET_PPC64)
7565 ctx.sf_mode = msr_sf;
7566 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
7567 #else
7568 ctx.mem_idx = (supervisor << 1) | little_endian;
7569 #endif
7570 ctx.dcache_line_size = env->dcache_line_size;
7571 ctx.fpu_enabled = msr_fp;
7572 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7573 ctx.spe_enabled = msr_spe;
7574 else
7575 ctx.spe_enabled = 0;
7576 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7577 ctx.altivec_enabled = msr_vr;
7578 else
7579 ctx.altivec_enabled = 0;
7580 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7581 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7582 else
7583 ctx.singlestep_enabled = 0;
7584 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7585 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7586 if (unlikely(env->singlestep_enabled))
7587 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7588 #if defined (DO_SINGLE_STEP) && 0
7589 /* Single step trace mode */
7590 msr_se = 1;
7591 #endif
7592 num_insns = 0;
7593 max_insns = tb->cflags & CF_COUNT_MASK;
7594 if (max_insns == 0)
7595 max_insns = CF_COUNT_MASK;
7596
7597 gen_icount_start();
7598 /* Set env in case of segfault during code fetch */
7599 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
7600 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7601 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7602 if (bp->pc == ctx.nip) {
7603 gen_update_nip(&ctx, ctx.nip);
7604 gen_helper_raise_debug();
7605 break;
7606 }
7607 }
7608 }
7609 if (unlikely(search_pc)) {
7610 j = gen_opc_ptr - gen_opc_buf;
7611 if (lj < j) {
7612 lj++;
7613 while (lj < j)
7614 gen_opc_instr_start[lj++] = 0;
7615 gen_opc_pc[lj] = ctx.nip;
7616 gen_opc_instr_start[lj] = 1;
7617 gen_opc_icount[lj] = num_insns;
7618 }
7619 }
7620 #if defined PPC_DEBUG_DISAS
7621 if (loglevel & CPU_LOG_TB_IN_ASM) {
7622 fprintf(logfile, "----------------\n");
7623 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
7624 ctx.nip, supervisor, (int)msr_ir);
7625 }
7626 #endif
7627 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7628 gen_io_start();
7629 if (unlikely(little_endian)) {
7630 ctx.opcode = bswap32(ldl_code(ctx.nip));
7631 } else {
7632 ctx.opcode = ldl_code(ctx.nip);
7633 }
7634 #if defined PPC_DEBUG_DISAS
7635 if (loglevel & CPU_LOG_TB_IN_ASM) {
7636 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
7637 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7638 opc3(ctx.opcode), little_endian ? "little" : "big");
7639 }
7640 #endif
7641 ctx.nip += 4;
7642 table = env->opcodes;
7643 num_insns++;
7644 handler = table[opc1(ctx.opcode)];
7645 if (is_indirect_opcode(handler)) {
7646 table = ind_table(handler);
7647 handler = table[opc2(ctx.opcode)];
7648 if (is_indirect_opcode(handler)) {
7649 table = ind_table(handler);
7650 handler = table[opc3(ctx.opcode)];
7651 }
7652 }
7653 /* Is opcode *REALLY* valid ? */
7654 if (unlikely(handler->handler == &gen_invalid)) {
7655 if (loglevel != 0) {
7656 fprintf(logfile, "invalid/unsupported opcode: "
7657 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7658 opc1(ctx.opcode), opc2(ctx.opcode),
7659 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7660 } else {
7661 printf("invalid/unsupported opcode: "
7662 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7663 opc1(ctx.opcode), opc2(ctx.opcode),
7664 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7665 }
7666 } else {
7667 if (unlikely((ctx.opcode & handler->inval) != 0)) {
7668 if (loglevel != 0) {
7669 fprintf(logfile, "invalid bits: %08x for opcode: "
7670 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7671 ctx.opcode & handler->inval, opc1(ctx.opcode),
7672 opc2(ctx.opcode), opc3(ctx.opcode),
7673 ctx.opcode, ctx.nip - 4);
7674 } else {
7675 printf("invalid bits: %08x for opcode: "
7676 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7677 ctx.opcode & handler->inval, opc1(ctx.opcode),
7678 opc2(ctx.opcode), opc3(ctx.opcode),
7679 ctx.opcode, ctx.nip - 4);
7680 }
7681 GEN_EXCP_INVAL(ctxp);
7682 break;
7683 }
7684 }
7685 (*(handler->handler))(&ctx);
7686 #if defined(DO_PPC_STATISTICS)
7687 handler->count++;
7688 #endif
7689 /* Check trace mode exceptions */
7690 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7691 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7692 ctx.exception != POWERPC_SYSCALL &&
7693 ctx.exception != POWERPC_EXCP_TRAP &&
7694 ctx.exception != POWERPC_EXCP_BRANCH)) {
7695 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
7696 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7697 (env->singlestep_enabled) ||
7698 num_insns >= max_insns)) {
7699 /* if we reach a page boundary or are single stepping, stop
7700 * generation
7701 */
7702 break;
7703 }
7704 #if defined (DO_SINGLE_STEP)
7705 break;
7706 #endif
7707 }
7708 if (tb->cflags & CF_LAST_IO)
7709 gen_io_end();
7710 if (ctx.exception == POWERPC_EXCP_NONE) {
7711 gen_goto_tb(&ctx, 0, ctx.nip);
7712 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7713 if (unlikely(env->singlestep_enabled)) {
7714 gen_update_nip(&ctx, ctx.nip);
7715 gen_helper_raise_debug();
7716 }
7717 /* Generate the return instruction */
7718 tcg_gen_exit_tb(0);
7719 }
7720 gen_icount_end(tb, num_insns);
7721 *gen_opc_ptr = INDEX_op_end;
7722 if (unlikely(search_pc)) {
7723 j = gen_opc_ptr - gen_opc_buf;
7724 lj++;
7725 while (lj <= j)
7726 gen_opc_instr_start[lj++] = 0;
7727 } else {
7728 tb->size = ctx.nip - pc_start;
7729 tb->icount = num_insns;
7730 }
7731 #if defined(DEBUG_DISAS)
7732 if (loglevel & CPU_LOG_TB_CPU) {
7733 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7734 cpu_dump_state(env, logfile, fprintf, 0);
7735 }
7736 if (loglevel & CPU_LOG_TB_IN_ASM) {
7737 int flags;
7738 flags = env->bfd_mach;
7739 flags |= little_endian << 16;
7740 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7741 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
7742 fprintf(logfile, "\n");
7743 }
7744 #endif
7745 }
7746
7747 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
7748 {
7749 gen_intermediate_code_internal(env, tb, 0);
7750 }
7751
7752 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
7753 {
7754 gen_intermediate_code_internal(env, tb, 1);
7755 }
7756
7757 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7758 unsigned long searched_pc, int pc_pos, void *puc)
7759 {
7760 env->nip = gen_opc_pc[pc_pos];
7761 }