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Fix qemu_ld64 constraint list
[qemu/mini2440/sniper_sniper_test.git] / hw / e1000.c
blob1a14051629deeec93e9aefc342aaecbca85d665e
1 /*
2 * QEMU e1000 emulation
3 *
4 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
5 * Copyright (c) 2008 Qumranet
6 * Based on work done by:
7 * Copyright (c) 2007 Dan Aloni
8 * Copyright (c) 2004 Antony T Curtis
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25
26 #include "hw.h"
27 #include "pci.h"
28 #include "net.h"
29
30 #include "e1000_hw.h"
31
32 #define DEBUG
33
34 #ifdef DEBUG
35 enum {
36 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
37 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
38 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
39 DEBUG_RXFILTER, DEBUG_NOTYET,
40 };
41 #define DBGBIT(x) (1<<DEBUG_##x)
42 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
43
44 #define DBGOUT(what, fmt, params...) do { \
45 if (debugflags & DBGBIT(what)) \
46 fprintf(stderr, "e1000: " fmt, ##params); \
47 } while (0)
48 #else
49 #define DBGOUT(what, fmt, params...) do {} while (0)
50 #endif
51
52 #define IOPORT_SIZE 0x40
53 #define PNPMMIO_SIZE 0x20000
54
55 /*
56 * HW models:
57 * E1000_DEV_ID_82540EM works with Windows and Linux
58 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
59 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
60 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
61 * Others never tested
62 */
63 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
64
65 /*
66 * May need to specify additional MAC-to-PHY entries --
67 * Intel's Windows driver refuses to initialize unless they match
68 */
69 enum {
70 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
71 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
72 /* default to E1000_DEV_ID_82540EM */ 0xc20
73 };
74
75 typedef struct E1000State_st {
76 PCIDevice dev;
77 VLANClientState *vc;
78 NICInfo *nd;
79 uint32_t mmio_base;
80 int mmio_index;
81
82 uint32_t mac_reg[0x8000];
83 uint16_t phy_reg[0x20];
84 uint16_t eeprom_data[64];
85
86 uint32_t rxbuf_size;
87 uint32_t rxbuf_min_shift;
88 int check_rxov;
89 struct e1000_tx {
90 unsigned char header[256];
91 unsigned char data[0x10000];
92 uint16_t size;
93 unsigned char sum_needed;
94 uint8_t ipcss;
95 uint8_t ipcso;
96 uint16_t ipcse;
97 uint8_t tucss;
98 uint8_t tucso;
99 uint16_t tucse;
100 uint8_t hdr_len;
101 uint16_t mss;
102 uint32_t paylen;
103 uint16_t tso_frames;
104 char tse;
105 char ip;
106 char tcp;
107 char cptse; // current packet tse bit
108 } tx;
109
110 struct {
111 uint32_t val_in; // shifted in from guest driver
112 uint16_t bitnum_in;
113 uint16_t bitnum_out;
114 uint16_t reading;
115 uint32_t old_eecd;
116 } eecd_state;
117 } E1000State;
118
119 #define defreg(x) x = (E1000_##x>>2)
120 enum {
121 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
122 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
123 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
124 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
125 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
126 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
127 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
128 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
129 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
130 defreg(RA), defreg(MTA), defreg(CRCERRS),
131 };
132
133 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
134 static char phy_regcap[0x20] = {
135 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
136 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
137 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
138 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
139 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
140 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
141 };
142
143 static void
144 ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
145 uint32_t size, int type)
146 {
147 DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
148 }
149
150 static void
151 set_interrupt_cause(E1000State *s, int index, uint32_t val)
152 {
153 if (val)
154 val |= E1000_ICR_INT_ASSERTED;
155 s->mac_reg[ICR] = val;
156 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
157 }
158
159 static void
160 set_ics(E1000State *s, int index, uint32_t val)
161 {
162 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
163 s->mac_reg[IMS]);
164 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
165 }
166
167 static int
168 rxbufsize(uint32_t v)
169 {
170 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
171 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
172 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
173 switch (v) {
174 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
175 return 16384;
176 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
177 return 8192;
178 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
179 return 4096;
180 case E1000_RCTL_SZ_1024:
181 return 1024;
182 case E1000_RCTL_SZ_512:
183 return 512;
184 case E1000_RCTL_SZ_256:
185 return 256;
186 }
187 return 2048;
188 }
189
190 static void
191 set_rx_control(E1000State *s, int index, uint32_t val)
192 {
193 s->mac_reg[RCTL] = val;
194 s->rxbuf_size = rxbufsize(val);
195 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
196 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
197 s->mac_reg[RCTL]);
198 }
199
200 static void
201 set_mdic(E1000State *s, int index, uint32_t val)
202 {
203 uint32_t data = val & E1000_MDIC_DATA_MASK;
204 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
205
206 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
207 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
208 else if (val & E1000_MDIC_OP_READ) {
209 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
210 if (!(phy_regcap[addr] & PHY_R)) {
211 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
212 val |= E1000_MDIC_ERROR;
213 } else
214 val = (val ^ data) | s->phy_reg[addr];
215 } else if (val & E1000_MDIC_OP_WRITE) {
216 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
217 if (!(phy_regcap[addr] & PHY_W)) {
218 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
219 val |= E1000_MDIC_ERROR;
220 } else
221 s->phy_reg[addr] = data;
222 }
223 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
224 set_ics(s, 0, E1000_ICR_MDAC);
225 }
226
227 static uint32_t
228 get_eecd(E1000State *s, int index)
229 {
230 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
231
232 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
233 s->eecd_state.bitnum_out, s->eecd_state.reading);
234 if (!s->eecd_state.reading ||
235 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
236 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
237 ret |= E1000_EECD_DO;
238 return ret;
239 }
240
241 static void
242 set_eecd(E1000State *s, int index, uint32_t val)
243 {
244 uint32_t oldval = s->eecd_state.old_eecd;
245
246 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
247 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
248 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
249 return;
250 if (!(E1000_EECD_SK & val)) { // falling edge
251 s->eecd_state.bitnum_out++;
252 return;
253 }
254 if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset)
255 memset(&s->eecd_state, 0, sizeof s->eecd_state);
256 return;
257 }
258 s->eecd_state.val_in <<= 1;
259 if (val & E1000_EECD_DI)
260 s->eecd_state.val_in |= 1;
261 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
262 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
263 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
264 EEPROM_READ_OPCODE_MICROWIRE);
265 }
266 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
267 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
268 s->eecd_state.reading);
269 }
270
271 static uint32_t
272 flash_eerd_read(E1000State *s, int x)
273 {
274 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
275
276 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
277 return 0;
278 return (s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
279 E1000_EEPROM_RW_REG_DONE | r;
280 }
281
282 static unsigned int
283 do_cksum(uint8_t *dp, uint8_t *de)
284 {
285 unsigned int bsum[2] = {0, 0}, i, sum;
286
287 for (i = 1; dp < de; bsum[i^=1] += *dp++)
288 ;
289 sum = (bsum[0] << 8) + bsum[1];
290 sum = (sum >> 16) + (sum & 0xffff);
291 return ~(sum + (sum >> 16));
292 }
293
294 static void
295 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
296 {
297 if (cse && cse < n)
298 n = cse + 1;
299 if (sloc < n-1)
300 cpu_to_be16wu((uint16_t *)(data + sloc),
301 do_cksum(data + css, data + n));
302 }
303
304 static void
305 xmit_seg(E1000State *s)
306 {
307 uint16_t len, *sp;
308 unsigned int frames = s->tx.tso_frames, css, sofar, n;
309 struct e1000_tx *tp = &s->tx;
310
311 if (tp->tse && tp->cptse) {
312 css = tp->ipcss;
313 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
314 frames, tp->size, css);
315 if (tp->ip) { // IPv4
316 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
317 tp->size - css);
318 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
319 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
320 } else // IPv6
321 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
322 tp->size - css);
323 css = tp->tucss;
324 len = tp->size - css;
325 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
326 if (tp->tcp) {
327 sofar = frames * tp->mss;
328 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
329 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
330 if (tp->paylen - sofar > tp->mss)
331 tp->data[css + 13] &= ~9; // PSH, FIN
332 } else // UDP
333 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
334 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
335 // add pseudo-header length before checksum calculation
336 sp = (uint16_t *)(tp->data + tp->tucso);
337 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
338 }
339 tp->tso_frames++;
340 }
341
342 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
343 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
344 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
345 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
346 qemu_send_packet(s->vc, tp->data, tp->size);
347 s->mac_reg[TPT]++;
348 s->mac_reg[GPTC]++;
349 n = s->mac_reg[TOTL];
350 if ((s->mac_reg[TOTL] += s->tx.size) < n)
351 s->mac_reg[TOTH]++;
352 }
353
354 static void
355 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
356 {
357 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
358 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
359 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
360 unsigned int msh = 0xfffff, hdr = 0;
361 uint64_t addr;
362 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
363 struct e1000_tx *tp = &s->tx;
364
365 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
366 op = le32_to_cpu(xp->cmd_and_length);
367 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
368 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
369 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
370 tp->tucss = xp->upper_setup.tcp_fields.tucss;
371 tp->tucso = xp->upper_setup.tcp_fields.tucso;
372 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
373 tp->paylen = op & 0xfffff;
374 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
375 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
376 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
377 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
378 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
379 tp->tso_frames = 0;
380 if (tp->tucso == 0) { // this is probably wrong
381 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
382 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
383 }
384 return;
385 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
386 // data descriptor
387 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
388 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
389 } else
390 // legacy descriptor
391 tp->cptse = 0;
392
393 addr = le64_to_cpu(dp->buffer_addr);
394 if (tp->tse && tp->cptse) {
395 hdr = tp->hdr_len;
396 msh = hdr + tp->mss;
397 do {
398 bytes = split_size;
399 if (tp->size + bytes > msh)
400 bytes = msh - tp->size;
401 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
402 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
403 memmove(tp->header, tp->data, hdr);
404 tp->size = sz;
405 addr += bytes;
406 if (sz == msh) {
407 xmit_seg(s);
408 memmove(tp->data, tp->header, hdr);
409 tp->size = hdr;
410 }
411 } while (split_size -= bytes);
412 } else if (!tp->tse && tp->cptse) {
413 // context descriptor TSE is not set, while data descriptor TSE is set
414 DBGOUT(TXERR, "TCP segmentaion Error\n");
415 } else {
416 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
417 tp->size += split_size;
418 }
419
420 if (!(txd_lower & E1000_TXD_CMD_EOP))
421 return;
422 if (!(tp->tse && tp->cptse && tp->size < hdr))
423 xmit_seg(s);
424 tp->tso_frames = 0;
425 tp->sum_needed = 0;
426 tp->size = 0;
427 tp->cptse = 0;
428 }
429
430 static uint32_t
431 txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
432 {
433 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
434
435 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
436 return 0;
437 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
438 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
439 dp->upper.data = cpu_to_le32(txd_upper);
440 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
441 (void *)&dp->upper, sizeof(dp->upper));
442 return E1000_ICR_TXDW;
443 }
444
445 static void
446 start_xmit(E1000State *s)
447 {
448 target_phys_addr_t base;
449 struct e1000_tx_desc desc;
450 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
451
452 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
453 DBGOUT(TX, "tx disabled\n");
454 return;
455 }
456
457 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
458 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
459 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
460 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
461
462 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
463 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
464 desc.upper.data);
465
466 process_tx_desc(s, &desc);
467 cause |= txdesc_writeback(base, &desc);
468
469 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
470 s->mac_reg[TDH] = 0;
471 /*
472 * the following could happen only if guest sw assigns
473 * bogus values to TDT/TDLEN.
474 * there's nothing too intelligent we could do about this.
475 */
476 if (s->mac_reg[TDH] == tdh_start) {
477 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
478 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
479 break;
480 }
481 }
482 set_ics(s, 0, cause);
483 }
484
485 static int
486 receive_filter(E1000State *s, const uint8_t *buf, int size)
487 {
488 static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
489 static int mta_shift[] = {4, 3, 2, 0};
490 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
491
492 if (rctl & E1000_RCTL_UPE) // promiscuous
493 return 1;
494
495 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
496 return 1;
497
498 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
499 return 1;
500
501 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
502 if (!(rp[1] & E1000_RAH_AV))
503 continue;
504 ra[0] = cpu_to_le32(rp[0]);
505 ra[1] = cpu_to_le32(rp[1]);
506 if (!memcmp(buf, (uint8_t *)ra, 6)) {
507 DBGOUT(RXFILTER,
508 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
509 (int)(rp - s->mac_reg - RA)/2,
510 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
511 return 1;
512 }
513 }
514 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
515 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
516
517 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
518 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
519 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
520 return 1;
521 DBGOUT(RXFILTER,
522 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
523 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
524 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
525 s->mac_reg[MTA + (f >> 5)]);
526
527 return 0;
528 }
529
530 static int
531 e1000_can_receive(void *opaque)
532 {
533 E1000State *s = opaque;
534
535 return (!(s->mac_reg[RCTL] & E1000_RCTL_EN) ||
536 s->mac_reg[RDH] != s->mac_reg[RDT]);
537 }
538
539 static void
540 e1000_receive(void *opaque, const uint8_t *buf, int size)
541 {
542 E1000State *s = opaque;
543 struct e1000_rx_desc desc;
544 target_phys_addr_t base;
545 unsigned int n, rdt;
546 uint32_t rdh_start;
547
548 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
549 return;
550
551 if (size > s->rxbuf_size) {
552 DBGOUT(RX, "packet too large for buffers (%d > %d)\n", size,
553 s->rxbuf_size);
554 return;
555 }
556
557 if (!receive_filter(s, buf, size))
558 return;
559
560 rdh_start = s->mac_reg[RDH];
561 size += 4; // for the header
562 do {
563 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
564 set_ics(s, 0, E1000_ICS_RXO);
565 return;
566 }
567 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
568 sizeof(desc) * s->mac_reg[RDH];
569 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
570 desc.status |= E1000_RXD_STAT_DD;
571 if (desc.buffer_addr) {
572 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
573 (void *)buf, size);
574 desc.length = cpu_to_le16(size);
575 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
576 } else // as per intel docs; skip descriptors with null buf addr
577 DBGOUT(RX, "Null RX descriptor!!\n");
578 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
579
580 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
581 s->mac_reg[RDH] = 0;
582 s->check_rxov = 1;
583 /* see comment in start_xmit; same here */
584 if (s->mac_reg[RDH] == rdh_start) {
585 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
586 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
587 set_ics(s, 0, E1000_ICS_RXO);
588 return;
589 }
590 } while (desc.buffer_addr == 0);
591
592 s->mac_reg[GPRC]++;
593 s->mac_reg[TPR]++;
594 n = s->mac_reg[TORL];
595 if ((s->mac_reg[TORL] += size) < n)
596 s->mac_reg[TORH]++;
597
598 n = E1000_ICS_RXT0;
599 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
600 rdt += s->mac_reg[RDLEN] / sizeof(desc);
601 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) << s->rxbuf_min_shift >=
602 s->mac_reg[RDLEN])
603 n |= E1000_ICS_RXDMT0;
604
605 set_ics(s, 0, n);
606 }
607
608 static uint32_t
609 mac_readreg(E1000State *s, int index)
610 {
611 return s->mac_reg[index];
612 }
613
614 static uint32_t
615 mac_icr_read(E1000State *s, int index)
616 {
617 uint32_t ret = s->mac_reg[ICR];
618
619 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
620 set_interrupt_cause(s, 0, 0);
621 return ret;
622 }
623
624 static uint32_t
625 mac_read_clr4(E1000State *s, int index)
626 {
627 uint32_t ret = s->mac_reg[index];
628
629 s->mac_reg[index] = 0;
630 return ret;
631 }
632
633 static uint32_t
634 mac_read_clr8(E1000State *s, int index)
635 {
636 uint32_t ret = s->mac_reg[index];
637
638 s->mac_reg[index] = 0;
639 s->mac_reg[index-1] = 0;
640 return ret;
641 }
642
643 static void
644 mac_writereg(E1000State *s, int index, uint32_t val)
645 {
646 s->mac_reg[index] = val;
647 }
648
649 static void
650 set_rdt(E1000State *s, int index, uint32_t val)
651 {
652 s->check_rxov = 0;
653 s->mac_reg[index] = val & 0xffff;
654 }
655
656 static void
657 set_16bit(E1000State *s, int index, uint32_t val)
658 {
659 s->mac_reg[index] = val & 0xffff;
660 }
661
662 static void
663 set_dlen(E1000State *s, int index, uint32_t val)
664 {
665 s->mac_reg[index] = val & 0xfff80;
666 }
667
668 static void
669 set_tctl(E1000State *s, int index, uint32_t val)
670 {
671 s->mac_reg[index] = val;
672 s->mac_reg[TDT] &= 0xffff;
673 start_xmit(s);
674 }
675
676 static void
677 set_icr(E1000State *s, int index, uint32_t val)
678 {
679 DBGOUT(INTERRUPT, "set_icr %x\n", val);
680 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
681 }
682
683 static void
684 set_imc(E1000State *s, int index, uint32_t val)
685 {
686 s->mac_reg[IMS] &= ~val;
687 set_ics(s, 0, 0);
688 }
689
690 static void
691 set_ims(E1000State *s, int index, uint32_t val)
692 {
693 s->mac_reg[IMS] |= val;
694 set_ics(s, 0, 0);
695 }
696
697 #define getreg(x) [x] = mac_readreg
698 static uint32_t (*macreg_readops[])(E1000State *, int) = {
699 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
700 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
701 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
702 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
703 getreg(RDH), getreg(RDT),
704
705 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
706 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
707 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
708 [CRCERRS ... MPC] = &mac_readreg,
709 [RA ... RA+31] = &mac_readreg,
710 [MTA ... MTA+127] = &mac_readreg,
711 };
712 enum { NREADOPS = sizeof(macreg_readops) / sizeof(*macreg_readops) };
713
714 #define putreg(x) [x] = mac_writereg
715 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
716 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
717 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
718 putreg(RDBAL), putreg(LEDCTL),
719 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
720 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
721 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
722 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
723 [EECD] = set_eecd, [RCTL] = set_rx_control,
724 [RA ... RA+31] = &mac_writereg,
725 [MTA ... MTA+127] = &mac_writereg,
726 };
727 enum { NWRITEOPS = sizeof(macreg_writeops) / sizeof(*macreg_writeops) };
728
729 static void
730 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
731 {
732 E1000State *s = opaque;
733 unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
734
735 #ifdef TARGET_WORDS_BIGENDIAN
736 val = bswap32(val);
737 #endif
738 if (index < NWRITEOPS && macreg_writeops[index])
739 macreg_writeops[index](s, index, val);
740 else if (index < NREADOPS && macreg_readops[index])
741 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
742 else
743 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
744 index<<2, val);
745 }
746
747 static void
748 e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
749 {
750 // emulate hw without byte enables: no RMW
751 e1000_mmio_writel(opaque, addr & ~3,
752 (val & 0xffff) << (8*(addr & 3)));
753 }
754
755 static void
756 e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
757 {
758 // emulate hw without byte enables: no RMW
759 e1000_mmio_writel(opaque, addr & ~3,
760 (val & 0xff) << (8*(addr & 3)));
761 }
762
763 static uint32_t
764 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
765 {
766 E1000State *s = opaque;
767 unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
768
769 if (index < NREADOPS && macreg_readops[index])
770 {
771 uint32_t val = macreg_readops[index](s, index);
772 #ifdef TARGET_WORDS_BIGENDIAN
773 val = bswap32(val);
774 #endif
775 return val;
776 }
777 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
778 return 0;
779 }
780
781 static uint32_t
782 e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
783 {
784 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
785 (8 * (addr & 3))) & 0xff;
786 }
787
788 static uint32_t
789 e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
790 {
791 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
792 (8 * (addr & 3))) & 0xffff;
793 }
794
795 int mac_regtosave[] = {
796 CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,
797 LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,
798 RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,
799 TDT, TORH, TORL, TOTH, TOTL, TPR, TPT, TXDCTL, WUFC,
800 };
801 enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave };
802
803 struct {
804 int size;
805 int array0;
806 } mac_regarraystosave[] = { {32, RA}, {128, MTA} };
807 enum { MAC_NARRAYS = sizeof mac_regarraystosave/sizeof *mac_regarraystosave };
808
809 static void
810 nic_save(QEMUFile *f, void *opaque)
811 {
812 E1000State *s = (E1000State *)opaque;
813 int i, j;
814
815 pci_device_save(&s->dev, f);
816 qemu_put_be32s(f, &s->mmio_base);
817 qemu_put_be32s(f, &s->rxbuf_size);
818 qemu_put_be32s(f, &s->rxbuf_min_shift);
819 qemu_put_be32s(f, &s->eecd_state.val_in);
820 qemu_put_be16s(f, &s->eecd_state.bitnum_in);
821 qemu_put_be16s(f, &s->eecd_state.bitnum_out);
822 qemu_put_be16s(f, &s->eecd_state.reading);
823 qemu_put_be32s(f, &s->eecd_state.old_eecd);
824 qemu_put_8s(f, &s->tx.ipcss);
825 qemu_put_8s(f, &s->tx.ipcso);
826 qemu_put_be16s(f, &s->tx.ipcse);
827 qemu_put_8s(f, &s->tx.tucss);
828 qemu_put_8s(f, &s->tx.tucso);
829 qemu_put_be16s(f, &s->tx.tucse);
830 qemu_put_be32s(f, &s->tx.paylen);
831 qemu_put_8s(f, &s->tx.hdr_len);
832 qemu_put_be16s(f, &s->tx.mss);
833 qemu_put_be16s(f, &s->tx.size);
834 qemu_put_be16s(f, &s->tx.tso_frames);
835 qemu_put_8s(f, &s->tx.sum_needed);
836 qemu_put_8s(f, &s->tx.ip);
837 qemu_put_8s(f, &s->tx.tcp);
838 qemu_put_buffer(f, s->tx.header, sizeof s->tx.header);
839 qemu_put_buffer(f, s->tx.data, sizeof s->tx.data);
840 for (i = 0; i < 64; i++)
841 qemu_put_be16s(f, s->eeprom_data + i);
842 for (i = 0; i < 0x20; i++)
843 qemu_put_be16s(f, s->phy_reg + i);
844 for (i = 0; i < MAC_NSAVE; i++)
845 qemu_put_be32s(f, s->mac_reg + mac_regtosave[i]);
846 for (i = 0; i < MAC_NARRAYS; i++)
847 for (j = 0; j < mac_regarraystosave[i].size; j++)
848 qemu_put_be32s(f,
849 s->mac_reg + mac_regarraystosave[i].array0 + j);
850 }
851
852 static int
853 nic_load(QEMUFile *f, void *opaque, int version_id)
854 {
855 E1000State *s = (E1000State *)opaque;
856 int i, j, ret;
857
858 if ((ret = pci_device_load(&s->dev, f)) < 0)
859 return ret;
860 if (version_id == 1)
861 qemu_get_be32s(f, &i); /* once some unused instance id */
862 qemu_get_be32s(f, &s->mmio_base);
863 qemu_get_be32s(f, &s->rxbuf_size);
864 qemu_get_be32s(f, &s->rxbuf_min_shift);
865 qemu_get_be32s(f, &s->eecd_state.val_in);
866 qemu_get_be16s(f, &s->eecd_state.bitnum_in);
867 qemu_get_be16s(f, &s->eecd_state.bitnum_out);
868 qemu_get_be16s(f, &s->eecd_state.reading);
869 qemu_get_be32s(f, &s->eecd_state.old_eecd);
870 qemu_get_8s(f, &s->tx.ipcss);
871 qemu_get_8s(f, &s->tx.ipcso);
872 qemu_get_be16s(f, &s->tx.ipcse);
873 qemu_get_8s(f, &s->tx.tucss);
874 qemu_get_8s(f, &s->tx.tucso);
875 qemu_get_be16s(f, &s->tx.tucse);
876 qemu_get_be32s(f, &s->tx.paylen);
877 qemu_get_8s(f, &s->tx.hdr_len);
878 qemu_get_be16s(f, &s->tx.mss);
879 qemu_get_be16s(f, &s->tx.size);
880 qemu_get_be16s(f, &s->tx.tso_frames);
881 qemu_get_8s(f, &s->tx.sum_needed);
882 qemu_get_8s(f, &s->tx.ip);
883 qemu_get_8s(f, &s->tx.tcp);
884 qemu_get_buffer(f, s->tx.header, sizeof s->tx.header);
885 qemu_get_buffer(f, s->tx.data, sizeof s->tx.data);
886 for (i = 0; i < 64; i++)
887 qemu_get_be16s(f, s->eeprom_data + i);
888 for (i = 0; i < 0x20; i++)
889 qemu_get_be16s(f, s->phy_reg + i);
890 for (i = 0; i < MAC_NSAVE; i++)
891 qemu_get_be32s(f, s->mac_reg + mac_regtosave[i]);
892 for (i = 0; i < MAC_NARRAYS; i++)
893 for (j = 0; j < mac_regarraystosave[i].size; j++)
894 qemu_get_be32s(f,
895 s->mac_reg + mac_regarraystosave[i].array0 + j);
896 return 0;
897 }
898
899 static uint16_t e1000_eeprom_template[64] = {
900 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
901 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
902 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
903 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
904 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
905 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
906 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
907 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
908 };
909
910 static uint16_t phy_reg_init[] = {
911 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
912 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
913 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
914 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
915 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
916 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
917 };
918
919 static uint32_t mac_reg_init[] = {
920 [PBA] = 0x00100030,
921 [LEDCTL] = 0x602,
922 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
923 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
924 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
925 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
926 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
927 E1000_STATUS_LU,
928 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
929 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
930 E1000_MANC_RMCP_EN,
931 };
932
933 /* PCI interface */
934
935 static CPUWriteMemoryFunc *e1000_mmio_write[] = {
936 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
937 };
938
939 static CPUReadMemoryFunc *e1000_mmio_read[] = {
940 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
941 };
942
943 static void
944 e1000_mmio_map(PCIDevice *pci_dev, int region_num,
945 uint32_t addr, uint32_t size, int type)
946 {
947 E1000State *d = (E1000State *)pci_dev;
948
949 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
950
951 d->mmio_base = addr;
952 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
953 }
954
955 void
956 pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn)
957 {
958 E1000State *d;
959 uint8_t *pci_conf;
960 uint16_t checksum = 0;
961 char *info_str = "e1000";
962 int i;
963
964 d = (E1000State *)pci_register_device(bus, "e1000",
965 sizeof(E1000State), devfn, NULL, NULL);
966
967 pci_conf = d->dev.config;
968 memset(pci_conf, 0, 256);
969
970 *(uint16_t *)(pci_conf+0x00) = cpu_to_le16(0x8086);
971 *(uint16_t *)(pci_conf+0x02) = cpu_to_le16(E1000_DEVID);
972 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
973 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
974 pci_conf[0x08] = 0x03;
975 pci_conf[0x0a] = 0x00; // ethernet network controller
976 pci_conf[0x0b] = 0x02;
977 pci_conf[0x0c] = 0x10;
978
979 pci_conf[0x3d] = 1; // interrupt pin 0
980
981 d->mmio_index = cpu_register_io_memory(0, e1000_mmio_read,
982 e1000_mmio_write, d);
983
984 pci_register_io_region((PCIDevice *)d, 0, PNPMMIO_SIZE,
985 PCI_ADDRESS_SPACE_MEM, e1000_mmio_map);
986
987 pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,
988 PCI_ADDRESS_SPACE_IO, ioport_map);
989
990 d->nd = nd;
991 memmove(d->eeprom_data, e1000_eeprom_template,
992 sizeof e1000_eeprom_template);
993 for (i = 0; i < 3; i++)
994 d->eeprom_data[i] = (nd->macaddr[2*i+1]<<8) | nd->macaddr[2*i];
995 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
996 checksum += d->eeprom_data[i];
997 checksum = (uint16_t) EEPROM_SUM - checksum;
998 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
999
1000 memset(d->phy_reg, 0, sizeof d->phy_reg);
1001 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1002 memset(d->mac_reg, 0, sizeof d->mac_reg);
1003 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1004 d->rxbuf_min_shift = 1;
1005 memset(&d->tx, 0, sizeof d->tx);
1006
1007 d->vc = qemu_new_vlan_client(nd->vlan, e1000_receive,
1008 e1000_can_receive, d);
1009
1010 snprintf(d->vc->info_str, sizeof(d->vc->info_str),
1011 "%s macaddr=%02x:%02x:%02x:%02x:%02x:%02x", info_str,
1012 d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2],
1013 d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]);
1014
1015 register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1016 }