tcg/tcg-dyngen.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <assert.h>
  25 #include <stdarg.h>
  26 #include <stdlib.h>
  27 #include <stdio.h>
  28 #include <string.h>
  29 #include <inttypes.h>
  30
  31 #include "config.h"
  32 #include "osdep.h"
  33
  34 #include "tcg.h"
  35
  36 int __op_param1, __op_param2, __op_param3;
  37 #if defined(__sparc__) || defined(__arm__)
  38   void __op_gen_label1(){}
  39   void __op_gen_label2(){}
  40   void __op_gen_label3(){}
  41 #else
  42   int __op_gen_label1, __op_gen_label2, __op_gen_label3;
  43 #endif
  44 int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
  45
  46 #if 0
  47 #if defined(__s390__)
  48 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  49 {
  50 }
  51 #elif defined(__ia64__)
  52 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  53 {
  54     while (start < stop) {
  55         asm volatile ("fc %0" :: "r"(start));
  56         start += 32;
  57     }
  58     asm volatile (";;sync.i;;srlz.i;;");
  59 }
  60 #elif defined(__powerpc__)
  61
  62 #define MIN_CACHE_LINE_SIZE 8 /* conservative value */
  63
  64 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  65 {
  66     unsigned long p;
  67
  68     start &= ~(MIN_CACHE_LINE_SIZE - 1);
  69     stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
  70
  71     for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
  72         asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
  73     }
  74     asm volatile ("sync" : : : "memory");
  75     for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
  76         asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
  77     }
  78     asm volatile ("sync" : : : "memory");
  79     asm volatile ("isync" : : : "memory");
  80 }
  81 #elif defined(__alpha__)
  82 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  83 {
  84     asm ("imb");
  85 }
  86 #elif defined(__sparc__)
  87 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  88 {
  89         unsigned long p;
  90
  91         p = start & ~(8UL - 1UL);
  92         stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
  93
  94         for (; p < stop; p += 8)
  95                 __asm__ __volatile__("flush\t%0" : : "r" (p));
  96 }
  97 #elif defined(__arm__)
  98 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  99 {
 100     register unsigned long _beg __asm ("a1") = start;
 101     register unsigned long _end __asm ("a2") = stop;
 102     register unsigned long _flg __asm ("a3") = 0;
 103     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 104 }
 105 #elif defined(__mc68000)
 106
 107 # include <asm/cachectl.h>
 108 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 109 {
 110     cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
 111 }
 112 #elif defined(__mips__)
 113
 114 #include <sys/cachectl.h>
 115 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 116 {
 117     _flush_cache ((void *)start, stop - start, BCACHE);
 118 }
 119 #else
 120 #error unsupported CPU
 121 #endif
 122
 123 #ifdef __alpha__
 124
 125 register int gp asm("$29");
 126
 127 static inline void immediate_ldah(void *p, int val) {
 128     uint32_t *dest = p;
 129     long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff;
 130
 131     *dest &= ~0xffff;
 132     *dest |= high;
 133     *dest |= 31 << 16;
 134 }
 135 static inline void immediate_lda(void *dest, int val) {
 136     *(uint16_t *) dest = val;
 137 }
 138 void fix_bsr(void *p, int offset) {
 139     uint32_t *dest = p;
 140     *dest &= ~((1 << 21) - 1);
 141     *dest |= (offset >> 2) & ((1 << 21) - 1);
 142 }
 143
 144 #endif /* __alpha__ */
 145
 146 #ifdef __ia64
 147
 148 /* Patch instruction with "val" where "mask" has 1 bits. */
 149 static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
 150 {
 151     uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
 152 #   define insn_mask ((1UL << 41) - 1)
 153     unsigned long shift;
 154
 155     b0 = b[0]; b1 = b[1];
 156     shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */
 157     if (shift >= 64) {
 158         m1 = mask << (shift - 64);
 159         v1 = val << (shift - 64);
 160     } else {
 161         m0 = mask << shift; m1 = mask >> (64 - shift);
 162         v0 = val  << shift; v1 = val >> (64 - shift);
 163         b[0] = (b0 & ~m0) | (v0 & m0);
 164     }
 165     b[1] = (b1 & ~m1) | (v1 & m1);
 166 }
 167
 168 static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val)
 169 {
 170         ia64_patch(insn_addr,
 171                    0x011ffffe000UL,
 172                    (  ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
 173                     | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
 174         ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18);
 175 }
 176
 177 static inline void ia64_imm64 (void *insn, uint64_t val)
 178 {
 179     /* Ignore the slot number of the relocation; GCC and Intel
 180        toolchains differed for some time on whether IMM64 relocs are
 181        against slot 1 (Intel) or slot 2 (GCC).  */
 182     uint64_t insn_addr = (uint64_t) insn & ~3UL;
 183
 184     ia64_patch(insn_addr + 2,
 185                0x01fffefe000UL,
 186                (  ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
 187                 | ((val & 0x0000000000200000UL) <<  0) /* bit 21 -> 21 */
 188                 | ((val & 0x00000000001f0000UL) <<  6) /* bit 16 -> 22 */
 189                 | ((val & 0x000000000000ff80UL) << 20) /* bit  7 -> 27 */
 190                 | ((val & 0x000000000000007fUL) << 13) /* bit  0 -> 13 */)
 191             );
 192     ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
 193 }
 194
 195 static inline void ia64_imm60b (void *insn, uint64_t val)
 196 {
 197     /* Ignore the slot number of the relocation; GCC and Intel
 198        toolchains differed for some time on whether IMM64 relocs are
 199        against slot 1 (Intel) or slot 2 (GCC).  */
 200     uint64_t insn_addr = (uint64_t) insn & ~3UL;
 201
 202     if (val + ((uint64_t) 1 << 59) >= (1UL << 60))
 203         fprintf(stderr, "%s: value %ld out of IMM60 range\n",
 204                 __FUNCTION__, (int64_t) val);
 205     ia64_patch_imm60(insn_addr + 2, val);
 206 }
 207
 208 static inline void ia64_imm22 (void *insn, uint64_t val)
 209 {
 210     if (val + (1 << 21) >= (1 << 22))
 211         fprintf(stderr, "%s: value %li out of IMM22 range\n",
 212                 __FUNCTION__, (int64_t)val);
 213     ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
 214                (  ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
 215                 | ((val & 0x1f0000UL) <<  6) /* bit 16 -> 22 */
 216                 | ((val & 0x00ff80UL) << 20) /* bit  7 -> 27 */
 217                 | ((val & 0x00007fUL) << 13) /* bit  0 -> 13 */));
 218 }
 219
 220 /* Like ia64_imm22(), but also clear bits 20-21.  For addl, this has
 221    the effect of turning "addl rX=imm22,rY" into "addl
 222    rX=imm22,r0".  */
 223 static inline void ia64_imm22_r0 (void *insn, uint64_t val)
 224 {
 225     if (val + (1 << 21) >= (1 << 22))
 226         fprintf(stderr, "%s: value %li out of IMM22 range\n",
 227                 __FUNCTION__, (int64_t)val);
 228     ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20),
 229                (  ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
 230                 | ((val & 0x1f0000UL) <<  6) /* bit 16 -> 22 */
 231                 | ((val & 0x00ff80UL) << 20) /* bit  7 -> 27 */
 232                 | ((val & 0x00007fUL) << 13) /* bit  0 -> 13 */));
 233 }
 234
 235 static inline void ia64_imm21b (void *insn, uint64_t val)
 236 {
 237     if (val + (1 << 20) >= (1 << 21))
 238         fprintf(stderr, "%s: value %li out of IMM21b range\n",
 239                 __FUNCTION__, (int64_t)val);
 240     ia64_patch((uint64_t) insn, 0x11ffffe000UL,
 241                (  ((val & 0x100000UL) << 16) /* bit 20 -> 36 */
 242                 | ((val & 0x0fffffUL) << 13) /* bit  0 -> 13 */));
 243 }
 244
 245 static inline void ia64_nop_b (void *insn)
 246 {
 247     ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37);
 248 }
 249
 250 static inline void ia64_ldxmov(void *insn, uint64_t val)
 251 {
 252     if (val + (1 << 21) < (1 << 22))
 253         ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37);
 254 }
 255
 256 static inline int ia64_patch_ltoff(void *insn, uint64_t val,
 257                                    int relaxable)
 258 {
 259     if (relaxable && (val + (1 << 21) < (1 << 22))) {
 260         ia64_imm22_r0(insn, val);
 261         return 0;
 262     }
 263     return 1;
 264 }
 265
 266 struct ia64_fixup {
 267     struct ia64_fixup *next;
 268     void *addr;                 /* address that needs to be patched */
 269     long value;
 270 };
 271
 272 #define IA64_PLT(insn, plt_index)                       \
 273 do {                                                    \
 274     struct ia64_fixup *fixup = alloca(sizeof(*fixup));  \
 275     fixup->next = plt_fixes;                            \
 276     plt_fixes = fixup;                                  \
 277     fixup->addr = (insn);                               \
 278     fixup->value = (plt_index);                         \
 279     plt_offset[(plt_index)] = 1;                        \
 280 } while (0)
 281
 282 #define IA64_LTOFF(insn, val, relaxable)                        \
 283 do {                                                            \
 284     if (ia64_patch_ltoff(insn, val, relaxable)) {               \
 285         struct ia64_fixup *fixup = alloca(sizeof(*fixup));      \
 286         fixup->next = ltoff_fixes;                              \
 287         ltoff_fixes = fixup;                                    \
 288         fixup->addr = (insn);                                   \
 289         fixup->value = (val);                                   \
 290     }                                                           \
 291 } while (0)
 292
 293 static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
 294                                      struct ia64_fixup *ltoff_fixes,
 295                                      uint64_t gp,
 296                                      struct ia64_fixup *plt_fixes,
 297                                      int num_plts,
 298                                      unsigned long *plt_target,
 299                                      unsigned int *plt_offset)
 300 {
 301     static const uint8_t plt_bundle[] = {
 302         0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */
 303         0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60,
 304
 305         0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */
 306         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0
 307     };
 308     uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start;
 309     uint64_t *vp;
 310     struct ia64_fixup *fixup;
 311     unsigned int offset = 0;
 312     struct fdesc {
 313         long ip;
 314         long gp;
 315     } *fdesc;
 316     int i;
 317
 318     if (plt_fixes) {
 319         plt_start = gen_code_ptr;
 320
 321         for (i = 0; i < num_plts; ++i) {
 322             if (plt_offset[i]) {
 323                 plt_offset[i] = offset;
 324                 offset += sizeof(plt_bundle);
 325
 326                 fdesc = (struct fdesc *) plt_target[i];
 327                 memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
 328                 ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
 329                 ia64_imm60b(gen_code_ptr + 0x12,
 330                             (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4);
 331                 gen_code_ptr += sizeof(plt_bundle);
 332             }
 333         }
 334
 335         for (fixup = plt_fixes; fixup; fixup = fixup->next)
 336             ia64_imm21b(fixup->addr,
 337                         ((long) plt_start + plt_offset[fixup->value]
 338                          - ((long) fixup->addr & ~0xf)) >> 4);
 339     }
 340
 341     got_start = gen_code_ptr;
 342
 343     /* First, create the GOT: */
 344     for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
 345         /* first check if we already have this value in the GOT: */
 346         for (vp = (uint64_t *) got_start; vp < (uint64_t *) gen_code_ptr; ++vp)
 347             if (*vp == fixup->value)
 348                 break;
 349         if (vp == (uint64_t *) gen_code_ptr) {
 350             /* Nope, we need to put the value in the GOT: */
 351             *vp = fixup->value;
 352             gen_code_ptr += 8;
 353         }
 354         ia64_imm22(fixup->addr, (long) vp - gp);
 355     }
 356     /* Keep code ptr aligned. */
 357     if ((long) gen_code_ptr & 15)
 358         gen_code_ptr += 8;
 359     *gen_code_pp = gen_code_ptr;
 360 }
 361 #endif
 362 #endif
 363
 364 #ifdef CONFIG_DYNGEN_OP
 365
 366 #if defined __hppa__
 367 struct hppa_branch_stub {
 368     uint32_t *location;
 369     long target;
 370     struct hppa_branch_stub *next;
 371 };
 372
 373 #define HPPA_RECORD_BRANCH(LIST, LOC, TARGET) \
 374 do { \
 375     struct hppa_branch_stub *stub = alloca(sizeof(struct hppa_branch_stub)); \
 376     stub->location = LOC; \
 377     stub->target = TARGET; \
 378     stub->next = LIST; \
 379     LIST = stub; \
 380 } while (0)
 381
 382 static inline void hppa_process_stubs(struct hppa_branch_stub *stub,
 383                                       uint8_t **gen_code_pp)
 384 {
 385     uint32_t *s = (uint32_t *)*gen_code_pp;
 386     uint32_t *p = s + 1;
 387
 388     if (!stub) return;
 389
 390     for (; stub != NULL; stub = stub->next) {
 391         unsigned long l = (unsigned long)p;
 392         /* stub:
 393          * ldil L'target, %r1
 394          * be,n R'target(%sr4,%r1)
 395          */
 396         *p++ = 0x20200000 | reassemble_21(lrsel(stub->target, 0));
 397         *p++ = 0xe0202002 | (reassemble_17(rrsel(stub->target, 0) >> 2));
 398         hppa_patch17f(stub->location, l, 0);
 399     }
 400     /* b,l,n stub,%r0 */
 401     *s = 0xe8000002 | reassemble_17((p - s) - 2);
 402     *gen_code_pp = (uint8_t *)p;
 403 }
 404 #endif /* __hppa__ */
 405
 406 const TCGArg *dyngen_op(TCGContext *s, int opc, const TCGArg *opparam_ptr)
 407 {
 408     uint8_t *gen_code_ptr;
 409
 410 #ifdef __hppa__
 411     struct hppa_branch_stub *hppa_stubs = NULL;
 412 #endif
 413
 414     gen_code_ptr = s->code_ptr;
 415     switch(opc) {
 416
 417 /* op.h is dynamically generated by dyngen.c from op.c */
 418 #include "op.h"
 419
 420     default:
 421         tcg_abort();
 422     }
 423
 424 #ifdef __hppa__
 425     hppa_process_stubs(hppa_stubs, &gen_code_ptr);
 426 #endif
 427
 428     s->code_ptr = gen_code_ptr;
 429     return opparam_ptr;
 430 }
 431 #endif