qemu: zero ioport_opaque on isa_unassign_ioport (Marcelo Tosatti)
[qemu/mini2440/sniper_sniper_test.git] / hw / ppc.h
blob75eb11a32853412605fa3c01041b4f2616662c0b
1 /* PowerPC hardware exceptions management helpers */
2 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
3 typedef struct clk_setup_t clk_setup_t;
4 struct clk_setup_t {
5 clk_setup_cb cb;
6 void *opaque;
7 };
8 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
10 if (clk->cb != NULL)
11 (*clk->cb)(clk->opaque, freq);
14 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
15 /* Embedded PowerPC DCR management */
16 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
17 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
18 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
19 int (*dcr_write_error)(int dcrn));
20 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
21 dcr_read_cb drc_read, dcr_write_cb dcr_write);
22 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
23 /* Embedded PowerPC reset */
24 void ppc40x_core_reset (CPUState *env);
25 void ppc40x_chip_reset (CPUState *env);
26 void ppc40x_system_reset (CPUState *env);
27 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
29 extern CPUWriteMemoryFunc *PPC_io_write[];
30 extern CPUReadMemoryFunc *PPC_io_read[];
31 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
33 void ppc40x_irq_init (CPUState *env);
34 void ppc6xx_irq_init (CPUState *env);
35 void ppc970_irq_init (CPUState *env);
37 /* PPC machines for OpenBIOS */
38 enum {
39 ARCH_PREP = 0,
40 ARCH_MAC99,
41 ARCH_HEATHROW,