2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the LGPL.
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
15 #include "scsi-disk.h"
18 //#define DEBUG_LSI_REG
21 #define DPRINTF(fmt, args...) \
22 do { printf("lsi_scsi: " fmt , ##args); } while (0)
23 #define BADF(fmt, args...) \
24 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
26 #define DPRINTF(fmt, args...) do {} while(0)
27 #define BADF(fmt, args...) \
28 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
31 #define LSI_SCNTL0_TRG 0x01
32 #define LSI_SCNTL0_AAP 0x02
33 #define LSI_SCNTL0_EPC 0x08
34 #define LSI_SCNTL0_WATN 0x10
35 #define LSI_SCNTL0_START 0x20
37 #define LSI_SCNTL1_SST 0x01
38 #define LSI_SCNTL1_IARB 0x02
39 #define LSI_SCNTL1_AESP 0x04
40 #define LSI_SCNTL1_RST 0x08
41 #define LSI_SCNTL1_CON 0x10
42 #define LSI_SCNTL1_DHP 0x20
43 #define LSI_SCNTL1_ADB 0x40
44 #define LSI_SCNTL1_EXC 0x80
46 #define LSI_SCNTL2_WSR 0x01
47 #define LSI_SCNTL2_VUE0 0x02
48 #define LSI_SCNTL2_VUE1 0x04
49 #define LSI_SCNTL2_WSS 0x08
50 #define LSI_SCNTL2_SLPHBEN 0x10
51 #define LSI_SCNTL2_SLPMD 0x20
52 #define LSI_SCNTL2_CHM 0x40
53 #define LSI_SCNTL2_SDU 0x80
55 #define LSI_ISTAT0_DIP 0x01
56 #define LSI_ISTAT0_SIP 0x02
57 #define LSI_ISTAT0_INTF 0x04
58 #define LSI_ISTAT0_CON 0x08
59 #define LSI_ISTAT0_SEM 0x10
60 #define LSI_ISTAT0_SIGP 0x20
61 #define LSI_ISTAT0_SRST 0x40
62 #define LSI_ISTAT0_ABRT 0x80
64 #define LSI_ISTAT1_SI 0x01
65 #define LSI_ISTAT1_SRUN 0x02
66 #define LSI_ISTAT1_FLSH 0x04
68 #define LSI_SSTAT0_SDP0 0x01
69 #define LSI_SSTAT0_RST 0x02
70 #define LSI_SSTAT0_WOA 0x04
71 #define LSI_SSTAT0_LOA 0x08
72 #define LSI_SSTAT0_AIP 0x10
73 #define LSI_SSTAT0_OLF 0x20
74 #define LSI_SSTAT0_ORF 0x40
75 #define LSI_SSTAT0_ILF 0x80
77 #define LSI_SIST0_PAR 0x01
78 #define LSI_SIST0_RST 0x02
79 #define LSI_SIST0_UDC 0x04
80 #define LSI_SIST0_SGE 0x08
81 #define LSI_SIST0_RSL 0x10
82 #define LSI_SIST0_SEL 0x20
83 #define LSI_SIST0_CMP 0x40
84 #define LSI_SIST0_MA 0x80
86 #define LSI_SIST1_HTH 0x01
87 #define LSI_SIST1_GEN 0x02
88 #define LSI_SIST1_STO 0x04
89 #define LSI_SIST1_SBMC 0x10
91 #define LSI_SOCL_IO 0x01
92 #define LSI_SOCL_CD 0x02
93 #define LSI_SOCL_MSG 0x04
94 #define LSI_SOCL_ATN 0x08
95 #define LSI_SOCL_SEL 0x10
96 #define LSI_SOCL_BSY 0x20
97 #define LSI_SOCL_ACK 0x40
98 #define LSI_SOCL_REQ 0x80
100 #define LSI_DSTAT_IID 0x01
101 #define LSI_DSTAT_SIR 0x04
102 #define LSI_DSTAT_SSI 0x08
103 #define LSI_DSTAT_ABRT 0x10
104 #define LSI_DSTAT_BF 0x20
105 #define LSI_DSTAT_MDPE 0x40
106 #define LSI_DSTAT_DFE 0x80
108 #define LSI_DCNTL_COM 0x01
109 #define LSI_DCNTL_IRQD 0x02
110 #define LSI_DCNTL_STD 0x04
111 #define LSI_DCNTL_IRQM 0x08
112 #define LSI_DCNTL_SSM 0x10
113 #define LSI_DCNTL_PFEN 0x20
114 #define LSI_DCNTL_PFF 0x40
115 #define LSI_DCNTL_CLSE 0x80
117 #define LSI_DMODE_MAN 0x01
118 #define LSI_DMODE_BOF 0x02
119 #define LSI_DMODE_ERMP 0x04
120 #define LSI_DMODE_ERL 0x08
121 #define LSI_DMODE_DIOM 0x10
122 #define LSI_DMODE_SIOM 0x20
124 #define LSI_CTEST2_DACK 0x01
125 #define LSI_CTEST2_DREQ 0x02
126 #define LSI_CTEST2_TEOP 0x04
127 #define LSI_CTEST2_PCICIE 0x08
128 #define LSI_CTEST2_CM 0x10
129 #define LSI_CTEST2_CIO 0x20
130 #define LSI_CTEST2_SIGP 0x40
131 #define LSI_CTEST2_DDIR 0x80
133 #define LSI_CTEST5_BL2 0x04
134 #define LSI_CTEST5_DDIR 0x08
135 #define LSI_CTEST5_MASR 0x10
136 #define LSI_CTEST5_DFSN 0x20
137 #define LSI_CTEST5_BBCK 0x40
138 #define LSI_CTEST5_ADCK 0x80
140 #define LSI_CCNTL0_DILS 0x01
141 #define LSI_CCNTL0_DISFC 0x10
142 #define LSI_CCNTL0_ENNDJ 0x20
143 #define LSI_CCNTL0_PMJCTL 0x40
144 #define LSI_CCNTL0_ENPMJ 0x80
146 #define LSI_CCNTL1_EN64DBMV 0x01
147 #define LSI_CCNTL1_EN64TIBMV 0x02
148 #define LSI_CCNTL1_64TIMOD 0x04
149 #define LSI_CCNTL1_DDAC 0x08
150 #define LSI_CCNTL1_ZMOD 0x80
152 #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
162 /* Maximum length of MSG IN data. */
163 #define LSI_MAX_MSGIN_LEN 8
165 /* Flag set if this is a tagged command. */
166 #define LSI_TAG_VALID (1 << 16)
178 uint32_t script_ram_base
;
180 int carry
; /* ??? Should this be an a visible register somewhere? */
182 /* Action to take at the end of a MSG IN phase.
183 0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
186 uint8_t msg
[LSI_MAX_MSGIN_LEN
];
187 /* 0 if SCRIPTS are running or stopped.
188 * 1 if a Wait Reselect instruction has been issued.
189 * 2 if processing DMA from lsi_execute_script.
190 * 3 if a DMA operation is in progress. */
192 SCSIDevice
*scsi_dev
[LSI_MAX_DEVS
];
193 SCSIDevice
*current_dev
;
195 /* The tag is a combination of the device ID and the SCSI tag. */
196 uint32_t current_tag
;
197 uint32_t current_dma_len
;
198 int command_complete
;
263 uint32_t scratch
[18]; /* SCRATCHA-SCRATCHR */
265 /* Script ram is stored as 32-bit words in host byteorder. */
266 uint32_t script_ram
[2048];
269 static void lsi_soft_reset(LSIState
*s
)
279 memset(s
->scratch
, 0, sizeof(s
->scratch
));
334 static int lsi_dma_40bit(LSIState
*s
)
336 if ((s
->ccntl1
& LSI_CCNTL1_40BIT
) == LSI_CCNTL1_40BIT
)
341 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
);
342 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
);
343 static void lsi_execute_script(LSIState
*s
);
345 static inline uint32_t read_dword(LSIState
*s
, uint32_t addr
)
349 /* Optimize reading from SCRIPTS RAM. */
350 if ((addr
& 0xffffe000) == s
->script_ram_base
) {
351 return s
->script_ram
[(addr
& 0x1fff) >> 2];
353 cpu_physical_memory_read(addr
, (uint8_t *)&buf
, 4);
354 return cpu_to_le32(buf
);
357 static void lsi_stop_script(LSIState
*s
)
359 s
->istat1
&= ~LSI_ISTAT1_SRUN
;
362 static void lsi_update_irq(LSIState
*s
)
365 static int last_level
;
367 /* It's unclear whether the DIP/SIP bits should be cleared when the
368 Interrupt Status Registers are cleared or when istat0 is read.
369 We currently do the formwer, which seems to work. */
372 if (s
->dstat
& s
->dien
)
374 s
->istat0
|= LSI_ISTAT0_DIP
;
376 s
->istat0
&= ~LSI_ISTAT0_DIP
;
379 if (s
->sist0
|| s
->sist1
) {
380 if ((s
->sist0
& s
->sien0
) || (s
->sist1
& s
->sien1
))
382 s
->istat0
|= LSI_ISTAT0_SIP
;
384 s
->istat0
&= ~LSI_ISTAT0_SIP
;
386 if (s
->istat0
& LSI_ISTAT0_INTF
)
389 if (level
!= last_level
) {
390 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
391 level
, s
->dstat
, s
->sist1
, s
->sist0
);
394 qemu_set_irq(s
->pci_dev
.irq
[0], level
);
397 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
398 static void lsi_script_scsi_interrupt(LSIState
*s
, int stat0
, int stat1
)
403 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
404 stat1
, stat0
, s
->sist1
, s
->sist0
);
407 /* Stop processor on fatal or unmasked interrupt. As a special hack
408 we don't stop processing when raising STO. Instead continue
409 execution and stop at the next insn that accesses the SCSI bus. */
410 mask0
= s
->sien0
| ~(LSI_SIST0_CMP
| LSI_SIST0_SEL
| LSI_SIST0_RSL
);
411 mask1
= s
->sien1
| ~(LSI_SIST1_GEN
| LSI_SIST1_HTH
);
412 mask1
&= ~LSI_SIST1_STO
;
413 if (s
->sist0
& mask0
|| s
->sist1
& mask1
) {
419 /* Stop SCRIPTS execution and raise a DMA interrupt. */
420 static void lsi_script_dma_interrupt(LSIState
*s
, int stat
)
422 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat
, s
->dstat
);
428 static inline void lsi_set_phase(LSIState
*s
, int phase
)
430 s
->sstat1
= (s
->sstat1
& ~PHASE_MASK
) | phase
;
433 static void lsi_bad_phase(LSIState
*s
, int out
, int new_phase
)
435 /* Trigger a phase mismatch. */
436 if (s
->ccntl0
& LSI_CCNTL0_ENPMJ
) {
437 if ((s
->ccntl0
& LSI_CCNTL0_PMJCTL
) || out
) {
442 DPRINTF("Data phase mismatch jump to %08x\n", s
->dsp
);
444 DPRINTF("Phase mismatch interrupt\n");
445 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
448 lsi_set_phase(s
, new_phase
);
452 /* Resume SCRIPTS execution after a DMA operation. */
453 static void lsi_resume_script(LSIState
*s
)
455 if (s
->waiting
!= 2) {
457 lsi_execute_script(s
);
463 /* Initiate a SCSI layer data transfer. */
464 static void lsi_do_dma(LSIState
*s
, int out
)
467 target_phys_addr_t addr
;
469 if (!s
->current_dma_len
) {
470 /* Wait until data is available. */
471 DPRINTF("DMA no data available\n");
476 if (count
> s
->current_dma_len
)
477 count
= s
->current_dma_len
;
480 if (lsi_dma_40bit(s
))
481 addr
|= ((uint64_t)s
->dnad64
<< 32);
483 addr
|= ((uint64_t)s
->sbms
<< 32);
485 DPRINTF("DMA addr=0x" TARGET_FMT_plx
" len=%d\n", addr
, count
);
490 if (s
->dma_buf
== NULL
) {
491 s
->dma_buf
= s
->current_dev
->get_buf(s
->current_dev
,
495 /* ??? Set SFBR to first data byte. */
497 cpu_physical_memory_read(addr
, s
->dma_buf
, count
);
499 cpu_physical_memory_write(addr
, s
->dma_buf
, count
);
501 s
->current_dma_len
-= count
;
502 if (s
->current_dma_len
== 0) {
505 /* Write the data. */
506 s
->current_dev
->write_data(s
->current_dev
, s
->current_tag
);
508 /* Request any remaining data. */
509 s
->current_dev
->read_data(s
->current_dev
, s
->current_tag
);
513 lsi_resume_script(s
);
518 /* Add a command to the queue. */
519 static void lsi_queue_command(LSIState
*s
)
523 DPRINTF("Queueing tag=0x%x\n", s
->current_tag
);
524 if (s
->queue_len
== s
->active_commands
) {
526 s
->queue
= qemu_realloc(s
->queue
, s
->queue_len
* sizeof(lsi_queue
));
528 p
= &s
->queue
[s
->active_commands
++];
529 p
->tag
= s
->current_tag
;
531 p
->out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
534 /* Queue a byte for a MSG IN phase. */
535 static void lsi_add_msg_byte(LSIState
*s
, uint8_t data
)
537 if (s
->msg_len
>= LSI_MAX_MSGIN_LEN
) {
538 BADF("MSG IN data too long\n");
540 DPRINTF("MSG IN 0x%02x\n", data
);
541 s
->msg
[s
->msg_len
++] = data
;
545 /* Perform reselection to continue a command. */
546 static void lsi_reselect(LSIState
*s
, uint32_t tag
)
553 for (n
= 0; n
< s
->active_commands
; n
++) {
558 if (n
== s
->active_commands
) {
559 BADF("Reselected non-existant command tag=0x%x\n", tag
);
562 id
= (tag
>> 8) & 0xf;
564 DPRINTF("Reselected target %d\n", id
);
565 s
->current_dev
= s
->scsi_dev
[id
];
566 s
->current_tag
= tag
;
567 s
->scntl1
|= LSI_SCNTL1_CON
;
568 lsi_set_phase(s
, PHASE_MI
);
569 s
->msg_action
= p
->out
? 2 : 3;
570 s
->current_dma_len
= p
->pending
;
572 lsi_add_msg_byte(s
, 0x80);
573 if (s
->current_tag
& LSI_TAG_VALID
) {
574 lsi_add_msg_byte(s
, 0x20);
575 lsi_add_msg_byte(s
, tag
& 0xff);
578 s
->active_commands
--;
579 if (n
!= s
->active_commands
) {
580 s
->queue
[n
] = s
->queue
[s
->active_commands
];
584 /* Record that data is available for a queued command. Returns zero if
585 the device was reselected, nonzero if the IO is deferred. */
586 static int lsi_queue_tag(LSIState
*s
, uint32_t tag
, uint32_t arg
)
590 for (i
= 0; i
< s
->active_commands
; i
++) {
594 BADF("Multiple IO pending for tag %d\n", tag
);
597 if (s
->waiting
== 1) {
598 /* Reselect device. */
599 lsi_reselect(s
, tag
);
602 DPRINTF("Queueing IO tag=0x%x\n", tag
);
608 BADF("IO with unknown tag %d\n", tag
);
612 /* Callback to indicate that the SCSI layer has completed a transfer. */
613 static void lsi_command_complete(void *opaque
, int reason
, uint32_t tag
,
616 LSIState
*s
= (LSIState
*)opaque
;
619 out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
620 if (reason
== SCSI_REASON_DONE
) {
621 DPRINTF("Command complete sense=%d\n", (int)arg
);
623 s
->command_complete
= 2;
624 if (s
->waiting
&& s
->dbc
!= 0) {
625 /* Raise phase mismatch for short transfers. */
626 lsi_bad_phase(s
, out
, PHASE_ST
);
628 lsi_set_phase(s
, PHASE_ST
);
630 lsi_resume_script(s
);
634 if (s
->waiting
== 1 || tag
!= s
->current_tag
) {
635 if (lsi_queue_tag(s
, tag
, arg
))
638 DPRINTF("Data ready tag=0x%x len=%d\n", tag
, arg
);
639 s
->current_dma_len
= arg
;
640 s
->command_complete
= 1;
643 if (s
->waiting
== 1 || s
->dbc
== 0) {
644 lsi_resume_script(s
);
650 static void lsi_do_command(LSIState
*s
)
655 DPRINTF("Send command len=%d\n", s
->dbc
);
658 cpu_physical_memory_read(s
->dnad
, buf
, s
->dbc
);
660 s
->command_complete
= 0;
661 n
= s
->current_dev
->send_command(s
->current_dev
, s
->current_tag
, buf
,
664 lsi_set_phase(s
, PHASE_DI
);
665 s
->current_dev
->read_data(s
->current_dev
, s
->current_tag
);
667 lsi_set_phase(s
, PHASE_DO
);
668 s
->current_dev
->write_data(s
->current_dev
, s
->current_tag
);
671 if (!s
->command_complete
) {
673 /* Command did not complete immediately so disconnect. */
674 lsi_add_msg_byte(s
, 2); /* SAVE DATA POINTER */
675 lsi_add_msg_byte(s
, 4); /* DISCONNECT */
677 lsi_set_phase(s
, PHASE_MI
);
679 lsi_queue_command(s
);
681 /* wait command complete */
682 lsi_set_phase(s
, PHASE_DI
);
687 static void lsi_do_status(LSIState
*s
)
690 DPRINTF("Get status len=%d sense=%d\n", s
->dbc
, s
->sense
);
692 BADF("Bad Status move\n");
696 cpu_physical_memory_write(s
->dnad
, &sense
, 1);
697 lsi_set_phase(s
, PHASE_MI
);
699 lsi_add_msg_byte(s
, 0); /* COMMAND COMPLETE */
702 static void lsi_disconnect(LSIState
*s
)
704 s
->scntl1
&= ~LSI_SCNTL1_CON
;
705 s
->sstat1
&= ~PHASE_MASK
;
708 static void lsi_do_msgin(LSIState
*s
)
711 DPRINTF("Message in len=%d/%d\n", s
->dbc
, s
->msg_len
);
716 cpu_physical_memory_write(s
->dnad
, s
->msg
, len
);
717 /* Linux drivers rely on the last byte being in the SIDL. */
718 s
->sidl
= s
->msg
[len
- 1];
721 memmove(s
->msg
, s
->msg
+ len
, s
->msg_len
);
723 /* ??? Check if ATN (not yet implemented) is asserted and maybe
724 switch to PHASE_MO. */
725 switch (s
->msg_action
) {
727 lsi_set_phase(s
, PHASE_CMD
);
733 lsi_set_phase(s
, PHASE_DO
);
736 lsi_set_phase(s
, PHASE_DI
);
744 /* Read the next byte during a MSGOUT phase. */
745 static uint8_t lsi_get_msgbyte(LSIState
*s
)
748 cpu_physical_memory_read(s
->dnad
, &data
, 1);
754 static void lsi_do_msgout(LSIState
*s
)
759 DPRINTF("MSG out len=%d\n", s
->dbc
);
761 msg
= lsi_get_msgbyte(s
);
766 DPRINTF("MSG: Disconnect\n");
770 DPRINTF("MSG: No Operation\n");
771 lsi_set_phase(s
, PHASE_CMD
);
774 len
= lsi_get_msgbyte(s
);
775 msg
= lsi_get_msgbyte(s
);
776 DPRINTF("Extended message 0x%x (len %d)\n", msg
, len
);
779 DPRINTF("SDTR (ignored)\n");
783 DPRINTF("WDTR (ignored)\n");
790 case 0x20: /* SIMPLE queue */
791 s
->current_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
792 DPRINTF("SIMPLE queue tag=0x%x\n", s
->current_tag
& 0xff);
794 case 0x21: /* HEAD of queue */
795 BADF("HEAD queue not implemented\n");
796 s
->current_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
798 case 0x22: /* ORDERED queue */
799 BADF("ORDERED queue not implemented\n");
800 s
->current_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
803 if ((msg
& 0x80) == 0) {
806 s
->current_lun
= msg
& 7;
807 DPRINTF("Select LUN %d\n", s
->current_lun
);
808 lsi_set_phase(s
, PHASE_CMD
);
814 BADF("Unimplemented message 0x%02x\n", msg
);
815 lsi_set_phase(s
, PHASE_MI
);
816 lsi_add_msg_byte(s
, 7); /* MESSAGE REJECT */
820 /* Sign extend a 24-bit value. */
821 static inline int32_t sxt24(int32_t n
)
823 return (n
<< 8) >> 8;
826 static void lsi_memcpy(LSIState
*s
, uint32_t dest
, uint32_t src
, int count
)
829 uint8_t buf
[TARGET_PAGE_SIZE
];
831 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest
, src
, count
);
833 n
= (count
> TARGET_PAGE_SIZE
) ? TARGET_PAGE_SIZE
: count
;
834 cpu_physical_memory_read(src
, buf
, n
);
835 cpu_physical_memory_write(dest
, buf
, n
);
842 static void lsi_wait_reselect(LSIState
*s
)
845 DPRINTF("Wait Reselect\n");
846 if (s
->current_dma_len
)
847 BADF("Reselect with pending DMA\n");
848 for (i
= 0; i
< s
->active_commands
; i
++) {
849 if (s
->queue
[i
].pending
) {
850 lsi_reselect(s
, s
->queue
[i
].tag
);
854 if (s
->current_dma_len
== 0) {
859 static void lsi_execute_script(LSIState
*s
)
862 uint32_t addr
, addr_high
;
864 int insn_processed
= 0;
866 s
->istat1
|= LSI_ISTAT1_SRUN
;
869 insn
= read_dword(s
, s
->dsp
);
870 addr
= read_dword(s
, s
->dsp
+ 4);
872 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s
->dsp
, insn
, addr
);
874 s
->dcmd
= insn
>> 24;
876 switch (insn
>> 30) {
877 case 0: /* Block move. */
878 if (s
->sist1
& LSI_SIST1_STO
) {
879 DPRINTF("Delayed select timeout\n");
883 s
->dbc
= insn
& 0xffffff;
885 if (insn
& (1 << 29)) {
886 /* Indirect addressing. */
887 addr
= read_dword(s
, addr
);
888 } else if (insn
& (1 << 28)) {
891 /* Table indirect addressing. */
892 offset
= sxt24(addr
);
893 cpu_physical_memory_read(s
->dsa
+ offset
, (uint8_t *)buf
, 8);
894 /* byte count is stored in bits 0:23 only */
895 s
->dbc
= cpu_to_le32(buf
[0]) & 0xffffff;
897 addr
= cpu_to_le32(buf
[1]);
899 /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
900 * table, bits [31:24] */
901 if (lsi_dma_40bit(s
))
902 addr_high
= cpu_to_le32(buf
[0]) >> 24;
904 if ((s
->sstat1
& PHASE_MASK
) != ((insn
>> 24) & 7)) {
905 DPRINTF("Wrong phase got %d expected %d\n",
906 s
->sstat1
& PHASE_MASK
, (insn
>> 24) & 7);
907 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
911 s
->dnad64
= addr_high
;
914 switch (s
->sstat1
& 0x7) {
923 s
->current_dma_len
= s
->dbc
;
941 BADF("Unimplemented phase %d\n", s
->sstat1
& PHASE_MASK
);
944 s
->dfifo
= s
->dbc
& 0xff;
945 s
->ctest5
= (s
->ctest5
& 0xfc) | ((s
->dbc
>> 8) & 3);
948 s
->ua
= addr
+ s
->dbc
;
951 case 1: /* IO or Read/Write instruction. */
952 opcode
= (insn
>> 27) & 7;
956 if (insn
& (1 << 25)) {
957 id
= read_dword(s
, s
->dsa
+ sxt24(insn
));
961 id
= (id
>> 16) & 0xf;
962 if (insn
& (1 << 26)) {
963 addr
= s
->dsp
+ sxt24(addr
);
969 if (s
->current_dma_len
&& (s
->ssid
& 0xf) == id
) {
970 DPRINTF("Already reselected by target %d\n", id
);
973 s
->sstat0
|= LSI_SSTAT0_WOA
;
974 s
->scntl1
&= ~LSI_SCNTL1_IARB
;
975 if (id
>= LSI_MAX_DEVS
|| !s
->scsi_dev
[id
]) {
976 DPRINTF("Selected absent target %d\n", id
);
977 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_STO
);
981 DPRINTF("Selected target %d%s\n",
982 id
, insn
& (1 << 3) ? " ATN" : "");
983 /* ??? Linux drivers compain when this is set. Maybe
984 it only applies in low-level mode (unimplemented).
985 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
986 s
->current_dev
= s
->scsi_dev
[id
];
987 s
->current_tag
= id
<< 8;
988 s
->scntl1
|= LSI_SCNTL1_CON
;
989 if (insn
& (1 << 3)) {
990 s
->socl
|= LSI_SOCL_ATN
;
992 lsi_set_phase(s
, PHASE_MO
);
994 case 1: /* Disconnect */
995 DPRINTF("Wait Disconect\n");
996 s
->scntl1
&= ~LSI_SCNTL1_CON
;
998 case 2: /* Wait Reselect */
999 lsi_wait_reselect(s
);
1002 DPRINTF("Set%s%s%s%s\n",
1003 insn
& (1 << 3) ? " ATN" : "",
1004 insn
& (1 << 6) ? " ACK" : "",
1005 insn
& (1 << 9) ? " TM" : "",
1006 insn
& (1 << 10) ? " CC" : "");
1007 if (insn
& (1 << 3)) {
1008 s
->socl
|= LSI_SOCL_ATN
;
1009 lsi_set_phase(s
, PHASE_MO
);
1011 if (insn
& (1 << 9)) {
1012 BADF("Target mode not implemented\n");
1015 if (insn
& (1 << 10))
1019 DPRINTF("Clear%s%s%s%s\n",
1020 insn
& (1 << 3) ? " ATN" : "",
1021 insn
& (1 << 6) ? " ACK" : "",
1022 insn
& (1 << 9) ? " TM" : "",
1023 insn
& (1 << 10) ? " CC" : "");
1024 if (insn
& (1 << 3)) {
1025 s
->socl
&= ~LSI_SOCL_ATN
;
1027 if (insn
& (1 << 10))
1038 static const char *opcode_names
[3] =
1039 {"Write", "Read", "Read-Modify-Write"};
1040 static const char *operator_names
[8] =
1041 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1044 reg
= ((insn
>> 16) & 0x7f) | (insn
& 0x80);
1045 data8
= (insn
>> 8) & 0xff;
1046 opcode
= (insn
>> 27) & 7;
1047 operator = (insn
>> 24) & 7;
1048 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1049 opcode_names
[opcode
- 5], reg
,
1050 operator_names
[operator], data8
, s
->sfbr
,
1051 (insn
& (1 << 23)) ? " SFBR" : "");
1054 case 5: /* From SFBR */
1058 case 6: /* To SFBR */
1060 op0
= lsi_reg_readb(s
, reg
);
1063 case 7: /* Read-modify-write */
1065 op0
= lsi_reg_readb(s
, reg
);
1066 if (insn
& (1 << 23)) {
1078 case 1: /* Shift left */
1080 op0
= (op0
<< 1) | s
->carry
;
1094 op0
= (op0
>> 1) | (s
->carry
<< 7);
1099 s
->carry
= op0
< op1
;
1102 op0
+= op1
+ s
->carry
;
1104 s
->carry
= op0
<= op1
;
1106 s
->carry
= op0
< op1
;
1111 case 5: /* From SFBR */
1112 case 7: /* Read-modify-write */
1113 lsi_reg_writeb(s
, reg
, op0
);
1115 case 6: /* To SFBR */
1122 case 2: /* Transfer Control. */
1127 if ((insn
& 0x002e0000) == 0) {
1131 if (s
->sist1
& LSI_SIST1_STO
) {
1132 DPRINTF("Delayed select timeout\n");
1136 cond
= jmp
= (insn
& (1 << 19)) != 0;
1137 if (cond
== jmp
&& (insn
& (1 << 21))) {
1138 DPRINTF("Compare carry %d\n", s
->carry
== jmp
);
1139 cond
= s
->carry
!= 0;
1141 if (cond
== jmp
&& (insn
& (1 << 17))) {
1142 DPRINTF("Compare phase %d %c= %d\n",
1143 (s
->sstat1
& PHASE_MASK
),
1145 ((insn
>> 24) & 7));
1146 cond
= (s
->sstat1
& PHASE_MASK
) == ((insn
>> 24) & 7);
1148 if (cond
== jmp
&& (insn
& (1 << 18))) {
1151 mask
= (~insn
>> 8) & 0xff;
1152 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1153 s
->sfbr
, mask
, jmp
? '=' : '!', insn
& mask
);
1154 cond
= (s
->sfbr
& mask
) == (insn
& mask
);
1157 if (insn
& (1 << 23)) {
1158 /* Relative address. */
1159 addr
= s
->dsp
+ sxt24(addr
);
1161 switch ((insn
>> 27) & 7) {
1163 DPRINTF("Jump to 0x%08x\n", addr
);
1167 DPRINTF("Call 0x%08x\n", addr
);
1171 case 2: /* Return */
1172 DPRINTF("Return to 0x%08x\n", s
->temp
);
1175 case 3: /* Interrupt */
1176 DPRINTF("Interrupt 0x%08x\n", s
->dsps
);
1177 if ((insn
& (1 << 20)) != 0) {
1178 s
->istat0
|= LSI_ISTAT0_INTF
;
1181 lsi_script_dma_interrupt(s
, LSI_DSTAT_SIR
);
1185 DPRINTF("Illegal transfer control\n");
1186 lsi_script_dma_interrupt(s
, LSI_DSTAT_IID
);
1190 DPRINTF("Control condition failed\n");
1196 if ((insn
& (1 << 29)) == 0) {
1199 /* ??? The docs imply the destination address is loaded into
1200 the TEMP register. However the Linux drivers rely on
1201 the value being presrved. */
1202 dest
= read_dword(s
, s
->dsp
);
1204 lsi_memcpy(s
, dest
, addr
, insn
& 0xffffff);
1211 if (insn
& (1 << 28)) {
1212 addr
= s
->dsa
+ sxt24(addr
);
1215 reg
= (insn
>> 16) & 0xff;
1216 if (insn
& (1 << 24)) {
1217 cpu_physical_memory_read(addr
, data
, n
);
1218 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg
, n
,
1219 addr
, *(int *)data
);
1220 for (i
= 0; i
< n
; i
++) {
1221 lsi_reg_writeb(s
, reg
+ i
, data
[i
]);
1224 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg
, n
, addr
);
1225 for (i
= 0; i
< n
; i
++) {
1226 data
[i
] = lsi_reg_readb(s
, reg
+ i
);
1228 cpu_physical_memory_write(addr
, data
, n
);
1232 if (insn_processed
> 10000 && !s
->waiting
) {
1233 /* Some windows drivers make the device spin waiting for a memory
1234 location to change. If we have been executed a lot of code then
1235 assume this is the case and force an unexpected device disconnect.
1236 This is apparently sufficient to beat the drivers into submission.
1238 if (!(s
->sien0
& LSI_SIST0_UDC
))
1239 fprintf(stderr
, "inf. loop with UDC masked\n");
1240 lsi_script_scsi_interrupt(s
, LSI_SIST0_UDC
, 0);
1242 } else if (s
->istat1
& LSI_ISTAT1_SRUN
&& !s
->waiting
) {
1243 if (s
->dcntl
& LSI_DCNTL_SSM
) {
1244 lsi_script_dma_interrupt(s
, LSI_DSTAT_SSI
);
1249 DPRINTF("SCRIPTS execution stopped\n");
1252 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
)
1255 #define CASE_GET_REG32(name, addr) \
1256 case addr: return s->name & 0xff; \
1257 case addr + 1: return (s->name >> 8) & 0xff; \
1258 case addr + 2: return (s->name >> 16) & 0xff; \
1259 case addr + 3: return (s->name >> 24) & 0xff;
1261 #ifdef DEBUG_LSI_REG
1262 DPRINTF("Read reg %x\n", offset
);
1265 case 0x00: /* SCNTL0 */
1267 case 0x01: /* SCNTL1 */
1269 case 0x02: /* SCNTL2 */
1271 case 0x03: /* SCNTL3 */
1273 case 0x04: /* SCID */
1275 case 0x05: /* SXFER */
1277 case 0x06: /* SDID */
1279 case 0x07: /* GPREG0 */
1281 case 0x08: /* Revision ID */
1283 case 0xa: /* SSID */
1285 case 0xb: /* SBCL */
1286 /* ??? This is not correct. However it's (hopefully) only
1287 used for diagnostics, so should be ok. */
1289 case 0xc: /* DSTAT */
1290 tmp
= s
->dstat
| 0x80;
1291 if ((s
->istat0
& LSI_ISTAT0_INTF
) == 0)
1295 case 0x0d: /* SSTAT0 */
1297 case 0x0e: /* SSTAT1 */
1299 case 0x0f: /* SSTAT2 */
1300 return s
->scntl1
& LSI_SCNTL1_CON
? 0 : 2;
1301 CASE_GET_REG32(dsa
, 0x10)
1302 case 0x14: /* ISTAT0 */
1304 case 0x16: /* MBOX0 */
1306 case 0x17: /* MBOX1 */
1308 case 0x18: /* CTEST0 */
1310 case 0x19: /* CTEST1 */
1312 case 0x1a: /* CTEST2 */
1313 tmp
= s
->ctest2
| LSI_CTEST2_DACK
| LSI_CTEST2_CM
;
1314 if (s
->istat0
& LSI_ISTAT0_SIGP
) {
1315 s
->istat0
&= ~LSI_ISTAT0_SIGP
;
1316 tmp
|= LSI_CTEST2_SIGP
;
1319 case 0x1b: /* CTEST3 */
1321 CASE_GET_REG32(temp
, 0x1c)
1322 case 0x20: /* DFIFO */
1324 case 0x21: /* CTEST4 */
1326 case 0x22: /* CTEST5 */
1328 case 0x23: /* CTEST6 */
1330 case 0x24: /* DBC[0:7] */
1331 return s
->dbc
& 0xff;
1332 case 0x25: /* DBC[8:15] */
1333 return (s
->dbc
>> 8) & 0xff;
1334 case 0x26: /* DBC[16->23] */
1335 return (s
->dbc
>> 16) & 0xff;
1336 case 0x27: /* DCMD */
1338 CASE_GET_REG32(dsp
, 0x2c)
1339 CASE_GET_REG32(dsps
, 0x30)
1340 CASE_GET_REG32(scratch
[0], 0x34)
1341 case 0x38: /* DMODE */
1343 case 0x39: /* DIEN */
1345 case 0x3b: /* DCNTL */
1347 case 0x40: /* SIEN0 */
1349 case 0x41: /* SIEN1 */
1351 case 0x42: /* SIST0 */
1356 case 0x43: /* SIST1 */
1361 case 0x46: /* MACNTL */
1363 case 0x47: /* GPCNTL0 */
1365 case 0x48: /* STIME0 */
1367 case 0x4a: /* RESPID0 */
1369 case 0x4b: /* RESPID1 */
1371 case 0x4d: /* STEST1 */
1373 case 0x4e: /* STEST2 */
1375 case 0x4f: /* STEST3 */
1377 case 0x50: /* SIDL */
1378 /* This is needed by the linux drivers. We currently only update it
1379 during the MSG IN phase. */
1381 case 0x52: /* STEST4 */
1383 case 0x56: /* CCNTL0 */
1385 case 0x57: /* CCNTL1 */
1387 case 0x58: /* SBDL */
1388 /* Some drivers peek at the data bus during the MSG IN phase. */
1389 if ((s
->sstat1
& PHASE_MASK
) == PHASE_MI
)
1392 case 0x59: /* SBDL high */
1394 CASE_GET_REG32(mmrs
, 0xa0)
1395 CASE_GET_REG32(mmws
, 0xa4)
1396 CASE_GET_REG32(sfs
, 0xa8)
1397 CASE_GET_REG32(drs
, 0xac)
1398 CASE_GET_REG32(sbms
, 0xb0)
1399 CASE_GET_REG32(dmbs
, 0xb4)
1400 CASE_GET_REG32(dnad64
, 0xb8)
1401 CASE_GET_REG32(pmjad1
, 0xc0)
1402 CASE_GET_REG32(pmjad2
, 0xc4)
1403 CASE_GET_REG32(rbc
, 0xc8)
1404 CASE_GET_REG32(ua
, 0xcc)
1405 CASE_GET_REG32(ia
, 0xd4)
1406 CASE_GET_REG32(sbc
, 0xd8)
1407 CASE_GET_REG32(csbc
, 0xdc)
1409 if (offset
>= 0x5c && offset
< 0xa0) {
1412 n
= (offset
- 0x58) >> 2;
1413 shift
= (offset
& 3) * 8;
1414 return (s
->scratch
[n
] >> shift
) & 0xff;
1416 BADF("readb 0x%x\n", offset
);
1418 #undef CASE_GET_REG32
1421 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
)
1423 #define CASE_SET_REG32(name, addr) \
1424 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1425 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1426 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1427 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1429 #ifdef DEBUG_LSI_REG
1430 DPRINTF("Write reg %x = %02x\n", offset
, val
);
1433 case 0x00: /* SCNTL0 */
1435 if (val
& LSI_SCNTL0_START
) {
1436 BADF("Start sequence not implemented\n");
1439 case 0x01: /* SCNTL1 */
1440 s
->scntl1
= val
& ~LSI_SCNTL1_SST
;
1441 if (val
& LSI_SCNTL1_IARB
) {
1442 BADF("Immediate Arbritration not implemented\n");
1444 if (val
& LSI_SCNTL1_RST
) {
1445 s
->sstat0
|= LSI_SSTAT0_RST
;
1446 lsi_script_scsi_interrupt(s
, LSI_SIST0_RST
, 0);
1448 s
->sstat0
&= ~LSI_SSTAT0_RST
;
1451 case 0x02: /* SCNTL2 */
1452 val
&= ~(LSI_SCNTL2_WSR
| LSI_SCNTL2_WSS
);
1455 case 0x03: /* SCNTL3 */
1458 case 0x04: /* SCID */
1461 case 0x05: /* SXFER */
1464 case 0x06: /* SDID */
1465 if ((val
& 0xf) != (s
->ssid
& 0xf))
1466 BADF("Destination ID does not match SSID\n");
1467 s
->sdid
= val
& 0xf;
1469 case 0x07: /* GPREG0 */
1471 case 0x08: /* SFBR */
1472 /* The CPU is not allowed to write to this register. However the
1473 SCRIPTS register move instructions are. */
1476 case 0x0a: case 0x0b:
1477 /* Openserver writes to these readonly registers on startup */
1479 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1480 /* Linux writes to these readonly registers on startup. */
1482 CASE_SET_REG32(dsa
, 0x10)
1483 case 0x14: /* ISTAT0 */
1484 s
->istat0
= (s
->istat0
& 0x0f) | (val
& 0xf0);
1485 if (val
& LSI_ISTAT0_ABRT
) {
1486 lsi_script_dma_interrupt(s
, LSI_DSTAT_ABRT
);
1488 if (val
& LSI_ISTAT0_INTF
) {
1489 s
->istat0
&= ~LSI_ISTAT0_INTF
;
1492 if (s
->waiting
== 1 && val
& LSI_ISTAT0_SIGP
) {
1493 DPRINTF("Woken by SIGP\n");
1496 lsi_execute_script(s
);
1498 if (val
& LSI_ISTAT0_SRST
) {
1502 case 0x16: /* MBOX0 */
1505 case 0x17: /* MBOX1 */
1508 case 0x1a: /* CTEST2 */
1509 s
->ctest2
= val
& LSI_CTEST2_PCICIE
;
1511 case 0x1b: /* CTEST3 */
1512 s
->ctest3
= val
& 0x0f;
1514 CASE_SET_REG32(temp
, 0x1c)
1515 case 0x21: /* CTEST4 */
1517 BADF("Unimplemented CTEST4-FBL 0x%x\n", val
);
1521 case 0x22: /* CTEST5 */
1522 if (val
& (LSI_CTEST5_ADCK
| LSI_CTEST5_BBCK
)) {
1523 BADF("CTEST5 DMA increment not implemented\n");
1527 case 0x2c: /* DSP[0:7] */
1528 s
->dsp
&= 0xffffff00;
1531 case 0x2d: /* DSP[8:15] */
1532 s
->dsp
&= 0xffff00ff;
1535 case 0x2e: /* DSP[16:23] */
1536 s
->dsp
&= 0xff00ffff;
1537 s
->dsp
|= val
<< 16;
1539 case 0x2f: /* DSP[24:31] */
1540 s
->dsp
&= 0x00ffffff;
1541 s
->dsp
|= val
<< 24;
1542 if ((s
->dmode
& LSI_DMODE_MAN
) == 0
1543 && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1544 lsi_execute_script(s
);
1546 CASE_SET_REG32(dsps
, 0x30)
1547 CASE_SET_REG32(scratch
[0], 0x34)
1548 case 0x38: /* DMODE */
1549 if (val
& (LSI_DMODE_SIOM
| LSI_DMODE_DIOM
)) {
1550 BADF("IO mappings not implemented\n");
1554 case 0x39: /* DIEN */
1558 case 0x3b: /* DCNTL */
1559 s
->dcntl
= val
& ~(LSI_DCNTL_PFF
| LSI_DCNTL_STD
);
1560 if ((val
& LSI_DCNTL_STD
) && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1561 lsi_execute_script(s
);
1563 case 0x40: /* SIEN0 */
1567 case 0x41: /* SIEN1 */
1571 case 0x47: /* GPCNTL0 */
1573 case 0x48: /* STIME0 */
1576 case 0x49: /* STIME1 */
1578 DPRINTF("General purpose timer not implemented\n");
1579 /* ??? Raising the interrupt immediately seems to be sufficient
1580 to keep the FreeBSD driver happy. */
1581 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_GEN
);
1584 case 0x4a: /* RESPID0 */
1587 case 0x4b: /* RESPID1 */
1590 case 0x4d: /* STEST1 */
1593 case 0x4e: /* STEST2 */
1595 BADF("Low level mode not implemented\n");
1599 case 0x4f: /* STEST3 */
1601 BADF("SCSI FIFO test mode not implemented\n");
1605 case 0x56: /* CCNTL0 */
1608 case 0x57: /* CCNTL1 */
1611 CASE_SET_REG32(mmrs
, 0xa0)
1612 CASE_SET_REG32(mmws
, 0xa4)
1613 CASE_SET_REG32(sfs
, 0xa8)
1614 CASE_SET_REG32(drs
, 0xac)
1615 CASE_SET_REG32(sbms
, 0xb0)
1616 CASE_SET_REG32(dmbs
, 0xb4)
1617 CASE_SET_REG32(dnad64
, 0xb8)
1618 CASE_SET_REG32(pmjad1
, 0xc0)
1619 CASE_SET_REG32(pmjad2
, 0xc4)
1620 CASE_SET_REG32(rbc
, 0xc8)
1621 CASE_SET_REG32(ua
, 0xcc)
1622 CASE_SET_REG32(ia
, 0xd4)
1623 CASE_SET_REG32(sbc
, 0xd8)
1624 CASE_SET_REG32(csbc
, 0xdc)
1626 if (offset
>= 0x5c && offset
< 0xa0) {
1629 n
= (offset
- 0x58) >> 2;
1630 shift
= (offset
& 3) * 8;
1631 s
->scratch
[n
] &= ~(0xff << shift
);
1632 s
->scratch
[n
] |= (val
& 0xff) << shift
;
1634 BADF("Unhandled writeb 0x%x = 0x%x\n", offset
, val
);
1637 #undef CASE_SET_REG32
1640 static void lsi_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1642 LSIState
*s
= (LSIState
*)opaque
;
1644 lsi_reg_writeb(s
, addr
& 0xff, val
);
1647 static void lsi_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1649 LSIState
*s
= (LSIState
*)opaque
;
1652 lsi_reg_writeb(s
, addr
, val
& 0xff);
1653 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1656 static void lsi_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1658 LSIState
*s
= (LSIState
*)opaque
;
1661 lsi_reg_writeb(s
, addr
, val
& 0xff);
1662 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1663 lsi_reg_writeb(s
, addr
+ 2, (val
>> 16) & 0xff);
1664 lsi_reg_writeb(s
, addr
+ 3, (val
>> 24) & 0xff);
1667 static uint32_t lsi_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1669 LSIState
*s
= (LSIState
*)opaque
;
1671 return lsi_reg_readb(s
, addr
& 0xff);
1674 static uint32_t lsi_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1676 LSIState
*s
= (LSIState
*)opaque
;
1680 val
= lsi_reg_readb(s
, addr
);
1681 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1685 static uint32_t lsi_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1687 LSIState
*s
= (LSIState
*)opaque
;
1690 val
= lsi_reg_readb(s
, addr
);
1691 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1692 val
|= lsi_reg_readb(s
, addr
+ 2) << 16;
1693 val
|= lsi_reg_readb(s
, addr
+ 3) << 24;
1697 static CPUReadMemoryFunc
*lsi_mmio_readfn
[3] = {
1703 static CPUWriteMemoryFunc
*lsi_mmio_writefn
[3] = {
1709 static void lsi_ram_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1711 LSIState
*s
= (LSIState
*)opaque
;
1716 newval
= s
->script_ram
[addr
>> 2];
1717 shift
= (addr
& 3) * 8;
1718 newval
&= ~(0xff << shift
);
1719 newval
|= val
<< shift
;
1720 s
->script_ram
[addr
>> 2] = newval
;
1723 static void lsi_ram_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1725 LSIState
*s
= (LSIState
*)opaque
;
1729 newval
= s
->script_ram
[addr
>> 2];
1731 newval
= (newval
& 0xffff) | (val
<< 16);
1733 newval
= (newval
& 0xffff0000) | val
;
1735 s
->script_ram
[addr
>> 2] = newval
;
1739 static void lsi_ram_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1741 LSIState
*s
= (LSIState
*)opaque
;
1744 s
->script_ram
[addr
>> 2] = val
;
1747 static uint32_t lsi_ram_readb(void *opaque
, target_phys_addr_t addr
)
1749 LSIState
*s
= (LSIState
*)opaque
;
1753 val
= s
->script_ram
[addr
>> 2];
1754 val
>>= (addr
& 3) * 8;
1758 static uint32_t lsi_ram_readw(void *opaque
, target_phys_addr_t addr
)
1760 LSIState
*s
= (LSIState
*)opaque
;
1764 val
= s
->script_ram
[addr
>> 2];
1767 return le16_to_cpu(val
);
1770 static uint32_t lsi_ram_readl(void *opaque
, target_phys_addr_t addr
)
1772 LSIState
*s
= (LSIState
*)opaque
;
1775 return le32_to_cpu(s
->script_ram
[addr
>> 2]);
1778 static CPUReadMemoryFunc
*lsi_ram_readfn
[3] = {
1784 static CPUWriteMemoryFunc
*lsi_ram_writefn
[3] = {
1790 static uint32_t lsi_io_readb(void *opaque
, uint32_t addr
)
1792 LSIState
*s
= (LSIState
*)opaque
;
1793 return lsi_reg_readb(s
, addr
& 0xff);
1796 static uint32_t lsi_io_readw(void *opaque
, uint32_t addr
)
1798 LSIState
*s
= (LSIState
*)opaque
;
1801 val
= lsi_reg_readb(s
, addr
);
1802 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1806 static uint32_t lsi_io_readl(void *opaque
, uint32_t addr
)
1808 LSIState
*s
= (LSIState
*)opaque
;
1811 val
= lsi_reg_readb(s
, addr
);
1812 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1813 val
|= lsi_reg_readb(s
, addr
+ 2) << 16;
1814 val
|= lsi_reg_readb(s
, addr
+ 3) << 24;
1818 static void lsi_io_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
1820 LSIState
*s
= (LSIState
*)opaque
;
1821 lsi_reg_writeb(s
, addr
& 0xff, val
);
1824 static void lsi_io_writew(void *opaque
, uint32_t addr
, uint32_t val
)
1826 LSIState
*s
= (LSIState
*)opaque
;
1828 lsi_reg_writeb(s
, addr
, val
& 0xff);
1829 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1832 static void lsi_io_writel(void *opaque
, uint32_t addr
, uint32_t val
)
1834 LSIState
*s
= (LSIState
*)opaque
;
1836 lsi_reg_writeb(s
, addr
, val
& 0xff);
1837 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1838 lsi_reg_writeb(s
, addr
+ 2, (val
>> 16) & 0xff);
1839 lsi_reg_writeb(s
, addr
+ 3, (val
>> 24) & 0xff);
1842 static void lsi_io_mapfunc(PCIDevice
*pci_dev
, int region_num
,
1843 uint32_t addr
, uint32_t size
, int type
)
1845 LSIState
*s
= (LSIState
*)pci_dev
;
1847 DPRINTF("Mapping IO at %08x\n", addr
);
1849 register_ioport_write(addr
, 256, 1, lsi_io_writeb
, s
);
1850 register_ioport_read(addr
, 256, 1, lsi_io_readb
, s
);
1851 register_ioport_write(addr
, 256, 2, lsi_io_writew
, s
);
1852 register_ioport_read(addr
, 256, 2, lsi_io_readw
, s
);
1853 register_ioport_write(addr
, 256, 4, lsi_io_writel
, s
);
1854 register_ioport_read(addr
, 256, 4, lsi_io_readl
, s
);
1857 static void lsi_ram_mapfunc(PCIDevice
*pci_dev
, int region_num
,
1858 uint32_t addr
, uint32_t size
, int type
)
1860 LSIState
*s
= (LSIState
*)pci_dev
;
1862 DPRINTF("Mapping ram at %08x\n", addr
);
1863 s
->script_ram_base
= addr
;
1864 cpu_register_physical_memory(addr
+ 0, 0x2000, s
->ram_io_addr
);
1867 static void lsi_mmio_mapfunc(PCIDevice
*pci_dev
, int region_num
,
1868 uint32_t addr
, uint32_t size
, int type
)
1870 LSIState
*s
= (LSIState
*)pci_dev
;
1872 DPRINTF("Mapping registers at %08x\n", addr
);
1873 cpu_register_physical_memory(addr
+ 0, 0x400, s
->mmio_io_addr
);
1876 void lsi_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
)
1878 LSIState
*s
= (LSIState
*)opaque
;
1881 for (id
= 0; id
< LSI_MAX_DEVS
; id
++) {
1882 if (s
->scsi_dev
[id
] == NULL
)
1886 if (id
>= LSI_MAX_DEVS
) {
1887 BADF("Bad Device ID %d\n", id
);
1890 if (s
->scsi_dev
[id
]) {
1891 DPRINTF("Destroying device %d\n", id
);
1892 s
->scsi_dev
[id
]->destroy(s
->scsi_dev
[id
]);
1894 DPRINTF("Attaching block device %d\n", id
);
1895 s
->scsi_dev
[id
] = scsi_generic_init(bd
, 1, lsi_command_complete
, s
);
1896 if (s
->scsi_dev
[id
] == NULL
)
1897 s
->scsi_dev
[id
] = scsi_disk_init(bd
, 1, lsi_command_complete
, s
);
1900 void *lsi_scsi_init(PCIBus
*bus
, int devfn
)
1904 s
= (LSIState
*)pci_register_device(bus
, "LSI53C895A SCSI HBA",
1905 sizeof(*s
), devfn
, NULL
, NULL
);
1907 fprintf(stderr
, "lsi-scsi: Failed to register PCI device\n");
1911 /* PCI Vendor ID (word) */
1912 s
->pci_dev
.config
[0x00] = 0x00;
1913 s
->pci_dev
.config
[0x01] = 0x10;
1914 /* PCI device ID (word) */
1915 s
->pci_dev
.config
[0x02] = 0x12;
1916 s
->pci_dev
.config
[0x03] = 0x00;
1917 /* PCI base class code */
1918 s
->pci_dev
.config
[0x0b] = 0x01;
1919 /* PCI subsystem ID */
1920 s
->pci_dev
.config
[0x2e] = 0x00;
1921 s
->pci_dev
.config
[0x2f] = 0x10;
1922 /* PCI latency timer = 255 */
1923 s
->pci_dev
.config
[0x0d] = 0xff;
1924 /* Interrupt pin 1 */
1925 s
->pci_dev
.config
[0x3d] = 0x01;
1927 s
->mmio_io_addr
= cpu_register_io_memory(0, lsi_mmio_readfn
,
1928 lsi_mmio_writefn
, s
);
1929 s
->ram_io_addr
= cpu_register_io_memory(0, lsi_ram_readfn
,
1930 lsi_ram_writefn
, s
);
1932 pci_register_io_region((struct PCIDevice
*)s
, 0, 256,
1933 PCI_ADDRESS_SPACE_IO
, lsi_io_mapfunc
);
1934 pci_register_io_region((struct PCIDevice
*)s
, 1, 0x400,
1935 PCI_ADDRESS_SPACE_MEM
, lsi_mmio_mapfunc
);
1936 pci_register_io_region((struct PCIDevice
*)s
, 2, 0x2000,
1937 PCI_ADDRESS_SPACE_MEM
, lsi_ram_mapfunc
);
1938 s
->queue
= qemu_malloc(sizeof(lsi_queue
));
1940 s
->active_commands
= 0;