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Prepare for handling different BSD mmap() flags
[qemu/mini2440/sniper_sniper_test.git] / hw / cirrus_vga.c
blobe0cf458d76771ba8b3c25578fd07e52f7806464e
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35
36 /*
37 * TODO:
38 * - destination write mask support not complete (bits 5..7)
39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
43 //#define DEBUG_CIRRUS
44 //#define DEBUG_BITBLT
45
46 /***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
52 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
53
54 // ID
55 #define CIRRUS_ID_CLGD5422 (0x23<<2)
56 #define CIRRUS_ID_CLGD5426 (0x24<<2)
57 #define CIRRUS_ID_CLGD5424 (0x25<<2)
58 #define CIRRUS_ID_CLGD5428 (0x26<<2)
59 #define CIRRUS_ID_CLGD5430 (0x28<<2)
60 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
61 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
62 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
63
64 // sequencer 0x07
65 #define CIRRUS_SR7_BPP_VGA 0x00
66 #define CIRRUS_SR7_BPP_SVGA 0x01
67 #define CIRRUS_SR7_BPP_MASK 0x0e
68 #define CIRRUS_SR7_BPP_8 0x00
69 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
70 #define CIRRUS_SR7_BPP_24 0x04
71 #define CIRRUS_SR7_BPP_16 0x06
72 #define CIRRUS_SR7_BPP_32 0x08
73 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
74
75 // sequencer 0x0f
76 #define CIRRUS_MEMSIZE_512k 0x08
77 #define CIRRUS_MEMSIZE_1M 0x10
78 #define CIRRUS_MEMSIZE_2M 0x18
79 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
80
81 // sequencer 0x12
82 #define CIRRUS_CURSOR_SHOW 0x01
83 #define CIRRUS_CURSOR_HIDDENPEL 0x02
84 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
85
86 // sequencer 0x17
87 #define CIRRUS_BUSTYPE_VLBFAST 0x10
88 #define CIRRUS_BUSTYPE_PCI 0x20
89 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
90 #define CIRRUS_BUSTYPE_ISA 0x38
91 #define CIRRUS_MMIO_ENABLE 0x04
92 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
93 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
94
95 // control 0x0b
96 #define CIRRUS_BANKING_DUAL 0x01
97 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
98
99 // control 0x30
100 #define CIRRUS_BLTMODE_BACKWARDS 0x01
101 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
102 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
103 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
104 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
105 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
106 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
107 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
108 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
109 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
110 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
111
112 // control 0x31
113 #define CIRRUS_BLT_BUSY 0x01
114 #define CIRRUS_BLT_START 0x02
115 #define CIRRUS_BLT_RESET 0x04
116 #define CIRRUS_BLT_FIFOUSED 0x10
117 #define CIRRUS_BLT_AUTOSTART 0x80
118
119 // control 0x32
120 #define CIRRUS_ROP_0 0x00
121 #define CIRRUS_ROP_SRC_AND_DST 0x05
122 #define CIRRUS_ROP_NOP 0x06
123 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
124 #define CIRRUS_ROP_NOTDST 0x0b
125 #define CIRRUS_ROP_SRC 0x0d
126 #define CIRRUS_ROP_1 0x0e
127 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
128 #define CIRRUS_ROP_SRC_XOR_DST 0x59
129 #define CIRRUS_ROP_SRC_OR_DST 0x6d
130 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
131 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
132 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
133 #define CIRRUS_ROP_NOTSRC 0xd0
134 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
135 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136
137 #define CIRRUS_ROP_NOP_INDEX 2
138 #define CIRRUS_ROP_SRC_INDEX 5
139
140 // control 0x33
141 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
142 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
143 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
144
145 // memory-mapped IO
146 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
147 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
148 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
149 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
150 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
151 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
152 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
153 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
154 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
155 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
156 #define CIRRUS_MMIO_BLTROP 0x1a // byte
157 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
160 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
161 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
168 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
169 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
170 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
171 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
172 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
173 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
174 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175
176 // PCI 0x00: vendor, 0x02: device
177 #define PCI_VENDOR_CIRRUS 0x1013
178 #define PCI_DEVICE_CLGD5462 0x00d0
179 #define PCI_DEVICE_CLGD5465 0x00d6
180
181 // PCI 0x04: command(word), 0x06(word): status
182 #define PCI_COMMAND_IOACCESS 0x0001
183 #define PCI_COMMAND_MEMACCESS 0x0002
184 #define PCI_COMMAND_BUSMASTER 0x0004
185 #define PCI_COMMAND_SPECIALCYCLE 0x0008
186 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
187 #define PCI_COMMAND_PALETTESNOOPING 0x0020
188 #define PCI_COMMAND_PARITYDETECTION 0x0040
189 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
190 #define PCI_COMMAND_SERR 0x0100
191 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
192 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
193 #define PCI_CLASS_BASE_DISPLAY 0x03
194 // PCI 0x08, 0x00ff0000
195 #define PCI_CLASS_SUB_VGA 0x00
196 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
197 #define PCI_CLASS_HEADERTYPE_00h 0x00
198 // 0x10-0x3f (headertype 00h)
199 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
200 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
201 #define PCI_MAP_MEM 0x0
202 #define PCI_MAP_IO 0x1
203 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
204 #define PCI_MAP_IO_ADDR_MASK (~0x3)
205 #define PCI_MAP_MEMFLAGS_32BIT 0x0
206 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
207 #define PCI_MAP_MEMFLAGS_64BIT 0x4
208 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
209 // PCI 0x28: cardbus CIS pointer
210 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
211 // PCI 0x30: expansion ROM base address
212 #define PCI_ROMBIOS_ENABLED 0x1
213 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
214 // PCI 0x38: reserved
215 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
216
217 #define CIRRUS_PNPMMIO_SIZE 0x1000
218
219
220 /* I/O and memory hook */
221 #define CIRRUS_HOOK_NOT_HANDLED 0
222 #define CIRRUS_HOOK_HANDLED 1
223
224 #define BLTUNSAFE(s) \
225 ( \
226 ( /* check dst is within bounds */ \
227 (s)->cirrus_blt_height * (s)->cirrus_blt_dstpitch \
228 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
229 (s)->vram_size \
230 ) || \
231 ( /* check src is within bounds */ \
232 (s)->cirrus_blt_height * (s)->cirrus_blt_srcpitch \
233 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
234 (s)->vram_size \
235 ) \
236 )
237
238 struct CirrusVGAState;
239 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
240 uint8_t * dst, const uint8_t * src,
241 int dstpitch, int srcpitch,
242 int bltwidth, int bltheight);
243 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
244 uint8_t *dst, int dst_pitch, int width, int height);
245
246 typedef struct CirrusVGAState {
247 VGA_STATE_COMMON
248
249 int cirrus_linear_io_addr;
250 int cirrus_linear_bitblt_io_addr;
251 int cirrus_mmio_io_addr;
252 uint32_t cirrus_addr_mask;
253 uint32_t linear_mmio_mask;
254 uint8_t cirrus_shadow_gr0;
255 uint8_t cirrus_shadow_gr1;
256 uint8_t cirrus_hidden_dac_lockindex;
257 uint8_t cirrus_hidden_dac_data;
258 uint32_t cirrus_bank_base[2];
259 uint32_t cirrus_bank_limit[2];
260 uint8_t cirrus_hidden_palette[48];
261 uint32_t hw_cursor_x;
262 uint32_t hw_cursor_y;
263 int cirrus_blt_pixelwidth;
264 int cirrus_blt_width;
265 int cirrus_blt_height;
266 int cirrus_blt_dstpitch;
267 int cirrus_blt_srcpitch;
268 uint32_t cirrus_blt_fgcol;
269 uint32_t cirrus_blt_bgcol;
270 uint32_t cirrus_blt_dstaddr;
271 uint32_t cirrus_blt_srcaddr;
272 uint8_t cirrus_blt_mode;
273 uint8_t cirrus_blt_modeext;
274 cirrus_bitblt_rop_t cirrus_rop;
275 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
276 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
277 uint8_t *cirrus_srcptr;
278 uint8_t *cirrus_srcptr_end;
279 uint32_t cirrus_srccounter;
280 /* hwcursor display state */
281 int last_hw_cursor_size;
282 int last_hw_cursor_x;
283 int last_hw_cursor_y;
284 int last_hw_cursor_y_start;
285 int last_hw_cursor_y_end;
286 int real_vram_size; /* XXX: suppress that */
287 CPUWriteMemoryFunc **cirrus_linear_write;
288 } CirrusVGAState;
289
290 typedef struct PCICirrusVGAState {
291 PCIDevice dev;
292 CirrusVGAState cirrus_vga;
293 } PCICirrusVGAState;
294
295 static uint8_t rop_to_index[256];
296
297 /***************************************
298 *
299 * prototypes.
300 *
301 ***************************************/
302
303
304 static void cirrus_bitblt_reset(CirrusVGAState *s);
305 static void cirrus_update_memory_access(CirrusVGAState *s);
306
307 /***************************************
308 *
309 * raster operations
310 *
311 ***************************************/
312
313 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
314 uint8_t *dst,const uint8_t *src,
315 int dstpitch,int srcpitch,
316 int bltwidth,int bltheight)
317 {
318 }
319
320 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
321 uint8_t *dst,
322 int dstpitch, int bltwidth,int bltheight)
323 {
324 }
325
326 #define ROP_NAME 0
327 #define ROP_OP(d, s) d = 0
328 #include "cirrus_vga_rop.h"
329
330 #define ROP_NAME src_and_dst
331 #define ROP_OP(d, s) d = (s) & (d)
332 #include "cirrus_vga_rop.h"
333
334 #define ROP_NAME src_and_notdst
335 #define ROP_OP(d, s) d = (s) & (~(d))
336 #include "cirrus_vga_rop.h"
337
338 #define ROP_NAME notdst
339 #define ROP_OP(d, s) d = ~(d)
340 #include "cirrus_vga_rop.h"
341
342 #define ROP_NAME src
343 #define ROP_OP(d, s) d = s
344 #include "cirrus_vga_rop.h"
345
346 #define ROP_NAME 1
347 #define ROP_OP(d, s) d = ~0
348 #include "cirrus_vga_rop.h"
349
350 #define ROP_NAME notsrc_and_dst
351 #define ROP_OP(d, s) d = (~(s)) & (d)
352 #include "cirrus_vga_rop.h"
353
354 #define ROP_NAME src_xor_dst
355 #define ROP_OP(d, s) d = (s) ^ (d)
356 #include "cirrus_vga_rop.h"
357
358 #define ROP_NAME src_or_dst
359 #define ROP_OP(d, s) d = (s) | (d)
360 #include "cirrus_vga_rop.h"
361
362 #define ROP_NAME notsrc_or_notdst
363 #define ROP_OP(d, s) d = (~(s)) | (~(d))
364 #include "cirrus_vga_rop.h"
365
366 #define ROP_NAME src_notxor_dst
367 #define ROP_OP(d, s) d = ~((s) ^ (d))
368 #include "cirrus_vga_rop.h"
369
370 #define ROP_NAME src_or_notdst
371 #define ROP_OP(d, s) d = (s) | (~(d))
372 #include "cirrus_vga_rop.h"
373
374 #define ROP_NAME notsrc
375 #define ROP_OP(d, s) d = (~(s))
376 #include "cirrus_vga_rop.h"
377
378 #define ROP_NAME notsrc_or_dst
379 #define ROP_OP(d, s) d = (~(s)) | (d)
380 #include "cirrus_vga_rop.h"
381
382 #define ROP_NAME notsrc_and_notdst
383 #define ROP_OP(d, s) d = (~(s)) & (~(d))
384 #include "cirrus_vga_rop.h"
385
386 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
387 cirrus_bitblt_rop_fwd_0,
388 cirrus_bitblt_rop_fwd_src_and_dst,
389 cirrus_bitblt_rop_nop,
390 cirrus_bitblt_rop_fwd_src_and_notdst,
391 cirrus_bitblt_rop_fwd_notdst,
392 cirrus_bitblt_rop_fwd_src,
393 cirrus_bitblt_rop_fwd_1,
394 cirrus_bitblt_rop_fwd_notsrc_and_dst,
395 cirrus_bitblt_rop_fwd_src_xor_dst,
396 cirrus_bitblt_rop_fwd_src_or_dst,
397 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
398 cirrus_bitblt_rop_fwd_src_notxor_dst,
399 cirrus_bitblt_rop_fwd_src_or_notdst,
400 cirrus_bitblt_rop_fwd_notsrc,
401 cirrus_bitblt_rop_fwd_notsrc_or_dst,
402 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
403 };
404
405 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
406 cirrus_bitblt_rop_bkwd_0,
407 cirrus_bitblt_rop_bkwd_src_and_dst,
408 cirrus_bitblt_rop_nop,
409 cirrus_bitblt_rop_bkwd_src_and_notdst,
410 cirrus_bitblt_rop_bkwd_notdst,
411 cirrus_bitblt_rop_bkwd_src,
412 cirrus_bitblt_rop_bkwd_1,
413 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
414 cirrus_bitblt_rop_bkwd_src_xor_dst,
415 cirrus_bitblt_rop_bkwd_src_or_dst,
416 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
417 cirrus_bitblt_rop_bkwd_src_notxor_dst,
418 cirrus_bitblt_rop_bkwd_src_or_notdst,
419 cirrus_bitblt_rop_bkwd_notsrc,
420 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
421 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
422 };
423
424 #define TRANSP_ROP(name) {\
425 name ## _8,\
426 name ## _16,\
427 }
428 #define TRANSP_NOP(func) {\
429 func,\
430 func,\
431 }
432
433 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
436 TRANSP_NOP(cirrus_bitblt_rop_nop),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
450 };
451
452 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
455 TRANSP_NOP(cirrus_bitblt_rop_nop),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
469 };
470
471 #define ROP2(name) {\
472 name ## _8,\
473 name ## _16,\
474 name ## _24,\
475 name ## _32,\
476 }
477
478 #define ROP_NOP2(func) {\
479 func,\
480 func,\
481 func,\
482 func,\
483 }
484
485 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
486 ROP2(cirrus_patternfill_0),
487 ROP2(cirrus_patternfill_src_and_dst),
488 ROP_NOP2(cirrus_bitblt_rop_nop),
489 ROP2(cirrus_patternfill_src_and_notdst),
490 ROP2(cirrus_patternfill_notdst),
491 ROP2(cirrus_patternfill_src),
492 ROP2(cirrus_patternfill_1),
493 ROP2(cirrus_patternfill_notsrc_and_dst),
494 ROP2(cirrus_patternfill_src_xor_dst),
495 ROP2(cirrus_patternfill_src_or_dst),
496 ROP2(cirrus_patternfill_notsrc_or_notdst),
497 ROP2(cirrus_patternfill_src_notxor_dst),
498 ROP2(cirrus_patternfill_src_or_notdst),
499 ROP2(cirrus_patternfill_notsrc),
500 ROP2(cirrus_patternfill_notsrc_or_dst),
501 ROP2(cirrus_patternfill_notsrc_and_notdst),
502 };
503
504 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
505 ROP2(cirrus_colorexpand_transp_0),
506 ROP2(cirrus_colorexpand_transp_src_and_dst),
507 ROP_NOP2(cirrus_bitblt_rop_nop),
508 ROP2(cirrus_colorexpand_transp_src_and_notdst),
509 ROP2(cirrus_colorexpand_transp_notdst),
510 ROP2(cirrus_colorexpand_transp_src),
511 ROP2(cirrus_colorexpand_transp_1),
512 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
513 ROP2(cirrus_colorexpand_transp_src_xor_dst),
514 ROP2(cirrus_colorexpand_transp_src_or_dst),
515 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
516 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
517 ROP2(cirrus_colorexpand_transp_src_or_notdst),
518 ROP2(cirrus_colorexpand_transp_notsrc),
519 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
520 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
521 };
522
523 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
524 ROP2(cirrus_colorexpand_0),
525 ROP2(cirrus_colorexpand_src_and_dst),
526 ROP_NOP2(cirrus_bitblt_rop_nop),
527 ROP2(cirrus_colorexpand_src_and_notdst),
528 ROP2(cirrus_colorexpand_notdst),
529 ROP2(cirrus_colorexpand_src),
530 ROP2(cirrus_colorexpand_1),
531 ROP2(cirrus_colorexpand_notsrc_and_dst),
532 ROP2(cirrus_colorexpand_src_xor_dst),
533 ROP2(cirrus_colorexpand_src_or_dst),
534 ROP2(cirrus_colorexpand_notsrc_or_notdst),
535 ROP2(cirrus_colorexpand_src_notxor_dst),
536 ROP2(cirrus_colorexpand_src_or_notdst),
537 ROP2(cirrus_colorexpand_notsrc),
538 ROP2(cirrus_colorexpand_notsrc_or_dst),
539 ROP2(cirrus_colorexpand_notsrc_and_notdst),
540 };
541
542 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
543 ROP2(cirrus_colorexpand_pattern_transp_0),
544 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
545 ROP_NOP2(cirrus_bitblt_rop_nop),
546 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
547 ROP2(cirrus_colorexpand_pattern_transp_notdst),
548 ROP2(cirrus_colorexpand_pattern_transp_src),
549 ROP2(cirrus_colorexpand_pattern_transp_1),
550 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
551 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
552 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
553 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
554 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
555 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
556 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
557 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
558 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
559 };
560
561 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
562 ROP2(cirrus_colorexpand_pattern_0),
563 ROP2(cirrus_colorexpand_pattern_src_and_dst),
564 ROP_NOP2(cirrus_bitblt_rop_nop),
565 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
566 ROP2(cirrus_colorexpand_pattern_notdst),
567 ROP2(cirrus_colorexpand_pattern_src),
568 ROP2(cirrus_colorexpand_pattern_1),
569 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
570 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
571 ROP2(cirrus_colorexpand_pattern_src_or_dst),
572 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
573 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
574 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
575 ROP2(cirrus_colorexpand_pattern_notsrc),
576 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
577 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
578 };
579
580 static const cirrus_fill_t cirrus_fill[16][4] = {
581 ROP2(cirrus_fill_0),
582 ROP2(cirrus_fill_src_and_dst),
583 ROP_NOP2(cirrus_bitblt_fill_nop),
584 ROP2(cirrus_fill_src_and_notdst),
585 ROP2(cirrus_fill_notdst),
586 ROP2(cirrus_fill_src),
587 ROP2(cirrus_fill_1),
588 ROP2(cirrus_fill_notsrc_and_dst),
589 ROP2(cirrus_fill_src_xor_dst),
590 ROP2(cirrus_fill_src_or_dst),
591 ROP2(cirrus_fill_notsrc_or_notdst),
592 ROP2(cirrus_fill_src_notxor_dst),
593 ROP2(cirrus_fill_src_or_notdst),
594 ROP2(cirrus_fill_notsrc),
595 ROP2(cirrus_fill_notsrc_or_dst),
596 ROP2(cirrus_fill_notsrc_and_notdst),
597 };
598
599 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
600 {
601 unsigned int color;
602 switch (s->cirrus_blt_pixelwidth) {
603 case 1:
604 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
605 break;
606 case 2:
607 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
608 s->cirrus_blt_fgcol = le16_to_cpu(color);
609 break;
610 case 3:
611 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
612 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
613 break;
614 default:
615 case 4:
616 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
617 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
618 s->cirrus_blt_fgcol = le32_to_cpu(color);
619 break;
620 }
621 }
622
623 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
624 {
625 unsigned int color;
626 switch (s->cirrus_blt_pixelwidth) {
627 case 1:
628 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
629 break;
630 case 2:
631 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
632 s->cirrus_blt_bgcol = le16_to_cpu(color);
633 break;
634 case 3:
635 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
636 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
637 break;
638 default:
639 case 4:
640 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
641 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
642 s->cirrus_blt_bgcol = le32_to_cpu(color);
643 break;
644 }
645 }
646
647 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
648 int off_pitch, int bytesperline,
649 int lines)
650 {
651 int y;
652 int off_cur;
653 int off_cur_end;
654
655 for (y = 0; y < lines; y++) {
656 off_cur = off_begin;
657 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
658 off_cur &= TARGET_PAGE_MASK;
659 while (off_cur < off_cur_end) {
660 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
661 off_cur += TARGET_PAGE_SIZE;
662 }
663 off_begin += off_pitch;
664 }
665 }
666
667 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
668 const uint8_t * src)
669 {
670 uint8_t *dst;
671
672 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
673
674 if (BLTUNSAFE(s))
675 return 0;
676
677 (*s->cirrus_rop) (s, dst, src,
678 s->cirrus_blt_dstpitch, 0,
679 s->cirrus_blt_width, s->cirrus_blt_height);
680 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
681 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
682 s->cirrus_blt_height);
683 return 1;
684 }
685
686 /* fill */
687
688 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
689 {
690 cirrus_fill_t rop_func;
691
692 if (BLTUNSAFE(s))
693 return 0;
694 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
695 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
696 s->cirrus_blt_dstpitch,
697 s->cirrus_blt_width, s->cirrus_blt_height);
698 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
699 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
700 s->cirrus_blt_height);
701 cirrus_bitblt_reset(s);
702 return 1;
703 }
704
705 /***************************************
706 *
707 * bitblt (video-to-video)
708 *
709 ***************************************/
710
711 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
712 {
713 return cirrus_bitblt_common_patterncopy(s,
714 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
715 s->cirrus_addr_mask));
716 }
717
718 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
719 {
720 int sx, sy;
721 int dx, dy;
722 int width, height;
723 int depth;
724 int notify = 0;
725
726 depth = s->get_bpp((VGAState *)s) / 8;
727 s->get_resolution((VGAState *)s, &width, &height);
728
729 /* extra x, y */
730 sx = (src % (width * depth)) / depth;
731 sy = (src / (width * depth));
732 dx = (dst % (width *depth)) / depth;
733 dy = (dst / (width * depth));
734
735 /* normalize width */
736 w /= depth;
737
738 /* if we're doing a backward copy, we have to adjust
739 our x/y to be the upper left corner (instead of the lower
740 right corner) */
741 if (s->cirrus_blt_dstpitch < 0) {
742 sx -= (s->cirrus_blt_width / depth) - 1;
743 dx -= (s->cirrus_blt_width / depth) - 1;
744 sy -= s->cirrus_blt_height - 1;
745 dy -= s->cirrus_blt_height - 1;
746 }
747
748 /* are we in the visible portion of memory? */
749 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
750 (sx + w) <= width && (sy + h) <= height &&
751 (dx + w) <= width && (dy + h) <= height) {
752 notify = 1;
753 }
754
755 /* make to sure only copy if it's a plain copy ROP */
756 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
757 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
758 notify = 0;
759
760 /* we have to flush all pending changes so that the copy
761 is generated at the appropriate moment in time */
762 if (notify)
763 vga_hw_update();
764
765 (*s->cirrus_rop) (s, s->vram_ptr +
766 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
767 s->vram_ptr +
768 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
769 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
770 s->cirrus_blt_width, s->cirrus_blt_height);
771
772 if (notify)
773 qemu_console_copy(s->console,
774 sx, sy, dx, dy,
775 s->cirrus_blt_width / depth,
776 s->cirrus_blt_height);
777
778 /* we don't have to notify the display that this portion has
779 changed since qemu_console_copy implies this */
780
781 if (!notify)
782 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
783 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
784 s->cirrus_blt_height);
785 }
786
787 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
788 {
789 if (BLTUNSAFE(s))
790 return 0;
791
792 if (s->ds->dpy_copy) {
793 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
794 s->cirrus_blt_srcaddr - s->start_addr,
795 s->cirrus_blt_width, s->cirrus_blt_height);
796 } else {
797 (*s->cirrus_rop) (s, s->vram_ptr +
798 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
799 s->vram_ptr +
800 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
801 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
802 s->cirrus_blt_width, s->cirrus_blt_height);
803
804 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
805 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
806 s->cirrus_blt_height);
807 }
808
809 return 1;
810 }
811
812 /***************************************
813 *
814 * bitblt (cpu-to-video)
815 *
816 ***************************************/
817
818 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
819 {
820 int copy_count;
821 uint8_t *end_ptr;
822
823 if (s->cirrus_srccounter > 0) {
824 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
825 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
826 the_end:
827 s->cirrus_srccounter = 0;
828 cirrus_bitblt_reset(s);
829 } else {
830 /* at least one scan line */
831 do {
832 (*s->cirrus_rop)(s, s->vram_ptr +
833 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
834 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
835 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
836 s->cirrus_blt_width, 1);
837 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
838 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
839 if (s->cirrus_srccounter <= 0)
840 goto the_end;
841 /* more bytes than needed can be transfered because of
842 word alignment, so we keep them for the next line */
843 /* XXX: keep alignment to speed up transfer */
844 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
845 copy_count = s->cirrus_srcptr_end - end_ptr;
846 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
847 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
848 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
849 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
850 }
851 }
852 }
853
854 /***************************************
855 *
856 * bitblt wrapper
857 *
858 ***************************************/
859
860 static void cirrus_bitblt_reset(CirrusVGAState * s)
861 {
862 s->gr[0x31] &=
863 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
864 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
865 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
866 s->cirrus_srccounter = 0;
867 cirrus_update_memory_access(s);
868 }
869
870 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
871 {
872 int w;
873
874 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
875 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
876 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
877
878 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
879 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
880 s->cirrus_blt_srcpitch = 8;
881 } else {
882 /* XXX: check for 24 bpp */
883 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
884 }
885 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
886 } else {
887 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
888 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
889 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
890 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
891 else
892 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
893 } else {
894 /* always align input size to 32 bits */
895 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
896 }
897 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
898 }
899 s->cirrus_srcptr = s->cirrus_bltbuf;
900 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
901 cirrus_update_memory_access(s);
902 return 1;
903 }
904
905 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
906 {
907 /* XXX */
908 #ifdef DEBUG_BITBLT
909 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
910 #endif
911 return 0;
912 }
913
914 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
915 {
916 int ret;
917
918 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
919 ret = cirrus_bitblt_videotovideo_patterncopy(s);
920 } else {
921 ret = cirrus_bitblt_videotovideo_copy(s);
922 }
923 if (ret)
924 cirrus_bitblt_reset(s);
925 return ret;
926 }
927
928 static void cirrus_bitblt_start(CirrusVGAState * s)
929 {
930 uint8_t blt_rop;
931
932 s->gr[0x31] |= CIRRUS_BLT_BUSY;
933
934 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
935 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
936 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
937 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
938 s->cirrus_blt_dstaddr =
939 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
940 s->cirrus_blt_srcaddr =
941 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
942 s->cirrus_blt_mode = s->gr[0x30];
943 s->cirrus_blt_modeext = s->gr[0x33];
944 blt_rop = s->gr[0x32];
945
946 #ifdef DEBUG_BITBLT
947 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
948 blt_rop,
949 s->cirrus_blt_mode,
950 s->cirrus_blt_modeext,
951 s->cirrus_blt_width,
952 s->cirrus_blt_height,
953 s->cirrus_blt_dstpitch,
954 s->cirrus_blt_srcpitch,
955 s->cirrus_blt_dstaddr,
956 s->cirrus_blt_srcaddr,
957 s->gr[0x2f]);
958 #endif
959
960 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
961 case CIRRUS_BLTMODE_PIXELWIDTH8:
962 s->cirrus_blt_pixelwidth = 1;
963 break;
964 case CIRRUS_BLTMODE_PIXELWIDTH16:
965 s->cirrus_blt_pixelwidth = 2;
966 break;
967 case CIRRUS_BLTMODE_PIXELWIDTH24:
968 s->cirrus_blt_pixelwidth = 3;
969 break;
970 case CIRRUS_BLTMODE_PIXELWIDTH32:
971 s->cirrus_blt_pixelwidth = 4;
972 break;
973 default:
974 #ifdef DEBUG_BITBLT
975 printf("cirrus: bitblt - pixel width is unknown\n");
976 #endif
977 goto bitblt_ignore;
978 }
979 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
980
981 if ((s->
982 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
983 CIRRUS_BLTMODE_MEMSYSDEST))
984 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
985 #ifdef DEBUG_BITBLT
986 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
987 #endif
988 goto bitblt_ignore;
989 }
990
991 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
992 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
993 CIRRUS_BLTMODE_TRANSPARENTCOMP |
994 CIRRUS_BLTMODE_PATTERNCOPY |
995 CIRRUS_BLTMODE_COLOREXPAND)) ==
996 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
997 cirrus_bitblt_fgcol(s);
998 cirrus_bitblt_solidfill(s, blt_rop);
999 } else {
1000 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1001 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1002 CIRRUS_BLTMODE_COLOREXPAND) {
1003
1004 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1005 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1006 cirrus_bitblt_bgcol(s);
1007 else
1008 cirrus_bitblt_fgcol(s);
1009 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1010 } else {
1011 cirrus_bitblt_fgcol(s);
1012 cirrus_bitblt_bgcol(s);
1013 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014 }
1015 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1016 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1017 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1018 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1019 cirrus_bitblt_bgcol(s);
1020 else
1021 cirrus_bitblt_fgcol(s);
1022 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1023 } else {
1024 cirrus_bitblt_fgcol(s);
1025 cirrus_bitblt_bgcol(s);
1026 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1027 }
1028 } else {
1029 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030 }
1031 } else {
1032 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1033 if (s->cirrus_blt_pixelwidth > 2) {
1034 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1035 goto bitblt_ignore;
1036 }
1037 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1038 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1039 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1040 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1041 } else {
1042 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1043 }
1044 } else {
1045 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1046 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1047 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1048 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1049 } else {
1050 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1051 }
1052 }
1053 }
1054 // setup bitblt engine.
1055 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1056 if (!cirrus_bitblt_cputovideo(s))
1057 goto bitblt_ignore;
1058 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1059 if (!cirrus_bitblt_videotocpu(s))
1060 goto bitblt_ignore;
1061 } else {
1062 if (!cirrus_bitblt_videotovideo(s))
1063 goto bitblt_ignore;
1064 }
1065 }
1066 return;
1067 bitblt_ignore:;
1068 cirrus_bitblt_reset(s);
1069 }
1070
1071 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1072 {
1073 unsigned old_value;
1074
1075 old_value = s->gr[0x31];
1076 s->gr[0x31] = reg_value;
1077
1078 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1079 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1080 cirrus_bitblt_reset(s);
1081 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1082 ((reg_value & CIRRUS_BLT_START) != 0)) {
1083 cirrus_bitblt_start(s);
1084 }
1085 }
1086
1087
1088 /***************************************
1089 *
1090 * basic parameters
1091 *
1092 ***************************************/
1093
1094 static void cirrus_get_offsets(VGAState *s1,
1095 uint32_t *pline_offset,
1096 uint32_t *pstart_addr,
1097 uint32_t *pline_compare)
1098 {
1099 CirrusVGAState * s = (CirrusVGAState *)s1;
1100 uint32_t start_addr, line_offset, line_compare;
1101
1102 line_offset = s->cr[0x13]
1103 | ((s->cr[0x1b] & 0x10) << 4);
1104 line_offset <<= 3;
1105 *pline_offset = line_offset;
1106
1107 start_addr = (s->cr[0x0c] << 8)
1108 | s->cr[0x0d]
1109 | ((s->cr[0x1b] & 0x01) << 16)
1110 | ((s->cr[0x1b] & 0x0c) << 15)
1111 | ((s->cr[0x1d] & 0x80) << 12);
1112 *pstart_addr = start_addr;
1113
1114 line_compare = s->cr[0x18] |
1115 ((s->cr[0x07] & 0x10) << 4) |
1116 ((s->cr[0x09] & 0x40) << 3);
1117 *pline_compare = line_compare;
1118 }
1119
1120 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1121 {
1122 uint32_t ret = 16;
1123
1124 switch (s->cirrus_hidden_dac_data & 0xf) {
1125 case 0:
1126 ret = 15;
1127 break; /* Sierra HiColor */
1128 case 1:
1129 ret = 16;
1130 break; /* XGA HiColor */
1131 default:
1132 #ifdef DEBUG_CIRRUS
1133 printf("cirrus: invalid DAC value %x in 16bpp\n",
1134 (s->cirrus_hidden_dac_data & 0xf));
1135 #endif
1136 ret = 15; /* XXX */
1137 break;
1138 }
1139 return ret;
1140 }
1141
1142 static int cirrus_get_bpp(VGAState *s1)
1143 {
1144 CirrusVGAState * s = (CirrusVGAState *)s1;
1145 uint32_t ret = 8;
1146
1147 if ((s->sr[0x07] & 0x01) != 0) {
1148 /* Cirrus SVGA */
1149 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1150 case CIRRUS_SR7_BPP_8:
1151 ret = 8;
1152 break;
1153 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1154 ret = cirrus_get_bpp16_depth(s);
1155 break;
1156 case CIRRUS_SR7_BPP_24:
1157 ret = 24;
1158 break;
1159 case CIRRUS_SR7_BPP_16:
1160 ret = cirrus_get_bpp16_depth(s);
1161 break;
1162 case CIRRUS_SR7_BPP_32:
1163 ret = 32;
1164 break;
1165 default:
1166 #ifdef DEBUG_CIRRUS
1167 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1168 #endif
1169 ret = 8;
1170 break;
1171 }
1172 } else {
1173 /* VGA */
1174 ret = 0;
1175 }
1176
1177 return ret;
1178 }
1179
1180 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1181 {
1182 int width, height;
1183
1184 width = (s->cr[0x01] + 1) * 8;
1185 height = s->cr[0x12] |
1186 ((s->cr[0x07] & 0x02) << 7) |
1187 ((s->cr[0x07] & 0x40) << 3);
1188 height = (height + 1);
1189 /* interlace support */
1190 if (s->cr[0x1a] & 0x01)
1191 height = height * 2;
1192 *pwidth = width;
1193 *pheight = height;
1194 }
1195
1196 /***************************************
1197 *
1198 * bank memory
1199 *
1200 ***************************************/
1201
1202 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1203 {
1204 unsigned offset;
1205 unsigned limit;
1206
1207 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1208 offset = s->gr[0x09 + bank_index];
1209 else /* single bank */
1210 offset = s->gr[0x09];
1211
1212 if ((s->gr[0x0b] & 0x20) != 0)
1213 offset <<= 14;
1214 else
1215 offset <<= 12;
1216
1217 if (s->real_vram_size <= offset)
1218 limit = 0;
1219 else
1220 limit = s->real_vram_size - offset;
1221
1222 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1223 if (limit > 0x8000) {
1224 offset += 0x8000;
1225 limit -= 0x8000;
1226 } else {
1227 limit = 0;
1228 }
1229 }
1230
1231 if (limit > 0) {
1232 /* Thinking about changing bank base? First, drop the dirty bitmap information
1233 * on the current location, otherwise we lose this pointer forever */
1234 if (s->lfb_vram_mapped) {
1235 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1236 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1237 }
1238 s->cirrus_bank_base[bank_index] = offset;
1239 s->cirrus_bank_limit[bank_index] = limit;
1240 } else {
1241 s->cirrus_bank_base[bank_index] = 0;
1242 s->cirrus_bank_limit[bank_index] = 0;
1243 }
1244 }
1245
1246 /***************************************
1247 *
1248 * I/O access between 0x3c4-0x3c5
1249 *
1250 ***************************************/
1251
1252 static int
1253 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1254 {
1255 switch (reg_index) {
1256 case 0x00: // Standard VGA
1257 case 0x01: // Standard VGA
1258 case 0x02: // Standard VGA
1259 case 0x03: // Standard VGA
1260 case 0x04: // Standard VGA
1261 return CIRRUS_HOOK_NOT_HANDLED;
1262 case 0x06: // Unlock Cirrus extensions
1263 *reg_value = s->sr[reg_index];
1264 break;
1265 case 0x10:
1266 case 0x30:
1267 case 0x50:
1268 case 0x70: // Graphics Cursor X
1269 case 0x90:
1270 case 0xb0:
1271 case 0xd0:
1272 case 0xf0: // Graphics Cursor X
1273 *reg_value = s->sr[0x10];
1274 break;
1275 case 0x11:
1276 case 0x31:
1277 case 0x51:
1278 case 0x71: // Graphics Cursor Y
1279 case 0x91:
1280 case 0xb1:
1281 case 0xd1:
1282 case 0xf1: // Graphics Cursor Y
1283 *reg_value = s->sr[0x11];
1284 break;
1285 case 0x05: // ???
1286 case 0x07: // Extended Sequencer Mode
1287 case 0x08: // EEPROM Control
1288 case 0x09: // Scratch Register 0
1289 case 0x0a: // Scratch Register 1
1290 case 0x0b: // VCLK 0
1291 case 0x0c: // VCLK 1
1292 case 0x0d: // VCLK 2
1293 case 0x0e: // VCLK 3
1294 case 0x0f: // DRAM Control
1295 case 0x12: // Graphics Cursor Attribute
1296 case 0x13: // Graphics Cursor Pattern Address
1297 case 0x14: // Scratch Register 2
1298 case 0x15: // Scratch Register 3
1299 case 0x16: // Performance Tuning Register
1300 case 0x17: // Configuration Readback and Extended Control
1301 case 0x18: // Signature Generator Control
1302 case 0x19: // Signal Generator Result
1303 case 0x1a: // Signal Generator Result
1304 case 0x1b: // VCLK 0 Denominator & Post
1305 case 0x1c: // VCLK 1 Denominator & Post
1306 case 0x1d: // VCLK 2 Denominator & Post
1307 case 0x1e: // VCLK 3 Denominator & Post
1308 case 0x1f: // BIOS Write Enable and MCLK select
1309 #ifdef DEBUG_CIRRUS
1310 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1311 #endif
1312 *reg_value = s->sr[reg_index];
1313 break;
1314 default:
1315 #ifdef DEBUG_CIRRUS
1316 printf("cirrus: inport sr_index %02x\n", reg_index);
1317 #endif
1318 *reg_value = 0xff;
1319 break;
1320 }
1321
1322 return CIRRUS_HOOK_HANDLED;
1323 }
1324
1325 static int
1326 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1327 {
1328 switch (reg_index) {
1329 case 0x00: // Standard VGA
1330 case 0x01: // Standard VGA
1331 case 0x02: // Standard VGA
1332 case 0x03: // Standard VGA
1333 case 0x04: // Standard VGA
1334 return CIRRUS_HOOK_NOT_HANDLED;
1335 case 0x06: // Unlock Cirrus extensions
1336 reg_value &= 0x17;
1337 if (reg_value == 0x12) {
1338 s->sr[reg_index] = 0x12;
1339 } else {
1340 s->sr[reg_index] = 0x0f;
1341 }
1342 break;
1343 case 0x10:
1344 case 0x30:
1345 case 0x50:
1346 case 0x70: // Graphics Cursor X
1347 case 0x90:
1348 case 0xb0:
1349 case 0xd0:
1350 case 0xf0: // Graphics Cursor X
1351 s->sr[0x10] = reg_value;
1352 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1353 break;
1354 case 0x11:
1355 case 0x31:
1356 case 0x51:
1357 case 0x71: // Graphics Cursor Y
1358 case 0x91:
1359 case 0xb1:
1360 case 0xd1:
1361 case 0xf1: // Graphics Cursor Y
1362 s->sr[0x11] = reg_value;
1363 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1364 break;
1365 case 0x07: // Extended Sequencer Mode
1366 cirrus_update_memory_access(s);
1367 case 0x08: // EEPROM Control
1368 case 0x09: // Scratch Register 0
1369 case 0x0a: // Scratch Register 1
1370 case 0x0b: // VCLK 0
1371 case 0x0c: // VCLK 1
1372 case 0x0d: // VCLK 2
1373 case 0x0e: // VCLK 3
1374 case 0x0f: // DRAM Control
1375 case 0x12: // Graphics Cursor Attribute
1376 case 0x13: // Graphics Cursor Pattern Address
1377 case 0x14: // Scratch Register 2
1378 case 0x15: // Scratch Register 3
1379 case 0x16: // Performance Tuning Register
1380 case 0x18: // Signature Generator Control
1381 case 0x19: // Signature Generator Result
1382 case 0x1a: // Signature Generator Result
1383 case 0x1b: // VCLK 0 Denominator & Post
1384 case 0x1c: // VCLK 1 Denominator & Post
1385 case 0x1d: // VCLK 2 Denominator & Post
1386 case 0x1e: // VCLK 3 Denominator & Post
1387 case 0x1f: // BIOS Write Enable and MCLK select
1388 s->sr[reg_index] = reg_value;
1389 #ifdef DEBUG_CIRRUS
1390 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1391 reg_index, reg_value);
1392 #endif
1393 break;
1394 case 0x17: // Configuration Readback and Extended Control
1395 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1396 cirrus_update_memory_access(s);
1397 break;
1398 default:
1399 #ifdef DEBUG_CIRRUS
1400 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1401 reg_value);
1402 #endif
1403 break;
1404 }
1405
1406 return CIRRUS_HOOK_HANDLED;
1407 }
1408
1409 /***************************************
1410 *
1411 * I/O access at 0x3c6
1412 *
1413 ***************************************/
1414
1415 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1416 {
1417 *reg_value = 0xff;
1418 if (++s->cirrus_hidden_dac_lockindex == 5) {
1419 *reg_value = s->cirrus_hidden_dac_data;
1420 s->cirrus_hidden_dac_lockindex = 0;
1421 }
1422 }
1423
1424 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1425 {
1426 if (s->cirrus_hidden_dac_lockindex == 4) {
1427 s->cirrus_hidden_dac_data = reg_value;
1428 #if defined(DEBUG_CIRRUS)
1429 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1430 #endif
1431 }
1432 s->cirrus_hidden_dac_lockindex = 0;
1433 }
1434
1435 /***************************************
1436 *
1437 * I/O access at 0x3c9
1438 *
1439 ***************************************/
1440
1441 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1442 {
1443 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1444 return CIRRUS_HOOK_NOT_HANDLED;
1445 *reg_value =
1446 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1447 s->dac_sub_index];
1448 if (++s->dac_sub_index == 3) {
1449 s->dac_sub_index = 0;
1450 s->dac_read_index++;
1451 }
1452 return CIRRUS_HOOK_HANDLED;
1453 }
1454
1455 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1456 {
1457 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1458 return CIRRUS_HOOK_NOT_HANDLED;
1459 s->dac_cache[s->dac_sub_index] = reg_value;
1460 if (++s->dac_sub_index == 3) {
1461 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1462 s->dac_cache, 3);
1463 /* XXX update cursor */
1464 s->dac_sub_index = 0;
1465 s->dac_write_index++;
1466 }
1467 return CIRRUS_HOOK_HANDLED;
1468 }
1469
1470 /***************************************
1471 *
1472 * I/O access between 0x3ce-0x3cf
1473 *
1474 ***************************************/
1475
1476 static int
1477 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1478 {
1479 switch (reg_index) {
1480 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1481 *reg_value = s->cirrus_shadow_gr0;
1482 return CIRRUS_HOOK_HANDLED;
1483 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1484 *reg_value = s->cirrus_shadow_gr1;
1485 return CIRRUS_HOOK_HANDLED;
1486 case 0x02: // Standard VGA
1487 case 0x03: // Standard VGA
1488 case 0x04: // Standard VGA
1489 case 0x06: // Standard VGA
1490 case 0x07: // Standard VGA
1491 case 0x08: // Standard VGA
1492 return CIRRUS_HOOK_NOT_HANDLED;
1493 case 0x05: // Standard VGA, Cirrus extended mode
1494 default:
1495 break;
1496 }
1497
1498 if (reg_index < 0x3a) {
1499 *reg_value = s->gr[reg_index];
1500 } else {
1501 #ifdef DEBUG_CIRRUS
1502 printf("cirrus: inport gr_index %02x\n", reg_index);
1503 #endif
1504 *reg_value = 0xff;
1505 }
1506
1507 return CIRRUS_HOOK_HANDLED;
1508 }
1509
1510 static int
1511 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1512 {
1513 #if defined(DEBUG_BITBLT) && 0
1514 printf("gr%02x: %02x\n", reg_index, reg_value);
1515 #endif
1516 switch (reg_index) {
1517 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1518 s->cirrus_shadow_gr0 = reg_value;
1519 return CIRRUS_HOOK_NOT_HANDLED;
1520 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1521 s->cirrus_shadow_gr1 = reg_value;
1522 return CIRRUS_HOOK_NOT_HANDLED;
1523 case 0x02: // Standard VGA
1524 case 0x03: // Standard VGA
1525 case 0x04: // Standard VGA
1526 case 0x06: // Standard VGA
1527 case 0x07: // Standard VGA
1528 case 0x08: // Standard VGA
1529 return CIRRUS_HOOK_NOT_HANDLED;
1530 case 0x05: // Standard VGA, Cirrus extended mode
1531 s->gr[reg_index] = reg_value & 0x7f;
1532 cirrus_update_memory_access(s);
1533 break;
1534 case 0x09: // bank offset #0
1535 case 0x0A: // bank offset #1
1536 s->gr[reg_index] = reg_value;
1537 cirrus_update_bank_ptr(s, 0);
1538 cirrus_update_bank_ptr(s, 1);
1539 cirrus_update_memory_access(s);
1540 break;
1541 case 0x0B:
1542 s->gr[reg_index] = reg_value;
1543 cirrus_update_bank_ptr(s, 0);
1544 cirrus_update_bank_ptr(s, 1);
1545 cirrus_update_memory_access(s);
1546 break;
1547 case 0x10: // BGCOLOR 0x0000ff00
1548 case 0x11: // FGCOLOR 0x0000ff00
1549 case 0x12: // BGCOLOR 0x00ff0000
1550 case 0x13: // FGCOLOR 0x00ff0000
1551 case 0x14: // BGCOLOR 0xff000000
1552 case 0x15: // FGCOLOR 0xff000000
1553 case 0x20: // BLT WIDTH 0x0000ff
1554 case 0x22: // BLT HEIGHT 0x0000ff
1555 case 0x24: // BLT DEST PITCH 0x0000ff
1556 case 0x26: // BLT SRC PITCH 0x0000ff
1557 case 0x28: // BLT DEST ADDR 0x0000ff
1558 case 0x29: // BLT DEST ADDR 0x00ff00
1559 case 0x2c: // BLT SRC ADDR 0x0000ff
1560 case 0x2d: // BLT SRC ADDR 0x00ff00
1561 case 0x2f: // BLT WRITEMASK
1562 case 0x30: // BLT MODE
1563 case 0x32: // RASTER OP
1564 case 0x33: // BLT MODEEXT
1565 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1566 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1567 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1568 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1569 s->gr[reg_index] = reg_value;
1570 break;
1571 case 0x21: // BLT WIDTH 0x001f00
1572 case 0x23: // BLT HEIGHT 0x001f00
1573 case 0x25: // BLT DEST PITCH 0x001f00
1574 case 0x27: // BLT SRC PITCH 0x001f00
1575 s->gr[reg_index] = reg_value & 0x1f;
1576 break;
1577 case 0x2a: // BLT DEST ADDR 0x3f0000
1578 s->gr[reg_index] = reg_value & 0x3f;
1579 /* if auto start mode, starts bit blt now */
1580 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1581 cirrus_bitblt_start(s);
1582 }
1583 break;
1584 case 0x2e: // BLT SRC ADDR 0x3f0000
1585 s->gr[reg_index] = reg_value & 0x3f;
1586 break;
1587 case 0x31: // BLT STATUS/START
1588 cirrus_write_bitblt(s, reg_value);
1589 break;
1590 default:
1591 #ifdef DEBUG_CIRRUS
1592 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1593 reg_value);
1594 #endif
1595 break;
1596 }
1597
1598 return CIRRUS_HOOK_HANDLED;
1599 }
1600
1601 /***************************************
1602 *
1603 * I/O access between 0x3d4-0x3d5
1604 *
1605 ***************************************/
1606
1607 static int
1608 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1609 {
1610 switch (reg_index) {
1611 case 0x00: // Standard VGA
1612 case 0x01: // Standard VGA
1613 case 0x02: // Standard VGA
1614 case 0x03: // Standard VGA
1615 case 0x04: // Standard VGA
1616 case 0x05: // Standard VGA
1617 case 0x06: // Standard VGA
1618 case 0x07: // Standard VGA
1619 case 0x08: // Standard VGA
1620 case 0x09: // Standard VGA
1621 case 0x0a: // Standard VGA
1622 case 0x0b: // Standard VGA
1623 case 0x0c: // Standard VGA
1624 case 0x0d: // Standard VGA
1625 case 0x0e: // Standard VGA
1626 case 0x0f: // Standard VGA
1627 case 0x10: // Standard VGA
1628 case 0x11: // Standard VGA
1629 case 0x12: // Standard VGA
1630 case 0x13: // Standard VGA
1631 case 0x14: // Standard VGA
1632 case 0x15: // Standard VGA
1633 case 0x16: // Standard VGA
1634 case 0x17: // Standard VGA
1635 case 0x18: // Standard VGA
1636 return CIRRUS_HOOK_NOT_HANDLED;
1637 case 0x24: // Attribute Controller Toggle Readback (R)
1638 *reg_value = (s->ar_flip_flop << 7);
1639 break;
1640 case 0x19: // Interlace End
1641 case 0x1a: // Miscellaneous Control
1642 case 0x1b: // Extended Display Control
1643 case 0x1c: // Sync Adjust and Genlock
1644 case 0x1d: // Overlay Extended Control
1645 case 0x22: // Graphics Data Latches Readback (R)
1646 case 0x25: // Part Status
1647 case 0x27: // Part ID (R)
1648 *reg_value = s->cr[reg_index];
1649 break;
1650 case 0x26: // Attribute Controller Index Readback (R)
1651 *reg_value = s->ar_index & 0x3f;
1652 break;
1653 default:
1654 #ifdef DEBUG_CIRRUS
1655 printf("cirrus: inport cr_index %02x\n", reg_index);
1656 *reg_value = 0xff;
1657 #endif
1658 break;
1659 }
1660
1661 return CIRRUS_HOOK_HANDLED;
1662 }
1663
1664 static int
1665 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1666 {
1667 switch (reg_index) {
1668 case 0x00: // Standard VGA
1669 case 0x01: // Standard VGA
1670 case 0x02: // Standard VGA
1671 case 0x03: // Standard VGA
1672 case 0x04: // Standard VGA
1673 case 0x05: // Standard VGA
1674 case 0x06: // Standard VGA
1675 case 0x07: // Standard VGA
1676 case 0x08: // Standard VGA
1677 case 0x09: // Standard VGA
1678 case 0x0a: // Standard VGA
1679 case 0x0b: // Standard VGA
1680 case 0x0c: // Standard VGA
1681 case 0x0d: // Standard VGA
1682 case 0x0e: // Standard VGA
1683 case 0x0f: // Standard VGA
1684 case 0x10: // Standard VGA
1685 case 0x11: // Standard VGA
1686 case 0x12: // Standard VGA
1687 case 0x13: // Standard VGA
1688 case 0x14: // Standard VGA
1689 case 0x15: // Standard VGA
1690 case 0x16: // Standard VGA
1691 case 0x17: // Standard VGA
1692 case 0x18: // Standard VGA
1693 return CIRRUS_HOOK_NOT_HANDLED;
1694 case 0x19: // Interlace End
1695 case 0x1a: // Miscellaneous Control
1696 case 0x1b: // Extended Display Control
1697 case 0x1c: // Sync Adjust and Genlock
1698 case 0x1d: // Overlay Extended Control
1699 s->cr[reg_index] = reg_value;
1700 #ifdef DEBUG_CIRRUS
1701 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1702 reg_index, reg_value);
1703 #endif
1704 break;
1705 case 0x22: // Graphics Data Latches Readback (R)
1706 case 0x24: // Attribute Controller Toggle Readback (R)
1707 case 0x26: // Attribute Controller Index Readback (R)
1708 case 0x27: // Part ID (R)
1709 break;
1710 case 0x25: // Part Status
1711 default:
1712 #ifdef DEBUG_CIRRUS
1713 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1714 reg_value);
1715 #endif
1716 break;
1717 }
1718
1719 return CIRRUS_HOOK_HANDLED;
1720 }
1721
1722 /***************************************
1723 *
1724 * memory-mapped I/O (bitblt)
1725 *
1726 ***************************************/
1727
1728 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1729 {
1730 int value = 0xff;
1731
1732 switch (address) {
1733 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1734 cirrus_hook_read_gr(s, 0x00, &value);
1735 break;
1736 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1737 cirrus_hook_read_gr(s, 0x10, &value);
1738 break;
1739 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1740 cirrus_hook_read_gr(s, 0x12, &value);
1741 break;
1742 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1743 cirrus_hook_read_gr(s, 0x14, &value);
1744 break;
1745 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1746 cirrus_hook_read_gr(s, 0x01, &value);
1747 break;
1748 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1749 cirrus_hook_read_gr(s, 0x11, &value);
1750 break;
1751 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1752 cirrus_hook_read_gr(s, 0x13, &value);
1753 break;
1754 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1755 cirrus_hook_read_gr(s, 0x15, &value);
1756 break;
1757 case (CIRRUS_MMIO_BLTWIDTH + 0):
1758 cirrus_hook_read_gr(s, 0x20, &value);
1759 break;
1760 case (CIRRUS_MMIO_BLTWIDTH + 1):
1761 cirrus_hook_read_gr(s, 0x21, &value);
1762 break;
1763 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1764 cirrus_hook_read_gr(s, 0x22, &value);
1765 break;
1766 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1767 cirrus_hook_read_gr(s, 0x23, &value);
1768 break;
1769 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1770 cirrus_hook_read_gr(s, 0x24, &value);
1771 break;
1772 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1773 cirrus_hook_read_gr(s, 0x25, &value);
1774 break;
1775 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1776 cirrus_hook_read_gr(s, 0x26, &value);
1777 break;
1778 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1779 cirrus_hook_read_gr(s, 0x27, &value);
1780 break;
1781 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1782 cirrus_hook_read_gr(s, 0x28, &value);
1783 break;
1784 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1785 cirrus_hook_read_gr(s, 0x29, &value);
1786 break;
1787 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1788 cirrus_hook_read_gr(s, 0x2a, &value);
1789 break;
1790 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1791 cirrus_hook_read_gr(s, 0x2c, &value);
1792 break;
1793 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1794 cirrus_hook_read_gr(s, 0x2d, &value);
1795 break;
1796 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1797 cirrus_hook_read_gr(s, 0x2e, &value);
1798 break;
1799 case CIRRUS_MMIO_BLTWRITEMASK:
1800 cirrus_hook_read_gr(s, 0x2f, &value);
1801 break;
1802 case CIRRUS_MMIO_BLTMODE:
1803 cirrus_hook_read_gr(s, 0x30, &value);
1804 break;
1805 case CIRRUS_MMIO_BLTROP:
1806 cirrus_hook_read_gr(s, 0x32, &value);
1807 break;
1808 case CIRRUS_MMIO_BLTMODEEXT:
1809 cirrus_hook_read_gr(s, 0x33, &value);
1810 break;
1811 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1812 cirrus_hook_read_gr(s, 0x34, &value);
1813 break;
1814 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1815 cirrus_hook_read_gr(s, 0x35, &value);
1816 break;
1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1818 cirrus_hook_read_gr(s, 0x38, &value);
1819 break;
1820 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1821 cirrus_hook_read_gr(s, 0x39, &value);
1822 break;
1823 case CIRRUS_MMIO_BLTSTATUS:
1824 cirrus_hook_read_gr(s, 0x31, &value);
1825 break;
1826 default:
1827 #ifdef DEBUG_CIRRUS
1828 printf("cirrus: mmio read - address 0x%04x\n", address);
1829 #endif
1830 break;
1831 }
1832
1833 return (uint8_t) value;
1834 }
1835
1836 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1837 uint8_t value)
1838 {
1839 switch (address) {
1840 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1841 cirrus_hook_write_gr(s, 0x00, value);
1842 break;
1843 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1844 cirrus_hook_write_gr(s, 0x10, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1847 cirrus_hook_write_gr(s, 0x12, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1850 cirrus_hook_write_gr(s, 0x14, value);
1851 break;
1852 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1853 cirrus_hook_write_gr(s, 0x01, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1856 cirrus_hook_write_gr(s, 0x11, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1859 cirrus_hook_write_gr(s, 0x13, value);
1860 break;
1861 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1862 cirrus_hook_write_gr(s, 0x15, value);
1863 break;
1864 case (CIRRUS_MMIO_BLTWIDTH + 0):
1865 cirrus_hook_write_gr(s, 0x20, value);
1866 break;
1867 case (CIRRUS_MMIO_BLTWIDTH + 1):
1868 cirrus_hook_write_gr(s, 0x21, value);
1869 break;
1870 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1871 cirrus_hook_write_gr(s, 0x22, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1874 cirrus_hook_write_gr(s, 0x23, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1877 cirrus_hook_write_gr(s, 0x24, value);
1878 break;
1879 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1880 cirrus_hook_write_gr(s, 0x25, value);
1881 break;
1882 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1883 cirrus_hook_write_gr(s, 0x26, value);
1884 break;
1885 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1886 cirrus_hook_write_gr(s, 0x27, value);
1887 break;
1888 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1889 cirrus_hook_write_gr(s, 0x28, value);
1890 break;
1891 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1892 cirrus_hook_write_gr(s, 0x29, value);
1893 break;
1894 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1895 cirrus_hook_write_gr(s, 0x2a, value);
1896 break;
1897 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1898 /* ignored */
1899 break;
1900 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1901 cirrus_hook_write_gr(s, 0x2c, value);
1902 break;
1903 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1904 cirrus_hook_write_gr(s, 0x2d, value);
1905 break;
1906 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1907 cirrus_hook_write_gr(s, 0x2e, value);
1908 break;
1909 case CIRRUS_MMIO_BLTWRITEMASK:
1910 cirrus_hook_write_gr(s, 0x2f, value);
1911 break;
1912 case CIRRUS_MMIO_BLTMODE:
1913 cirrus_hook_write_gr(s, 0x30, value);
1914 break;
1915 case CIRRUS_MMIO_BLTROP:
1916 cirrus_hook_write_gr(s, 0x32, value);
1917 break;
1918 case CIRRUS_MMIO_BLTMODEEXT:
1919 cirrus_hook_write_gr(s, 0x33, value);
1920 break;
1921 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1922 cirrus_hook_write_gr(s, 0x34, value);
1923 break;
1924 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1925 cirrus_hook_write_gr(s, 0x35, value);
1926 break;
1927 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1928 cirrus_hook_write_gr(s, 0x38, value);
1929 break;
1930 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1931 cirrus_hook_write_gr(s, 0x39, value);
1932 break;
1933 case CIRRUS_MMIO_BLTSTATUS:
1934 cirrus_hook_write_gr(s, 0x31, value);
1935 break;
1936 default:
1937 #ifdef DEBUG_CIRRUS
1938 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1939 address, value);
1940 #endif
1941 break;
1942 }
1943 }
1944
1945 /***************************************
1946 *
1947 * write mode 4/5
1948 *
1949 * assume TARGET_PAGE_SIZE >= 16
1950 *
1951 ***************************************/
1952
1953 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1954 unsigned mode,
1955 unsigned offset,
1956 uint32_t mem_value)
1957 {
1958 int x;
1959 unsigned val = mem_value;
1960 uint8_t *dst;
1961
1962 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1963 for (x = 0; x < 8; x++) {
1964 if (val & 0x80) {
1965 *dst = s->cirrus_shadow_gr1;
1966 } else if (mode == 5) {
1967 *dst = s->cirrus_shadow_gr0;
1968 }
1969 val <<= 1;
1970 dst++;
1971 }
1972 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1973 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1974 }
1975
1976 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1977 unsigned mode,
1978 unsigned offset,
1979 uint32_t mem_value)
1980 {
1981 int x;
1982 unsigned val = mem_value;
1983 uint8_t *dst;
1984
1985 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1986 for (x = 0; x < 8; x++) {
1987 if (val & 0x80) {
1988 *dst = s->cirrus_shadow_gr1;
1989 *(dst + 1) = s->gr[0x11];
1990 } else if (mode == 5) {
1991 *dst = s->cirrus_shadow_gr0;
1992 *(dst + 1) = s->gr[0x10];
1993 }
1994 val <<= 1;
1995 dst += 2;
1996 }
1997 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1998 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1999 }
2000
2001 /***************************************
2002 *
2003 * memory access between 0xa0000-0xbffff
2004 *
2005 ***************************************/
2006
2007 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2008 {
2009 CirrusVGAState *s = opaque;
2010 unsigned bank_index;
2011 unsigned bank_offset;
2012 uint32_t val;
2013
2014 if ((s->sr[0x07] & 0x01) == 0) {
2015 return vga_mem_readb(s, addr);
2016 }
2017
2018 addr &= 0x1ffff;
2019
2020 if (addr < 0x10000) {
2021 /* XXX handle bitblt */
2022 /* video memory */
2023 bank_index = addr >> 15;
2024 bank_offset = addr & 0x7fff;
2025 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2026 bank_offset += s->cirrus_bank_base[bank_index];
2027 if ((s->gr[0x0B] & 0x14) == 0x14) {
2028 bank_offset <<= 4;
2029 } else if (s->gr[0x0B] & 0x02) {
2030 bank_offset <<= 3;
2031 }
2032 bank_offset &= s->cirrus_addr_mask;
2033 val = *(s->vram_ptr + bank_offset);
2034 } else
2035 val = 0xff;
2036 } else if (addr >= 0x18000 && addr < 0x18100) {
2037 /* memory-mapped I/O */
2038 val = 0xff;
2039 if ((s->sr[0x17] & 0x44) == 0x04) {
2040 val = cirrus_mmio_blt_read(s, addr & 0xff);
2041 }
2042 } else {
2043 val = 0xff;
2044 #ifdef DEBUG_CIRRUS
2045 printf("cirrus: mem_readb %06x\n", addr);
2046 #endif
2047 }
2048 return val;
2049 }
2050
2051 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2052 {
2053 uint32_t v;
2054 #ifdef TARGET_WORDS_BIGENDIAN
2055 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2056 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2057 #else
2058 v = cirrus_vga_mem_readb(opaque, addr);
2059 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2060 #endif
2061 return v;
2062 }
2063
2064 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2065 {
2066 uint32_t v;
2067 #ifdef TARGET_WORDS_BIGENDIAN
2068 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2069 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2070 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2071 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2072 #else
2073 v = cirrus_vga_mem_readb(opaque, addr);
2074 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2075 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2076 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2077 #endif
2078 return v;
2079 }
2080
2081 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2082 uint32_t mem_value)
2083 {
2084 CirrusVGAState *s = opaque;
2085 unsigned bank_index;
2086 unsigned bank_offset;
2087 unsigned mode;
2088
2089 if ((s->sr[0x07] & 0x01) == 0) {
2090 vga_mem_writeb(s, addr, mem_value);
2091 return;
2092 }
2093
2094 addr &= 0x1ffff;
2095
2096 if (addr < 0x10000) {
2097 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2098 /* bitblt */
2099 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2100 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2101 cirrus_bitblt_cputovideo_next(s);
2102 }
2103 } else {
2104 /* video memory */
2105 bank_index = addr >> 15;
2106 bank_offset = addr & 0x7fff;
2107 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2108 bank_offset += s->cirrus_bank_base[bank_index];
2109 if ((s->gr[0x0B] & 0x14) == 0x14) {
2110 bank_offset <<= 4;
2111 } else if (s->gr[0x0B] & 0x02) {
2112 bank_offset <<= 3;
2113 }
2114 bank_offset &= s->cirrus_addr_mask;
2115 mode = s->gr[0x05] & 0x7;
2116 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2117 *(s->vram_ptr + bank_offset) = mem_value;
2118 cpu_physical_memory_set_dirty(s->vram_offset +
2119 bank_offset);
2120 } else {
2121 if ((s->gr[0x0B] & 0x14) != 0x14) {
2122 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2123 bank_offset,
2124 mem_value);
2125 } else {
2126 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2127 bank_offset,
2128 mem_value);
2129 }
2130 }
2131 }
2132 }
2133 } else if (addr >= 0x18000 && addr < 0x18100) {
2134 /* memory-mapped I/O */
2135 if ((s->sr[0x17] & 0x44) == 0x04) {
2136 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2137 }
2138 } else {
2139 #ifdef DEBUG_CIRRUS
2140 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2141 #endif
2142 }
2143 }
2144
2145 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2146 {
2147 #ifdef TARGET_WORDS_BIGENDIAN
2148 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2149 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2150 #else
2151 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2153 #endif
2154 }
2155
2156 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2157 {
2158 #ifdef TARGET_WORDS_BIGENDIAN
2159 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2160 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2161 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2162 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2163 #else
2164 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2165 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2166 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2167 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2168 #endif
2169 }
2170
2171 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2172 cirrus_vga_mem_readb,
2173 cirrus_vga_mem_readw,
2174 cirrus_vga_mem_readl,
2175 };
2176
2177 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2178 cirrus_vga_mem_writeb,
2179 cirrus_vga_mem_writew,
2180 cirrus_vga_mem_writel,
2181 };
2182
2183 /***************************************
2184 *
2185 * hardware cursor
2186 *
2187 ***************************************/
2188
2189 static inline void invalidate_cursor1(CirrusVGAState *s)
2190 {
2191 if (s->last_hw_cursor_size) {
2192 vga_invalidate_scanlines((VGAState *)s,
2193 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2194 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2195 }
2196 }
2197
2198 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2199 {
2200 const uint8_t *src;
2201 uint32_t content;
2202 int y, y_min, y_max;
2203
2204 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2205 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2206 src += (s->sr[0x13] & 0x3c) * 256;
2207 y_min = 64;
2208 y_max = -1;
2209 for(y = 0; y < 64; y++) {
2210 content = ((uint32_t *)src)[0] |
2211 ((uint32_t *)src)[1] |
2212 ((uint32_t *)src)[2] |
2213 ((uint32_t *)src)[3];
2214 if (content) {
2215 if (y < y_min)
2216 y_min = y;
2217 if (y > y_max)
2218 y_max = y;
2219 }
2220 src += 16;
2221 }
2222 } else {
2223 src += (s->sr[0x13] & 0x3f) * 256;
2224 y_min = 32;
2225 y_max = -1;
2226 for(y = 0; y < 32; y++) {
2227 content = ((uint32_t *)src)[0] |
2228 ((uint32_t *)(src + 128))[0];
2229 if (content) {
2230 if (y < y_min)
2231 y_min = y;
2232 if (y > y_max)
2233 y_max = y;
2234 }
2235 src += 4;
2236 }
2237 }
2238 if (y_min > y_max) {
2239 s->last_hw_cursor_y_start = 0;
2240 s->last_hw_cursor_y_end = 0;
2241 } else {
2242 s->last_hw_cursor_y_start = y_min;
2243 s->last_hw_cursor_y_end = y_max + 1;
2244 }
2245 }
2246
2247 /* NOTE: we do not currently handle the cursor bitmap change, so we
2248 update the cursor only if it moves. */
2249 static void cirrus_cursor_invalidate(VGAState *s1)
2250 {
2251 CirrusVGAState *s = (CirrusVGAState *)s1;
2252 int size;
2253
2254 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2255 size = 0;
2256 } else {
2257 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2258 size = 64;
2259 else
2260 size = 32;
2261 }
2262 /* invalidate last cursor and new cursor if any change */
2263 if (s->last_hw_cursor_size != size ||
2264 s->last_hw_cursor_x != s->hw_cursor_x ||
2265 s->last_hw_cursor_y != s->hw_cursor_y) {
2266
2267 invalidate_cursor1(s);
2268
2269 s->last_hw_cursor_size = size;
2270 s->last_hw_cursor_x = s->hw_cursor_x;
2271 s->last_hw_cursor_y = s->hw_cursor_y;
2272 /* compute the real cursor min and max y */
2273 cirrus_cursor_compute_yrange(s);
2274 invalidate_cursor1(s);
2275 }
2276 }
2277
2278 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2279 {
2280 CirrusVGAState *s = (CirrusVGAState *)s1;
2281 int w, h, bpp, x1, x2, poffset;
2282 unsigned int color0, color1;
2283 const uint8_t *palette, *src;
2284 uint32_t content;
2285
2286 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2287 return;
2288 /* fast test to see if the cursor intersects with the scan line */
2289 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2290 h = 64;
2291 } else {
2292 h = 32;
2293 }
2294 if (scr_y < s->hw_cursor_y ||
2295 scr_y >= (s->hw_cursor_y + h))
2296 return;
2297
2298 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2299 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2300 src += (s->sr[0x13] & 0x3c) * 256;
2301 src += (scr_y - s->hw_cursor_y) * 16;
2302 poffset = 8;
2303 content = ((uint32_t *)src)[0] |
2304 ((uint32_t *)src)[1] |
2305 ((uint32_t *)src)[2] |
2306 ((uint32_t *)src)[3];
2307 } else {
2308 src += (s->sr[0x13] & 0x3f) * 256;
2309 src += (scr_y - s->hw_cursor_y) * 4;
2310 poffset = 128;
2311 content = ((uint32_t *)src)[0] |
2312 ((uint32_t *)(src + 128))[0];
2313 }
2314 /* if nothing to draw, no need to continue */
2315 if (!content)
2316 return;
2317 w = h;
2318
2319 x1 = s->hw_cursor_x;
2320 if (x1 >= s->last_scr_width)
2321 return;
2322 x2 = s->hw_cursor_x + w;
2323 if (x2 > s->last_scr_width)
2324 x2 = s->last_scr_width;
2325 w = x2 - x1;
2326 palette = s->cirrus_hidden_palette;
2327 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2328 c6_to_8(palette[0x0 * 3 + 1]),
2329 c6_to_8(palette[0x0 * 3 + 2]));
2330 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2331 c6_to_8(palette[0xf * 3 + 1]),
2332 c6_to_8(palette[0xf * 3 + 2]));
2333 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2334 d1 += x1 * bpp;
2335 switch(ds_get_bits_per_pixel(s->ds)) {
2336 default:
2337 break;
2338 case 8:
2339 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2340 break;
2341 case 15:
2342 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2343 break;
2344 case 16:
2345 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2346 break;
2347 case 32:
2348 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2349 break;
2350 }
2351 }
2352
2353 /***************************************
2354 *
2355 * LFB memory access
2356 *
2357 ***************************************/
2358
2359 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2360 {
2361 CirrusVGAState *s = (CirrusVGAState *) opaque;
2362 uint32_t ret;
2363
2364 addr &= s->cirrus_addr_mask;
2365
2366 if (((s->sr[0x17] & 0x44) == 0x44) &&
2367 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2368 /* memory-mapped I/O */
2369 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2370 } else if (0) {
2371 /* XXX handle bitblt */
2372 ret = 0xff;
2373 } else {
2374 /* video memory */
2375 if ((s->gr[0x0B] & 0x14) == 0x14) {
2376 addr <<= 4;
2377 } else if (s->gr[0x0B] & 0x02) {
2378 addr <<= 3;
2379 }
2380 addr &= s->cirrus_addr_mask;
2381 ret = *(s->vram_ptr + addr);
2382 }
2383
2384 return ret;
2385 }
2386
2387 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2388 {
2389 uint32_t v;
2390 #ifdef TARGET_WORDS_BIGENDIAN
2391 v = cirrus_linear_readb(opaque, addr) << 8;
2392 v |= cirrus_linear_readb(opaque, addr + 1);
2393 #else
2394 v = cirrus_linear_readb(opaque, addr);
2395 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2396 #endif
2397 return v;
2398 }
2399
2400 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2401 {
2402 uint32_t v;
2403 #ifdef TARGET_WORDS_BIGENDIAN
2404 v = cirrus_linear_readb(opaque, addr) << 24;
2405 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2406 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2407 v |= cirrus_linear_readb(opaque, addr + 3);
2408 #else
2409 v = cirrus_linear_readb(opaque, addr);
2410 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2411 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2412 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2413 #endif
2414 return v;
2415 }
2416
2417 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2418 uint32_t val)
2419 {
2420 CirrusVGAState *s = (CirrusVGAState *) opaque;
2421 unsigned mode;
2422
2423 addr &= s->cirrus_addr_mask;
2424
2425 if (((s->sr[0x17] & 0x44) == 0x44) &&
2426 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2427 /* memory-mapped I/O */
2428 cirrus_mmio_blt_write(s, addr & 0xff, val);
2429 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2430 /* bitblt */
2431 *s->cirrus_srcptr++ = (uint8_t) val;
2432 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2433 cirrus_bitblt_cputovideo_next(s);
2434 }
2435 } else {
2436 /* video memory */
2437 if ((s->gr[0x0B] & 0x14) == 0x14) {
2438 addr <<= 4;
2439 } else if (s->gr[0x0B] & 0x02) {
2440 addr <<= 3;
2441 }
2442 addr &= s->cirrus_addr_mask;
2443
2444 mode = s->gr[0x05] & 0x7;
2445 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2446 *(s->vram_ptr + addr) = (uint8_t) val;
2447 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2448 } else {
2449 if ((s->gr[0x0B] & 0x14) != 0x14) {
2450 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2451 } else {
2452 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2453 }
2454 }
2455 }
2456 }
2457
2458 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2459 uint32_t val)
2460 {
2461 #ifdef TARGET_WORDS_BIGENDIAN
2462 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2463 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2464 #else
2465 cirrus_linear_writeb(opaque, addr, val & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2467 #endif
2468 }
2469
2470 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2471 uint32_t val)
2472 {
2473 #ifdef TARGET_WORDS_BIGENDIAN
2474 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2475 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2476 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2477 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2478 #else
2479 cirrus_linear_writeb(opaque, addr, val & 0xff);
2480 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2481 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2482 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2483 #endif
2484 }
2485
2486
2487 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2488 cirrus_linear_readb,
2489 cirrus_linear_readw,
2490 cirrus_linear_readl,
2491 };
2492
2493 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2494 cirrus_linear_writeb,
2495 cirrus_linear_writew,
2496 cirrus_linear_writel,
2497 };
2498
2499 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2500 uint32_t val)
2501 {
2502 CirrusVGAState *s = (CirrusVGAState *) opaque;
2503
2504 addr &= s->cirrus_addr_mask;
2505 *(s->vram_ptr + addr) = val;
2506 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2507 }
2508
2509 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2510 uint32_t val)
2511 {
2512 CirrusVGAState *s = (CirrusVGAState *) opaque;
2513
2514 addr &= s->cirrus_addr_mask;
2515 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2516 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2517 }
2518
2519 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2520 uint32_t val)
2521 {
2522 CirrusVGAState *s = (CirrusVGAState *) opaque;
2523
2524 addr &= s->cirrus_addr_mask;
2525 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2526 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2527 }
2528
2529 /***************************************
2530 *
2531 * system to screen memory access
2532 *
2533 ***************************************/
2534
2535
2536 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2537 {
2538 uint32_t ret;
2539
2540 /* XXX handle bitblt */
2541 ret = 0xff;
2542 return ret;
2543 }
2544
2545 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2546 {
2547 uint32_t v;
2548 #ifdef TARGET_WORDS_BIGENDIAN
2549 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2550 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2551 #else
2552 v = cirrus_linear_bitblt_readb(opaque, addr);
2553 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2554 #endif
2555 return v;
2556 }
2557
2558 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2559 {
2560 uint32_t v;
2561 #ifdef TARGET_WORDS_BIGENDIAN
2562 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2563 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2564 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2565 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2566 #else
2567 v = cirrus_linear_bitblt_readb(opaque, addr);
2568 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2569 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2570 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2571 #endif
2572 return v;
2573 }
2574
2575 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2576 uint32_t val)
2577 {
2578 CirrusVGAState *s = (CirrusVGAState *) opaque;
2579
2580 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2581 /* bitblt */
2582 *s->cirrus_srcptr++ = (uint8_t) val;
2583 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2584 cirrus_bitblt_cputovideo_next(s);
2585 }
2586 }
2587 }
2588
2589 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2590 uint32_t val)
2591 {
2592 #ifdef TARGET_WORDS_BIGENDIAN
2593 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2594 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2595 #else
2596 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2598 #endif
2599 }
2600
2601 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2602 uint32_t val)
2603 {
2604 #ifdef TARGET_WORDS_BIGENDIAN
2605 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2606 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2607 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2608 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2609 #else
2610 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2611 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2612 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2613 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2614 #endif
2615 }
2616
2617
2618 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2619 cirrus_linear_bitblt_readb,
2620 cirrus_linear_bitblt_readw,
2621 cirrus_linear_bitblt_readl,
2622 };
2623
2624 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2625 cirrus_linear_bitblt_writeb,
2626 cirrus_linear_bitblt_writew,
2627 cirrus_linear_bitblt_writel,
2628 };
2629
2630 static void map_linear_vram(CirrusVGAState *s)
2631 {
2632
2633 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2634 s->map_addr = s->lfb_addr;
2635 s->map_end = s->lfb_end;
2636 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2637 vga_dirty_log_start((VGAState *)s);
2638 }
2639
2640 if (!s->map_addr)
2641 return;
2642
2643 s->lfb_vram_mapped = 0;
2644
2645 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2646 && !((s->sr[0x07] & 0x01) == 0)
2647 && !((s->gr[0x0B] & 0x14) == 0x14)
2648 && !(s->gr[0x0B] & 0x02)) {
2649
2650 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2651 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2652 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2653 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2654
2655 s->lfb_vram_mapped = 1;
2656 vga_dirty_log_start((VGAState *)s);
2657 }
2658 else {
2659 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, s->vga_io_memory);
2660 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, s->vga_io_memory);
2661 }
2662
2663 }
2664
2665 static void unmap_linear_vram(CirrusVGAState *s)
2666 {
2667 if (s->map_addr && s->lfb_addr && s->lfb_end) {
2668 vga_dirty_log_stop((VGAState *)s);
2669 s->map_addr = s->map_end = 0;
2670 }
2671
2672 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2673 s->vga_io_memory);
2674 }
2675
2676 /* Compute the memory access functions */
2677 static void cirrus_update_memory_access(CirrusVGAState *s)
2678 {
2679 unsigned mode;
2680
2681 if ((s->sr[0x17] & 0x44) == 0x44) {
2682 goto generic_io;
2683 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2684 goto generic_io;
2685 } else {
2686 if ((s->gr[0x0B] & 0x14) == 0x14) {
2687 goto generic_io;
2688 } else if (s->gr[0x0B] & 0x02) {
2689 goto generic_io;
2690 }
2691
2692 mode = s->gr[0x05] & 0x7;
2693 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2694 map_linear_vram(s);
2695 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2696 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2697 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2698 } else {
2699 generic_io:
2700 unmap_linear_vram(s);
2701 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2702 s->cirrus_linear_write[1] = cirrus_linear_writew;
2703 s->cirrus_linear_write[2] = cirrus_linear_writel;
2704 }
2705 }
2706 }
2707
2708
2709 /* I/O ports */
2710
2711 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2712 {
2713 CirrusVGAState *s = opaque;
2714 int val, index;
2715
2716 /* check port range access depending on color/monochrome mode */
2717 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2718 || (addr >= 0x3d0 && addr <= 0x3df
2719 && !(s->msr & MSR_COLOR_EMULATION))) {
2720 val = 0xff;
2721 } else {
2722 switch (addr) {
2723 case 0x3c0:
2724 if (s->ar_flip_flop == 0) {
2725 val = s->ar_index;
2726 } else {
2727 val = 0;
2728 }
2729 break;
2730 case 0x3c1:
2731 index = s->ar_index & 0x1f;
2732 if (index < 21)
2733 val = s->ar[index];
2734 else
2735 val = 0;
2736 break;
2737 case 0x3c2:
2738 val = s->st00;
2739 break;
2740 case 0x3c4:
2741 val = s->sr_index;
2742 break;
2743 case 0x3c5:
2744 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2745 break;
2746 val = s->sr[s->sr_index];
2747 #ifdef DEBUG_VGA_REG
2748 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2749 #endif
2750 break;
2751 case 0x3c6:
2752 cirrus_read_hidden_dac(s, &val);
2753 break;
2754 case 0x3c7:
2755 val = s->dac_state;
2756 break;
2757 case 0x3c8:
2758 val = s->dac_write_index;
2759 s->cirrus_hidden_dac_lockindex = 0;
2760 break;
2761 case 0x3c9:
2762 if (cirrus_hook_read_palette(s, &val))
2763 break;
2764 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2765 if (++s->dac_sub_index == 3) {
2766 s->dac_sub_index = 0;
2767 s->dac_read_index++;
2768 }
2769 break;
2770 case 0x3ca:
2771 val = s->fcr;
2772 break;
2773 case 0x3cc:
2774 val = s->msr;
2775 break;
2776 case 0x3ce:
2777 val = s->gr_index;
2778 break;
2779 case 0x3cf:
2780 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2781 break;
2782 val = s->gr[s->gr_index];
2783 #ifdef DEBUG_VGA_REG
2784 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2785 #endif
2786 break;
2787 case 0x3b4:
2788 case 0x3d4:
2789 val = s->cr_index;
2790 break;
2791 case 0x3b5:
2792 case 0x3d5:
2793 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2794 break;
2795 val = s->cr[s->cr_index];
2796 #ifdef DEBUG_VGA_REG
2797 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2798 #endif
2799 break;
2800 case 0x3ba:
2801 case 0x3da:
2802 /* just toggle to fool polling */
2803 val = s->st01 = s->retrace((VGAState *) s);
2804 s->ar_flip_flop = 0;
2805 break;
2806 default:
2807 val = 0x00;
2808 break;
2809 }
2810 }
2811 #if defined(DEBUG_VGA)
2812 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2813 #endif
2814 return val;
2815 }
2816
2817 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2818 {
2819 CirrusVGAState *s = opaque;
2820 int index;
2821
2822 /* check port range access depending on color/monochrome mode */
2823 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2824 || (addr >= 0x3d0 && addr <= 0x3df
2825 && !(s->msr & MSR_COLOR_EMULATION)))
2826 return;
2827
2828 #ifdef DEBUG_VGA
2829 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2830 #endif
2831
2832 switch (addr) {
2833 case 0x3c0:
2834 if (s->ar_flip_flop == 0) {
2835 val &= 0x3f;
2836 s->ar_index = val;
2837 } else {
2838 index = s->ar_index & 0x1f;
2839 switch (index) {
2840 case 0x00 ... 0x0f:
2841 s->ar[index] = val & 0x3f;
2842 break;
2843 case 0x10:
2844 s->ar[index] = val & ~0x10;
2845 break;
2846 case 0x11:
2847 s->ar[index] = val;
2848 break;
2849 case 0x12:
2850 s->ar[index] = val & ~0xc0;
2851 break;
2852 case 0x13:
2853 s->ar[index] = val & ~0xf0;
2854 break;
2855 case 0x14:
2856 s->ar[index] = val & ~0xf0;
2857 break;
2858 default:
2859 break;
2860 }
2861 }
2862 s->ar_flip_flop ^= 1;
2863 break;
2864 case 0x3c2:
2865 s->msr = val & ~0x10;
2866 s->update_retrace_info((VGAState *) s);
2867 break;
2868 case 0x3c4:
2869 s->sr_index = val;
2870 break;
2871 case 0x3c5:
2872 if (cirrus_hook_write_sr(s, s->sr_index, val))
2873 break;
2874 #ifdef DEBUG_VGA_REG
2875 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2876 #endif
2877 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2878 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2879 break;
2880 case 0x3c6:
2881 cirrus_write_hidden_dac(s, val);
2882 break;
2883 case 0x3c7:
2884 s->dac_read_index = val;
2885 s->dac_sub_index = 0;
2886 s->dac_state = 3;
2887 break;
2888 case 0x3c8:
2889 s->dac_write_index = val;
2890 s->dac_sub_index = 0;
2891 s->dac_state = 0;
2892 break;
2893 case 0x3c9:
2894 if (cirrus_hook_write_palette(s, val))
2895 break;
2896 s->dac_cache[s->dac_sub_index] = val;
2897 if (++s->dac_sub_index == 3) {
2898 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2899 s->dac_sub_index = 0;
2900 s->dac_write_index++;
2901 }
2902 break;
2903 case 0x3ce:
2904 s->gr_index = val;
2905 break;
2906 case 0x3cf:
2907 if (cirrus_hook_write_gr(s, s->gr_index, val))
2908 break;
2909 #ifdef DEBUG_VGA_REG
2910 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2911 #endif
2912 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2913 break;
2914 case 0x3b4:
2915 case 0x3d4:
2916 s->cr_index = val;
2917 break;
2918 case 0x3b5:
2919 case 0x3d5:
2920 if (cirrus_hook_write_cr(s, s->cr_index, val))
2921 break;
2922 #ifdef DEBUG_VGA_REG
2923 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2924 #endif
2925 /* handle CR0-7 protection */
2926 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2927 /* can always write bit 4 of CR7 */
2928 if (s->cr_index == 7)
2929 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2930 return;
2931 }
2932 switch (s->cr_index) {
2933 case 0x01: /* horizontal display end */
2934 case 0x07:
2935 case 0x09:
2936 case 0x0c:
2937 case 0x0d:
2938 case 0x12: /* vertical display end */
2939 s->cr[s->cr_index] = val;
2940 break;
2941
2942 default:
2943 s->cr[s->cr_index] = val;
2944 break;
2945 }
2946
2947 switch(s->cr_index) {
2948 case 0x00:
2949 case 0x04:
2950 case 0x05:
2951 case 0x06:
2952 case 0x07:
2953 case 0x11:
2954 case 0x17:
2955 s->update_retrace_info((VGAState *) s);
2956 break;
2957 }
2958 break;
2959 case 0x3ba:
2960 case 0x3da:
2961 s->fcr = val & 0x10;
2962 break;
2963 }
2964 }
2965
2966 /***************************************
2967 *
2968 * memory-mapped I/O access
2969 *
2970 ***************************************/
2971
2972 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2973 {
2974 CirrusVGAState *s = (CirrusVGAState *) opaque;
2975
2976 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2977
2978 if (addr >= 0x100) {
2979 return cirrus_mmio_blt_read(s, addr - 0x100);
2980 } else {
2981 return vga_ioport_read(s, addr + 0x3c0);
2982 }
2983 }
2984
2985 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2986 {
2987 uint32_t v;
2988 #ifdef TARGET_WORDS_BIGENDIAN
2989 v = cirrus_mmio_readb(opaque, addr) << 8;
2990 v |= cirrus_mmio_readb(opaque, addr + 1);
2991 #else
2992 v = cirrus_mmio_readb(opaque, addr);
2993 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2994 #endif
2995 return v;
2996 }
2997
2998 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2999 {
3000 uint32_t v;
3001 #ifdef TARGET_WORDS_BIGENDIAN
3002 v = cirrus_mmio_readb(opaque, addr) << 24;
3003 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3004 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3005 v |= cirrus_mmio_readb(opaque, addr + 3);
3006 #else
3007 v = cirrus_mmio_readb(opaque, addr);
3008 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3009 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3010 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3011 #endif
3012 return v;
3013 }
3014
3015 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3016 uint32_t val)
3017 {
3018 CirrusVGAState *s = (CirrusVGAState *) opaque;
3019
3020 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3021
3022 if (addr >= 0x100) {
3023 cirrus_mmio_blt_write(s, addr - 0x100, val);
3024 } else {
3025 vga_ioport_write(s, addr + 0x3c0, val);
3026 }
3027 }
3028
3029 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3030 uint32_t val)
3031 {
3032 #ifdef TARGET_WORDS_BIGENDIAN
3033 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3034 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3035 #else
3036 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3037 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3038 #endif
3039 }
3040
3041 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3042 uint32_t val)
3043 {
3044 #ifdef TARGET_WORDS_BIGENDIAN
3045 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3046 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3047 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3048 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3049 #else
3050 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3051 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3052 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3053 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3054 #endif
3055 }
3056
3057
3058 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3059 cirrus_mmio_readb,
3060 cirrus_mmio_readw,
3061 cirrus_mmio_readl,
3062 };
3063
3064 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3065 cirrus_mmio_writeb,
3066 cirrus_mmio_writew,
3067 cirrus_mmio_writel,
3068 };
3069
3070 /* load/save state */
3071
3072 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3073 {
3074 CirrusVGAState *s = opaque;
3075
3076 if (s->pci_dev)
3077 pci_device_save(s->pci_dev, f);
3078
3079 qemu_put_be32s(f, &s->latch);
3080 qemu_put_8s(f, &s->sr_index);
3081 qemu_put_buffer(f, s->sr, 256);
3082 qemu_put_8s(f, &s->gr_index);
3083 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3084 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3085 qemu_put_buffer(f, s->gr + 2, 254);
3086 qemu_put_8s(f, &s->ar_index);
3087 qemu_put_buffer(f, s->ar, 21);
3088 qemu_put_be32(f, s->ar_flip_flop);
3089 qemu_put_8s(f, &s->cr_index);
3090 qemu_put_buffer(f, s->cr, 256);
3091 qemu_put_8s(f, &s->msr);
3092 qemu_put_8s(f, &s->fcr);
3093 qemu_put_8s(f, &s->st00);
3094 qemu_put_8s(f, &s->st01);
3095
3096 qemu_put_8s(f, &s->dac_state);
3097 qemu_put_8s(f, &s->dac_sub_index);
3098 qemu_put_8s(f, &s->dac_read_index);
3099 qemu_put_8s(f, &s->dac_write_index);
3100 qemu_put_buffer(f, s->dac_cache, 3);
3101 qemu_put_buffer(f, s->palette, 768);
3102
3103 qemu_put_be32(f, s->bank_offset);
3104
3105 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3106 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3107
3108 qemu_put_be32s(f, &s->hw_cursor_x);
3109 qemu_put_be32s(f, &s->hw_cursor_y);
3110 /* XXX: we do not save the bitblt state - we assume we do not save
3111 the state when the blitter is active */
3112 }
3113
3114 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3115 {
3116 CirrusVGAState *s = opaque;
3117 int ret;
3118
3119 if (version_id > 2)
3120 return -EINVAL;
3121
3122 if (s->pci_dev && version_id >= 2) {
3123 ret = pci_device_load(s->pci_dev, f);
3124 if (ret < 0)
3125 return ret;
3126 }
3127
3128 qemu_get_be32s(f, &s->latch);
3129 qemu_get_8s(f, &s->sr_index);
3130 qemu_get_buffer(f, s->sr, 256);
3131 qemu_get_8s(f, &s->gr_index);
3132 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3133 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3134 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3135 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3136 qemu_get_buffer(f, s->gr + 2, 254);
3137 qemu_get_8s(f, &s->ar_index);
3138 qemu_get_buffer(f, s->ar, 21);
3139 s->ar_flip_flop=qemu_get_be32(f);
3140 qemu_get_8s(f, &s->cr_index);
3141 qemu_get_buffer(f, s->cr, 256);
3142 qemu_get_8s(f, &s->msr);
3143 qemu_get_8s(f, &s->fcr);
3144 qemu_get_8s(f, &s->st00);
3145 qemu_get_8s(f, &s->st01);
3146
3147 qemu_get_8s(f, &s->dac_state);
3148 qemu_get_8s(f, &s->dac_sub_index);
3149 qemu_get_8s(f, &s->dac_read_index);
3150 qemu_get_8s(f, &s->dac_write_index);
3151 qemu_get_buffer(f, s->dac_cache, 3);
3152 qemu_get_buffer(f, s->palette, 768);
3153
3154 s->bank_offset=qemu_get_be32(f);
3155
3156 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3157 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3158
3159 qemu_get_be32s(f, &s->hw_cursor_x);
3160 qemu_get_be32s(f, &s->hw_cursor_y);
3161
3162 cirrus_update_memory_access(s);
3163 /* force refresh */
3164 s->graphic_mode = -1;
3165 cirrus_update_bank_ptr(s, 0);
3166 cirrus_update_bank_ptr(s, 1);
3167 return 0;
3168 }
3169
3170 /***************************************
3171 *
3172 * initialize
3173 *
3174 ***************************************/
3175
3176 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3177 {
3178 int i;
3179 static int inited;
3180
3181 if (!inited) {
3182 inited = 1;
3183 for(i = 0;i < 256; i++)
3184 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3185 rop_to_index[CIRRUS_ROP_0] = 0;
3186 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3187 rop_to_index[CIRRUS_ROP_NOP] = 2;
3188 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3189 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3190 rop_to_index[CIRRUS_ROP_SRC] = 5;
3191 rop_to_index[CIRRUS_ROP_1] = 6;
3192 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3193 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3194 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3195 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3196 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3197 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3198 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3199 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3200 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3201 }
3202
3203 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3204
3205 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3206 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3207 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3208 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3209
3210 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3211
3212 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3213 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3214 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3215 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3216
3217 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3218 cirrus_vga_mem_write, s);
3219 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3220 s->vga_io_memory);
3221
3222 s->sr[0x06] = 0x0f;
3223 if (device_id == CIRRUS_ID_CLGD5446) {
3224 /* 4MB 64 bit memory config, always PCI */
3225 s->sr[0x1F] = 0x2d; // MemClock
3226 s->gr[0x18] = 0x0f; // fastest memory configuration
3227 #if 1
3228 s->sr[0x0f] = 0x98;
3229 s->sr[0x17] = 0x20;
3230 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3231 s->real_vram_size = 4096 * 1024;
3232 #else
3233 s->sr[0x0f] = 0x18;
3234 s->sr[0x17] = 0x20;
3235 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3236 s->real_vram_size = 2048 * 1024;
3237 #endif
3238 } else {
3239 s->sr[0x1F] = 0x22; // MemClock
3240 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3241 if (is_pci)
3242 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3243 else
3244 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3245 s->real_vram_size = 2048 * 1024;
3246 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3247 }
3248 s->cr[0x27] = device_id;
3249
3250 /* Win2K seems to assume that the pattern buffer is at 0xff
3251 initially ! */
3252 memset(s->vram_ptr, 0xff, s->real_vram_size);
3253
3254 s->cirrus_hidden_dac_lockindex = 5;
3255 s->cirrus_hidden_dac_data = 0;
3256
3257 /* I/O handler for LFB */
3258 s->cirrus_linear_io_addr =
3259 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3260 s);
3261 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3262
3263 /* I/O handler for LFB */
3264 s->cirrus_linear_bitblt_io_addr =
3265 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3266 s);
3267
3268 /* I/O handler for memory-mapped I/O */
3269 s->cirrus_mmio_io_addr =
3270 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3271
3272 /* XXX: s->vram_size must be a power of two */
3273 s->cirrus_addr_mask = s->real_vram_size - 1;
3274 s->linear_mmio_mask = s->real_vram_size - 256;
3275
3276 s->get_bpp = cirrus_get_bpp;
3277 s->get_offsets = cirrus_get_offsets;
3278 s->get_resolution = cirrus_get_resolution;
3279 s->cursor_invalidate = cirrus_cursor_invalidate;
3280 s->cursor_draw_line = cirrus_cursor_draw_line;
3281
3282 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3283 }
3284
3285 /***************************************
3286 *
3287 * ISA bus support
3288 *
3289 ***************************************/
3290
3291 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3292 ram_addr_t vga_ram_offset, int vga_ram_size)
3293 {
3294 CirrusVGAState *s;
3295
3296 s = qemu_mallocz(sizeof(CirrusVGAState));
3297
3298 vga_common_init((VGAState *)s,
3299 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3300 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3301 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3302 s->screen_dump, s->text_update, s);
3303 /* XXX ISA-LFB support */
3304 }
3305
3306 /***************************************
3307 *
3308 * PCI bus support
3309 *
3310 ***************************************/
3311
3312 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3313 uint32_t addr, uint32_t size, int type)
3314 {
3315 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3316
3317 /* XXX: add byte swapping apertures */
3318 cpu_register_physical_memory(addr, s->vram_size,
3319 s->cirrus_linear_io_addr);
3320 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3321 s->cirrus_linear_bitblt_io_addr);
3322
3323 s->map_addr = s->map_end = 0;
3324 s->lfb_addr = addr & TARGET_PAGE_MASK;
3325 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3326 /* account for overflow */
3327 if (s->lfb_end < addr + VGA_RAM_SIZE)
3328 s->lfb_end = addr + VGA_RAM_SIZE;
3329 }
3330
3331 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3332 uint32_t addr, uint32_t size, int type)
3333 {
3334 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3335
3336 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3337 s->cirrus_mmio_io_addr);
3338 }
3339
3340 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3341 ram_addr_t vga_ram_offset, int vga_ram_size)
3342 {
3343 PCICirrusVGAState *d;
3344 uint8_t *pci_conf;
3345 CirrusVGAState *s;
3346 int device_id;
3347
3348 device_id = CIRRUS_ID_CLGD5446;
3349
3350 /* setup PCI configuration registers */
3351 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3352 sizeof(PCICirrusVGAState),
3353 -1, NULL, NULL);
3354 pci_conf = d->dev.config;
3355 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3356 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3357 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3358 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3359 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3360 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3361 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3362 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3363
3364 /* setup VGA */
3365 s = &d->cirrus_vga;
3366 vga_common_init((VGAState *)s,
3367 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3368 cirrus_init_common(s, device_id, 1);
3369
3370 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3371 s->screen_dump, s->text_update, s);
3372
3373 s->pci_dev = (PCIDevice *)d;
3374
3375 /* setup memory space */
3376 /* memory #0 LFB */
3377 /* memory #1 memory-mapped I/O */
3378 /* XXX: s->vram_size must be a power of two */
3379 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3380 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3381 if (device_id == CIRRUS_ID_CLGD5446) {
3382 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3383 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3384 }
3385 /* XXX: ROM BIOS */
3386 }