4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
30 #include "qemu-common.h"
33 //#define DEBUG_FEATURES
35 static int cpu_sparc_find_by_name(sparc_def_t
*cpu_def
, const char *cpu_model
);
37 /* Sparc MMU emulation */
41 static spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
45 spin_lock(&global_cpu_lock
);
50 spin_unlock(&global_cpu_lock
);
53 #if defined(CONFIG_USER_ONLY)
55 int cpu_sparc_handle_mmu_fault(CPUState
*env1
, target_ulong address
, int rw
,
56 int mmu_idx
, int is_softmmu
)
59 env1
->exception_index
= TT_TFAULT
;
61 env1
->exception_index
= TT_DFAULT
;
67 #ifndef TARGET_SPARC64
69 * Sparc V8 Reference MMU (SRMMU)
71 static const int access_table
[8][8] = {
72 { 0, 0, 0, 0, 8, 0, 12, 12 },
73 { 0, 0, 0, 0, 8, 0, 0, 0 },
74 { 8, 8, 0, 0, 0, 8, 12, 12 },
75 { 8, 8, 0, 0, 0, 8, 0, 0 },
76 { 8, 0, 8, 0, 8, 8, 12, 12 },
77 { 8, 0, 8, 0, 8, 0, 8, 0 },
78 { 8, 8, 8, 0, 8, 8, 12, 12 },
79 { 8, 8, 8, 0, 8, 8, 8, 0 }
82 static const int perm_table
[2][8] = {
85 PAGE_READ
| PAGE_WRITE
,
86 PAGE_READ
| PAGE_EXEC
,
87 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
89 PAGE_READ
| PAGE_WRITE
,
90 PAGE_READ
| PAGE_EXEC
,
91 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
95 PAGE_READ
| PAGE_WRITE
,
96 PAGE_READ
| PAGE_EXEC
,
97 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
105 static int get_physical_address(CPUState
*env
, target_phys_addr_t
*physical
,
106 int *prot
, int *access_index
,
107 target_ulong address
, int rw
, int mmu_idx
)
109 int access_perms
= 0;
110 target_phys_addr_t pde_ptr
;
112 target_ulong virt_addr
;
113 int error_code
= 0, is_dirty
, is_user
;
114 unsigned long page_offset
;
116 is_user
= mmu_idx
== MMU_USER_IDX
;
117 virt_addr
= address
& TARGET_PAGE_MASK
;
119 if ((env
->mmuregs
[0] & MMU_E
) == 0) { /* MMU disabled */
120 // Boot mode: instruction fetches are taken from PROM
121 if (rw
== 2 && (env
->mmuregs
[0] & env
->def
->mmu_bm
)) {
122 *physical
= env
->prom_addr
| (address
& 0x7ffffULL
);
123 *prot
= PAGE_READ
| PAGE_EXEC
;
127 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
131 *access_index
= ((rw
& 1) << 2) | (rw
& 2) | (is_user
? 0 : 1);
132 *physical
= 0xffffffffffff0000ULL
;
134 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
135 /* Context base + context number */
136 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
137 pde
= ldl_phys(pde_ptr
);
140 switch (pde
& PTE_ENTRYTYPE_MASK
) {
142 case 0: /* Invalid */
144 case 2: /* L0 PTE, maybe should not happen? */
145 case 3: /* Reserved */
148 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
149 pde
= ldl_phys(pde_ptr
);
151 switch (pde
& PTE_ENTRYTYPE_MASK
) {
153 case 0: /* Invalid */
154 return (1 << 8) | (1 << 2);
155 case 3: /* Reserved */
156 return (1 << 8) | (4 << 2);
158 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
159 pde
= ldl_phys(pde_ptr
);
161 switch (pde
& PTE_ENTRYTYPE_MASK
) {
163 case 0: /* Invalid */
164 return (2 << 8) | (1 << 2);
165 case 3: /* Reserved */
166 return (2 << 8) | (4 << 2);
168 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
169 pde
= ldl_phys(pde_ptr
);
171 switch (pde
& PTE_ENTRYTYPE_MASK
) {
173 case 0: /* Invalid */
174 return (3 << 8) | (1 << 2);
175 case 1: /* PDE, should not happen */
176 case 3: /* Reserved */
177 return (3 << 8) | (4 << 2);
179 virt_addr
= address
& TARGET_PAGE_MASK
;
180 page_offset
= (address
& TARGET_PAGE_MASK
) &
181 (TARGET_PAGE_SIZE
- 1);
185 virt_addr
= address
& ~0x3ffff;
186 page_offset
= address
& 0x3ffff;
190 virt_addr
= address
& ~0xffffff;
191 page_offset
= address
& 0xffffff;
195 /* update page modified and dirty bits */
196 is_dirty
= (rw
& 1) && !(pde
& PG_MODIFIED_MASK
);
197 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
198 pde
|= PG_ACCESSED_MASK
;
200 pde
|= PG_MODIFIED_MASK
;
201 stl_phys_notdirty(pde_ptr
, pde
);
204 access_perms
= (pde
& PTE_ACCESS_MASK
) >> PTE_ACCESS_SHIFT
;
205 error_code
= access_table
[*access_index
][access_perms
];
206 if (error_code
&& !((env
->mmuregs
[0] & MMU_NF
) && is_user
))
209 /* the page can be put in the TLB */
210 *prot
= perm_table
[is_user
][access_perms
];
211 if (!(pde
& PG_MODIFIED_MASK
)) {
212 /* only set write access if already dirty... otherwise wait
214 *prot
&= ~PAGE_WRITE
;
217 /* Even if large ptes, we map only one 4KB page in the cache to
218 avoid filling it too fast */
219 *physical
= ((target_phys_addr_t
)(pde
& PTE_ADDR_MASK
) << 4) + page_offset
;
223 /* Perform address translation */
224 int cpu_sparc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
225 int mmu_idx
, int is_softmmu
)
227 target_phys_addr_t paddr
;
229 int error_code
= 0, prot
, ret
= 0, access_index
;
231 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
,
232 address
, rw
, mmu_idx
);
233 if (error_code
== 0) {
234 vaddr
= address
& TARGET_PAGE_MASK
;
235 paddr
&= TARGET_PAGE_MASK
;
237 printf("Translate at " TARGET_FMT_lx
" -> " TARGET_FMT_plx
", vaddr "
238 TARGET_FMT_lx
"\n", address
, paddr
, vaddr
);
240 ret
= tlb_set_page_exec(env
, vaddr
, paddr
, prot
, mmu_idx
, is_softmmu
);
244 if (env
->mmuregs
[3]) /* Fault status register */
245 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
246 env
->mmuregs
[3] |= (access_index
<< 5) | error_code
| 2;
247 env
->mmuregs
[4] = address
; /* Fault address register */
249 if ((env
->mmuregs
[0] & MMU_NF
) || env
->psret
== 0) {
250 // No fault mode: if a mapping is available, just override
251 // permissions. If no mapping is available, redirect accesses to
252 // neverland. Fake/overridden mappings will be flushed when
253 // switching to normal mode.
254 vaddr
= address
& TARGET_PAGE_MASK
;
255 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
256 ret
= tlb_set_page_exec(env
, vaddr
, paddr
, prot
, mmu_idx
, is_softmmu
);
260 env
->exception_index
= TT_TFAULT
;
262 env
->exception_index
= TT_DFAULT
;
267 target_ulong
mmu_probe(CPUState
*env
, target_ulong address
, int mmulev
)
269 target_phys_addr_t pde_ptr
;
272 /* Context base + context number */
273 pde_ptr
= (target_phys_addr_t
)(env
->mmuregs
[1] << 4) +
274 (env
->mmuregs
[2] << 2);
275 pde
= ldl_phys(pde_ptr
);
277 switch (pde
& PTE_ENTRYTYPE_MASK
) {
279 case 0: /* Invalid */
280 case 2: /* PTE, maybe should not happen? */
281 case 3: /* Reserved */
286 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
287 pde
= ldl_phys(pde_ptr
);
289 switch (pde
& PTE_ENTRYTYPE_MASK
) {
291 case 0: /* Invalid */
292 case 3: /* Reserved */
299 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
300 pde
= ldl_phys(pde_ptr
);
302 switch (pde
& PTE_ENTRYTYPE_MASK
) {
304 case 0: /* Invalid */
305 case 3: /* Reserved */
312 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
313 pde
= ldl_phys(pde_ptr
);
315 switch (pde
& PTE_ENTRYTYPE_MASK
) {
317 case 0: /* Invalid */
318 case 1: /* PDE, should not happen */
319 case 3: /* Reserved */
331 void dump_mmu(CPUState
*env
)
333 target_ulong va
, va1
, va2
;
334 unsigned int n
, m
, o
;
335 target_phys_addr_t pde_ptr
, pa
;
338 printf("MMU dump:\n");
339 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
340 pde
= ldl_phys(pde_ptr
);
341 printf("Root ptr: " TARGET_FMT_plx
", ctx: %d\n",
342 (target_phys_addr_t
)env
->mmuregs
[1] << 4, env
->mmuregs
[2]);
343 for (n
= 0, va
= 0; n
< 256; n
++, va
+= 16 * 1024 * 1024) {
344 pde
= mmu_probe(env
, va
, 2);
346 pa
= cpu_get_phys_page_debug(env
, va
);
347 printf("VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_plx
348 " PDE: " TARGET_FMT_lx
"\n", va
, pa
, pde
);
349 for (m
= 0, va1
= va
; m
< 64; m
++, va1
+= 256 * 1024) {
350 pde
= mmu_probe(env
, va1
, 1);
352 pa
= cpu_get_phys_page_debug(env
, va1
);
353 printf(" VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_plx
354 " PDE: " TARGET_FMT_lx
"\n", va1
, pa
, pde
);
355 for (o
= 0, va2
= va1
; o
< 64; o
++, va2
+= 4 * 1024) {
356 pde
= mmu_probe(env
, va2
, 0);
358 pa
= cpu_get_phys_page_debug(env
, va2
);
359 printf(" VA: " TARGET_FMT_lx
", PA: "
360 TARGET_FMT_plx
" PTE: " TARGET_FMT_lx
"\n",
368 printf("MMU dump ends\n");
370 #endif /* DEBUG_MMU */
372 #else /* !TARGET_SPARC64 */
374 * UltraSparc IIi I/DMMUs
376 static int get_physical_address_data(CPUState
*env
,
377 target_phys_addr_t
*physical
, int *prot
,
378 target_ulong address
, int rw
, int is_user
)
383 if ((env
->lsu
& DMMU_E
) == 0) { /* DMMU disabled */
385 *prot
= PAGE_READ
| PAGE_WRITE
;
389 for (i
= 0; i
< 64; i
++) {
390 switch ((env
->dtlb_tte
[i
] >> 61) & 3) {
393 mask
= 0xffffffffffffe000ULL
;
396 mask
= 0xffffffffffff0000ULL
;
399 mask
= 0xfffffffffff80000ULL
;
402 mask
= 0xffffffffffc00000ULL
;
405 // ctx match, vaddr match?
406 if (env
->dmmuregs
[1] == (env
->dtlb_tag
[i
] & 0x1fff) &&
407 (address
& mask
) == (env
->dtlb_tag
[i
] & ~0x1fffULL
)) {
409 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) == 0 ||
410 ((env
->dtlb_tte
[i
] & 0x4) && is_user
) ||
411 (!(env
->dtlb_tte
[i
] & 0x2) && (rw
== 1))) {
412 if (env
->dmmuregs
[3]) /* Fault status register */
413 env
->dmmuregs
[3] = 2; /* overflow (not read before
415 env
->dmmuregs
[3] |= (is_user
<< 3) | ((rw
== 1) << 2) | 1;
416 env
->dmmuregs
[4] = address
; /* Fault address register */
417 env
->exception_index
= TT_DFAULT
;
419 printf("DFAULT at 0x%" PRIx64
"\n", address
);
423 *physical
= (env
->dtlb_tte
[i
] & mask
& 0x1fffffff000ULL
) +
424 (address
& ~mask
& 0x1fffffff000ULL
);
426 if (env
->dtlb_tte
[i
] & 0x2)
432 printf("DMISS at 0x%" PRIx64
"\n", address
);
434 env
->dmmuregs
[6] = (address
& ~0x1fffULL
) | (env
->dmmuregs
[1] & 0x1fff);
435 env
->exception_index
= TT_DMISS
;
439 static int get_physical_address_code(CPUState
*env
,
440 target_phys_addr_t
*physical
, int *prot
,
441 target_ulong address
, int is_user
)
446 if ((env
->lsu
& IMMU_E
) == 0) { /* IMMU disabled */
452 for (i
= 0; i
< 64; i
++) {
453 switch ((env
->itlb_tte
[i
] >> 61) & 3) {
456 mask
= 0xffffffffffffe000ULL
;
459 mask
= 0xffffffffffff0000ULL
;
462 mask
= 0xfffffffffff80000ULL
;
465 mask
= 0xffffffffffc00000ULL
;
468 // ctx match, vaddr match?
469 if (env
->dmmuregs
[1] == (env
->itlb_tag
[i
] & 0x1fff) &&
470 (address
& mask
) == (env
->itlb_tag
[i
] & ~0x1fffULL
)) {
472 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) == 0 ||
473 ((env
->itlb_tte
[i
] & 0x4) && is_user
)) {
474 if (env
->immuregs
[3]) /* Fault status register */
475 env
->immuregs
[3] = 2; /* overflow (not read before
477 env
->immuregs
[3] |= (is_user
<< 3) | 1;
478 env
->exception_index
= TT_TFAULT
;
480 printf("TFAULT at 0x%" PRIx64
"\n", address
);
484 *physical
= (env
->itlb_tte
[i
] & mask
& 0x1fffffff000ULL
) +
485 (address
& ~mask
& 0x1fffffff000ULL
);
491 printf("TMISS at 0x%" PRIx64
"\n", address
);
493 env
->immuregs
[6] = (address
& ~0x1fffULL
) | (env
->dmmuregs
[1] & 0x1fff);
494 env
->exception_index
= TT_TMISS
;
498 static int get_physical_address(CPUState
*env
, target_phys_addr_t
*physical
,
499 int *prot
, int *access_index
,
500 target_ulong address
, int rw
, int mmu_idx
)
502 int is_user
= mmu_idx
== MMU_USER_IDX
;
505 return get_physical_address_code(env
, physical
, prot
, address
,
508 return get_physical_address_data(env
, physical
, prot
, address
, rw
,
512 /* Perform address translation */
513 int cpu_sparc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
514 int mmu_idx
, int is_softmmu
)
516 target_ulong virt_addr
, vaddr
;
517 target_phys_addr_t paddr
;
518 int error_code
= 0, prot
, ret
= 0, access_index
;
520 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
,
521 address
, rw
, mmu_idx
);
522 if (error_code
== 0) {
523 virt_addr
= address
& TARGET_PAGE_MASK
;
524 vaddr
= virt_addr
+ ((address
& TARGET_PAGE_MASK
) &
525 (TARGET_PAGE_SIZE
- 1));
527 printf("Translate at 0x%" PRIx64
" -> 0x%" PRIx64
", vaddr 0x%" PRIx64
528 "\n", address
, paddr
, vaddr
);
530 ret
= tlb_set_page_exec(env
, vaddr
, paddr
, prot
, mmu_idx
, is_softmmu
);
538 void dump_mmu(CPUState
*env
)
543 printf("MMU contexts: Primary: %" PRId64
", Secondary: %" PRId64
"\n",
544 env
->dmmuregs
[1], env
->dmmuregs
[2]);
545 if ((env
->lsu
& DMMU_E
) == 0) {
546 printf("DMMU disabled\n");
548 printf("DMMU dump:\n");
549 for (i
= 0; i
< 64; i
++) {
550 switch ((env
->dtlb_tte
[i
] >> 61) & 3) {
565 if ((env
->dtlb_tte
[i
] & 0x8000000000000000ULL
) != 0) {
566 printf("VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_lx
567 ", %s, %s, %s, %s, ctx %" PRId64
"\n",
568 env
->dtlb_tag
[i
] & ~0x1fffULL
,
569 env
->dtlb_tte
[i
] & 0x1ffffffe000ULL
,
571 env
->dtlb_tte
[i
] & 0x4? "priv": "user",
572 env
->dtlb_tte
[i
] & 0x2? "RW": "RO",
573 env
->dtlb_tte
[i
] & 0x40? "locked": "unlocked",
574 env
->dtlb_tag
[i
] & 0x1fffULL
);
578 if ((env
->lsu
& IMMU_E
) == 0) {
579 printf("IMMU disabled\n");
581 printf("IMMU dump:\n");
582 for (i
= 0; i
< 64; i
++) {
583 switch ((env
->itlb_tte
[i
] >> 61) & 3) {
598 if ((env
->itlb_tte
[i
] & 0x8000000000000000ULL
) != 0) {
599 printf("VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_lx
600 ", %s, %s, %s, ctx %" PRId64
"\n",
601 env
->itlb_tag
[i
] & ~0x1fffULL
,
602 env
->itlb_tte
[i
] & 0x1ffffffe000ULL
,
604 env
->itlb_tte
[i
] & 0x4? "priv": "user",
605 env
->itlb_tte
[i
] & 0x40? "locked": "unlocked",
606 env
->itlb_tag
[i
] & 0x1fffULL
);
611 #endif /* DEBUG_MMU */
613 #endif /* TARGET_SPARC64 */
614 #endif /* !CONFIG_USER_ONLY */
617 #if defined(CONFIG_USER_ONLY)
618 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
624 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
626 target_phys_addr_t phys_addr
;
627 int prot
, access_index
;
629 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
, 2,
630 MMU_KERNEL_IDX
) != 0)
631 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
,
632 0, MMU_KERNEL_IDX
) != 0)
634 if (cpu_get_physical_page_desc(phys_addr
) == IO_MEM_UNASSIGNED
)
640 void cpu_reset(CPUSPARCState
*env
)
645 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
646 #if defined(CONFIG_USER_ONLY)
647 env
->user_mode_only
= 1;
648 #ifdef TARGET_SPARC64
649 env
->cleanwin
= env
->nwindows
- 2;
650 env
->cansave
= env
->nwindows
- 2;
651 env
->pstate
= PS_RMO
| PS_PEF
| PS_IE
;
652 env
->asi
= 0x82; // Primary no-fault
658 #ifdef TARGET_SPARC64
659 env
->pstate
= PS_PRIV
;
660 env
->hpstate
= HS_PRIV
;
661 env
->tsptr
= &env
->ts
[env
->tl
& MAXTL_MASK
];
663 env
->mmuregs
[0] &= ~(MMU_E
| MMU_NF
);
664 env
->mmuregs
[0] |= env
->def
->mmu_bm
;
667 env
->npc
= env
->pc
+ 4;
671 static int cpu_sparc_register(CPUSPARCState
*env
, const char *cpu_model
)
673 sparc_def_t def1
, *def
= &def1
;
675 if (cpu_sparc_find_by_name(def
, cpu_model
) < 0)
678 env
->def
= qemu_mallocz(sizeof(*def
));
679 memcpy(env
->def
, def
, sizeof(*def
));
680 #if defined(CONFIG_USER_ONLY)
681 if ((env
->def
->features
& CPU_FEATURE_FLOAT
))
682 env
->def
->features
|= CPU_FEATURE_FLOAT128
;
684 env
->cpu_model_str
= cpu_model
;
685 env
->version
= def
->iu_version
;
686 env
->fsr
= def
->fpu_version
;
687 env
->nwindows
= def
->nwindows
;
688 #if !defined(TARGET_SPARC64)
689 env
->mmuregs
[0] |= def
->mmu_version
;
690 cpu_sparc_set_id(env
, 0);
691 env
->mxccregs
[7] |= def
->mxcc_version
;
693 env
->mmu_version
= def
->mmu_version
;
694 env
->maxtl
= def
->maxtl
;
695 env
->version
|= def
->maxtl
<< 8;
696 env
->version
|= def
->nwindows
- 1;
701 static void cpu_sparc_close(CPUSPARCState
*env
)
707 CPUSPARCState
*cpu_sparc_init(const char *cpu_model
)
711 env
= qemu_mallocz(sizeof(CPUSPARCState
));
716 gen_intermediate_code_init(env
);
718 if (cpu_sparc_register(env
, cpu_model
) < 0) {
719 cpu_sparc_close(env
);
727 void cpu_sparc_set_id(CPUSPARCState
*env
, unsigned int cpu
)
729 #if !defined(TARGET_SPARC64)
730 env
->mxccregs
[7] = ((cpu
+ 8) & 0xf) << 24;
734 static const sparc_def_t sparc_defs
[] = {
735 #ifdef TARGET_SPARC64
737 .name
= "Fujitsu Sparc64",
738 .iu_version
= ((0x04ULL
<< 48) | (0x02ULL
<< 32) | (0ULL << 24)),
739 .fpu_version
= 0x00000000,
740 .mmu_version
= mmu_us_12
,
743 .features
= CPU_DEFAULT_FEATURES
,
746 .name
= "Fujitsu Sparc64 III",
747 .iu_version
= ((0x04ULL
<< 48) | (0x03ULL
<< 32) | (0ULL << 24)),
748 .fpu_version
= 0x00000000,
749 .mmu_version
= mmu_us_12
,
752 .features
= CPU_DEFAULT_FEATURES
,
755 .name
= "Fujitsu Sparc64 IV",
756 .iu_version
= ((0x04ULL
<< 48) | (0x04ULL
<< 32) | (0ULL << 24)),
757 .fpu_version
= 0x00000000,
758 .mmu_version
= mmu_us_12
,
761 .features
= CPU_DEFAULT_FEATURES
,
764 .name
= "Fujitsu Sparc64 V",
765 .iu_version
= ((0x04ULL
<< 48) | (0x05ULL
<< 32) | (0x51ULL
<< 24)),
766 .fpu_version
= 0x00000000,
767 .mmu_version
= mmu_us_12
,
770 .features
= CPU_DEFAULT_FEATURES
,
773 .name
= "TI UltraSparc I",
774 .iu_version
= ((0x17ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
775 .fpu_version
= 0x00000000,
776 .mmu_version
= mmu_us_12
,
779 .features
= CPU_DEFAULT_FEATURES
,
782 .name
= "TI UltraSparc II",
783 .iu_version
= ((0x17ULL
<< 48) | (0x11ULL
<< 32) | (0x20ULL
<< 24)),
784 .fpu_version
= 0x00000000,
785 .mmu_version
= mmu_us_12
,
788 .features
= CPU_DEFAULT_FEATURES
,
791 .name
= "TI UltraSparc IIi",
792 .iu_version
= ((0x17ULL
<< 48) | (0x12ULL
<< 32) | (0x91ULL
<< 24)),
793 .fpu_version
= 0x00000000,
794 .mmu_version
= mmu_us_12
,
797 .features
= CPU_DEFAULT_FEATURES
,
800 .name
= "TI UltraSparc IIe",
801 .iu_version
= ((0x17ULL
<< 48) | (0x13ULL
<< 32) | (0x14ULL
<< 24)),
802 .fpu_version
= 0x00000000,
803 .mmu_version
= mmu_us_12
,
806 .features
= CPU_DEFAULT_FEATURES
,
809 .name
= "Sun UltraSparc III",
810 .iu_version
= ((0x3eULL
<< 48) | (0x14ULL
<< 32) | (0x34ULL
<< 24)),
811 .fpu_version
= 0x00000000,
812 .mmu_version
= mmu_us_12
,
815 .features
= CPU_DEFAULT_FEATURES
,
818 .name
= "Sun UltraSparc III Cu",
819 .iu_version
= ((0x3eULL
<< 48) | (0x15ULL
<< 32) | (0x41ULL
<< 24)),
820 .fpu_version
= 0x00000000,
821 .mmu_version
= mmu_us_3
,
824 .features
= CPU_DEFAULT_FEATURES
,
827 .name
= "Sun UltraSparc IIIi",
828 .iu_version
= ((0x3eULL
<< 48) | (0x16ULL
<< 32) | (0x34ULL
<< 24)),
829 .fpu_version
= 0x00000000,
830 .mmu_version
= mmu_us_12
,
833 .features
= CPU_DEFAULT_FEATURES
,
836 .name
= "Sun UltraSparc IV",
837 .iu_version
= ((0x3eULL
<< 48) | (0x18ULL
<< 32) | (0x31ULL
<< 24)),
838 .fpu_version
= 0x00000000,
839 .mmu_version
= mmu_us_4
,
842 .features
= CPU_DEFAULT_FEATURES
,
845 .name
= "Sun UltraSparc IV+",
846 .iu_version
= ((0x3eULL
<< 48) | (0x19ULL
<< 32) | (0x22ULL
<< 24)),
847 .fpu_version
= 0x00000000,
848 .mmu_version
= mmu_us_12
,
851 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_CMT
,
854 .name
= "Sun UltraSparc IIIi+",
855 .iu_version
= ((0x3eULL
<< 48) | (0x22ULL
<< 32) | (0ULL << 24)),
856 .fpu_version
= 0x00000000,
857 .mmu_version
= mmu_us_3
,
860 .features
= CPU_DEFAULT_FEATURES
,
863 .name
= "Sun UltraSparc T1",
864 // defined in sparc_ifu_fdp.v and ctu.h
865 .iu_version
= ((0x3eULL
<< 48) | (0x23ULL
<< 32) | (0x02ULL
<< 24)),
866 .fpu_version
= 0x00000000,
867 .mmu_version
= mmu_sun4v
,
870 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
874 .name
= "Sun UltraSparc T2",
875 // defined in tlu_asi_ctl.v and n2_revid_cust.v
876 .iu_version
= ((0x3eULL
<< 48) | (0x24ULL
<< 32) | (0x02ULL
<< 24)),
877 .fpu_version
= 0x00000000,
878 .mmu_version
= mmu_sun4v
,
881 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
885 .name
= "NEC UltraSparc I",
886 .iu_version
= ((0x22ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
887 .fpu_version
= 0x00000000,
888 .mmu_version
= mmu_us_12
,
891 .features
= CPU_DEFAULT_FEATURES
,
895 .name
= "Fujitsu MB86900",
896 .iu_version
= 0x00 << 24, /* Impl 0, ver 0 */
897 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
898 .mmu_version
= 0x00 << 24, /* Impl 0, ver 0 */
899 .mmu_bm
= 0x00004000,
900 .mmu_ctpr_mask
= 0x007ffff0,
901 .mmu_cxr_mask
= 0x0000003f,
902 .mmu_sfsr_mask
= 0xffffffff,
903 .mmu_trcr_mask
= 0xffffffff,
905 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_FSMULD
,
908 .name
= "Fujitsu MB86904",
909 .iu_version
= 0x04 << 24, /* Impl 0, ver 4 */
910 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
911 .mmu_version
= 0x04 << 24, /* Impl 0, ver 4 */
912 .mmu_bm
= 0x00004000,
913 .mmu_ctpr_mask
= 0x00ffffc0,
914 .mmu_cxr_mask
= 0x000000ff,
915 .mmu_sfsr_mask
= 0x00016fff,
916 .mmu_trcr_mask
= 0x00ffffff,
918 .features
= CPU_DEFAULT_FEATURES
,
921 .name
= "Fujitsu MB86907",
922 .iu_version
= 0x05 << 24, /* Impl 0, ver 5 */
923 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
924 .mmu_version
= 0x05 << 24, /* Impl 0, ver 5 */
925 .mmu_bm
= 0x00004000,
926 .mmu_ctpr_mask
= 0xffffffc0,
927 .mmu_cxr_mask
= 0x000000ff,
928 .mmu_sfsr_mask
= 0x00016fff,
929 .mmu_trcr_mask
= 0xffffffff,
931 .features
= CPU_DEFAULT_FEATURES
,
934 .name
= "LSI L64811",
935 .iu_version
= 0x10 << 24, /* Impl 1, ver 0 */
936 .fpu_version
= 1 << 17, /* FPU version 1 (LSI L64814) */
937 .mmu_version
= 0x10 << 24,
938 .mmu_bm
= 0x00004000,
939 .mmu_ctpr_mask
= 0x007ffff0,
940 .mmu_cxr_mask
= 0x0000003f,
941 .mmu_sfsr_mask
= 0xffffffff,
942 .mmu_trcr_mask
= 0xffffffff,
944 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
948 .name
= "Cypress CY7C601",
949 .iu_version
= 0x11 << 24, /* Impl 1, ver 1 */
950 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
951 .mmu_version
= 0x10 << 24,
952 .mmu_bm
= 0x00004000,
953 .mmu_ctpr_mask
= 0x007ffff0,
954 .mmu_cxr_mask
= 0x0000003f,
955 .mmu_sfsr_mask
= 0xffffffff,
956 .mmu_trcr_mask
= 0xffffffff,
958 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
962 .name
= "Cypress CY7C611",
963 .iu_version
= 0x13 << 24, /* Impl 1, ver 3 */
964 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
965 .mmu_version
= 0x10 << 24,
966 .mmu_bm
= 0x00004000,
967 .mmu_ctpr_mask
= 0x007ffff0,
968 .mmu_cxr_mask
= 0x0000003f,
969 .mmu_sfsr_mask
= 0xffffffff,
970 .mmu_trcr_mask
= 0xffffffff,
972 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
976 .name
= "TI MicroSparc I",
977 .iu_version
= 0x41000000,
978 .fpu_version
= 4 << 17,
979 .mmu_version
= 0x41000000,
980 .mmu_bm
= 0x00004000,
981 .mmu_ctpr_mask
= 0x007ffff0,
982 .mmu_cxr_mask
= 0x0000003f,
983 .mmu_sfsr_mask
= 0x00016fff,
984 .mmu_trcr_mask
= 0x0000003f,
986 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_MUL
|
987 CPU_FEATURE_DIV
| CPU_FEATURE_FLUSH
| CPU_FEATURE_FSQRT
|
991 .name
= "TI MicroSparc II",
992 .iu_version
= 0x42000000,
993 .fpu_version
= 4 << 17,
994 .mmu_version
= 0x02000000,
995 .mmu_bm
= 0x00004000,
996 .mmu_ctpr_mask
= 0x00ffffc0,
997 .mmu_cxr_mask
= 0x000000ff,
998 .mmu_sfsr_mask
= 0x00016fff,
999 .mmu_trcr_mask
= 0x00ffffff,
1001 .features
= CPU_DEFAULT_FEATURES
,
1004 .name
= "TI MicroSparc IIep",
1005 .iu_version
= 0x42000000,
1006 .fpu_version
= 4 << 17,
1007 .mmu_version
= 0x04000000,
1008 .mmu_bm
= 0x00004000,
1009 .mmu_ctpr_mask
= 0x00ffffc0,
1010 .mmu_cxr_mask
= 0x000000ff,
1011 .mmu_sfsr_mask
= 0x00016bff,
1012 .mmu_trcr_mask
= 0x00ffffff,
1014 .features
= CPU_DEFAULT_FEATURES
,
1017 .name
= "TI SuperSparc 40", // STP1020NPGA
1018 .iu_version
= 0x41000000, // SuperSPARC 2.x
1019 .fpu_version
= 0 << 17,
1020 .mmu_version
= 0x00000800, // SuperSPARC 2.x, no MXCC
1021 .mmu_bm
= 0x00002000,
1022 .mmu_ctpr_mask
= 0xffffffc0,
1023 .mmu_cxr_mask
= 0x0000ffff,
1024 .mmu_sfsr_mask
= 0xffffffff,
1025 .mmu_trcr_mask
= 0xffffffff,
1027 .features
= CPU_DEFAULT_FEATURES
,
1030 .name
= "TI SuperSparc 50", // STP1020PGA
1031 .iu_version
= 0x40000000, // SuperSPARC 3.x
1032 .fpu_version
= 0 << 17,
1033 .mmu_version
= 0x01000800, // SuperSPARC 3.x, no MXCC
1034 .mmu_bm
= 0x00002000,
1035 .mmu_ctpr_mask
= 0xffffffc0,
1036 .mmu_cxr_mask
= 0x0000ffff,
1037 .mmu_sfsr_mask
= 0xffffffff,
1038 .mmu_trcr_mask
= 0xffffffff,
1040 .features
= CPU_DEFAULT_FEATURES
,
1043 .name
= "TI SuperSparc 51",
1044 .iu_version
= 0x40000000, // SuperSPARC 3.x
1045 .fpu_version
= 0 << 17,
1046 .mmu_version
= 0x01000000, // SuperSPARC 3.x, MXCC
1047 .mmu_bm
= 0x00002000,
1048 .mmu_ctpr_mask
= 0xffffffc0,
1049 .mmu_cxr_mask
= 0x0000ffff,
1050 .mmu_sfsr_mask
= 0xffffffff,
1051 .mmu_trcr_mask
= 0xffffffff,
1052 .mxcc_version
= 0x00000104,
1054 .features
= CPU_DEFAULT_FEATURES
,
1057 .name
= "TI SuperSparc 60", // STP1020APGA
1058 .iu_version
= 0x40000000, // SuperSPARC 3.x
1059 .fpu_version
= 0 << 17,
1060 .mmu_version
= 0x01000800, // SuperSPARC 3.x, no MXCC
1061 .mmu_bm
= 0x00002000,
1062 .mmu_ctpr_mask
= 0xffffffc0,
1063 .mmu_cxr_mask
= 0x0000ffff,
1064 .mmu_sfsr_mask
= 0xffffffff,
1065 .mmu_trcr_mask
= 0xffffffff,
1067 .features
= CPU_DEFAULT_FEATURES
,
1070 .name
= "TI SuperSparc 61",
1071 .iu_version
= 0x44000000, // SuperSPARC 3.x
1072 .fpu_version
= 0 << 17,
1073 .mmu_version
= 0x01000000, // SuperSPARC 3.x, MXCC
1074 .mmu_bm
= 0x00002000,
1075 .mmu_ctpr_mask
= 0xffffffc0,
1076 .mmu_cxr_mask
= 0x0000ffff,
1077 .mmu_sfsr_mask
= 0xffffffff,
1078 .mmu_trcr_mask
= 0xffffffff,
1079 .mxcc_version
= 0x00000104,
1081 .features
= CPU_DEFAULT_FEATURES
,
1084 .name
= "TI SuperSparc II",
1085 .iu_version
= 0x40000000, // SuperSPARC II 1.x
1086 .fpu_version
= 0 << 17,
1087 .mmu_version
= 0x08000000, // SuperSPARC II 1.x, MXCC
1088 .mmu_bm
= 0x00002000,
1089 .mmu_ctpr_mask
= 0xffffffc0,
1090 .mmu_cxr_mask
= 0x0000ffff,
1091 .mmu_sfsr_mask
= 0xffffffff,
1092 .mmu_trcr_mask
= 0xffffffff,
1093 .mxcc_version
= 0x00000104,
1095 .features
= CPU_DEFAULT_FEATURES
,
1098 .name
= "Ross RT625",
1099 .iu_version
= 0x1e000000,
1100 .fpu_version
= 1 << 17,
1101 .mmu_version
= 0x1e000000,
1102 .mmu_bm
= 0x00004000,
1103 .mmu_ctpr_mask
= 0x007ffff0,
1104 .mmu_cxr_mask
= 0x0000003f,
1105 .mmu_sfsr_mask
= 0xffffffff,
1106 .mmu_trcr_mask
= 0xffffffff,
1108 .features
= CPU_DEFAULT_FEATURES
,
1111 .name
= "Ross RT620",
1112 .iu_version
= 0x1f000000,
1113 .fpu_version
= 1 << 17,
1114 .mmu_version
= 0x1f000000,
1115 .mmu_bm
= 0x00004000,
1116 .mmu_ctpr_mask
= 0x007ffff0,
1117 .mmu_cxr_mask
= 0x0000003f,
1118 .mmu_sfsr_mask
= 0xffffffff,
1119 .mmu_trcr_mask
= 0xffffffff,
1121 .features
= CPU_DEFAULT_FEATURES
,
1124 .name
= "BIT B5010",
1125 .iu_version
= 0x20000000,
1126 .fpu_version
= 0 << 17, /* B5010/B5110/B5120/B5210 */
1127 .mmu_version
= 0x20000000,
1128 .mmu_bm
= 0x00004000,
1129 .mmu_ctpr_mask
= 0x007ffff0,
1130 .mmu_cxr_mask
= 0x0000003f,
1131 .mmu_sfsr_mask
= 0xffffffff,
1132 .mmu_trcr_mask
= 0xffffffff,
1134 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1138 .name
= "Matsushita MN10501",
1139 .iu_version
= 0x50000000,
1140 .fpu_version
= 0 << 17,
1141 .mmu_version
= 0x50000000,
1142 .mmu_bm
= 0x00004000,
1143 .mmu_ctpr_mask
= 0x007ffff0,
1144 .mmu_cxr_mask
= 0x0000003f,
1145 .mmu_sfsr_mask
= 0xffffffff,
1146 .mmu_trcr_mask
= 0xffffffff,
1148 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_MUL
| CPU_FEATURE_FSQRT
|
1152 .name
= "Weitek W8601",
1153 .iu_version
= 0x90 << 24, /* Impl 9, ver 0 */
1154 .fpu_version
= 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1155 .mmu_version
= 0x10 << 24,
1156 .mmu_bm
= 0x00004000,
1157 .mmu_ctpr_mask
= 0x007ffff0,
1158 .mmu_cxr_mask
= 0x0000003f,
1159 .mmu_sfsr_mask
= 0xffffffff,
1160 .mmu_trcr_mask
= 0xffffffff,
1162 .features
= CPU_DEFAULT_FEATURES
,
1166 .iu_version
= 0xf2000000,
1167 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1168 .mmu_version
= 0xf2000000,
1169 .mmu_bm
= 0x00004000,
1170 .mmu_ctpr_mask
= 0x007ffff0,
1171 .mmu_cxr_mask
= 0x0000003f,
1172 .mmu_sfsr_mask
= 0xffffffff,
1173 .mmu_trcr_mask
= 0xffffffff,
1175 .features
= CPU_DEFAULT_FEATURES
,
1179 .iu_version
= 0xf3000000,
1180 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1181 .mmu_version
= 0xf3000000,
1182 .mmu_bm
= 0x00004000,
1183 .mmu_ctpr_mask
= 0x007ffff0,
1184 .mmu_cxr_mask
= 0x0000003f,
1185 .mmu_sfsr_mask
= 0xffffffff,
1186 .mmu_trcr_mask
= 0xffffffff,
1188 .features
= CPU_DEFAULT_FEATURES
,
1193 static const char * const feature_name
[] = {
1210 static void print_features(FILE *f
,
1211 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1212 uint32_t features
, const char *prefix
)
1216 for (i
= 0; i
< ARRAY_SIZE(feature_name
); i
++)
1217 if (feature_name
[i
] && (features
& (1 << i
))) {
1219 (*cpu_fprintf
)(f
, "%s", prefix
);
1220 (*cpu_fprintf
)(f
, "%s ", feature_name
[i
]);
1224 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
)
1228 for (i
= 0; i
< ARRAY_SIZE(feature_name
); i
++)
1229 if (feature_name
[i
] && !strcmp(flagname
, feature_name
[i
])) {
1230 *features
|= 1 << i
;
1233 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
1236 static int cpu_sparc_find_by_name(sparc_def_t
*cpu_def
, const char *cpu_model
)
1239 const sparc_def_t
*def
= NULL
;
1240 char *s
= strdup(cpu_model
);
1241 char *featurestr
, *name
= strtok(s
, ",");
1242 uint32_t plus_features
= 0;
1243 uint32_t minus_features
= 0;
1244 long long iu_version
;
1245 uint32_t fpu_version
, mmu_version
, nwindows
;
1247 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
1248 if (strcasecmp(name
, sparc_defs
[i
].name
) == 0) {
1249 def
= &sparc_defs
[i
];
1254 memcpy(cpu_def
, def
, sizeof(*def
));
1256 featurestr
= strtok(NULL
, ",");
1257 while (featurestr
) {
1260 if (featurestr
[0] == '+') {
1261 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
);
1262 } else if (featurestr
[0] == '-') {
1263 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
);
1264 } else if ((val
= strchr(featurestr
, '='))) {
1266 if (!strcmp(featurestr
, "iu_version")) {
1269 iu_version
= strtoll(val
, &err
, 0);
1270 if (!*val
|| *err
) {
1271 fprintf(stderr
, "bad numerical value %s\n", val
);
1274 cpu_def
->iu_version
= iu_version
;
1275 #ifdef DEBUG_FEATURES
1276 fprintf(stderr
, "iu_version %llx\n", iu_version
);
1278 } else if (!strcmp(featurestr
, "fpu_version")) {
1281 fpu_version
= strtol(val
, &err
, 0);
1282 if (!*val
|| *err
) {
1283 fprintf(stderr
, "bad numerical value %s\n", val
);
1286 cpu_def
->fpu_version
= fpu_version
;
1287 #ifdef DEBUG_FEATURES
1288 fprintf(stderr
, "fpu_version %llx\n", fpu_version
);
1290 } else if (!strcmp(featurestr
, "mmu_version")) {
1293 mmu_version
= strtol(val
, &err
, 0);
1294 if (!*val
|| *err
) {
1295 fprintf(stderr
, "bad numerical value %s\n", val
);
1298 cpu_def
->mmu_version
= mmu_version
;
1299 #ifdef DEBUG_FEATURES
1300 fprintf(stderr
, "mmu_version %llx\n", mmu_version
);
1302 } else if (!strcmp(featurestr
, "nwindows")) {
1305 nwindows
= strtol(val
, &err
, 0);
1306 if (!*val
|| *err
|| nwindows
> MAX_NWINDOWS
||
1307 nwindows
< MIN_NWINDOWS
) {
1308 fprintf(stderr
, "bad numerical value %s\n", val
);
1311 cpu_def
->nwindows
= nwindows
;
1312 #ifdef DEBUG_FEATURES
1313 fprintf(stderr
, "nwindows %d\n", nwindows
);
1316 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1320 fprintf(stderr
, "feature string `%s' not in format "
1321 "(+feature|-feature|feature=xyz)\n", featurestr
);
1324 featurestr
= strtok(NULL
, ",");
1326 cpu_def
->features
|= plus_features
;
1327 cpu_def
->features
&= ~minus_features
;
1328 #ifdef DEBUG_FEATURES
1329 print_features(stderr
, fprintf
, cpu_def
->features
, NULL
);
1339 void sparc_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
1343 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
1344 (*cpu_fprintf
)(f
, "Sparc %16s IU " TARGET_FMT_lx
" FPU %08x MMU %08x NWINS %d ",
1346 sparc_defs
[i
].iu_version
,
1347 sparc_defs
[i
].fpu_version
,
1348 sparc_defs
[i
].mmu_version
,
1349 sparc_defs
[i
].nwindows
);
1350 print_features(f
, cpu_fprintf
, CPU_DEFAULT_FEATURES
&
1351 ~sparc_defs
[i
].features
, "-");
1352 print_features(f
, cpu_fprintf
, ~CPU_DEFAULT_FEATURES
&
1353 sparc_defs
[i
].features
, "+");
1354 (*cpu_fprintf
)(f
, "\n");
1356 (*cpu_fprintf
)(f
, "Default CPU feature flags (use '-' to remove): ");
1357 print_features(f
, cpu_fprintf
, CPU_DEFAULT_FEATURES
, NULL
);
1358 (*cpu_fprintf
)(f
, "\n");
1359 (*cpu_fprintf
)(f
, "Available CPU feature flags (use '+' to add): ");
1360 print_features(f
, cpu_fprintf
, ~CPU_DEFAULT_FEATURES
, NULL
);
1361 (*cpu_fprintf
)(f
, "\n");
1362 (*cpu_fprintf
)(f
, "Numerical features (use '=' to set): iu_version "
1363 "fpu_version mmu_version nwindows\n");
1366 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1368 void cpu_dump_state(CPUState
*env
, FILE *f
,
1369 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1374 cpu_fprintf(f
, "pc: " TARGET_FMT_lx
" npc: " TARGET_FMT_lx
"\n", env
->pc
,
1376 cpu_fprintf(f
, "General Registers:\n");
1377 for (i
= 0; i
< 4; i
++)
1378 cpu_fprintf(f
, "%%g%c: " TARGET_FMT_lx
"\t", i
+ '0', env
->gregs
[i
]);
1379 cpu_fprintf(f
, "\n");
1381 cpu_fprintf(f
, "%%g%c: " TARGET_FMT_lx
"\t", i
+ '0', env
->gregs
[i
]);
1382 cpu_fprintf(f
, "\nCurrent Register Window:\n");
1383 for (x
= 0; x
< 3; x
++) {
1384 for (i
= 0; i
< 4; i
++)
1385 cpu_fprintf(f
, "%%%c%d: " TARGET_FMT_lx
"\t",
1386 (x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i')), i
,
1387 env
->regwptr
[i
+ x
* 8]);
1388 cpu_fprintf(f
, "\n");
1390 cpu_fprintf(f
, "%%%c%d: " TARGET_FMT_lx
"\t",
1391 (x
== 0 ? 'o' : x
== 1 ? 'l' : 'i'), i
,
1392 env
->regwptr
[i
+ x
* 8]);
1393 cpu_fprintf(f
, "\n");
1395 cpu_fprintf(f
, "\nFloating Point Registers:\n");
1396 for (i
= 0; i
< 32; i
++) {
1398 cpu_fprintf(f
, "%%f%02d:", i
);
1399 cpu_fprintf(f
, " %016f", *(float *)&env
->fpr
[i
]);
1401 cpu_fprintf(f
, "\n");
1403 #ifdef TARGET_SPARC64
1404 cpu_fprintf(f
, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1405 env
->pstate
, GET_CCR(env
), env
->asi
, env
->tl
, env
->fprs
);
1406 cpu_fprintf(f
, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1407 "cleanwin %d cwp %d\n",
1408 env
->cansave
, env
->canrestore
, env
->otherwin
, env
->wstate
,
1409 env
->cleanwin
, env
->nwindows
- 1 - env
->cwp
);
1411 cpu_fprintf(f
, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1412 GET_PSR(env
), GET_FLAG(PSR_ZERO
, 'Z'), GET_FLAG(PSR_OVF
, 'V'),
1413 GET_FLAG(PSR_NEG
, 'N'), GET_FLAG(PSR_CARRY
, 'C'),
1414 env
->psrs
?'S':'-', env
->psrps
?'P':'-',
1415 env
->psret
?'E':'-', env
->wim
);
1417 cpu_fprintf(f
, "fsr: 0x%08x\n", env
->fsr
);