hw/iommu.c

   1 /*
   2  * QEMU SPARC iommu emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26
  27 /* debug iommu */
  28 //#define DEBUG_IOMMU
  29
  30 #ifdef DEBUG_IOMMU
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("IOMMU: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 #define IOMMU_NREGS         (4*4096/4)
  38 #define IOMMU_CTRL          (0x0000 >> 2)
  39 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  40 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  41 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  42 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  43 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  44 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  45 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  46 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  47 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  48 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  49 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  50 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  51 #define IOMMU_CTRL_MASK     0x0000001d
  52
  53 #define IOMMU_BASE          (0x0004 >> 2)
  54 #define IOMMU_BASE_MASK     0x07fffc00
  55
  56 #define IOMMU_TLBFLUSH      (0x0014 >> 2)
  57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
  58
  59 #define IOMMU_PGFLUSH       (0x0018 >> 2)
  60 #define IOMMU_PGFLUSH_MASK  0xffffffff
  61
  62 #define IOMMU_AFSR          (0x1000 >> 2)
  63 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  64 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  65                                           transaction */
  66 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  67                                           12.8 us. */
  68 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  69                                           acknowledge */
  70 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  71 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  72 #define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  73                                           hardware */
  74 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  75 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  76 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  77 #define IOMMU_AFSR_MASK     0xff0fffff
  78
  79 #define IOMMU_AFAR          (0x1004 >> 2)
  80
  81 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  82 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  83 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  84 #define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
  85 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
  86                                           bypass enabled */
  87 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
  88 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
  89 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
  90                                           produced by this device as pure
  91                                           physical. */
  92 #define IOMMU_SBCFG_MASK    0x00010003
  93
  94 #define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
  95 #define IOMMU_ARBEN_MASK    0x001f0000
  96 #define IOMMU_MID           0x00000008
  97
  98 #define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
  99 #define IOMMU_MASK_ID_MASK  0x00ffffff
 100
 101 #define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
 102 #define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */
 103
 104 /* The format of an iopte in the page tables */
 105 #define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
 106 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 107                                           Viking/MXCC) */
 108 #define IOPTE_WRITE         0x00000004 /* Writeable */
 109 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 110 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
 111
 112 #define PAGE_SHIFT      12
 113 #define PAGE_SIZE       (1 << PAGE_SHIFT)
 114 #define PAGE_MASK       (PAGE_SIZE - 1)
 115
 116 typedef struct IOMMUState {
 117     target_phys_addr_t addr;
 118     uint32_t regs[IOMMU_NREGS];
 119     target_phys_addr_t iostart;
 120     uint32_t version;
 121     qemu_irq irq;
 122 } IOMMUState;
 123
 124 static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
 125 {
 126     IOMMUState *s = opaque;
 127     target_phys_addr_t saddr;
 128     uint32_t ret;
 129
 130     saddr = (addr - s->addr) >> 2;
 131     switch (saddr) {
 132     default:
 133         ret = s->regs[saddr];
 134         break;
 135     case IOMMU_AFAR:
 136     case IOMMU_AFSR:
 137         ret = s->regs[saddr];
 138         qemu_irq_lower(s->irq);
 139         break;
 140     }
 141     DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
 142     return ret;
 143 }
 144
 145 static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
 146                              uint32_t val)
 147 {
 148     IOMMUState *s = opaque;
 149     target_phys_addr_t saddr;
 150
 151     saddr = (addr - s->addr) >> 2;
 152     DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
 153     switch (saddr) {
 154     case IOMMU_CTRL:
 155         switch (val & IOMMU_CTRL_RNGE) {
 156         case IOMMU_RNGE_16MB:
 157             s->iostart = 0xffffffffff000000ULL;
 158             break;
 159         case IOMMU_RNGE_32MB:
 160             s->iostart = 0xfffffffffe000000ULL;
 161             break;
 162         case IOMMU_RNGE_64MB:
 163             s->iostart = 0xfffffffffc000000ULL;
 164             break;
 165         case IOMMU_RNGE_128MB:
 166             s->iostart = 0xfffffffff8000000ULL;
 167             break;
 168         case IOMMU_RNGE_256MB:
 169             s->iostart = 0xfffffffff0000000ULL;
 170             break;
 171         case IOMMU_RNGE_512MB:
 172             s->iostart = 0xffffffffe0000000ULL;
 173             break;
 174         case IOMMU_RNGE_1GB:
 175             s->iostart = 0xffffffffc0000000ULL;
 176             break;
 177         default:
 178         case IOMMU_RNGE_2GB:
 179             s->iostart = 0xffffffff80000000ULL;
 180             break;
 181         }
 182         DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
 183         s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 184         break;
 185     case IOMMU_BASE:
 186         s->regs[saddr] = val & IOMMU_BASE_MASK;
 187         break;
 188     case IOMMU_TLBFLUSH:
 189         DPRINTF("tlb flush %x\n", val);
 190         s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 191         break;
 192     case IOMMU_PGFLUSH:
 193         DPRINTF("page flush %x\n", val);
 194         s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 195         break;
 196     case IOMMU_AFAR:
 197         s->regs[saddr] = val;
 198         qemu_irq_lower(s->irq);
 199         break;
 200     case IOMMU_AFSR:
 201         s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
 202         qemu_irq_lower(s->irq);
 203         break;
 204     case IOMMU_SBCFG0:
 205     case IOMMU_SBCFG1:
 206     case IOMMU_SBCFG2:
 207     case IOMMU_SBCFG3:
 208         s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 209         break;
 210     case IOMMU_ARBEN:
 211         // XXX implement SBus probing: fault when reading unmapped
 212         // addresses, fault cause and address stored to MMU/IOMMU
 213         s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 214         break;
 215     case IOMMU_MASK_ID:
 216         s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
 217         break;
 218     default:
 219         s->regs[saddr] = val;
 220         break;
 221     }
 222 }
 223
 224 static CPUReadMemoryFunc *iommu_mem_read[3] = {
 225     NULL,
 226     NULL,
 227     iommu_mem_readl,
 228 };
 229
 230 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
 231     NULL,
 232     NULL,
 233     iommu_mem_writel,
 234 };
 235
 236 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
 237 {
 238     uint32_t ret;
 239     target_phys_addr_t iopte;
 240 #ifdef DEBUG_IOMMU
 241     target_phys_addr_t pa = addr;
 242 #endif
 243
 244     iopte = s->regs[IOMMU_BASE] << 4;
 245     addr &= ~s->iostart;
 246     iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
 247     cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
 248     tswap32s(&ret);
 249     DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
 250             ", *pte = %x\n", pa, iopte, ret);
 251
 252     return ret;
 253 }
 254
 255 static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
 256                                              uint32_t pte)
 257 {
 258     uint32_t tmppte;
 259     target_phys_addr_t pa;
 260
 261     tmppte = pte;
 262     pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
 263     DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
 264             " (iopte = %x)\n", addr, pa, tmppte);
 265
 266     return pa;
 267 }
 268
 269 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
 270                            int is_write)
 271 {
 272     DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
 273     s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 274         IOMMU_AFSR_FAV;
 275     if (!is_write)
 276         s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 277     s->regs[IOMMU_AFAR] = addr;
 278     qemu_irq_raise(s->irq);
 279 }
 280
 281 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
 282                            uint8_t *buf, int len, int is_write)
 283 {
 284     int l;
 285     uint32_t flags;
 286     target_phys_addr_t page, phys_addr;
 287
 288     while (len > 0) {
 289         page = addr & TARGET_PAGE_MASK;
 290         l = (page + TARGET_PAGE_SIZE) - addr;
 291         if (l > len)
 292             l = len;
 293         flags = iommu_page_get_flags(opaque, page);
 294         if (!(flags & IOPTE_VALID)) {
 295             iommu_bad_addr(opaque, page, is_write);
 296             return;
 297         }
 298         phys_addr = iommu_translate_pa(addr, flags);
 299         if (is_write) {
 300             if (!(flags & IOPTE_WRITE)) {
 301                 iommu_bad_addr(opaque, page, is_write);
 302                 return;
 303             }
 304             cpu_physical_memory_write(phys_addr, buf, l);
 305         } else {
 306             cpu_physical_memory_read(phys_addr, buf, l);
 307         }
 308         len -= l;
 309         buf += l;
 310         addr += l;
 311     }
 312 }
 313
 314 static void iommu_save(QEMUFile *f, void *opaque)
 315 {
 316     IOMMUState *s = opaque;
 317     int i;
 318
 319     for (i = 0; i < IOMMU_NREGS; i++)
 320         qemu_put_be32s(f, &s->regs[i]);
 321     qemu_put_be64s(f, &s->iostart);
 322 }
 323
 324 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
 325 {
 326     IOMMUState *s = opaque;
 327     int i;
 328
 329     if (version_id != 2)
 330         return -EINVAL;
 331
 332     for (i = 0; i < IOMMU_NREGS; i++)
 333         qemu_get_be32s(f, &s->regs[i]);
 334     qemu_get_be64s(f, &s->iostart);
 335
 336     return 0;
 337 }
 338
 339 static void iommu_reset(void *opaque)
 340 {
 341     IOMMUState *s = opaque;
 342
 343     memset(s->regs, 0, IOMMU_NREGS * 4);
 344     s->iostart = 0;
 345     s->regs[IOMMU_CTRL] = s->version;
 346     s->regs[IOMMU_ARBEN] = IOMMU_MID;
 347     s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 348     s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
 349     qemu_irq_lower(s->irq);
 350 }
 351
 352 void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
 353 {
 354     IOMMUState *s;
 355     int iommu_io_memory;
 356
 357     s = qemu_mallocz(sizeof(IOMMUState));
 358     if (!s)
 359         return NULL;
 360
 361     s->addr = addr;
 362     s->version = version;
 363     s->irq = irq;
 364
 365     iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
 366                                              iommu_mem_write, s);
 367     cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
 368
 369     register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
 370     qemu_register_reset(iommu_reset, s);
 371     iommu_reset(s);
 372     return s;
 373 }