hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pci.h"
  27
  28 #define VERBOSE
  29 #define EMBED_STDVGA
  30 #undef DIRECT_VRAM
  31 #define HW_RECT_ACCEL
  32 #define HW_FILL_ACCEL
  33 #define HW_MOUSE_ACCEL
  34
  35 #ifdef EMBED_STDVGA
  36 # include "vga_int.h"
  37 #endif
  38
  39 struct vmsvga_state_s {
  40 #ifdef EMBED_STDVGA
  41     VGA_STATE_COMMON
  42 #endif
  43
  44     int width;
  45     int height;
  46     int invalidated;
  47     int depth;
  48     int bypp;
  49     int enable;
  50     int config;
  51     struct {
  52         int id;
  53         int x;
  54         int y;
  55         int on;
  56     } cursor;
  57
  58 #ifndef EMBED_STDVGA
  59     DisplayState *ds;
  60     QEMUConsole *console;
  61     int vram_size;
  62     ram_addr_t vram_offset;
  63 #endif
  64     uint8_t *vram;
  65     target_phys_addr_t vram_base;
  66
  67     int index;
  68     int scratch_size;
  69     uint32_t *scratch;
  70     int new_width;
  71     int new_height;
  72     uint32_t guest;
  73     uint32_t svgaid;
  74     uint32_t wred;
  75     uint32_t wgreen;
  76     uint32_t wblue;
  77     int syncing;
  78     int fb_size;
  79
  80     union {
  81         uint32_t *fifo;
  82         struct __attribute__((__packed__)) {
  83             uint32_t min;
  84             uint32_t max;
  85             uint32_t next_cmd;
  86             uint32_t stop;
  87             /* Add registers here when adding capabilities.  */
  88             uint32_t fifo[0];
  89         } *cmd;
  90     };
  91
  92 #define REDRAW_FIFO_LEN 512
  93     struct vmsvga_rect_s {
  94         int x, y, w, h;
  95     } redraw_fifo[REDRAW_FIFO_LEN];
  96     int redraw_fifo_first, redraw_fifo_last;
  97 };
  98
  99 struct pci_vmsvga_state_s {
 100     PCIDevice card;
 101     struct vmsvga_state_s chip;
 102 };
 103
 104 #define SVGA_MAGIC              0x900000UL
 105 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
 106 #define SVGA_ID_0               SVGA_MAKE_ID(0)
 107 #define SVGA_ID_1               SVGA_MAKE_ID(1)
 108 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 109
 110 #define SVGA_LEGACY_BASE_PORT   0x4560
 111 #define SVGA_INDEX_PORT         0x0
 112 #define SVGA_VALUE_PORT         0x1
 113 #define SVGA_BIOS_PORT          0x2
 114
 115 #define SVGA_VERSION_2
 116
 117 #ifdef SVGA_VERSION_2
 118 # define SVGA_ID                SVGA_ID_2
 119 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 120 # define SVGA_IO_MUL            1
 121 # define SVGA_FIFO_SIZE         0x10000
 122 # define SVGA_MEM_BASE          0xe0000000
 123 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 124 #else
 125 # define SVGA_ID                SVGA_ID_1
 126 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 127 # define SVGA_IO_MUL            4
 128 # define SVGA_FIFO_SIZE         0x10000
 129 # define SVGA_MEM_BASE          0xe0000000
 130 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 131 #endif
 132
 133 enum {
 134     /* ID 0, 1 and 2 registers */
 135     SVGA_REG_ID = 0,
 136     SVGA_REG_ENABLE = 1,
 137     SVGA_REG_WIDTH = 2,
 138     SVGA_REG_HEIGHT = 3,
 139     SVGA_REG_MAX_WIDTH = 4,
 140     SVGA_REG_MAX_HEIGHT = 5,
 141     SVGA_REG_DEPTH = 6,
 142     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 143     SVGA_REG_PSEUDOCOLOR = 8,
 144     SVGA_REG_RED_MASK = 9,
 145     SVGA_REG_GREEN_MASK = 10,
 146     SVGA_REG_BLUE_MASK = 11,
 147     SVGA_REG_BYTES_PER_LINE = 12,
 148     SVGA_REG_FB_START = 13,
 149     SVGA_REG_FB_OFFSET = 14,
 150     SVGA_REG_VRAM_SIZE = 15,
 151     SVGA_REG_FB_SIZE = 16,
 152
 153     /* ID 1 and 2 registers */
 154     SVGA_REG_CAPABILITIES = 17,
 155     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 156     SVGA_REG_MEM_SIZE = 19,
 157     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 158     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 159     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 160     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 161     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 162     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 163     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 164     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 165     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 166     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 167     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 168     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 169     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 170
 171     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 172     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 173     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 174 };
 175
 176 #define SVGA_CAP_NONE                   0
 177 #define SVGA_CAP_RECT_FILL              (1 << 0)
 178 #define SVGA_CAP_RECT_COPY              (1 << 1)
 179 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 180 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 181 #define SVGA_CAP_RASTER_OP              (1 << 4)
 182 #define SVGA_CAP_CURSOR                 (1 << 5)
 183 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 184 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 185 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 186 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 187 #define SVGA_CAP_GLYPH                  (1 << 10)
 188 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 189 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 190 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 191 #define SVGA_CAP_3D                     (1 << 14)
 192 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 193 #define SVGA_CAP_MULTIMON               (1 << 16)
 194 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 195
 196 /*
 197  * FIFO offsets (seen as an array of 32-bit words)
 198  */
 199 enum {
 200     /*
 201      * The original defined FIFO offsets
 202      */
 203     SVGA_FIFO_MIN = 0,
 204     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 205     SVGA_FIFO_NEXT_CMD,
 206     SVGA_FIFO_STOP,
 207
 208     /*
 209      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 210      */
 211     SVGA_FIFO_CAPABILITIES = 4,
 212     SVGA_FIFO_FLAGS,
 213     SVGA_FIFO_FENCE,
 214     SVGA_FIFO_3D_HWVERSION,
 215     SVGA_FIFO_PITCHLOCK,
 216 };
 217
 218 #define SVGA_FIFO_CAP_NONE              0
 219 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 220 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 221 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 222
 223 #define SVGA_FIFO_FLAG_NONE             0
 224 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 225
 226 /* These values can probably be changed arbitrarily.  */
 227 #define SVGA_SCRATCH_SIZE               0x8000
 228 #define SVGA_MAX_WIDTH                  2360
 229 #define SVGA_MAX_HEIGHT                 1770
 230
 231 #ifdef VERBOSE
 232 # define GUEST_OS_BASE          0x5001
 233 static const char *vmsvga_guest_id[] = {
 234     [0x00 ... 0x15] = "an unknown OS",
 235     [0x00] = "Dos",
 236     [0x01] = "Windows 3.1",
 237     [0x02] = "Windows 95",
 238     [0x03] = "Windows 98",
 239     [0x04] = "Windows ME",
 240     [0x05] = "Windows NT",
 241     [0x06] = "Windows 2000",
 242     [0x07] = "Linux",
 243     [0x08] = "OS/2",
 244     [0x0a] = "BSD",
 245     [0x0b] = "Whistler",
 246     [0x15] = "Windows 2003",
 247 };
 248 #endif
 249
 250 enum {
 251     SVGA_CMD_INVALID_CMD = 0,
 252     SVGA_CMD_UPDATE = 1,
 253     SVGA_CMD_RECT_FILL = 2,
 254     SVGA_CMD_RECT_COPY = 3,
 255     SVGA_CMD_DEFINE_BITMAP = 4,
 256     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 257     SVGA_CMD_DEFINE_PIXMAP = 6,
 258     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 259     SVGA_CMD_RECT_BITMAP_FILL = 8,
 260     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 261     SVGA_CMD_RECT_BITMAP_COPY = 10,
 262     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 263     SVGA_CMD_FREE_OBJECT = 12,
 264     SVGA_CMD_RECT_ROP_FILL = 13,
 265     SVGA_CMD_RECT_ROP_COPY = 14,
 266     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 267     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 268     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 269     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 270     SVGA_CMD_DEFINE_CURSOR = 19,
 271     SVGA_CMD_DISPLAY_CURSOR = 20,
 272     SVGA_CMD_MOVE_CURSOR = 21,
 273     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 274     SVGA_CMD_DRAW_GLYPH = 23,
 275     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 276     SVGA_CMD_UPDATE_VERBOSE = 25,
 277     SVGA_CMD_SURFACE_FILL = 26,
 278     SVGA_CMD_SURFACE_COPY = 27,
 279     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 280     SVGA_CMD_FRONT_ROP_FILL = 29,
 281     SVGA_CMD_FENCE = 30,
 282 };
 283
 284 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 285 enum {
 286     SVGA_CURSOR_ON_HIDE = 0,
 287     SVGA_CURSOR_ON_SHOW = 1,
 288     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 289     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 290 };
 291
 292 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 293                 int x, int y, int w, int h)
 294 {
 295 #ifndef DIRECT_VRAM
 296     int line;
 297     int bypl;
 298     int width;
 299     int start;
 300     uint8_t *src;
 301     uint8_t *dst;
 302
 303     if (x + w > s->width) {
 304         fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
 305                         __FUNCTION__, x, w);
 306         x = MIN(x, s->width);
 307         w = s->width - x;
 308     }
 309
 310     if (y + h > s->height) {
 311         fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
 312                         __FUNCTION__, y, h);
 313         y = MIN(y, s->height);
 314         h = s->height - y;
 315     }
 316
 317     line = h;
 318     bypl = s->bypp * s->width;
 319     width = s->bypp * w;
 320     start = s->bypp * x + bypl * y;
 321     src = s->vram + start;
 322     dst = s->ds->data + start;
 323
 324     for (; line > 0; line --, src += bypl, dst += bypl)
 325         memcpy(dst, src, width);
 326 #endif
 327
 328     dpy_update(s->ds, x, y, w, h);
 329 }
 330
 331 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 332 {
 333 #ifndef DIRECT_VRAM
 334     memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
 335 #endif
 336
 337     dpy_update(s->ds, 0, 0, s->width, s->height);
 338 }
 339
 340 #ifdef DIRECT_VRAM
 341 # define vmsvga_update_rect_delayed     vmsvga_update_rect
 342 #else
 343 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 344                 int x, int y, int w, int h)
 345 {
 346     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
 347     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 348     rect->x = x;
 349     rect->y = y;
 350     rect->w = w;
 351     rect->h = h;
 352 }
 353 #endif
 354
 355 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 356 {
 357     struct vmsvga_rect_s *rect;
 358     if (s->invalidated) {
 359         s->redraw_fifo_first = s->redraw_fifo_last;
 360         return;
 361     }
 362     /* Overlapping region updates can be optimised out here - if someone
 363      * knows a smart algorithm to do that, please share.  */
 364     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 365         rect = &s->redraw_fifo[s->redraw_fifo_first ++];
 366         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 367         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 368     }
 369 }
 370
 371 #ifdef HW_RECT_ACCEL
 372 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 373                 int x0, int y0, int x1, int y1, int w, int h)
 374 {
 375 # ifdef DIRECT_VRAM
 376     uint8_t *vram = s->ds->data;
 377 # else
 378     uint8_t *vram = s->vram;
 379 # endif
 380     int bypl = s->bypp * s->width;
 381     int width = s->bypp * w;
 382     int line = h;
 383     uint8_t *ptr[2];
 384
 385 # ifdef DIRECT_VRAM
 386     if (s->ds->dpy_copy)
 387         s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
 388     else
 389 # endif
 390     {
 391         if (y1 > y0) {
 392             ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 393             ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 394             for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
 395                 memmove(ptr[1], ptr[0], width);
 396         } else {
 397             ptr[0] = vram + s->bypp * x0 + bypl * y0;
 398             ptr[1] = vram + s->bypp * x1 + bypl * y1;
 399             for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
 400                 memmove(ptr[1], ptr[0], width);
 401         }
 402     }
 403
 404     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 405 }
 406 #endif
 407
 408 #ifdef HW_FILL_ACCEL
 409 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 410                 uint32_t c, int x, int y, int w, int h)
 411 {
 412 # ifdef DIRECT_VRAM
 413     uint8_t *vram = s->ds->data;
 414 # else
 415     uint8_t *vram = s->vram;
 416 # endif
 417     int bypp = s->bypp;
 418     int bypl = bypp * s->width;
 419     int width = bypp * w;
 420     int line = h;
 421     int column;
 422     uint8_t *fst = vram + bypp * x + bypl * y;
 423     uint8_t *dst;
 424     uint8_t *src;
 425     uint8_t col[4];
 426
 427 # ifdef DIRECT_VRAM
 428     if (s->ds->dpy_fill)
 429         s->ds->dpy_fill(s->ds, x, y, w, h, c);
 430     else
 431 # endif
 432     {
 433         col[0] = c;
 434         col[1] = c >> 8;
 435         col[2] = c >> 16;
 436         col[3] = c >> 24;
 437
 438         if (line --) {
 439             dst = fst;
 440             src = col;
 441             for (column = width; column > 0; column --) {
 442                 *(dst ++) = *(src ++);
 443                 if (src - col == bypp)
 444                     src = col;
 445             }
 446             dst = fst;
 447             for (; line > 0; line --) {
 448                 dst += bypl;
 449                 memcpy(dst, fst, width);
 450             }
 451         }
 452     }
 453
 454     vmsvga_update_rect_delayed(s, x, y, w, h);
 455 }
 456 #endif
 457
 458 struct vmsvga_cursor_definition_s {
 459     int width;
 460     int height;
 461     int id;
 462     int bpp;
 463     int hot_x;
 464     int hot_y;
 465     uint32_t mask[1024];
 466     uint32_t image[1024];
 467 };
 468
 469 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 470 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 471
 472 #ifdef HW_MOUSE_ACCEL
 473 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 474                 struct vmsvga_cursor_definition_s *c)
 475 {
 476     int i;
 477     for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
 478         c->mask[i] = ~c->mask[i];
 479
 480     if (s->ds->cursor_define)
 481         s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
 482                         (uint8_t *) c->image, (uint8_t *) c->mask);
 483 }
 484 #endif
 485
 486 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
 487 {
 488     if (!s->config || !s->enable)
 489         return 1;
 490     return (s->cmd->next_cmd == s->cmd->stop);
 491 }
 492
 493 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 494 {
 495     uint32_t cmd = s->fifo[s->cmd->stop >> 2];
 496     s->cmd->stop += 4;
 497     if (s->cmd->stop >= s->cmd->max)
 498         s->cmd->stop = s->cmd->min;
 499     return cmd;
 500 }
 501
 502 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 503 {
 504     uint32_t cmd, colour;
 505     int args = 0;
 506     int x, y, dx, dy, width, height;
 507     struct vmsvga_cursor_definition_s cursor;
 508     while (!vmsvga_fifo_empty(s))
 509         switch (cmd = vmsvga_fifo_read(s)) {
 510         case SVGA_CMD_UPDATE:
 511         case SVGA_CMD_UPDATE_VERBOSE:
 512             x = vmsvga_fifo_read(s);
 513             y = vmsvga_fifo_read(s);
 514             width = vmsvga_fifo_read(s);
 515             height = vmsvga_fifo_read(s);
 516             vmsvga_update_rect_delayed(s, x, y, width, height);
 517             break;
 518
 519         case SVGA_CMD_RECT_FILL:
 520             colour = vmsvga_fifo_read(s);
 521             x = vmsvga_fifo_read(s);
 522             y = vmsvga_fifo_read(s);
 523             width = vmsvga_fifo_read(s);
 524             height = vmsvga_fifo_read(s);
 525 #ifdef HW_FILL_ACCEL
 526             vmsvga_fill_rect(s, colour, x, y, width, height);
 527             break;
 528 #else
 529             goto badcmd;
 530 #endif
 531
 532         case SVGA_CMD_RECT_COPY:
 533             x = vmsvga_fifo_read(s);
 534             y = vmsvga_fifo_read(s);
 535             dx = vmsvga_fifo_read(s);
 536             dy = vmsvga_fifo_read(s);
 537             width = vmsvga_fifo_read(s);
 538             height = vmsvga_fifo_read(s);
 539 #ifdef HW_RECT_ACCEL
 540             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 541             break;
 542 #else
 543             goto badcmd;
 544 #endif
 545
 546         case SVGA_CMD_DEFINE_CURSOR:
 547             cursor.id = vmsvga_fifo_read(s);
 548             cursor.hot_x = vmsvga_fifo_read(s);
 549             cursor.hot_y = vmsvga_fifo_read(s);
 550             cursor.width = x = vmsvga_fifo_read(s);
 551             cursor.height = y = vmsvga_fifo_read(s);
 552             vmsvga_fifo_read(s);
 553             cursor.bpp = vmsvga_fifo_read(s);
 554             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
 555                 cursor.mask[args] = vmsvga_fifo_read(s);
 556             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
 557                 cursor.image[args] = vmsvga_fifo_read(s);
 558 #ifdef HW_MOUSE_ACCEL
 559             vmsvga_cursor_define(s, &cursor);
 560             break;
 561 #else
 562             args = 0;
 563             goto badcmd;
 564 #endif
 565
 566         /*
 567          * Other commands that we at least know the number of arguments
 568          * for so we can avoid FIFO desync if driver uses them illegally.
 569          */
 570         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 571             vmsvga_fifo_read(s);
 572             vmsvga_fifo_read(s);
 573             vmsvga_fifo_read(s);
 574             x = vmsvga_fifo_read(s);
 575             y = vmsvga_fifo_read(s);
 576             args = x * y;
 577             goto badcmd;
 578         case SVGA_CMD_RECT_ROP_FILL:
 579             args = 6;
 580             goto badcmd;
 581         case SVGA_CMD_RECT_ROP_COPY:
 582             args = 7;
 583             goto badcmd;
 584         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 585             vmsvga_fifo_read(s);
 586             vmsvga_fifo_read(s);
 587             args = 7 + (vmsvga_fifo_read(s) >> 2);
 588             goto badcmd;
 589         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 590             args = 12;
 591             goto badcmd;
 592
 593         /*
 594          * Other commands that are not listed as depending on any
 595          * CAPABILITIES bits, but are not described in the README either.
 596          */
 597         case SVGA_CMD_SURFACE_FILL:
 598         case SVGA_CMD_SURFACE_COPY:
 599         case SVGA_CMD_FRONT_ROP_FILL:
 600         case SVGA_CMD_FENCE:
 601         case SVGA_CMD_INVALID_CMD:
 602             break; /* Nop */
 603
 604         default:
 605         badcmd:
 606             while (args --)
 607                 vmsvga_fifo_read(s);
 608             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 609                             __FUNCTION__, cmd);
 610             break;
 611         }
 612
 613     s->syncing = 0;
 614 }
 615
 616 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 617 {
 618     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 619     return s->index;
 620 }
 621
 622 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 623 {
 624     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 625     s->index = index;
 626 }
 627
 628 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 629 {
 630     uint32_t caps;
 631     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 632     switch (s->index) {
 633     case SVGA_REG_ID:
 634         return s->svgaid;
 635
 636     case SVGA_REG_ENABLE:
 637         return s->enable;
 638
 639     case SVGA_REG_WIDTH:
 640         return s->width;
 641
 642     case SVGA_REG_HEIGHT:
 643         return s->height;
 644
 645     case SVGA_REG_MAX_WIDTH:
 646         return SVGA_MAX_WIDTH;
 647
 648     case SVGA_REG_MAX_HEIGHT:
 649         return SVGA_MAX_HEIGHT;
 650
 651     case SVGA_REG_DEPTH:
 652         return s->depth;
 653
 654     case SVGA_REG_BITS_PER_PIXEL:
 655         return (s->depth + 7) & ~7;
 656
 657     case SVGA_REG_PSEUDOCOLOR:
 658         return 0x0;
 659
 660     case SVGA_REG_RED_MASK:
 661         return s->wred;
 662     case SVGA_REG_GREEN_MASK:
 663         return s->wgreen;
 664     case SVGA_REG_BLUE_MASK:
 665         return s->wblue;
 666
 667     case SVGA_REG_BYTES_PER_LINE:
 668         return ((s->depth + 7) >> 3) * s->new_width;
 669
 670     case SVGA_REG_FB_START:
 671         return s->vram_base;
 672
 673     case SVGA_REG_FB_OFFSET:
 674         return 0x0;
 675
 676     case SVGA_REG_VRAM_SIZE:
 677         return s->vram_size - SVGA_FIFO_SIZE;
 678
 679     case SVGA_REG_FB_SIZE:
 680         return s->fb_size;
 681
 682     case SVGA_REG_CAPABILITIES:
 683         caps = SVGA_CAP_NONE;
 684 #ifdef HW_RECT_ACCEL
 685         caps |= SVGA_CAP_RECT_COPY;
 686 #endif
 687 #ifdef HW_FILL_ACCEL
 688         caps |= SVGA_CAP_RECT_FILL;
 689 #endif
 690 #ifdef HW_MOUSE_ACCEL
 691         if (s->ds->mouse_set)
 692             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 693                     SVGA_CAP_CURSOR_BYPASS;
 694 #endif
 695         return caps;
 696
 697     case SVGA_REG_MEM_START:
 698         return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
 699
 700     case SVGA_REG_MEM_SIZE:
 701         return SVGA_FIFO_SIZE;
 702
 703     case SVGA_REG_CONFIG_DONE:
 704         return s->config;
 705
 706     case SVGA_REG_SYNC:
 707     case SVGA_REG_BUSY:
 708         return s->syncing;
 709
 710     case SVGA_REG_GUEST_ID:
 711         return s->guest;
 712
 713     case SVGA_REG_CURSOR_ID:
 714         return s->cursor.id;
 715
 716     case SVGA_REG_CURSOR_X:
 717         return s->cursor.x;
 718
 719     case SVGA_REG_CURSOR_Y:
 720         return s->cursor.x;
 721
 722     case SVGA_REG_CURSOR_ON:
 723         return s->cursor.on;
 724
 725     case SVGA_REG_HOST_BITS_PER_PIXEL:
 726         return (s->depth + 7) & ~7;
 727
 728     case SVGA_REG_SCRATCH_SIZE:
 729         return s->scratch_size;
 730
 731     case SVGA_REG_MEM_REGS:
 732     case SVGA_REG_NUM_DISPLAYS:
 733     case SVGA_REG_PITCHLOCK:
 734     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 735         return 0;
 736
 737     default:
 738         if (s->index >= SVGA_SCRATCH_BASE &&
 739                 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
 740             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 741         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 742     }
 743
 744     return 0;
 745 }
 746
 747 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 748 {
 749     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 750     switch (s->index) {
 751     case SVGA_REG_ID:
 752         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
 753             s->svgaid = value;
 754         break;
 755
 756     case SVGA_REG_ENABLE:
 757         s->enable = value;
 758         s->config &= !!value;
 759         s->width = -1;
 760         s->height = -1;
 761         s->invalidated = 1;
 762 #ifdef EMBED_STDVGA
 763         s->invalidate(opaque);
 764 #endif
 765         if (s->enable)
 766             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 767         break;
 768
 769     case SVGA_REG_WIDTH:
 770         s->new_width = value;
 771         s->invalidated = 1;
 772         break;
 773
 774     case SVGA_REG_HEIGHT:
 775         s->new_height = value;
 776         s->invalidated = 1;
 777         break;
 778
 779     case SVGA_REG_DEPTH:
 780     case SVGA_REG_BITS_PER_PIXEL:
 781         if (value != s->depth) {
 782             printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
 783             s->config = 0;
 784         }
 785         break;
 786
 787     case SVGA_REG_CONFIG_DONE:
 788         if (value) {
 789             s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
 790             /* Check range and alignment.  */
 791             if ((s->cmd->min | s->cmd->max |
 792                         s->cmd->next_cmd | s->cmd->stop) & 3)
 793                 break;
 794             if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
 795                 break;
 796             if (s->cmd->max > SVGA_FIFO_SIZE)
 797                 break;
 798             if (s->cmd->max < s->cmd->min + 10 * 1024)
 799                 break;
 800         }
 801         s->config = !!value;
 802         break;
 803
 804     case SVGA_REG_SYNC:
 805         s->syncing = 1;
 806         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 807         break;
 808
 809     case SVGA_REG_GUEST_ID:
 810         s->guest = value;
 811 #ifdef VERBOSE
 812         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 813                 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
 814             printf("%s: guest runs %s.\n", __FUNCTION__,
 815                             vmsvga_guest_id[value - GUEST_OS_BASE]);
 816 #endif
 817         break;
 818
 819     case SVGA_REG_CURSOR_ID:
 820         s->cursor.id = value;
 821         break;
 822
 823     case SVGA_REG_CURSOR_X:
 824         s->cursor.x = value;
 825         break;
 826
 827     case SVGA_REG_CURSOR_Y:
 828         s->cursor.y = value;
 829         break;
 830
 831     case SVGA_REG_CURSOR_ON:
 832         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 833         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 834 #ifdef HW_MOUSE_ACCEL
 835         if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
 836             s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
 837 #endif
 838         break;
 839
 840     case SVGA_REG_MEM_REGS:
 841     case SVGA_REG_NUM_DISPLAYS:
 842     case SVGA_REG_PITCHLOCK:
 843     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 844         break;
 845
 846     default:
 847         if (s->index >= SVGA_SCRATCH_BASE &&
 848                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 849             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 850             break;
 851         }
 852         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 853     }
 854 }
 855
 856 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 857 {
 858     printf("%s: what are we supposed to return?\n", __FUNCTION__);
 859     return 0xcafe;
 860 }
 861
 862 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 863 {
 864     printf("%s: what are we supposed to do with (%08x)?\n",
 865                     __FUNCTION__, data);
 866 }
 867
 868 static inline void vmsvga_size(struct vmsvga_state_s *s)
 869 {
 870     if (s->new_width != s->width || s->new_height != s->height) {
 871         s->width = s->new_width;
 872         s->height = s->new_height;
 873         qemu_console_resize(s->console, s->width, s->height);
 874         s->invalidated = 1;
 875     }
 876 }
 877
 878 static void vmsvga_update_display(void *opaque)
 879 {
 880     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 881     if (!s->enable) {
 882 #ifdef EMBED_STDVGA
 883         s->update(opaque);
 884 #endif
 885         return;
 886     }
 887
 888     vmsvga_size(s);
 889
 890     vmsvga_fifo_run(s);
 891     vmsvga_update_rect_flush(s);
 892
 893     /*
 894      * Is it more efficient to look at vram VGA-dirty bits or wait
 895      * for the driver to issue SVGA_CMD_UPDATE?
 896      */
 897     if (s->invalidated) {
 898         s->invalidated = 0;
 899         vmsvga_update_screen(s);
 900     }
 901 }
 902
 903 static void vmsvga_reset(struct vmsvga_state_s *s)
 904 {
 905     s->index = 0;
 906     s->enable = 0;
 907     s->config = 0;
 908     s->width = -1;
 909     s->height = -1;
 910     s->svgaid = SVGA_ID;
 911     s->depth = s->ds->depth ? s->ds->depth : 24;
 912     s->bypp = (s->depth + 7) >> 3;
 913     s->cursor.on = 0;
 914     s->redraw_fifo_first = 0;
 915     s->redraw_fifo_last = 0;
 916     switch (s->depth) {
 917     case 8:
 918         s->wred   = 0x00000007;
 919         s->wgreen = 0x00000038;
 920         s->wblue  = 0x000000c0;
 921         break;
 922     case 15:
 923         s->wred   = 0x0000001f;
 924         s->wgreen = 0x000003e0;
 925         s->wblue  = 0x00007c00;
 926         break;
 927     case 16:
 928         s->wred   = 0x0000001f;
 929         s->wgreen = 0x000007e0;
 930         s->wblue  = 0x0000f800;
 931         break;
 932     case 24:
 933         s->wred   = 0x00ff0000;
 934         s->wgreen = 0x0000ff00;
 935         s->wblue  = 0x000000ff;
 936         break;
 937     case 32:
 938         s->wred   = 0x00ff0000;
 939         s->wgreen = 0x0000ff00;
 940         s->wblue  = 0x000000ff;
 941         break;
 942     }
 943     s->syncing = 0;
 944 }
 945
 946 static void vmsvga_invalidate_display(void *opaque)
 947 {
 948     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 949     if (!s->enable) {
 950 #ifdef EMBED_STDVGA
 951         s->invalidate(opaque);
 952 #endif
 953         return;
 954     }
 955
 956     s->invalidated = 1;
 957 }
 958
 959 /* save the vga display in a PPM image even if no display is
 960    available */
 961 static void vmsvga_screen_dump(void *opaque, const char *filename)
 962 {
 963     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 964     if (!s->enable) {
 965 #ifdef EMBED_STDVGA
 966         s->screen_dump(opaque, filename);
 967 #endif
 968         return;
 969     }
 970
 971     if (s->depth == 32) {
 972         ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
 973     }
 974 }
 975
 976 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
 977 {
 978     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 979
 980     if (s->text_update)
 981         s->text_update(opaque, chardata);
 982 }
 983
 984 #ifdef DIRECT_VRAM
 985 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
 986 {
 987     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 988     addr -= s->vram_base;
 989     if (addr < s->fb_size)
 990         return *(uint8_t *) (s->ds->data + addr);
 991     else
 992         return *(uint8_t *) (s->vram + addr);
 993 }
 994
 995 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
 996 {
 997     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 998     addr -= s->vram_base;
 999     if (addr < s->fb_size)
1000         return *(uint16_t *) (s->ds->data + addr);
1001     else
1002         return *(uint16_t *) (s->vram + addr);
1003 }
1004
1005 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1006 {
1007     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1008     addr -= s->vram_base;
1009     if (addr < s->fb_size)
1010         return *(uint32_t *) (s->ds->data + addr);
1011     else
1012         return *(uint32_t *) (s->vram + addr);
1013 }
1014
1015 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1016                 uint32_t value)
1017 {
1018     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1019     addr -= s->vram_base;
1020     if (addr < s->fb_size)
1021         *(uint8_t *) (s->ds->data + addr) = value;
1022     else
1023         *(uint8_t *) (s->vram + addr) = value;
1024 }
1025
1026 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1027                 uint32_t value)
1028 {
1029     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1030     addr -= s->vram_base;
1031     if (addr < s->fb_size)
1032         *(uint16_t *) (s->ds->data + addr) = value;
1033     else
1034         *(uint16_t *) (s->vram + addr) = value;
1035 }
1036
1037 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1038                 uint32_t value)
1039 {
1040     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1041     addr -= s->vram_base;
1042     if (addr < s->fb_size)
1043         *(uint32_t *) (s->ds->data + addr) = value;
1044     else
1045         *(uint32_t *) (s->vram + addr) = value;
1046 }
1047
1048 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1049     vmsvga_vram_readb,
1050     vmsvga_vram_readw,
1051     vmsvga_vram_readl,
1052 };
1053
1054 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1055     vmsvga_vram_writeb,
1056     vmsvga_vram_writew,
1057     vmsvga_vram_writel,
1058 };
1059 #endif
1060
1061 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1062 {
1063     qemu_put_be32(f, s->depth);
1064     qemu_put_be32(f, s->enable);
1065     qemu_put_be32(f, s->config);
1066     qemu_put_be32(f, s->cursor.id);
1067     qemu_put_be32(f, s->cursor.x);
1068     qemu_put_be32(f, s->cursor.y);
1069     qemu_put_be32(f, s->cursor.on);
1070     qemu_put_be32(f, s->index);
1071     qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1072     qemu_put_be32(f, s->new_width);
1073     qemu_put_be32(f, s->new_height);
1074     qemu_put_be32s(f, &s->guest);
1075     qemu_put_be32s(f, &s->svgaid);
1076     qemu_put_be32(f, s->syncing);
1077     qemu_put_be32(f, s->fb_size);
1078 }
1079
1080 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1081 {
1082     int depth;
1083     depth=qemu_get_be32(f);
1084     s->enable=qemu_get_be32(f);
1085     s->config=qemu_get_be32(f);
1086     s->cursor.id=qemu_get_be32(f);
1087     s->cursor.x=qemu_get_be32(f);
1088     s->cursor.y=qemu_get_be32(f);
1089     s->cursor.on=qemu_get_be32(f);
1090     s->index=qemu_get_be32(f);
1091     qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1092     s->new_width=qemu_get_be32(f);
1093     s->new_height=qemu_get_be32(f);
1094     qemu_get_be32s(f, &s->guest);
1095     qemu_get_be32s(f, &s->svgaid);
1096     s->syncing=qemu_get_be32(f);
1097     s->fb_size=qemu_get_be32(f);
1098
1099     if (s->enable && depth != s->depth) {
1100         printf("%s: need colour depth of %i bits to resume operation.\n",
1101                         __FUNCTION__, depth);
1102         return -EINVAL;
1103     }
1104
1105     s->invalidated = 1;
1106     if (s->config)
1107         s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1108
1109     return 0;
1110 }
1111
1112 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1113                 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1114                 int vga_ram_size)
1115 {
1116     s->ds = ds;
1117     s->vram = vga_ram_base;
1118     s->vram_size = vga_ram_size;
1119     s->vram_offset = vga_ram_offset;
1120
1121     s->scratch_size = SVGA_SCRATCH_SIZE;
1122     s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1123
1124     vmsvga_reset(s);
1125
1126 #ifdef EMBED_STDVGA
1127     vga_common_init((VGAState *) s, ds,
1128                     vga_ram_base, vga_ram_offset, vga_ram_size);
1129     vga_init((VGAState *) s);
1130 #endif
1131
1132     s->console = graphic_console_init(ds, vmsvga_update_display,
1133                                       vmsvga_invalidate_display,
1134                                       vmsvga_screen_dump,
1135                                       vmsvga_text_update, s);
1136 }
1137
1138 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1139 {
1140     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1141     pci_device_save(&s->card, f);
1142     vmsvga_save(&s->chip, f);
1143 }
1144
1145 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1146 {
1147     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1148     int ret;
1149
1150     ret = pci_device_load(&s->card, f);
1151     if (ret < 0)
1152         return ret;
1153
1154     ret = vmsvga_load(&s->chip, f);
1155     if (ret < 0)
1156         return ret;
1157
1158     return 0;
1159 }
1160
1161 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1162                 uint32_t addr, uint32_t size, int type)
1163 {
1164     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1165     struct vmsvga_state_s *s = &d->chip;
1166
1167     register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1168                     1, 4, vmsvga_index_read, s);
1169     register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1170                     1, 4, vmsvga_index_write, s);
1171     register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1172                     1, 4, vmsvga_value_read, s);
1173     register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1174                     1, 4, vmsvga_value_write, s);
1175     register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1176                     1, 4, vmsvga_bios_read, s);
1177     register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1178                     1, 4, vmsvga_bios_write, s);
1179 }
1180
1181 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1182                 uint32_t addr, uint32_t size, int type)
1183 {
1184     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1185     struct vmsvga_state_s *s = &d->chip;
1186     int iomemtype;
1187
1188     s->vram_base = addr;
1189 #ifdef DIRECT_VRAM
1190     iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1191                     vmsvga_vram_write, s);
1192 #else
1193     iomemtype = s->vram_offset | IO_MEM_RAM;
1194 #endif
1195     cpu_register_physical_memory(s->vram_base, s->vram_size,
1196                     iomemtype);
1197 }
1198
1199 #define PCI_VENDOR_ID_VMWARE            0x15ad
1200 #define PCI_DEVICE_ID_VMWARE_SVGA2      0x0405
1201 #define PCI_DEVICE_ID_VMWARE_SVGA       0x0710
1202 #define PCI_DEVICE_ID_VMWARE_NET        0x0720
1203 #define PCI_DEVICE_ID_VMWARE_SCSI       0x0730
1204 #define PCI_DEVICE_ID_VMWARE_IDE        0x1729
1205 #define PCI_CLASS_BASE_DISPLAY          0x03
1206 #define PCI_CLASS_SUB_VGA               0x00
1207 #define PCI_CLASS_HEADERTYPE_00h        0x00
1208
1209 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1210                      unsigned long vga_ram_offset, int vga_ram_size)
1211 {
1212     struct pci_vmsvga_state_s *s;
1213
1214     /* Setup PCI configuration */
1215     s = (struct pci_vmsvga_state_s *)
1216         pci_register_device(bus, "QEMUware SVGA",
1217                 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1218     s->card.config[PCI_VENDOR_ID]       = PCI_VENDOR_ID_VMWARE & 0xff;
1219     s->card.config[PCI_VENDOR_ID + 1]   = PCI_VENDOR_ID_VMWARE >> 8;
1220     s->card.config[PCI_DEVICE_ID]       = SVGA_PCI_DEVICE_ID & 0xff;
1221     s->card.config[PCI_DEVICE_ID + 1]   = SVGA_PCI_DEVICE_ID >> 8;
1222     s->card.config[PCI_COMMAND]         = 0x07;         /* I/O + Memory */
1223     s->card.config[PCI_CLASS_DEVICE]    = PCI_CLASS_SUB_VGA;
1224     s->card.config[0x0b]                = PCI_CLASS_BASE_DISPLAY;
1225     s->card.config[0x0c]                = 0x08;         /* Cache line size */
1226     s->card.config[0x0d]                = 0x40;         /* Latency timer */
1227     s->card.config[0x0e]                = PCI_CLASS_HEADERTYPE_00h;
1228     s->card.config[0x2c]                = PCI_VENDOR_ID_VMWARE & 0xff;
1229     s->card.config[0x2d]                = PCI_VENDOR_ID_VMWARE >> 8;
1230     s->card.config[0x2e]                = SVGA_PCI_DEVICE_ID & 0xff;
1231     s->card.config[0x2f]                = SVGA_PCI_DEVICE_ID >> 8;
1232     s->card.config[0x3c]                = 0xff;         /* End */
1233
1234     pci_register_io_region(&s->card, 0, 0x10,
1235                     PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1236     pci_register_io_region(&s->card, 1, vga_ram_size,
1237                     PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1238
1239     vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1240
1241     register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1242 }