hw/cuda.c

   1 /*
   2  * QEMU PowerMac CUDA device support
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc_mac.h"
  27 #include "qemu-timer.h"
  28 #include "sysemu.h"
  29
  30 /* XXX: implement all timer modes */
  31
  32 /* debug CUDA */
  33 //#define DEBUG_CUDA
  34
  35 /* debug CUDA packets */
  36 //#define DEBUG_CUDA_PACKET
  37
  38 #ifdef DEBUG_CUDA
  39 #define CUDA_DPRINTF(fmt, args...) \
  40 do { printf("CUDA: " fmt , ##args); } while (0)
  41 #else
  42 #define CUDA_DPRINTF(fmt, args...)
  43 #endif
  44
  45 /* Bits in B data register: all active low */
  46 #define TREQ            0x08            /* Transfer request (input) */
  47 #define TACK            0x10            /* Transfer acknowledge (output) */
  48 #define TIP             0x20            /* Transfer in progress (output) */
  49
  50 /* Bits in ACR */
  51 #define SR_CTRL         0x1c            /* Shift register control bits */
  52 #define SR_EXT          0x0c            /* Shift on external clock */
  53 #define SR_OUT          0x10            /* Shift out if 1 */
  54
  55 /* Bits in IFR and IER */
  56 #define IER_SET         0x80            /* set bits in IER */
  57 #define IER_CLR         0               /* clear bits in IER */
  58 #define SR_INT          0x04            /* Shift register full/empty */
  59 #define T1_INT          0x40            /* Timer 1 interrupt */
  60 #define T2_INT          0x20            /* Timer 2 interrupt */
  61
  62 /* Bits in ACR */
  63 #define T1MODE          0xc0            /* Timer 1 mode */
  64 #define T1MODE_CONT     0x40            /*  continuous interrupts */
  65
  66 /* commands (1st byte) */
  67 #define ADB_PACKET      0
  68 #define CUDA_PACKET     1
  69 #define ERROR_PACKET    2
  70 #define TIMER_PACKET    3
  71 #define POWER_PACKET    4
  72 #define MACIIC_PACKET   5
  73 #define PMU_PACKET      6
  74
  75
  76 /* CUDA commands (2nd byte) */
  77 #define CUDA_WARM_START                 0x0
  78 #define CUDA_AUTOPOLL                   0x1
  79 #define CUDA_GET_6805_ADDR              0x2
  80 #define CUDA_GET_TIME                   0x3
  81 #define CUDA_GET_PRAM                   0x7
  82 #define CUDA_SET_6805_ADDR              0x8
  83 #define CUDA_SET_TIME                   0x9
  84 #define CUDA_POWERDOWN                  0xa
  85 #define CUDA_POWERUP_TIME               0xb
  86 #define CUDA_SET_PRAM                   0xc
  87 #define CUDA_MS_RESET                   0xd
  88 #define CUDA_SEND_DFAC                  0xe
  89 #define CUDA_BATTERY_SWAP_SENSE         0x10
  90 #define CUDA_RESET_SYSTEM               0x11
  91 #define CUDA_SET_IPL                    0x12
  92 #define CUDA_FILE_SERVER_FLAG           0x13
  93 #define CUDA_SET_AUTO_RATE              0x14
  94 #define CUDA_GET_AUTO_RATE              0x16
  95 #define CUDA_SET_DEVICE_LIST            0x19
  96 #define CUDA_GET_DEVICE_LIST            0x1a
  97 #define CUDA_SET_ONE_SECOND_MODE        0x1b
  98 #define CUDA_SET_POWER_MESSAGES         0x21
  99 #define CUDA_GET_SET_IIC                0x22
 100 #define CUDA_WAKEUP                     0x23
 101 #define CUDA_TIMER_TICKLE               0x24
 102 #define CUDA_COMBINED_FORMAT_IIC        0x25
 103
 104 #define CUDA_TIMER_FREQ (4700000 / 6)
 105 #define CUDA_ADB_POLL_FREQ 50
 106
 107 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
 108 #define RTC_OFFSET                      2082844800
 109
 110 typedef struct CUDATimer {
 111     int index;
 112     uint16_t latch;
 113     uint16_t counter_value; /* counter value at load time */
 114     int64_t load_time;
 115     int64_t next_irq_time;
 116     QEMUTimer *timer;
 117 } CUDATimer;
 118
 119 typedef struct CUDAState {
 120     /* cuda registers */
 121     uint8_t b;      /* B-side data */
 122     uint8_t a;      /* A-side data */
 123     uint8_t dirb;   /* B-side direction (1=output) */
 124     uint8_t dira;   /* A-side direction (1=output) */
 125     uint8_t sr;     /* Shift register */
 126     uint8_t acr;    /* Auxiliary control register */
 127     uint8_t pcr;    /* Peripheral control register */
 128     uint8_t ifr;    /* Interrupt flag register */
 129     uint8_t ier;    /* Interrupt enable register */
 130     uint8_t anh;    /* A-side data, no handshake */
 131
 132     CUDATimer timers[2];
 133
 134     uint8_t last_b; /* last value of B register */
 135     uint8_t last_acr; /* last value of B register */
 136
 137     int data_in_size;
 138     int data_in_index;
 139     int data_out_index;
 140
 141     qemu_irq irq;
 142     uint8_t autopoll;
 143     uint8_t data_in[128];
 144     uint8_t data_out[16];
 145     QEMUTimer *adb_poll_timer;
 146 } CUDAState;
 147
 148 static CUDAState cuda_state;
 149 ADBBusState adb_bus;
 150
 151 static void cuda_update(CUDAState *s);
 152 static void cuda_receive_packet_from_host(CUDAState *s,
 153                                           const uint8_t *data, int len);
 154 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 155                               int64_t current_time);
 156
 157 static void cuda_update_irq(CUDAState *s)
 158 {
 159     if (s->ifr & s->ier & (SR_INT | T1_INT)) {
 160         qemu_irq_raise(s->irq);
 161     } else {
 162         qemu_irq_lower(s->irq);
 163     }
 164 }
 165
 166 static unsigned int get_counter(CUDATimer *s)
 167 {
 168     int64_t d;
 169     unsigned int counter;
 170
 171     d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
 172                  CUDA_TIMER_FREQ, ticks_per_sec);
 173     if (s->index == 0) {
 174         /* the timer goes down from latch to -1 (period of latch + 2) */
 175         if (d <= (s->counter_value + 1)) {
 176             counter = (s->counter_value - d) & 0xffff;
 177         } else {
 178             counter = (d - (s->counter_value + 1)) % (s->latch + 2);
 179             counter = (s->latch - counter) & 0xffff;
 180         }
 181     } else {
 182         counter = (s->counter_value - d) & 0xffff;
 183     }
 184     return counter;
 185 }
 186
 187 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
 188 {
 189     CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
 190     ti->load_time = qemu_get_clock(vm_clock);
 191     ti->counter_value = val;
 192     cuda_timer_update(s, ti, ti->load_time);
 193 }
 194
 195 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
 196 {
 197     int64_t d, next_time;
 198     unsigned int counter;
 199
 200     /* current counter value */
 201     d = muldiv64(current_time - s->load_time,
 202                  CUDA_TIMER_FREQ, ticks_per_sec);
 203     /* the timer goes down from latch to -1 (period of latch + 2) */
 204     if (d <= (s->counter_value + 1)) {
 205         counter = (s->counter_value - d) & 0xffff;
 206     } else {
 207         counter = (d - (s->counter_value + 1)) % (s->latch + 2);
 208         counter = (s->latch - counter) & 0xffff;
 209     }
 210
 211     /* Note: we consider the irq is raised on 0 */
 212     if (counter == 0xffff) {
 213         next_time = d + s->latch + 1;
 214     } else if (counter == 0) {
 215         next_time = d + s->latch + 2;
 216     } else {
 217         next_time = d + counter;
 218     }
 219     CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
 220                  s->latch, d, next_time - d);
 221     next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
 222         s->load_time;
 223     if (next_time <= current_time)
 224         next_time = current_time + 1;
 225     return next_time;
 226 }
 227
 228 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 229                               int64_t current_time)
 230 {
 231     if (!ti->timer)
 232         return;
 233     if ((s->acr & T1MODE) != T1MODE_CONT) {
 234         qemu_del_timer(ti->timer);
 235     } else {
 236         ti->next_irq_time = get_next_irq_time(ti, current_time);
 237         qemu_mod_timer(ti->timer, ti->next_irq_time);
 238     }
 239 }
 240
 241 static void cuda_timer1(void *opaque)
 242 {
 243     CUDAState *s = opaque;
 244     CUDATimer *ti = &s->timers[0];
 245
 246     cuda_timer_update(s, ti, ti->next_irq_time);
 247     s->ifr |= T1_INT;
 248     cuda_update_irq(s);
 249 }
 250
 251 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
 252 {
 253     CUDAState *s = opaque;
 254     uint32_t val;
 255
 256     addr = (addr >> 9) & 0xf;
 257     switch(addr) {
 258     case 0:
 259         val = s->b;
 260         break;
 261     case 1:
 262         val = s->a;
 263         break;
 264     case 2:
 265         val = s->dirb;
 266         break;
 267     case 3:
 268         val = s->dira;
 269         break;
 270     case 4:
 271         val = get_counter(&s->timers[0]) & 0xff;
 272         s->ifr &= ~T1_INT;
 273         cuda_update_irq(s);
 274         break;
 275     case 5:
 276         val = get_counter(&s->timers[0]) >> 8;
 277         cuda_update_irq(s);
 278         break;
 279     case 6:
 280         val = s->timers[0].latch & 0xff;
 281         break;
 282     case 7:
 283         /* XXX: check this */
 284         val = (s->timers[0].latch >> 8) & 0xff;
 285         break;
 286     case 8:
 287         val = get_counter(&s->timers[1]) & 0xff;
 288         s->ifr &= ~T2_INT;
 289         break;
 290     case 9:
 291         val = get_counter(&s->timers[1]) >> 8;
 292         break;
 293     case 10:
 294         val = s->sr;
 295         s->ifr &= ~SR_INT;
 296         cuda_update_irq(s);
 297         break;
 298     case 11:
 299         val = s->acr;
 300         break;
 301     case 12:
 302         val = s->pcr;
 303         break;
 304     case 13:
 305         val = s->ifr;
 306         if (s->ifr & s->ier)
 307             val |= 0x80;
 308         break;
 309     case 14:
 310         val = s->ier | 0x80;
 311         break;
 312     default:
 313     case 15:
 314         val = s->anh;
 315         break;
 316     }
 317     if (addr != 13 || val != 0)
 318         CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
 319     return val;
 320 }
 321
 322 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 323 {
 324     CUDAState *s = opaque;
 325
 326     addr = (addr >> 9) & 0xf;
 327     CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
 328
 329     switch(addr) {
 330     case 0:
 331         s->b = val;
 332         cuda_update(s);
 333         break;
 334     case 1:
 335         s->a = val;
 336         break;
 337     case 2:
 338         s->dirb = val;
 339         break;
 340     case 3:
 341         s->dira = val;
 342         break;
 343     case 4:
 344         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 345         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 346         break;
 347     case 5:
 348         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 349         s->ifr &= ~T1_INT;
 350         set_counter(s, &s->timers[0], s->timers[0].latch);
 351         break;
 352     case 6:
 353         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 354         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 355         break;
 356     case 7:
 357         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 358         s->ifr &= ~T1_INT;
 359         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 360         break;
 361     case 8:
 362         s->timers[1].latch = val;
 363         set_counter(s, &s->timers[1], val);
 364         break;
 365     case 9:
 366         set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
 367         break;
 368     case 10:
 369         s->sr = val;
 370         break;
 371     case 11:
 372         s->acr = val;
 373         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 374         cuda_update(s);
 375         break;
 376     case 12:
 377         s->pcr = val;
 378         break;
 379     case 13:
 380         /* reset bits */
 381         s->ifr &= ~val;
 382         cuda_update_irq(s);
 383         break;
 384     case 14:
 385         if (val & IER_SET) {
 386             /* set bits */
 387             s->ier |= val & 0x7f;
 388         } else {
 389             /* reset bits */
 390             s->ier &= ~val;
 391         }
 392         cuda_update_irq(s);
 393         break;
 394     default:
 395     case 15:
 396         s->anh = val;
 397         break;
 398     }
 399 }
 400
 401 /* NOTE: TIP and TREQ are negated */
 402 static void cuda_update(CUDAState *s)
 403 {
 404     int packet_received, len;
 405
 406     packet_received = 0;
 407     if (!(s->b & TIP)) {
 408         /* transfer requested from host */
 409
 410         if (s->acr & SR_OUT) {
 411             /* data output */
 412             if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 413                 if (s->data_out_index < sizeof(s->data_out)) {
 414                     CUDA_DPRINTF("send: %02x\n", s->sr);
 415                     s->data_out[s->data_out_index++] = s->sr;
 416                     s->ifr |= SR_INT;
 417                     cuda_update_irq(s);
 418                 }
 419             }
 420         } else {
 421             if (s->data_in_index < s->data_in_size) {
 422                 /* data input */
 423                 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 424                     s->sr = s->data_in[s->data_in_index++];
 425                     CUDA_DPRINTF("recv: %02x\n", s->sr);
 426                     /* indicate end of transfer */
 427                     if (s->data_in_index >= s->data_in_size) {
 428                         s->b = (s->b | TREQ);
 429                     }
 430                     s->ifr |= SR_INT;
 431                     cuda_update_irq(s);
 432                 }
 433             }
 434         }
 435     } else {
 436         /* no transfer requested: handle sync case */
 437         if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
 438             /* update TREQ state each time TACK change state */
 439             if (s->b & TACK)
 440                 s->b = (s->b | TREQ);
 441             else
 442                 s->b = (s->b & ~TREQ);
 443             s->ifr |= SR_INT;
 444             cuda_update_irq(s);
 445         } else {
 446             if (!(s->last_b & TIP)) {
 447                 /* handle end of host to cuda transfer */
 448                 packet_received = (s->data_out_index > 0);
 449                 /* always an IRQ at the end of transfer */
 450                 s->ifr |= SR_INT;
 451                 cuda_update_irq(s);
 452             }
 453             /* signal if there is data to read */
 454             if (s->data_in_index < s->data_in_size) {
 455                 s->b = (s->b & ~TREQ);
 456             }
 457         }
 458     }
 459
 460     s->last_acr = s->acr;
 461     s->last_b = s->b;
 462
 463     /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
 464        recursively */
 465     if (packet_received) {
 466         len = s->data_out_index;
 467         s->data_out_index = 0;
 468         cuda_receive_packet_from_host(s, s->data_out, len);
 469     }
 470 }
 471
 472 static void cuda_send_packet_to_host(CUDAState *s,
 473                                      const uint8_t *data, int len)
 474 {
 475 #ifdef DEBUG_CUDA_PACKET
 476     {
 477         int i;
 478         printf("cuda_send_packet_to_host:\n");
 479         for(i = 0; i < len; i++)
 480             printf(" %02x", data[i]);
 481         printf("\n");
 482     }
 483 #endif
 484     memcpy(s->data_in, data, len);
 485     s->data_in_size = len;
 486     s->data_in_index = 0;
 487     cuda_update(s);
 488     s->ifr |= SR_INT;
 489     cuda_update_irq(s);
 490 }
 491
 492 static void cuda_adb_poll(void *opaque)
 493 {
 494     CUDAState *s = opaque;
 495     uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 496     int olen;
 497
 498     olen = adb_poll(&adb_bus, obuf + 2);
 499     if (olen > 0) {
 500         obuf[0] = ADB_PACKET;
 501         obuf[1] = 0x40; /* polled data */
 502         cuda_send_packet_to_host(s, obuf, olen + 2);
 503     }
 504     qemu_mod_timer(s->adb_poll_timer,
 505                    qemu_get_clock(vm_clock) +
 506                    (ticks_per_sec / CUDA_ADB_POLL_FREQ));
 507 }
 508
 509 static void cuda_receive_packet(CUDAState *s,
 510                                 const uint8_t *data, int len)
 511 {
 512     uint8_t obuf[16];
 513     int ti, autopoll;
 514
 515     switch(data[0]) {
 516     case CUDA_AUTOPOLL:
 517         autopoll = (data[1] != 0);
 518         if (autopoll != s->autopoll) {
 519             s->autopoll = autopoll;
 520             if (autopoll) {
 521                 qemu_mod_timer(s->adb_poll_timer,
 522                                qemu_get_clock(vm_clock) +
 523                                (ticks_per_sec / CUDA_ADB_POLL_FREQ));
 524             } else {
 525                 qemu_del_timer(s->adb_poll_timer);
 526             }
 527         }
 528         obuf[0] = CUDA_PACKET;
 529         obuf[1] = data[1];
 530         cuda_send_packet_to_host(s, obuf, 2);
 531         break;
 532     case CUDA_GET_TIME:
 533     case CUDA_SET_TIME:
 534         /* XXX: add time support ? */
 535         ti = time(NULL) + RTC_OFFSET;
 536         obuf[0] = CUDA_PACKET;
 537         obuf[1] = 0;
 538         obuf[2] = 0;
 539         obuf[3] = ti >> 24;
 540         obuf[4] = ti >> 16;
 541         obuf[5] = ti >> 8;
 542         obuf[6] = ti;
 543         cuda_send_packet_to_host(s, obuf, 7);
 544         break;
 545     case CUDA_FILE_SERVER_FLAG:
 546     case CUDA_SET_DEVICE_LIST:
 547     case CUDA_SET_AUTO_RATE:
 548     case CUDA_SET_POWER_MESSAGES:
 549         obuf[0] = CUDA_PACKET;
 550         obuf[1] = 0;
 551         cuda_send_packet_to_host(s, obuf, 2);
 552         break;
 553     case CUDA_POWERDOWN:
 554         obuf[0] = CUDA_PACKET;
 555         obuf[1] = 0;
 556         cuda_send_packet_to_host(s, obuf, 2);
 557         qemu_system_shutdown_request();
 558         break;
 559     case CUDA_RESET_SYSTEM:
 560         obuf[0] = CUDA_PACKET;
 561         obuf[1] = 0;
 562         cuda_send_packet_to_host(s, obuf, 2);
 563         qemu_system_reset_request();
 564         break;
 565     default:
 566         break;
 567     }
 568 }
 569
 570 static void cuda_receive_packet_from_host(CUDAState *s,
 571                                           const uint8_t *data, int len)
 572 {
 573 #ifdef DEBUG_CUDA_PACKET
 574     {
 575         int i;
 576         printf("cuda_receive_packet_from_host:\n");
 577         for(i = 0; i < len; i++)
 578             printf(" %02x", data[i]);
 579         printf("\n");
 580     }
 581 #endif
 582     switch(data[0]) {
 583     case ADB_PACKET:
 584         {
 585             uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 586             int olen;
 587             olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
 588             if (olen > 0) {
 589                 obuf[0] = ADB_PACKET;
 590                 obuf[1] = 0x00;
 591             } else {
 592                 /* error */
 593                 obuf[0] = ADB_PACKET;
 594                 obuf[1] = -olen;
 595                 olen = 0;
 596             }
 597             cuda_send_packet_to_host(s, obuf, olen + 2);
 598         }
 599         break;
 600     case CUDA_PACKET:
 601         cuda_receive_packet(s, data + 1, len - 1);
 602         break;
 603     }
 604 }
 605
 606 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 607 {
 608 }
 609
 610 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 611 {
 612 }
 613
 614 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
 615 {
 616     return 0;
 617 }
 618
 619 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
 620 {
 621     return 0;
 622 }
 623
 624 static CPUWriteMemoryFunc *cuda_write[] = {
 625     &cuda_writeb,
 626     &cuda_writew,
 627     &cuda_writel,
 628 };
 629
 630 static CPUReadMemoryFunc *cuda_read[] = {
 631     &cuda_readb,
 632     &cuda_readw,
 633     &cuda_readl,
 634 };
 635
 636 static void cuda_save_timer(QEMUFile *f, CUDATimer *s)
 637 {
 638     qemu_put_be16s(f, &s->latch);
 639     qemu_put_be16s(f, &s->counter_value);
 640     qemu_put_sbe64s(f, &s->load_time);
 641     qemu_put_sbe64s(f, &s->next_irq_time);
 642     if (s->timer)
 643         qemu_put_timer(f, s->timer);
 644 }
 645
 646 static void cuda_save(QEMUFile *f, void *opaque)
 647 {
 648     CUDAState *s = (CUDAState *)opaque;
 649
 650     qemu_put_ubyte(f, s->b);
 651     qemu_put_ubyte(f, s->a);
 652     qemu_put_ubyte(f, s->dirb);
 653     qemu_put_ubyte(f, s->dira);
 654     qemu_put_ubyte(f, s->sr);
 655     qemu_put_ubyte(f, s->acr);
 656     qemu_put_ubyte(f, s->pcr);
 657     qemu_put_ubyte(f, s->ifr);
 658     qemu_put_ubyte(f, s->ier);
 659     qemu_put_ubyte(f, s->anh);
 660     qemu_put_sbe32s(f, &s->data_in_size);
 661     qemu_put_sbe32s(f, &s->data_in_index);
 662     qemu_put_sbe32s(f, &s->data_out_index);
 663     qemu_put_ubyte(f, s->autopoll);
 664     qemu_put_buffer(f, s->data_in, sizeof(s->data_in));
 665     qemu_put_buffer(f, s->data_out, sizeof(s->data_out));
 666     cuda_save_timer(f, &s->timers[0]);
 667     cuda_save_timer(f, &s->timers[1]);
 668 }
 669
 670 static void cuda_load_timer(QEMUFile *f, CUDATimer *s)
 671 {
 672     qemu_get_be16s(f, &s->latch);
 673     qemu_get_be16s(f, &s->counter_value);
 674     qemu_get_sbe64s(f, &s->load_time);
 675     qemu_get_sbe64s(f, &s->next_irq_time);
 676     if (s->timer)
 677         qemu_get_timer(f, s->timer);
 678 }
 679
 680 static int cuda_load(QEMUFile *f, void *opaque, int version_id)
 681 {
 682     CUDAState *s = (CUDAState *)opaque;
 683
 684     if (version_id != 1)
 685         return -EINVAL;
 686
 687     s->b = qemu_get_ubyte(f);
 688     s->a = qemu_get_ubyte(f);
 689     s->dirb = qemu_get_ubyte(f);
 690     s->dira = qemu_get_ubyte(f);
 691     s->sr = qemu_get_ubyte(f);
 692     s->acr = qemu_get_ubyte(f);
 693     s->pcr = qemu_get_ubyte(f);
 694     s->ifr = qemu_get_ubyte(f);
 695     s->ier = qemu_get_ubyte(f);
 696     s->anh = qemu_get_ubyte(f);
 697     qemu_get_sbe32s(f, &s->data_in_size);
 698     qemu_get_sbe32s(f, &s->data_in_index);
 699     qemu_get_sbe32s(f, &s->data_out_index);
 700     s->autopoll = qemu_get_ubyte(f);
 701     qemu_get_buffer(f, s->data_in, sizeof(s->data_in));
 702     qemu_get_buffer(f, s->data_out, sizeof(s->data_out));
 703     cuda_load_timer(f, &s->timers[0]);
 704     cuda_load_timer(f, &s->timers[1]);
 705
 706     return 0;
 707 }
 708
 709 static void cuda_reset(void *opaque)
 710 {
 711     CUDAState *s = opaque;
 712
 713     s->b = 0;
 714     s->a = 0;
 715     s->dirb = 0;
 716     s->dira = 0;
 717     s->sr = 0;
 718     s->acr = 0;
 719     s->pcr = 0;
 720     s->ifr = 0;
 721     s->ier = 0;
 722     //    s->ier = T1_INT | SR_INT;
 723     s->anh = 0;
 724     s->data_in_size = 0;
 725     s->data_in_index = 0;
 726     s->data_out_index = 0;
 727     s->autopoll = 0;
 728
 729     s->timers[0].latch = 0xffff;
 730     set_counter(s, &s->timers[0], 0xffff);
 731
 732     s->timers[1].latch = 0;
 733     set_counter(s, &s->timers[1], 0xffff);
 734 }
 735
 736 void cuda_init (int *cuda_mem_index, qemu_irq irq)
 737 {
 738     CUDAState *s = &cuda_state;
 739
 740     s->irq = irq;
 741
 742     s->timers[0].index = 0;
 743     s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
 744
 745     s->timers[1].index = 1;
 746
 747     s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
 748     *cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
 749     register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
 750     qemu_register_reset(cuda_reset, s);
 751     cuda_reset(s);
 752 }