2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
33 void helper_raise_exception_err (uint32_t exception
, uint32_t error_code
)
36 printf("Raise exception %3x code : %d\n", exception
, error_code
);
38 env
->exception_index
= exception
;
39 env
->error_code
= error_code
;
43 void helper_raise_exception (uint32_t exception
)
45 helper_raise_exception_err(exception
, 0);
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong
helper_load_cr (void)
52 return (env
->crf
[0] << 28) |
62 void helper_store_cr (target_ulong val
, uint32_t mask
)
66 for (i
= 0, sh
= 7; i
< 8; i
++, sh
--) {
68 env
->crf
[i
] = (val
>> (sh
* 4)) & 0xFUL
;
72 /*****************************************************************************/
74 void helper_load_dump_spr (uint32_t sprn
)
77 fprintf(logfile
, "Read SPR %d %03x => " ADDRX
"\n",
78 sprn
, sprn
, env
->spr
[sprn
]);
82 void helper_store_dump_spr (uint32_t sprn
)
85 fprintf(logfile
, "Write SPR %d %03x <= " ADDRX
"\n",
86 sprn
, sprn
, env
->spr
[sprn
]);
90 target_ulong
helper_load_tbl (void)
92 return cpu_ppc_load_tbl(env
);
95 target_ulong
helper_load_tbu (void)
97 return cpu_ppc_load_tbu(env
);
100 target_ulong
helper_load_atbl (void)
102 return cpu_ppc_load_atbl(env
);
105 target_ulong
helper_load_atbu (void)
107 return cpu_ppc_load_atbu(env
);
110 target_ulong
helper_load_601_rtcl (void)
112 return cpu_ppc601_load_rtcl(env
);
115 target_ulong
helper_load_601_rtcu (void)
117 return cpu_ppc601_load_rtcu(env
);
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val
)
124 ppc_store_asr(env
, val
);
128 void helper_store_sdr1 (target_ulong val
)
130 ppc_store_sdr1(env
, val
);
133 void helper_store_tbl (target_ulong val
)
135 cpu_ppc_store_tbl(env
, val
);
138 void helper_store_tbu (target_ulong val
)
140 cpu_ppc_store_tbu(env
, val
);
143 void helper_store_atbl (target_ulong val
)
145 cpu_ppc_store_atbl(env
, val
);
148 void helper_store_atbu (target_ulong val
)
150 cpu_ppc_store_atbu(env
, val
);
153 void helper_store_601_rtcl (target_ulong val
)
155 cpu_ppc601_store_rtcl(env
, val
);
158 void helper_store_601_rtcu (target_ulong val
)
160 cpu_ppc601_store_rtcu(env
, val
);
163 target_ulong
helper_load_decr (void)
165 return cpu_ppc_load_decr(env
);
168 void helper_store_decr (target_ulong val
)
170 cpu_ppc_store_decr(env
, val
);
173 void helper_store_hid0_601 (target_ulong val
)
177 hid0
= env
->spr
[SPR_HID0
];
178 if ((val
^ hid0
) & 0x00000008) {
179 /* Change current endianness */
180 env
->hflags
&= ~(1 << MSR_LE
);
181 env
->hflags_nmsr
&= ~(1 << MSR_LE
);
182 env
->hflags_nmsr
|= (1 << MSR_LE
) & (((val
>> 3) & 1) << MSR_LE
);
183 env
->hflags
|= env
->hflags_nmsr
;
185 fprintf(logfile
, "%s: set endianness to %c => " ADDRX
"\n",
186 __func__
, val
& 0x8 ? 'l' : 'b', env
->hflags
);
189 env
->spr
[SPR_HID0
] = (uint32_t)val
;
192 void helper_store_403_pbr (uint32_t num
, target_ulong value
)
194 if (likely(env
->pb
[num
] != value
)) {
195 env
->pb
[num
] = value
;
196 /* Should be optimized */
201 target_ulong
helper_load_40x_pit (void)
203 return load_40x_pit(env
);
206 void helper_store_40x_pit (target_ulong val
)
208 store_40x_pit(env
, val
);
211 void helper_store_40x_dbcr0 (target_ulong val
)
213 store_40x_dbcr0(env
, val
);
216 void helper_store_40x_sler (target_ulong val
)
218 store_40x_sler(env
, val
);
221 void helper_store_booke_tcr (target_ulong val
)
223 store_booke_tcr(env
, val
);
226 void helper_store_booke_tsr (target_ulong val
)
228 store_booke_tsr(env
, val
);
231 void helper_store_ibatu (uint32_t nr
, target_ulong val
)
233 ppc_store_ibatu(env
, nr
, val
);
236 void helper_store_ibatl (uint32_t nr
, target_ulong val
)
238 ppc_store_ibatl(env
, nr
, val
);
241 void helper_store_dbatu (uint32_t nr
, target_ulong val
)
243 ppc_store_dbatu(env
, nr
, val
);
246 void helper_store_dbatl (uint32_t nr
, target_ulong val
)
248 ppc_store_dbatl(env
, nr
, val
);
251 void helper_store_601_batl (uint32_t nr
, target_ulong val
)
253 ppc_store_ibatl_601(env
, nr
, val
);
256 void helper_store_601_batu (uint32_t nr
, target_ulong val
)
258 ppc_store_ibatu_601(env
, nr
, val
);
262 /*****************************************************************************/
263 /* Memory load and stores */
265 static always_inline target_ulong
addr_add(target_ulong addr
, target_long arg
)
267 #if defined(TARGET_PPC64)
269 return (uint32_t)(addr
+ arg
);
275 void helper_lmw (target_ulong addr
, uint32_t reg
)
277 for (; reg
< 32; reg
++) {
279 env
->gpr
[reg
] = bswap32(ldl(addr
));
281 env
->gpr
[reg
] = ldl(addr
);
282 addr
= addr_add(addr
, 4);
286 void helper_stmw (target_ulong addr
, uint32_t reg
)
288 for (; reg
< 32; reg
++) {
290 stl(addr
, bswap32((uint32_t)env
->gpr
[reg
]));
292 stl(addr
, (uint32_t)env
->gpr
[reg
]);
293 addr
= addr_add(addr
, 4);
297 void helper_lsw(target_ulong addr
, uint32_t nb
, uint32_t reg
)
300 for (; nb
> 3; nb
-= 4) {
301 env
->gpr
[reg
] = ldl(addr
);
302 reg
= (reg
+ 1) % 32;
303 addr
= addr_add(addr
, 4);
305 if (unlikely(nb
> 0)) {
307 for (sh
= 24; nb
> 0; nb
--, sh
-= 8) {
308 env
->gpr
[reg
] |= ldub(addr
) << sh
;
309 addr
= addr_add(addr
, 1);
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
318 void helper_lswx(target_ulong addr
, uint32_t reg
, uint32_t ra
, uint32_t rb
)
320 if (likely(xer_bc
!= 0)) {
321 if (unlikely((ra
!= 0 && reg
< ra
&& (reg
+ xer_bc
) > ra
) ||
322 (reg
< rb
&& (reg
+ xer_bc
) > rb
))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
325 POWERPC_EXCP_INVAL_LSWX
);
327 helper_lsw(addr
, xer_bc
, reg
);
332 void helper_stsw(target_ulong addr
, uint32_t nb
, uint32_t reg
)
335 for (; nb
> 3; nb
-= 4) {
336 stl(addr
, env
->gpr
[reg
]);
337 reg
= (reg
+ 1) % 32;
338 addr
= addr_add(addr
, 4);
340 if (unlikely(nb
> 0)) {
341 for (sh
= 24; nb
> 0; nb
--, sh
-= 8) {
342 stb(addr
, (env
->gpr
[reg
] >> sh
) & 0xFF);
343 addr
= addr_add(addr
, 1);
348 static void do_dcbz(target_ulong addr
, int dcache_line_size
)
350 addr
&= ~(dcache_line_size
- 1);
352 for (i
= 0 ; i
< dcache_line_size
; i
+= 4) {
355 if (env
->reserve
== addr
)
356 env
->reserve
= (target_ulong
)-1ULL;
359 void helper_dcbz(target_ulong addr
)
361 do_dcbz(addr
, env
->dcache_line_size
);
364 void helper_dcbz_970(target_ulong addr
)
366 if (((env
->spr
[SPR_970_HID5
] >> 7) & 0x3) == 1)
369 do_dcbz(addr
, env
->dcache_line_size
);
372 void helper_icbi(target_ulong addr
)
376 addr
&= ~(env
->dcache_line_size
- 1);
377 /* Invalidate one cache line :
378 * PowerPC specification says this is to be treated like a load
379 * (not a fetch) by the MMU. To be sure it will be so,
380 * do the load "by hand".
383 tb_invalidate_page_range(addr
, addr
+ env
->icache_line_size
);
387 target_ulong
helper_lscbx (target_ulong addr
, uint32_t reg
, uint32_t ra
, uint32_t rb
)
391 for (i
= 0; i
< xer_bc
; i
++) {
393 addr
= addr_add(addr
, 1);
394 /* ra (if not 0) and rb are never modified */
395 if (likely(reg
!= rb
&& (ra
== 0 || reg
!= ra
))) {
396 env
->gpr
[reg
] = (env
->gpr
[reg
] & ~(0xFF << d
)) | (c
<< d
);
398 if (unlikely(c
== xer_cmp
))
400 if (likely(d
!= 0)) {
411 /*****************************************************************************/
412 /* Fixed point operations helpers */
413 #if defined(TARGET_PPC64)
415 /* multiply high word */
416 uint64_t helper_mulhd (uint64_t arg1
, uint64_t arg2
)
420 muls64(&tl
, &th
, arg1
, arg2
);
424 /* multiply high word unsigned */
425 uint64_t helper_mulhdu (uint64_t arg1
, uint64_t arg2
)
429 mulu64(&tl
, &th
, arg1
, arg2
);
433 uint64_t helper_mulldo (uint64_t arg1
, uint64_t arg2
)
438 muls64(&tl
, (uint64_t *)&th
, arg1
, arg2
);
439 /* If th != 0 && th != -1, then we had an overflow */
440 if (likely((uint64_t)(th
+ 1) <= 1)) {
441 env
->xer
&= ~(1 << XER_OV
);
443 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
449 target_ulong
helper_cntlzw (target_ulong t
)
454 #if defined(TARGET_PPC64)
455 target_ulong
helper_cntlzd (target_ulong t
)
461 /* shift right arithmetic helper */
462 target_ulong
helper_sraw (target_ulong value
, target_ulong shift
)
466 if (likely(!(shift
& 0x20))) {
467 if (likely((uint32_t)shift
!= 0)) {
469 ret
= (int32_t)value
>> shift
;
470 if (likely(ret
>= 0 || (value
& ((1 << shift
) - 1)) == 0)) {
471 env
->xer
&= ~(1 << XER_CA
);
473 env
->xer
|= (1 << XER_CA
);
476 ret
= (int32_t)value
;
477 env
->xer
&= ~(1 << XER_CA
);
480 ret
= (int32_t)value
>> 31;
482 env
->xer
|= (1 << XER_CA
);
484 env
->xer
&= ~(1 << XER_CA
);
487 return (target_long
)ret
;
490 #if defined(TARGET_PPC64)
491 target_ulong
helper_srad (target_ulong value
, target_ulong shift
)
495 if (likely(!(shift
& 0x40))) {
496 if (likely((uint64_t)shift
!= 0)) {
498 ret
= (int64_t)value
>> shift
;
499 if (likely(ret
>= 0 || (value
& ((1 << shift
) - 1)) == 0)) {
500 env
->xer
&= ~(1 << XER_CA
);
502 env
->xer
|= (1 << XER_CA
);
505 ret
= (int64_t)value
;
506 env
->xer
&= ~(1 << XER_CA
);
509 ret
= (int64_t)value
>> 63;
511 env
->xer
|= (1 << XER_CA
);
513 env
->xer
&= ~(1 << XER_CA
);
520 target_ulong
helper_popcntb (target_ulong val
)
522 val
= (val
& 0x55555555) + ((val
>> 1) & 0x55555555);
523 val
= (val
& 0x33333333) + ((val
>> 2) & 0x33333333);
524 val
= (val
& 0x0f0f0f0f) + ((val
>> 4) & 0x0f0f0f0f);
528 #if defined(TARGET_PPC64)
529 target_ulong
helper_popcntb_64 (target_ulong val
)
531 val
= (val
& 0x5555555555555555ULL
) + ((val
>> 1) & 0x5555555555555555ULL
);
532 val
= (val
& 0x3333333333333333ULL
) + ((val
>> 2) & 0x3333333333333333ULL
);
533 val
= (val
& 0x0f0f0f0f0f0f0f0fULL
) + ((val
>> 4) & 0x0f0f0f0f0f0f0f0fULL
);
538 /*****************************************************************************/
539 /* Floating point operations helpers */
540 uint64_t helper_float32_to_float64(uint32_t arg
)
545 d
.d
= float32_to_float64(f
.f
, &env
->fp_status
);
549 uint32_t helper_float64_to_float32(uint64_t arg
)
554 f
.f
= float64_to_float32(d
.d
, &env
->fp_status
);
558 static always_inline
int isden (float64 d
)
564 return ((u
.ll
>> 52) & 0x7FF) == 0;
567 uint32_t helper_compute_fprf (uint64_t arg
, uint32_t set_fprf
)
573 isneg
= float64_is_neg(farg
.d
);
574 if (unlikely(float64_is_nan(farg
.d
))) {
575 if (float64_is_signaling_nan(farg
.d
)) {
576 /* Signaling NaN: flags are undefined */
582 } else if (unlikely(float64_is_infinity(farg
.d
))) {
589 if (float64_is_zero(farg
.d
)) {
597 /* Denormalized numbers */
600 /* Normalized numbers */
611 /* We update FPSCR_FPRF */
612 env
->fpscr
&= ~(0x1F << FPSCR_FPRF
);
613 env
->fpscr
|= ret
<< FPSCR_FPRF
;
615 /* We just need fpcc to update Rc1 */
619 /* Floating-point invalid operations exception */
620 static always_inline
uint64_t fload_invalid_op_excp (int op
)
627 case POWERPC_EXCP_FP_VXSNAN
:
628 env
->fpscr
|= 1 << FPSCR_VXSNAN
;
630 case POWERPC_EXCP_FP_VXSOFT
:
631 env
->fpscr
|= 1 << FPSCR_VXSOFT
;
633 case POWERPC_EXCP_FP_VXISI
:
634 /* Magnitude subtraction of infinities */
635 env
->fpscr
|= 1 << FPSCR_VXISI
;
637 case POWERPC_EXCP_FP_VXIDI
:
638 /* Division of infinity by infinity */
639 env
->fpscr
|= 1 << FPSCR_VXIDI
;
641 case POWERPC_EXCP_FP_VXZDZ
:
642 /* Division of zero by zero */
643 env
->fpscr
|= 1 << FPSCR_VXZDZ
;
645 case POWERPC_EXCP_FP_VXIMZ
:
646 /* Multiplication of zero by infinity */
647 env
->fpscr
|= 1 << FPSCR_VXIMZ
;
649 case POWERPC_EXCP_FP_VXVC
:
650 /* Ordered comparison of NaN */
651 env
->fpscr
|= 1 << FPSCR_VXVC
;
652 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
653 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
654 /* We must update the target FPR before raising the exception */
656 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
657 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_VXVC
;
658 /* Update the floating-point enabled exception summary */
659 env
->fpscr
|= 1 << FPSCR_FEX
;
660 /* Exception is differed */
664 case POWERPC_EXCP_FP_VXSQRT
:
665 /* Square root of a negative number */
666 env
->fpscr
|= 1 << FPSCR_VXSQRT
;
668 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
670 /* Set the result to quiet NaN */
671 ret
= 0xFFF8000000000000ULL
;
672 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
673 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
676 case POWERPC_EXCP_FP_VXCVI
:
677 /* Invalid conversion */
678 env
->fpscr
|= 1 << FPSCR_VXCVI
;
679 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
681 /* Set the result to quiet NaN */
682 ret
= 0xFFF8000000000000ULL
;
683 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
684 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
688 /* Update the floating-point invalid operation summary */
689 env
->fpscr
|= 1 << FPSCR_VX
;
690 /* Update the floating-point exception summary */
691 env
->fpscr
|= 1 << FPSCR_FX
;
693 /* Update the floating-point enabled exception summary */
694 env
->fpscr
|= 1 << FPSCR_FEX
;
695 if (msr_fe0
!= 0 || msr_fe1
!= 0)
696 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_FP
| op
);
701 static always_inline
void float_zero_divide_excp (void)
703 env
->fpscr
|= 1 << FPSCR_ZX
;
704 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
705 /* Update the floating-point exception summary */
706 env
->fpscr
|= 1 << FPSCR_FX
;
708 /* Update the floating-point enabled exception summary */
709 env
->fpscr
|= 1 << FPSCR_FEX
;
710 if (msr_fe0
!= 0 || msr_fe1
!= 0) {
711 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
712 POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
);
717 static always_inline
void float_overflow_excp (void)
719 env
->fpscr
|= 1 << FPSCR_OX
;
720 /* Update the floating-point exception summary */
721 env
->fpscr
|= 1 << FPSCR_FX
;
723 /* XXX: should adjust the result */
724 /* Update the floating-point enabled exception summary */
725 env
->fpscr
|= 1 << FPSCR_FEX
;
726 /* We must update the target FPR before raising the exception */
727 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
728 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
730 env
->fpscr
|= 1 << FPSCR_XX
;
731 env
->fpscr
|= 1 << FPSCR_FI
;
735 static always_inline
void float_underflow_excp (void)
737 env
->fpscr
|= 1 << FPSCR_UX
;
738 /* Update the floating-point exception summary */
739 env
->fpscr
|= 1 << FPSCR_FX
;
741 /* XXX: should adjust the result */
742 /* Update the floating-point enabled exception summary */
743 env
->fpscr
|= 1 << FPSCR_FEX
;
744 /* We must update the target FPR before raising the exception */
745 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
746 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
750 static always_inline
void float_inexact_excp (void)
752 env
->fpscr
|= 1 << FPSCR_XX
;
753 /* Update the floating-point exception summary */
754 env
->fpscr
|= 1 << FPSCR_FX
;
756 /* Update the floating-point enabled exception summary */
757 env
->fpscr
|= 1 << FPSCR_FEX
;
758 /* We must update the target FPR before raising the exception */
759 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
760 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
764 static always_inline
void fpscr_set_rounding_mode (void)
768 /* Set rounding mode */
771 /* Best approximation (round to nearest) */
772 rnd_type
= float_round_nearest_even
;
775 /* Smaller magnitude (round toward zero) */
776 rnd_type
= float_round_to_zero
;
779 /* Round toward +infinite */
780 rnd_type
= float_round_up
;
784 /* Round toward -infinite */
785 rnd_type
= float_round_down
;
788 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
791 void helper_fpscr_clrbit (uint32_t bit
)
795 prev
= (env
->fpscr
>> bit
) & 1;
796 env
->fpscr
&= ~(1 << bit
);
801 fpscr_set_rounding_mode();
809 void helper_fpscr_setbit (uint32_t bit
)
813 prev
= (env
->fpscr
>> bit
) & 1;
814 env
->fpscr
|= 1 << bit
;
818 env
->fpscr
|= 1 << FPSCR_FX
;
822 env
->fpscr
|= 1 << FPSCR_FX
;
827 env
->fpscr
|= 1 << FPSCR_FX
;
832 env
->fpscr
|= 1 << FPSCR_FX
;
837 env
->fpscr
|= 1 << FPSCR_FX
;
850 env
->fpscr
|= 1 << FPSCR_VX
;
851 env
->fpscr
|= 1 << FPSCR_FX
;
858 env
->error_code
= POWERPC_EXCP_FP
;
860 env
->error_code
|= POWERPC_EXCP_FP_VXSNAN
;
862 env
->error_code
|= POWERPC_EXCP_FP_VXISI
;
864 env
->error_code
|= POWERPC_EXCP_FP_VXIDI
;
866 env
->error_code
|= POWERPC_EXCP_FP_VXZDZ
;
868 env
->error_code
|= POWERPC_EXCP_FP_VXIMZ
;
870 env
->error_code
|= POWERPC_EXCP_FP_VXVC
;
872 env
->error_code
|= POWERPC_EXCP_FP_VXSOFT
;
874 env
->error_code
|= POWERPC_EXCP_FP_VXSQRT
;
876 env
->error_code
|= POWERPC_EXCP_FP_VXCVI
;
883 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
890 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
897 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
;
904 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
910 fpscr_set_rounding_mode();
915 /* Update the floating-point enabled exception summary */
916 env
->fpscr
|= 1 << FPSCR_FEX
;
917 /* We have to update Rc1 before raising the exception */
918 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
924 void helper_store_fpscr (uint64_t arg
, uint32_t mask
)
927 * We use only the 32 LSB of the incoming fpr
935 new |= prev
& 0x60000000;
936 for (i
= 0; i
< 8; i
++) {
937 if (mask
& (1 << i
)) {
938 env
->fpscr
&= ~(0xF << (4 * i
));
939 env
->fpscr
|= new & (0xF << (4 * i
));
942 /* Update VX and FEX */
944 env
->fpscr
|= 1 << FPSCR_VX
;
946 env
->fpscr
&= ~(1 << FPSCR_VX
);
947 if ((fpscr_ex
& fpscr_eex
) != 0) {
948 env
->fpscr
|= 1 << FPSCR_FEX
;
949 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
950 /* XXX: we should compute it properly */
951 env
->error_code
= POWERPC_EXCP_FP
;
954 env
->fpscr
&= ~(1 << FPSCR_FEX
);
955 fpscr_set_rounding_mode();
958 void helper_float_check_status (void)
960 #ifdef CONFIG_SOFTFLOAT
961 if (env
->exception_index
== POWERPC_EXCP_PROGRAM
&&
962 (env
->error_code
& POWERPC_EXCP_FP
)) {
963 /* Differred floating-point exception after target FPR update */
964 if (msr_fe0
!= 0 || msr_fe1
!= 0)
965 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
967 int status
= get_float_exception_flags(&env
->fp_status
);
968 if (status
& float_flag_divbyzero
) {
969 float_zero_divide_excp();
970 } else if (status
& float_flag_overflow
) {
971 float_overflow_excp();
972 } else if (status
& float_flag_underflow
) {
973 float_underflow_excp();
974 } else if (status
& float_flag_inexact
) {
975 float_inexact_excp();
979 if (env
->exception_index
== POWERPC_EXCP_PROGRAM
&&
980 (env
->error_code
& POWERPC_EXCP_FP
)) {
981 /* Differred floating-point exception after target FPR update */
982 if (msr_fe0
!= 0 || msr_fe1
!= 0)
983 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
988 #ifdef CONFIG_SOFTFLOAT
989 void helper_reset_fpstatus (void)
991 set_float_exception_flags(0, &env
->fp_status
);
996 uint64_t helper_fadd (uint64_t arg1
, uint64_t arg2
)
998 CPU_DoubleU farg1
, farg2
;
1002 #if USE_PRECISE_EMULATION
1003 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1004 float64_is_signaling_nan(farg2
.d
))) {
1006 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1007 } else if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
) &&
1008 float64_is_neg(farg1
.d
) != float64_is_neg(farg2
.d
))) {
1009 /* Magnitude subtraction of infinities */
1010 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1012 farg1
.d
= float64_add(farg1
.d
, farg2
.d
, &env
->fp_status
);
1015 farg1
.d
= float64_add(farg1
.d
, farg2
.d
, &env
->fp_status
);
1021 uint64_t helper_fsub (uint64_t arg1
, uint64_t arg2
)
1023 CPU_DoubleU farg1
, farg2
;
1027 #if USE_PRECISE_EMULATION
1029 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1030 float64_is_signaling_nan(farg2
.d
))) {
1031 /* sNaN subtraction */
1032 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1033 } else if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
) &&
1034 float64_is_neg(farg1
.d
) == float64_is_neg(farg2
.d
))) {
1035 /* Magnitude subtraction of infinities */
1036 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1038 farg1
.d
= float64_sub(farg1
.d
, farg2
.d
, &env
->fp_status
);
1042 farg1
.d
= float64_sub(farg1
.d
, farg2
.d
, &env
->fp_status
);
1048 uint64_t helper_fmul (uint64_t arg1
, uint64_t arg2
)
1050 CPU_DoubleU farg1
, farg2
;
1054 #if USE_PRECISE_EMULATION
1055 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1056 float64_is_signaling_nan(farg2
.d
))) {
1057 /* sNaN multiplication */
1058 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1059 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1060 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1061 /* Multiplication of zero by infinity */
1062 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1064 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1067 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1073 uint64_t helper_fdiv (uint64_t arg1
, uint64_t arg2
)
1075 CPU_DoubleU farg1
, farg2
;
1079 #if USE_PRECISE_EMULATION
1080 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1081 float64_is_signaling_nan(farg2
.d
))) {
1083 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1084 } else if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
))) {
1085 /* Division of infinity by infinity */
1086 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI
);
1087 } else if (unlikely(float64_is_zero(farg1
.d
) && float64_is_zero(farg2
.d
))) {
1088 /* Division of zero by zero */
1089 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ
);
1091 farg1
.d
= float64_div(farg1
.d
, farg2
.d
, &env
->fp_status
);
1094 farg1
.d
= float64_div(farg1
.d
, farg2
.d
, &env
->fp_status
);
1100 uint64_t helper_fabs (uint64_t arg
)
1105 farg
.d
= float64_abs(farg
.d
);
1110 uint64_t helper_fnabs (uint64_t arg
)
1115 farg
.d
= float64_abs(farg
.d
);
1116 farg
.d
= float64_chs(farg
.d
);
1121 uint64_t helper_fneg (uint64_t arg
)
1126 farg
.d
= float64_chs(farg
.d
);
1130 /* fctiw - fctiw. */
1131 uint64_t helper_fctiw (uint64_t arg
)
1136 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1137 /* sNaN conversion */
1138 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1139 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1140 /* qNan / infinity conversion */
1141 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1143 farg
.ll
= float64_to_int32(farg
.d
, &env
->fp_status
);
1144 #if USE_PRECISE_EMULATION
1145 /* XXX: higher bits are not supposed to be significant.
1146 * to make tests easier, return the same as a real PowerPC 750
1148 farg
.ll
|= 0xFFF80000ULL
<< 32;
1154 /* fctiwz - fctiwz. */
1155 uint64_t helper_fctiwz (uint64_t arg
)
1160 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1161 /* sNaN conversion */
1162 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1163 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1164 /* qNan / infinity conversion */
1165 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1167 farg
.ll
= float64_to_int32_round_to_zero(farg
.d
, &env
->fp_status
);
1168 #if USE_PRECISE_EMULATION
1169 /* XXX: higher bits are not supposed to be significant.
1170 * to make tests easier, return the same as a real PowerPC 750
1172 farg
.ll
|= 0xFFF80000ULL
<< 32;
1178 #if defined(TARGET_PPC64)
1179 /* fcfid - fcfid. */
1180 uint64_t helper_fcfid (uint64_t arg
)
1183 farg
.d
= int64_to_float64(arg
, &env
->fp_status
);
1187 /* fctid - fctid. */
1188 uint64_t helper_fctid (uint64_t arg
)
1193 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1194 /* sNaN conversion */
1195 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1196 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1197 /* qNan / infinity conversion */
1198 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1200 farg
.ll
= float64_to_int64(farg
.d
, &env
->fp_status
);
1205 /* fctidz - fctidz. */
1206 uint64_t helper_fctidz (uint64_t arg
)
1211 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1212 /* sNaN conversion */
1213 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1214 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1215 /* qNan / infinity conversion */
1216 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1218 farg
.ll
= float64_to_int64_round_to_zero(farg
.d
, &env
->fp_status
);
1225 static always_inline
uint64_t do_fri (uint64_t arg
, int rounding_mode
)
1230 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1232 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1233 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1234 /* qNan / infinity round */
1235 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1237 set_float_rounding_mode(rounding_mode
, &env
->fp_status
);
1238 farg
.ll
= float64_round_to_int(farg
.d
, &env
->fp_status
);
1239 /* Restore rounding mode from FPSCR */
1240 fpscr_set_rounding_mode();
1245 uint64_t helper_frin (uint64_t arg
)
1247 return do_fri(arg
, float_round_nearest_even
);
1250 uint64_t helper_friz (uint64_t arg
)
1252 return do_fri(arg
, float_round_to_zero
);
1255 uint64_t helper_frip (uint64_t arg
)
1257 return do_fri(arg
, float_round_up
);
1260 uint64_t helper_frim (uint64_t arg
)
1262 return do_fri(arg
, float_round_down
);
1265 /* fmadd - fmadd. */
1266 uint64_t helper_fmadd (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1268 CPU_DoubleU farg1
, farg2
, farg3
;
1273 #if USE_PRECISE_EMULATION
1274 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1275 float64_is_signaling_nan(farg2
.d
) ||
1276 float64_is_signaling_nan(farg3
.d
))) {
1277 /* sNaN operation */
1278 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1279 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1280 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1281 /* Multiplication of zero by infinity */
1282 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1285 /* This is the way the PowerPC specification defines it */
1286 float128 ft0_128
, ft1_128
;
1288 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1289 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1290 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1291 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1292 float128_is_neg(ft0_128
) != float64_is_neg(farg3
.d
))) {
1293 /* Magnitude subtraction of infinities */
1294 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1296 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1297 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
1298 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1301 /* This is OK on x86 hosts */
1302 farg1
.d
= (farg1
.d
* farg2
.d
) + farg3
.d
;
1306 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1307 farg1
.d
= float64_add(farg1
.d
, farg3
.d
, &env
->fp_status
);
1312 /* fmsub - fmsub. */
1313 uint64_t helper_fmsub (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1315 CPU_DoubleU farg1
, farg2
, farg3
;
1320 #if USE_PRECISE_EMULATION
1321 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1322 float64_is_signaling_nan(farg2
.d
) ||
1323 float64_is_signaling_nan(farg3
.d
))) {
1324 /* sNaN operation */
1325 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1326 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1327 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1328 /* Multiplication of zero by infinity */
1329 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1332 /* This is the way the PowerPC specification defines it */
1333 float128 ft0_128
, ft1_128
;
1335 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1336 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1337 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1338 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1339 float128_is_neg(ft0_128
) == float64_is_neg(farg3
.d
))) {
1340 /* Magnitude subtraction of infinities */
1341 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1343 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1344 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
1345 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1348 /* This is OK on x86 hosts */
1349 farg1
.d
= (farg1
.d
* farg2
.d
) - farg3
.d
;
1353 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1354 farg1
.d
= float64_sub(farg1
.d
, farg3
.d
, &env
->fp_status
);
1359 /* fnmadd - fnmadd. */
1360 uint64_t helper_fnmadd (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1362 CPU_DoubleU farg1
, farg2
, farg3
;
1368 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1369 float64_is_signaling_nan(farg2
.d
) ||
1370 float64_is_signaling_nan(farg3
.d
))) {
1371 /* sNaN operation */
1372 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1373 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1374 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1375 /* Multiplication of zero by infinity */
1376 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1378 #if USE_PRECISE_EMULATION
1380 /* This is the way the PowerPC specification defines it */
1381 float128 ft0_128
, ft1_128
;
1383 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1384 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1385 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1386 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1387 float128_is_neg(ft0_128
) != float64_is_neg(farg3
.d
))) {
1388 /* Magnitude subtraction of infinities */
1389 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1391 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1392 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
1393 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1396 /* This is OK on x86 hosts */
1397 farg1
.d
= (farg1
.d
* farg2
.d
) + farg3
.d
;
1400 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1401 farg1
.d
= float64_add(farg1
.d
, farg3
.d
, &env
->fp_status
);
1403 if (likely(!float64_is_nan(farg1
.d
)))
1404 farg1
.d
= float64_chs(farg1
.d
);
1409 /* fnmsub - fnmsub. */
1410 uint64_t helper_fnmsub (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1412 CPU_DoubleU farg1
, farg2
, farg3
;
1418 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1419 float64_is_signaling_nan(farg2
.d
) ||
1420 float64_is_signaling_nan(farg3
.d
))) {
1421 /* sNaN operation */
1422 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1423 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1424 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1425 /* Multiplication of zero by infinity */
1426 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1428 #if USE_PRECISE_EMULATION
1430 /* This is the way the PowerPC specification defines it */
1431 float128 ft0_128
, ft1_128
;
1433 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1434 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1435 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1436 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1437 float128_is_neg(ft0_128
) == float64_is_neg(farg3
.d
))) {
1438 /* Magnitude subtraction of infinities */
1439 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1441 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1442 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
1443 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1446 /* This is OK on x86 hosts */
1447 farg1
.d
= (farg1
.d
* farg2
.d
) - farg3
.d
;
1450 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1451 farg1
.d
= float64_sub(farg1
.d
, farg3
.d
, &env
->fp_status
);
1453 if (likely(!float64_is_nan(farg1
.d
)))
1454 farg1
.d
= float64_chs(farg1
.d
);
1460 uint64_t helper_frsp (uint64_t arg
)
1466 #if USE_PRECISE_EMULATION
1467 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1468 /* sNaN square root */
1469 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1471 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
1472 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
1475 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
1476 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
1481 /* fsqrt - fsqrt. */
1482 uint64_t helper_fsqrt (uint64_t arg
)
1487 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1488 /* sNaN square root */
1489 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1490 } else if (unlikely(float64_is_neg(farg
.d
) && !float64_is_zero(farg
.d
))) {
1491 /* Square root of a negative nonzero number */
1492 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT
);
1494 farg
.d
= float64_sqrt(farg
.d
, &env
->fp_status
);
1500 uint64_t helper_fre (uint64_t arg
)
1502 CPU_DoubleU fone
, farg
;
1503 fone
.ll
= 0x3FF0000000000000ULL
; /* 1.0 */
1506 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1507 /* sNaN reciprocal */
1508 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1510 farg
.d
= float64_div(fone
.d
, farg
.d
, &env
->fp_status
);
1516 uint64_t helper_fres (uint64_t arg
)
1518 CPU_DoubleU fone
, farg
;
1520 fone
.ll
= 0x3FF0000000000000ULL
; /* 1.0 */
1523 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1524 /* sNaN reciprocal */
1525 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1527 farg
.d
= float64_div(fone
.d
, farg
.d
, &env
->fp_status
);
1528 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
1529 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
1534 /* frsqrte - frsqrte. */
1535 uint64_t helper_frsqrte (uint64_t arg
)
1537 CPU_DoubleU fone
, farg
;
1539 fone
.ll
= 0x3FF0000000000000ULL
; /* 1.0 */
1542 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1543 /* sNaN reciprocal square root */
1544 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1545 } else if (unlikely(float64_is_neg(farg
.d
) && !float64_is_zero(farg
.d
))) {
1546 /* Reciprocal square root of a negative nonzero number */
1547 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT
);
1549 farg
.d
= float64_sqrt(farg
.d
, &env
->fp_status
);
1550 farg
.d
= float64_div(fone
.d
, farg
.d
, &env
->fp_status
);
1551 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
1552 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
1558 uint64_t helper_fsel (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1564 if ((!float64_is_neg(farg1
.d
) || float64_is_zero(farg1
.d
)) && !float64_is_nan(farg1
.d
))
1570 void helper_fcmpu (uint64_t arg1
, uint64_t arg2
, uint32_t crfD
)
1572 CPU_DoubleU farg1
, farg2
;
1577 if (unlikely(float64_is_nan(farg1
.d
) ||
1578 float64_is_nan(farg2
.d
))) {
1580 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1582 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1588 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1589 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1590 env
->crf
[crfD
] = ret
;
1591 if (unlikely(ret
== 0x01UL
1592 && (float64_is_signaling_nan(farg1
.d
) ||
1593 float64_is_signaling_nan(farg2
.d
)))) {
1594 /* sNaN comparison */
1595 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1599 void helper_fcmpo (uint64_t arg1
, uint64_t arg2
, uint32_t crfD
)
1601 CPU_DoubleU farg1
, farg2
;
1606 if (unlikely(float64_is_nan(farg1
.d
) ||
1607 float64_is_nan(farg2
.d
))) {
1609 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1611 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1617 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1618 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1619 env
->crf
[crfD
] = ret
;
1620 if (unlikely (ret
== 0x01UL
)) {
1621 if (float64_is_signaling_nan(farg1
.d
) ||
1622 float64_is_signaling_nan(farg2
.d
)) {
1623 /* sNaN comparison */
1624 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
|
1625 POWERPC_EXCP_FP_VXVC
);
1627 /* qNaN comparison */
1628 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC
);
1633 #if !defined (CONFIG_USER_ONLY)
1634 void helper_store_msr (target_ulong val
)
1636 val
= hreg_store_msr(env
, val
, 0);
1638 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1639 helper_raise_exception(val
);
1643 static always_inline
void do_rfi (target_ulong nip
, target_ulong msr
,
1644 target_ulong msrm
, int keep_msrh
)
1646 #if defined(TARGET_PPC64)
1647 if (msr
& (1ULL << MSR_SF
)) {
1648 nip
= (uint64_t)nip
;
1649 msr
&= (uint64_t)msrm
;
1651 nip
= (uint32_t)nip
;
1652 msr
= (uint32_t)(msr
& msrm
);
1654 msr
|= env
->msr
& ~((uint64_t)0xFFFFFFFF);
1657 nip
= (uint32_t)nip
;
1658 msr
&= (uint32_t)msrm
;
1660 /* XXX: beware: this is false if VLE is supported */
1661 env
->nip
= nip
& ~((target_ulong
)0x00000003);
1662 hreg_store_msr(env
, msr
, 1);
1663 #if defined (DEBUG_OP)
1664 cpu_dump_rfi(env
->nip
, env
->msr
);
1666 /* No need to raise an exception here,
1667 * as rfi is always the last insn of a TB
1669 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1672 void helper_rfi (void)
1674 do_rfi(env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
1675 ~((target_ulong
)0xFFFF0000), 1);
1678 #if defined(TARGET_PPC64)
1679 void helper_rfid (void)
1681 do_rfi(env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
1682 ~((target_ulong
)0xFFFF0000), 0);
1685 void helper_hrfid (void)
1687 do_rfi(env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
],
1688 ~((target_ulong
)0xFFFF0000), 0);
1693 void helper_tw (target_ulong arg1
, target_ulong arg2
, uint32_t flags
)
1695 if (!likely(!(((int32_t)arg1
< (int32_t)arg2
&& (flags
& 0x10)) ||
1696 ((int32_t)arg1
> (int32_t)arg2
&& (flags
& 0x08)) ||
1697 ((int32_t)arg1
== (int32_t)arg2
&& (flags
& 0x04)) ||
1698 ((uint32_t)arg1
< (uint32_t)arg2
&& (flags
& 0x02)) ||
1699 ((uint32_t)arg1
> (uint32_t)arg2
&& (flags
& 0x01))))) {
1700 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1704 #if defined(TARGET_PPC64)
1705 void helper_td (target_ulong arg1
, target_ulong arg2
, uint32_t flags
)
1707 if (!likely(!(((int64_t)arg1
< (int64_t)arg2
&& (flags
& 0x10)) ||
1708 ((int64_t)arg1
> (int64_t)arg2
&& (flags
& 0x08)) ||
1709 ((int64_t)arg1
== (int64_t)arg2
&& (flags
& 0x04)) ||
1710 ((uint64_t)arg1
< (uint64_t)arg2
&& (flags
& 0x02)) ||
1711 ((uint64_t)arg1
> (uint64_t)arg2
&& (flags
& 0x01)))))
1712 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1716 /*****************************************************************************/
1717 /* PowerPC 601 specific instructions (POWER bridge) */
1719 target_ulong
helper_clcs (uint32_t arg
)
1723 /* Instruction cache line size */
1724 return env
->icache_line_size
;
1727 /* Data cache line size */
1728 return env
->dcache_line_size
;
1731 /* Minimum cache line size */
1732 return (env
->icache_line_size
< env
->dcache_line_size
) ?
1733 env
->icache_line_size
: env
->dcache_line_size
;
1736 /* Maximum cache line size */
1737 return (env
->icache_line_size
> env
->dcache_line_size
) ?
1738 env
->icache_line_size
: env
->dcache_line_size
;
1747 target_ulong
helper_div (target_ulong arg1
, target_ulong arg2
)
1749 uint64_t tmp
= (uint64_t)arg1
<< 32 | env
->spr
[SPR_MQ
];
1751 if (((int32_t)tmp
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1752 (int32_t)arg2
== 0) {
1753 env
->spr
[SPR_MQ
] = 0;
1756 env
->spr
[SPR_MQ
] = tmp
% arg2
;
1757 return tmp
/ (int32_t)arg2
;
1761 target_ulong
helper_divo (target_ulong arg1
, target_ulong arg2
)
1763 uint64_t tmp
= (uint64_t)arg1
<< 32 | env
->spr
[SPR_MQ
];
1765 if (((int32_t)tmp
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1766 (int32_t)arg2
== 0) {
1767 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1768 env
->spr
[SPR_MQ
] = 0;
1771 env
->spr
[SPR_MQ
] = tmp
% arg2
;
1772 tmp
/= (int32_t)arg2
;
1773 if ((int32_t)tmp
!= tmp
) {
1774 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1776 env
->xer
&= ~(1 << XER_OV
);
1782 target_ulong
helper_divs (target_ulong arg1
, target_ulong arg2
)
1784 if (((int32_t)arg1
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1785 (int32_t)arg2
== 0) {
1786 env
->spr
[SPR_MQ
] = 0;
1789 env
->spr
[SPR_MQ
] = (int32_t)arg1
% (int32_t)arg2
;
1790 return (int32_t)arg1
/ (int32_t)arg2
;
1794 target_ulong
helper_divso (target_ulong arg1
, target_ulong arg2
)
1796 if (((int32_t)arg1
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1797 (int32_t)arg2
== 0) {
1798 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1799 env
->spr
[SPR_MQ
] = 0;
1802 env
->xer
&= ~(1 << XER_OV
);
1803 env
->spr
[SPR_MQ
] = (int32_t)arg1
% (int32_t)arg2
;
1804 return (int32_t)arg1
/ (int32_t)arg2
;
1808 #if !defined (CONFIG_USER_ONLY)
1809 target_ulong
helper_rac (target_ulong addr
)
1813 target_ulong ret
= 0;
1815 /* We don't have to generate many instances of this instruction,
1816 * as rac is supervisor only.
1818 /* XXX: FIX THIS: Pretend we have no BAT */
1819 nb_BATs
= env
->nb_BATs
;
1821 if (get_physical_address(env
, &ctx
, addr
, 0, ACCESS_INT
) == 0)
1823 env
->nb_BATs
= nb_BATs
;
1827 void helper_rfsvc (void)
1829 do_rfi(env
->lr
, env
->ctr
, 0x0000FFFF, 0);
1833 /*****************************************************************************/
1834 /* 602 specific instructions */
1835 /* mfrom is the most crazy instruction ever seen, imho ! */
1836 /* Real implementation uses a ROM table. Do the same */
1837 /* Extremly decomposed:
1839 * return 256 * log10(10 + 1.0) + 0.5
1841 #if !defined (CONFIG_USER_ONLY)
1842 target_ulong
helper_602_mfrom (target_ulong arg
)
1844 if (likely(arg
< 602)) {
1845 #include "mfrom_table.c"
1846 return mfrom_ROM_table
[arg
];
1853 /*****************************************************************************/
1854 /* Embedded PowerPC specific helpers */
1856 /* XXX: to be improved to check access rights when in user-mode */
1857 target_ulong
helper_load_dcr (target_ulong dcrn
)
1859 target_ulong val
= 0;
1861 if (unlikely(env
->dcr_env
== NULL
)) {
1862 if (loglevel
!= 0) {
1863 fprintf(logfile
, "No DCR environment\n");
1865 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1866 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1867 } else if (unlikely(ppc_dcr_read(env
->dcr_env
, dcrn
, &val
) != 0)) {
1868 if (loglevel
!= 0) {
1869 fprintf(logfile
, "DCR read error %d %03x\n", (int)dcrn
, (int)dcrn
);
1871 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1872 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1877 void helper_store_dcr (target_ulong dcrn
, target_ulong val
)
1879 if (unlikely(env
->dcr_env
== NULL
)) {
1880 if (loglevel
!= 0) {
1881 fprintf(logfile
, "No DCR environment\n");
1883 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1884 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1885 } else if (unlikely(ppc_dcr_write(env
->dcr_env
, dcrn
, val
) != 0)) {
1886 if (loglevel
!= 0) {
1887 fprintf(logfile
, "DCR write error %d %03x\n", (int)dcrn
, (int)dcrn
);
1889 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1890 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1894 #if !defined(CONFIG_USER_ONLY)
1895 void helper_40x_rfci (void)
1897 do_rfi(env
->spr
[SPR_40x_SRR2
], env
->spr
[SPR_40x_SRR3
],
1898 ~((target_ulong
)0xFFFF0000), 0);
1901 void helper_rfci (void)
1903 do_rfi(env
->spr
[SPR_BOOKE_CSRR0
], SPR_BOOKE_CSRR1
,
1904 ~((target_ulong
)0x3FFF0000), 0);
1907 void helper_rfdi (void)
1909 do_rfi(env
->spr
[SPR_BOOKE_DSRR0
], SPR_BOOKE_DSRR1
,
1910 ~((target_ulong
)0x3FFF0000), 0);
1913 void helper_rfmci (void)
1915 do_rfi(env
->spr
[SPR_BOOKE_MCSRR0
], SPR_BOOKE_MCSRR1
,
1916 ~((target_ulong
)0x3FFF0000), 0);
1921 target_ulong
helper_dlmzb (target_ulong high
, target_ulong low
, uint32_t update_Rc
)
1927 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1928 if ((high
& mask
) == 0) {
1936 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1937 if ((low
& mask
) == 0) {
1949 env
->xer
= (env
->xer
& ~0x7F) | i
;
1951 env
->crf
[0] |= xer_so
;
1956 /*****************************************************************************/
1957 /* Altivec extension helpers */
1958 #if defined(WORDS_BIGENDIAN)
1966 #if defined(WORDS_BIGENDIAN)
1967 #define VECTOR_FOR_INORDER_I(index, element) \
1968 for (index = 0; index < ARRAY_SIZE(r->element); index++)
1970 #define VECTOR_FOR_INORDER_I(index, element) \
1971 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
1974 #define VARITH_DO(name, op, element) \
1975 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
1978 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
1979 r->element[i] = a->element[i] op b->element[i]; \
1982 #define VARITH(suffix, element) \
1983 VARITH_DO(add##suffix, +, element) \
1984 VARITH_DO(sub##suffix, -, element)
1991 #define VAVG_DO(name, element, etype) \
1992 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
1995 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
1996 etype x = (etype)a->element[i] + (etype)b->element[i] + 1; \
1997 r->element[i] = x >> 1; \
2001 #define VAVG(type, signed_element, signed_type, unsigned_element, unsigned_type) \
2002 VAVG_DO(avgs##type, signed_element, signed_type) \
2003 VAVG_DO(avgu##type, unsigned_element, unsigned_type)
2004 VAVG(b
, s8
, int16_t, u8
, uint16_t)
2005 VAVG(h
, s16
, int32_t, u16
, uint32_t)
2006 VAVG(w
, s32
, int64_t, u32
, uint64_t)
2010 #define VMINMAX_DO(name, compare, element) \
2011 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2014 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2015 if (a->element[i] compare b->element[i]) { \
2016 r->element[i] = b->element[i]; \
2018 r->element[i] = a->element[i]; \
2022 #define VMINMAX(suffix, element) \
2023 VMINMAX_DO(min##suffix, >, element) \
2024 VMINMAX_DO(max##suffix, <, element)
2034 #define VMRG_DO(name, element, highp) \
2035 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2039 size_t n_elems = ARRAY_SIZE(r->element); \
2040 for (i = 0; i < n_elems/2; i++) { \
2042 result.element[i*2+HI_IDX] = a->element[i]; \
2043 result.element[i*2+LO_IDX] = b->element[i]; \
2045 result.element[n_elems - i*2 - (1+HI_IDX)] = b->element[n_elems - i - 1]; \
2046 result.element[n_elems - i*2 - (1+LO_IDX)] = a->element[n_elems - i - 1]; \
2051 #if defined(WORDS_BIGENDIAN)
2058 #define VMRG(suffix, element) \
2059 VMRG_DO(mrgl##suffix, element, MRGHI) \
2060 VMRG_DO(mrgh##suffix, element, MRGLO)
2069 #undef VECTOR_FOR_INORDER_I
2073 /*****************************************************************************/
2074 /* SPE extension helpers */
2075 /* Use a table to make this quicker */
2076 static uint8_t hbrev
[16] = {
2077 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2078 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2081 static always_inline
uint8_t byte_reverse (uint8_t val
)
2083 return hbrev
[val
>> 4] | (hbrev
[val
& 0xF] << 4);
2086 static always_inline
uint32_t word_reverse (uint32_t val
)
2088 return byte_reverse(val
>> 24) | (byte_reverse(val
>> 16) << 8) |
2089 (byte_reverse(val
>> 8) << 16) | (byte_reverse(val
) << 24);
2092 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2093 target_ulong
helper_brinc (target_ulong arg1
, target_ulong arg2
)
2095 uint32_t a
, b
, d
, mask
;
2097 mask
= UINT32_MAX
>> (32 - MASKBITS
);
2100 d
= word_reverse(1 + word_reverse(a
| ~b
));
2101 return (arg1
& ~mask
) | (d
& b
);
2104 uint32_t helper_cntlsw32 (uint32_t val
)
2106 if (val
& 0x80000000)
2112 uint32_t helper_cntlzw32 (uint32_t val
)
2117 /* Single-precision floating-point conversions */
2118 static always_inline
uint32_t efscfsi (uint32_t val
)
2122 u
.f
= int32_to_float32(val
, &env
->spe_status
);
2127 static always_inline
uint32_t efscfui (uint32_t val
)
2131 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
2136 static always_inline
int32_t efsctsi (uint32_t val
)
2141 /* NaN are not treated the same way IEEE 754 does */
2142 if (unlikely(float32_is_nan(u
.f
)))
2145 return float32_to_int32(u
.f
, &env
->spe_status
);
2148 static always_inline
uint32_t efsctui (uint32_t val
)
2153 /* NaN are not treated the same way IEEE 754 does */
2154 if (unlikely(float32_is_nan(u
.f
)))
2157 return float32_to_uint32(u
.f
, &env
->spe_status
);
2160 static always_inline
uint32_t efsctsiz (uint32_t val
)
2165 /* NaN are not treated the same way IEEE 754 does */
2166 if (unlikely(float32_is_nan(u
.f
)))
2169 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
2172 static always_inline
uint32_t efsctuiz (uint32_t val
)
2177 /* NaN are not treated the same way IEEE 754 does */
2178 if (unlikely(float32_is_nan(u
.f
)))
2181 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
2184 static always_inline
uint32_t efscfsf (uint32_t val
)
2189 u
.f
= int32_to_float32(val
, &env
->spe_status
);
2190 tmp
= int64_to_float32(1ULL << 32, &env
->spe_status
);
2191 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
2196 static always_inline
uint32_t efscfuf (uint32_t val
)
2201 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
2202 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
2203 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
2208 static always_inline
uint32_t efsctsf (uint32_t val
)
2214 /* NaN are not treated the same way IEEE 754 does */
2215 if (unlikely(float32_is_nan(u
.f
)))
2217 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
2218 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
2220 return float32_to_int32(u
.f
, &env
->spe_status
);
2223 static always_inline
uint32_t efsctuf (uint32_t val
)
2229 /* NaN are not treated the same way IEEE 754 does */
2230 if (unlikely(float32_is_nan(u
.f
)))
2232 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
2233 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
2235 return float32_to_uint32(u
.f
, &env
->spe_status
);
2238 #define HELPER_SPE_SINGLE_CONV(name) \
2239 uint32_t helper_e##name (uint32_t val) \
2241 return e##name(val); \
2244 HELPER_SPE_SINGLE_CONV(fscfsi
);
2246 HELPER_SPE_SINGLE_CONV(fscfui
);
2248 HELPER_SPE_SINGLE_CONV(fscfuf
);
2250 HELPER_SPE_SINGLE_CONV(fscfsf
);
2252 HELPER_SPE_SINGLE_CONV(fsctsi
);
2254 HELPER_SPE_SINGLE_CONV(fsctui
);
2256 HELPER_SPE_SINGLE_CONV(fsctsiz
);
2258 HELPER_SPE_SINGLE_CONV(fsctuiz
);
2260 HELPER_SPE_SINGLE_CONV(fsctsf
);
2262 HELPER_SPE_SINGLE_CONV(fsctuf
);
2264 #define HELPER_SPE_VECTOR_CONV(name) \
2265 uint64_t helper_ev##name (uint64_t val) \
2267 return ((uint64_t)e##name(val >> 32) << 32) | \
2268 (uint64_t)e##name(val); \
2271 HELPER_SPE_VECTOR_CONV(fscfsi
);
2273 HELPER_SPE_VECTOR_CONV(fscfui
);
2275 HELPER_SPE_VECTOR_CONV(fscfuf
);
2277 HELPER_SPE_VECTOR_CONV(fscfsf
);
2279 HELPER_SPE_VECTOR_CONV(fsctsi
);
2281 HELPER_SPE_VECTOR_CONV(fsctui
);
2283 HELPER_SPE_VECTOR_CONV(fsctsiz
);
2285 HELPER_SPE_VECTOR_CONV(fsctuiz
);
2287 HELPER_SPE_VECTOR_CONV(fsctsf
);
2289 HELPER_SPE_VECTOR_CONV(fsctuf
);
2291 /* Single-precision floating-point arithmetic */
2292 static always_inline
uint32_t efsadd (uint32_t op1
, uint32_t op2
)
2297 u1
.f
= float32_add(u1
.f
, u2
.f
, &env
->spe_status
);
2301 static always_inline
uint32_t efssub (uint32_t op1
, uint32_t op2
)
2306 u1
.f
= float32_sub(u1
.f
, u2
.f
, &env
->spe_status
);
2310 static always_inline
uint32_t efsmul (uint32_t op1
, uint32_t op2
)
2315 u1
.f
= float32_mul(u1
.f
, u2
.f
, &env
->spe_status
);
2319 static always_inline
uint32_t efsdiv (uint32_t op1
, uint32_t op2
)
2324 u1
.f
= float32_div(u1
.f
, u2
.f
, &env
->spe_status
);
2328 #define HELPER_SPE_SINGLE_ARITH(name) \
2329 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2331 return e##name(op1, op2); \
2334 HELPER_SPE_SINGLE_ARITH(fsadd
);
2336 HELPER_SPE_SINGLE_ARITH(fssub
);
2338 HELPER_SPE_SINGLE_ARITH(fsmul
);
2340 HELPER_SPE_SINGLE_ARITH(fsdiv
);
2342 #define HELPER_SPE_VECTOR_ARITH(name) \
2343 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2345 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2346 (uint64_t)e##name(op1, op2); \
2349 HELPER_SPE_VECTOR_ARITH(fsadd
);
2351 HELPER_SPE_VECTOR_ARITH(fssub
);
2353 HELPER_SPE_VECTOR_ARITH(fsmul
);
2355 HELPER_SPE_VECTOR_ARITH(fsdiv
);
2357 /* Single-precision floating-point comparisons */
2358 static always_inline
uint32_t efststlt (uint32_t op1
, uint32_t op2
)
2363 return float32_lt(u1
.f
, u2
.f
, &env
->spe_status
) ? 4 : 0;
2366 static always_inline
uint32_t efststgt (uint32_t op1
, uint32_t op2
)
2371 return float32_le(u1
.f
, u2
.f
, &env
->spe_status
) ? 0 : 4;
2374 static always_inline
uint32_t efststeq (uint32_t op1
, uint32_t op2
)
2379 return float32_eq(u1
.f
, u2
.f
, &env
->spe_status
) ? 4 : 0;
2382 static always_inline
uint32_t efscmplt (uint32_t op1
, uint32_t op2
)
2384 /* XXX: TODO: test special values (NaN, infinites, ...) */
2385 return efststlt(op1
, op2
);
2388 static always_inline
uint32_t efscmpgt (uint32_t op1
, uint32_t op2
)
2390 /* XXX: TODO: test special values (NaN, infinites, ...) */
2391 return efststgt(op1
, op2
);
2394 static always_inline
uint32_t efscmpeq (uint32_t op1
, uint32_t op2
)
2396 /* XXX: TODO: test special values (NaN, infinites, ...) */
2397 return efststeq(op1
, op2
);
2400 #define HELPER_SINGLE_SPE_CMP(name) \
2401 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2403 return e##name(op1, op2) << 2; \
2406 HELPER_SINGLE_SPE_CMP(fststlt
);
2408 HELPER_SINGLE_SPE_CMP(fststgt
);
2410 HELPER_SINGLE_SPE_CMP(fststeq
);
2412 HELPER_SINGLE_SPE_CMP(fscmplt
);
2414 HELPER_SINGLE_SPE_CMP(fscmpgt
);
2416 HELPER_SINGLE_SPE_CMP(fscmpeq
);
2418 static always_inline
uint32_t evcmp_merge (int t0
, int t1
)
2420 return (t0
<< 3) | (t1
<< 2) | ((t0
| t1
) << 1) | (t0
& t1
);
2423 #define HELPER_VECTOR_SPE_CMP(name) \
2424 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2426 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2429 HELPER_VECTOR_SPE_CMP(fststlt
);
2431 HELPER_VECTOR_SPE_CMP(fststgt
);
2433 HELPER_VECTOR_SPE_CMP(fststeq
);
2435 HELPER_VECTOR_SPE_CMP(fscmplt
);
2437 HELPER_VECTOR_SPE_CMP(fscmpgt
);
2439 HELPER_VECTOR_SPE_CMP(fscmpeq
);
2441 /* Double-precision floating-point conversion */
2442 uint64_t helper_efdcfsi (uint32_t val
)
2446 u
.d
= int32_to_float64(val
, &env
->spe_status
);
2451 uint64_t helper_efdcfsid (uint64_t val
)
2455 u
.d
= int64_to_float64(val
, &env
->spe_status
);
2460 uint64_t helper_efdcfui (uint32_t val
)
2464 u
.d
= uint32_to_float64(val
, &env
->spe_status
);
2469 uint64_t helper_efdcfuid (uint64_t val
)
2473 u
.d
= uint64_to_float64(val
, &env
->spe_status
);
2478 uint32_t helper_efdctsi (uint64_t val
)
2483 /* NaN are not treated the same way IEEE 754 does */
2484 if (unlikely(float64_is_nan(u
.d
)))
2487 return float64_to_int32(u
.d
, &env
->spe_status
);
2490 uint32_t helper_efdctui (uint64_t val
)
2495 /* NaN are not treated the same way IEEE 754 does */
2496 if (unlikely(float64_is_nan(u
.d
)))
2499 return float64_to_uint32(u
.d
, &env
->spe_status
);
2502 uint32_t helper_efdctsiz (uint64_t val
)
2507 /* NaN are not treated the same way IEEE 754 does */
2508 if (unlikely(float64_is_nan(u
.d
)))
2511 return float64_to_int32_round_to_zero(u
.d
, &env
->spe_status
);
2514 uint64_t helper_efdctsidz (uint64_t val
)
2519 /* NaN are not treated the same way IEEE 754 does */
2520 if (unlikely(float64_is_nan(u
.d
)))
2523 return float64_to_int64_round_to_zero(u
.d
, &env
->spe_status
);
2526 uint32_t helper_efdctuiz (uint64_t val
)
2531 /* NaN are not treated the same way IEEE 754 does */
2532 if (unlikely(float64_is_nan(u
.d
)))
2535 return float64_to_uint32_round_to_zero(u
.d
, &env
->spe_status
);
2538 uint64_t helper_efdctuidz (uint64_t val
)
2543 /* NaN are not treated the same way IEEE 754 does */
2544 if (unlikely(float64_is_nan(u
.d
)))
2547 return float64_to_uint64_round_to_zero(u
.d
, &env
->spe_status
);
2550 uint64_t helper_efdcfsf (uint32_t val
)
2555 u
.d
= int32_to_float64(val
, &env
->spe_status
);
2556 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2557 u
.d
= float64_div(u
.d
, tmp
, &env
->spe_status
);
2562 uint64_t helper_efdcfuf (uint32_t val
)
2567 u
.d
= uint32_to_float64(val
, &env
->spe_status
);
2568 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2569 u
.d
= float64_div(u
.d
, tmp
, &env
->spe_status
);
2574 uint32_t helper_efdctsf (uint64_t val
)
2580 /* NaN are not treated the same way IEEE 754 does */
2581 if (unlikely(float64_is_nan(u
.d
)))
2583 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2584 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2586 return float64_to_int32(u
.d
, &env
->spe_status
);
2589 uint32_t helper_efdctuf (uint64_t val
)
2595 /* NaN are not treated the same way IEEE 754 does */
2596 if (unlikely(float64_is_nan(u
.d
)))
2598 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2599 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2601 return float64_to_uint32(u
.d
, &env
->spe_status
);
2604 uint32_t helper_efscfd (uint64_t val
)
2610 u2
.f
= float64_to_float32(u1
.d
, &env
->spe_status
);
2615 uint64_t helper_efdcfs (uint32_t val
)
2621 u2
.d
= float32_to_float64(u1
.f
, &env
->spe_status
);
2626 /* Double precision fixed-point arithmetic */
2627 uint64_t helper_efdadd (uint64_t op1
, uint64_t op2
)
2632 u1
.d
= float64_add(u1
.d
, u2
.d
, &env
->spe_status
);
2636 uint64_t helper_efdsub (uint64_t op1
, uint64_t op2
)
2641 u1
.d
= float64_sub(u1
.d
, u2
.d
, &env
->spe_status
);
2645 uint64_t helper_efdmul (uint64_t op1
, uint64_t op2
)
2650 u1
.d
= float64_mul(u1
.d
, u2
.d
, &env
->spe_status
);
2654 uint64_t helper_efddiv (uint64_t op1
, uint64_t op2
)
2659 u1
.d
= float64_div(u1
.d
, u2
.d
, &env
->spe_status
);
2663 /* Double precision floating point helpers */
2664 uint32_t helper_efdtstlt (uint64_t op1
, uint64_t op2
)
2669 return float64_lt(u1
.d
, u2
.d
, &env
->spe_status
) ? 4 : 0;
2672 uint32_t helper_efdtstgt (uint64_t op1
, uint64_t op2
)
2677 return float64_le(u1
.d
, u2
.d
, &env
->spe_status
) ? 0 : 4;
2680 uint32_t helper_efdtsteq (uint64_t op1
, uint64_t op2
)
2685 return float64_eq(u1
.d
, u2
.d
, &env
->spe_status
) ? 4 : 0;
2688 uint32_t helper_efdcmplt (uint64_t op1
, uint64_t op2
)
2690 /* XXX: TODO: test special values (NaN, infinites, ...) */
2691 return helper_efdtstlt(op1
, op2
);
2694 uint32_t helper_efdcmpgt (uint64_t op1
, uint64_t op2
)
2696 /* XXX: TODO: test special values (NaN, infinites, ...) */
2697 return helper_efdtstgt(op1
, op2
);
2700 uint32_t helper_efdcmpeq (uint64_t op1
, uint64_t op2
)
2702 /* XXX: TODO: test special values (NaN, infinites, ...) */
2703 return helper_efdtsteq(op1
, op2
);
2706 /*****************************************************************************/
2707 /* Softmmu support */
2708 #if !defined (CONFIG_USER_ONLY)
2710 #define MMUSUFFIX _mmu
2713 #include "softmmu_template.h"
2716 #include "softmmu_template.h"
2719 #include "softmmu_template.h"
2722 #include "softmmu_template.h"
2724 /* try to fill the TLB and return an exception if error. If retaddr is
2725 NULL, it means that the function was called in C code (i.e. not
2726 from generated code or from helper.c) */
2727 /* XXX: fix it to restore all registers */
2728 void tlb_fill (target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
2730 TranslationBlock
*tb
;
2731 CPUState
*saved_env
;
2735 /* XXX: hack to restore env in all cases, even if not called from
2738 env
= cpu_single_env
;
2739 ret
= cpu_ppc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
2740 if (unlikely(ret
!= 0)) {
2741 if (likely(retaddr
)) {
2742 /* now we have a real cpu fault */
2743 pc
= (unsigned long)retaddr
;
2744 tb
= tb_find_pc(pc
);
2746 /* the PC is inside the translated code. It means that we have
2747 a virtual CPU fault */
2748 cpu_restore_state(tb
, env
, pc
, NULL
);
2751 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
2756 /* Segment registers load and store */
2757 target_ulong
helper_load_sr (target_ulong sr_num
)
2759 return env
->sr
[sr_num
];
2762 void helper_store_sr (target_ulong sr_num
, target_ulong val
)
2764 ppc_store_sr(env
, sr_num
, val
);
2767 /* SLB management */
2768 #if defined(TARGET_PPC64)
2769 target_ulong
helper_load_slb (target_ulong slb_nr
)
2771 return ppc_load_slb(env
, slb_nr
);
2774 void helper_store_slb (target_ulong slb_nr
, target_ulong rs
)
2776 ppc_store_slb(env
, slb_nr
, rs
);
2779 void helper_slbia (void)
2781 ppc_slb_invalidate_all(env
);
2784 void helper_slbie (target_ulong addr
)
2786 ppc_slb_invalidate_one(env
, addr
);
2789 #endif /* defined(TARGET_PPC64) */
2791 /* TLB management */
2792 void helper_tlbia (void)
2794 ppc_tlb_invalidate_all(env
);
2797 void helper_tlbie (target_ulong addr
)
2799 ppc_tlb_invalidate_one(env
, addr
);
2802 /* Software driven TLBs management */
2803 /* PowerPC 602/603 software TLB load instructions helpers */
2804 static void do_6xx_tlb (target_ulong new_EPN
, int is_code
)
2806 target_ulong RPN
, CMP
, EPN
;
2809 RPN
= env
->spr
[SPR_RPA
];
2811 CMP
= env
->spr
[SPR_ICMP
];
2812 EPN
= env
->spr
[SPR_IMISS
];
2814 CMP
= env
->spr
[SPR_DCMP
];
2815 EPN
= env
->spr
[SPR_DMISS
];
2817 way
= (env
->spr
[SPR_SRR1
] >> 17) & 1;
2818 #if defined (DEBUG_SOFTWARE_TLB)
2819 if (loglevel
!= 0) {
2820 fprintf(logfile
, "%s: EPN " ADDRX
" " ADDRX
" PTE0 " ADDRX
2821 " PTE1 " ADDRX
" way %d\n",
2822 __func__
, new_EPN
, EPN
, CMP
, RPN
, way
);
2825 /* Store this TLB */
2826 ppc6xx_tlb_store(env
, (uint32_t)(new_EPN
& TARGET_PAGE_MASK
),
2827 way
, is_code
, CMP
, RPN
);
2830 void helper_6xx_tlbd (target_ulong EPN
)
2835 void helper_6xx_tlbi (target_ulong EPN
)
2840 /* PowerPC 74xx software TLB load instructions helpers */
2841 static void do_74xx_tlb (target_ulong new_EPN
, int is_code
)
2843 target_ulong RPN
, CMP
, EPN
;
2846 RPN
= env
->spr
[SPR_PTELO
];
2847 CMP
= env
->spr
[SPR_PTEHI
];
2848 EPN
= env
->spr
[SPR_TLBMISS
] & ~0x3;
2849 way
= env
->spr
[SPR_TLBMISS
] & 0x3;
2850 #if defined (DEBUG_SOFTWARE_TLB)
2851 if (loglevel
!= 0) {
2852 fprintf(logfile
, "%s: EPN " ADDRX
" " ADDRX
" PTE0 " ADDRX
2853 " PTE1 " ADDRX
" way %d\n",
2854 __func__
, new_EPN
, EPN
, CMP
, RPN
, way
);
2857 /* Store this TLB */
2858 ppc6xx_tlb_store(env
, (uint32_t)(new_EPN
& TARGET_PAGE_MASK
),
2859 way
, is_code
, CMP
, RPN
);
2862 void helper_74xx_tlbd (target_ulong EPN
)
2864 do_74xx_tlb(EPN
, 0);
2867 void helper_74xx_tlbi (target_ulong EPN
)
2869 do_74xx_tlb(EPN
, 1);
2872 static always_inline target_ulong
booke_tlb_to_page_size (int size
)
2874 return 1024 << (2 * size
);
2877 static always_inline
int booke_page_size_to_tlb (target_ulong page_size
)
2881 switch (page_size
) {
2915 #if defined (TARGET_PPC64)
2916 case 0x000100000000ULL
:
2919 case 0x000400000000ULL
:
2922 case 0x001000000000ULL
:
2925 case 0x004000000000ULL
:
2928 case 0x010000000000ULL
:
2940 /* Helpers for 4xx TLB management */
2941 target_ulong
helper_4xx_tlbre_lo (target_ulong entry
)
2948 tlb
= &env
->tlb
[entry
].tlbe
;
2950 if (tlb
->prot
& PAGE_VALID
)
2952 size
= booke_page_size_to_tlb(tlb
->size
);
2953 if (size
< 0 || size
> 0x7)
2956 env
->spr
[SPR_40x_PID
] = tlb
->PID
;
2960 target_ulong
helper_4xx_tlbre_hi (target_ulong entry
)
2966 tlb
= &env
->tlb
[entry
].tlbe
;
2968 if (tlb
->prot
& PAGE_EXEC
)
2970 if (tlb
->prot
& PAGE_WRITE
)
2975 void helper_4xx_tlbwe_hi (target_ulong entry
, target_ulong val
)
2978 target_ulong page
, end
;
2980 #if defined (DEBUG_SOFTWARE_TLB)
2981 if (loglevel
!= 0) {
2982 fprintf(logfile
, "%s entry %d val " ADDRX
"\n", __func__
, (int)entry
, val
);
2986 tlb
= &env
->tlb
[entry
].tlbe
;
2987 /* Invalidate previous TLB (if it's valid) */
2988 if (tlb
->prot
& PAGE_VALID
) {
2989 end
= tlb
->EPN
+ tlb
->size
;
2990 #if defined (DEBUG_SOFTWARE_TLB)
2991 if (loglevel
!= 0) {
2992 fprintf(logfile
, "%s: invalidate old TLB %d start " ADDRX
2993 " end " ADDRX
"\n", __func__
, (int)entry
, tlb
->EPN
, end
);
2996 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2997 tlb_flush_page(env
, page
);
2999 tlb
->size
= booke_tlb_to_page_size((val
>> 7) & 0x7);
3000 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
3001 * If this ever occurs, one should use the ppcemb target instead
3002 * of the ppc or ppc64 one
3004 if ((val
& 0x40) && tlb
->size
< TARGET_PAGE_SIZE
) {
3005 cpu_abort(env
, "TLB size " TARGET_FMT_lu
" < %u "
3006 "are not supported (%d)\n",
3007 tlb
->size
, TARGET_PAGE_SIZE
, (int)((val
>> 7) & 0x7));
3009 tlb
->EPN
= val
& ~(tlb
->size
- 1);
3011 tlb
->prot
|= PAGE_VALID
;
3013 tlb
->prot
&= ~PAGE_VALID
;
3015 /* XXX: TO BE FIXED */
3016 cpu_abort(env
, "Little-endian TLB entries are not supported by now\n");
3018 tlb
->PID
= env
->spr
[SPR_40x_PID
]; /* PID */
3019 tlb
->attr
= val
& 0xFF;
3020 #if defined (DEBUG_SOFTWARE_TLB)
3021 if (loglevel
!= 0) {
3022 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
3023 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
3024 (int)entry
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
3025 tlb
->prot
& PAGE_READ
? 'r' : '-',
3026 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
3027 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
3028 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
3031 /* Invalidate new TLB (if valid) */
3032 if (tlb
->prot
& PAGE_VALID
) {
3033 end
= tlb
->EPN
+ tlb
->size
;
3034 #if defined (DEBUG_SOFTWARE_TLB)
3035 if (loglevel
!= 0) {
3036 fprintf(logfile
, "%s: invalidate TLB %d start " ADDRX
3037 " end " ADDRX
"\n", __func__
, (int)entry
, tlb
->EPN
, end
);
3040 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
3041 tlb_flush_page(env
, page
);
3045 void helper_4xx_tlbwe_lo (target_ulong entry
, target_ulong val
)
3049 #if defined (DEBUG_SOFTWARE_TLB)
3050 if (loglevel
!= 0) {
3051 fprintf(logfile
, "%s entry %i val " ADDRX
"\n", __func__
, (int)entry
, val
);
3055 tlb
= &env
->tlb
[entry
].tlbe
;
3056 tlb
->RPN
= val
& 0xFFFFFC00;
3057 tlb
->prot
= PAGE_READ
;
3059 tlb
->prot
|= PAGE_EXEC
;
3061 tlb
->prot
|= PAGE_WRITE
;
3062 #if defined (DEBUG_SOFTWARE_TLB)
3063 if (loglevel
!= 0) {
3064 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
3065 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
3066 (int)entry
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
3067 tlb
->prot
& PAGE_READ
? 'r' : '-',
3068 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
3069 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
3070 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
3075 target_ulong
helper_4xx_tlbsx (target_ulong address
)
3077 return ppcemb_tlb_search(env
, address
, env
->spr
[SPR_40x_PID
]);
3080 /* PowerPC 440 TLB management */
3081 void helper_440_tlbwe (uint32_t word
, target_ulong entry
, target_ulong value
)
3084 target_ulong EPN
, RPN
, size
;
3087 #if defined (DEBUG_SOFTWARE_TLB)
3088 if (loglevel
!= 0) {
3089 fprintf(logfile
, "%s word %d entry %d value " ADDRX
"\n",
3090 __func__
, word
, (int)entry
, value
);
3095 tlb
= &env
->tlb
[entry
].tlbe
;
3098 /* Just here to please gcc */
3100 EPN
= value
& 0xFFFFFC00;
3101 if ((tlb
->prot
& PAGE_VALID
) && EPN
!= tlb
->EPN
)
3104 size
= booke_tlb_to_page_size((value
>> 4) & 0xF);
3105 if ((tlb
->prot
& PAGE_VALID
) && tlb
->size
< size
)
3109 tlb
->attr
|= (value
>> 8) & 1;
3110 if (value
& 0x200) {
3111 tlb
->prot
|= PAGE_VALID
;
3113 if (tlb
->prot
& PAGE_VALID
) {
3114 tlb
->prot
&= ~PAGE_VALID
;
3118 tlb
->PID
= env
->spr
[SPR_440_MMUCR
] & 0x000000FF;
3123 RPN
= value
& 0xFFFFFC0F;
3124 if ((tlb
->prot
& PAGE_VALID
) && tlb
->RPN
!= RPN
)
3129 tlb
->attr
= (tlb
->attr
& 0x1) | (value
& 0x0000FF00);
3130 tlb
->prot
= tlb
->prot
& PAGE_VALID
;
3132 tlb
->prot
|= PAGE_READ
<< 4;
3134 tlb
->prot
|= PAGE_WRITE
<< 4;
3136 tlb
->prot
|= PAGE_EXEC
<< 4;
3138 tlb
->prot
|= PAGE_READ
;
3140 tlb
->prot
|= PAGE_WRITE
;
3142 tlb
->prot
|= PAGE_EXEC
;
3147 target_ulong
helper_440_tlbre (uint32_t word
, target_ulong entry
)
3154 tlb
= &env
->tlb
[entry
].tlbe
;
3157 /* Just here to please gcc */
3160 size
= booke_page_size_to_tlb(tlb
->size
);
3161 if (size
< 0 || size
> 0xF)
3164 if (tlb
->attr
& 0x1)
3166 if (tlb
->prot
& PAGE_VALID
)
3168 env
->spr
[SPR_440_MMUCR
] &= ~0x000000FF;
3169 env
->spr
[SPR_440_MMUCR
] |= tlb
->PID
;
3175 ret
= tlb
->attr
& ~0x1;
3176 if (tlb
->prot
& (PAGE_READ
<< 4))
3178 if (tlb
->prot
& (PAGE_WRITE
<< 4))
3180 if (tlb
->prot
& (PAGE_EXEC
<< 4))
3182 if (tlb
->prot
& PAGE_READ
)
3184 if (tlb
->prot
& PAGE_WRITE
)
3186 if (tlb
->prot
& PAGE_EXEC
)
3193 target_ulong
helper_440_tlbsx (target_ulong address
)
3195 return ppcemb_tlb_search(env
, address
, env
->spr
[SPR_440_MMUCR
] & 0xFF);
3198 #endif /* !CONFIG_USER_ONLY */