hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35
  36 //#define DEBUG_IRQ
  37
  38 #ifdef DEBUG_IRQ
  39 #define DPRINTF(fmt, args...)                           \
  40     do { printf("CPUIRQ: " fmt , ##args); } while (0)
  41 #else
  42 #define DPRINTF(fmt, args...)
  43 #endif
  44
  45 #define KERNEL_LOAD_ADDR     0x00404000
  46 #define CMDLINE_ADDR         0x003ff000
  47 #define INITRD_LOAD_ADDR     0x00300000
  48 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  49 #define PROM_VADDR           0x000ffd00000ULL
  50 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  51 #define APB_MEM_BASE         0x1ff00000000ULL
  52 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  53 #define PROM_FILENAME        "openbios-sparc64"
  54 #define NVRAM_SIZE           0x2000
  55 #define MAX_IDE_BUS          2
  56 #define BIOS_CFG_IOPORT      0x510
  57
  58 #define MAX_PILS 16
  59
  60 struct hwdef {
  61     const char * const default_cpu_model;
  62     uint16_t machine_id;
  63     uint64_t prom_addr;
  64     uint64_t console_serial_base;
  65 };
  66
  67 int DMA_get_channel_mode (int nchan)
  68 {
  69     return 0;
  70 }
  71 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  72 {
  73     return 0;
  74 }
  75 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  76 {
  77     return 0;
  78 }
  79 void DMA_hold_DREQ (int nchan) {}
  80 void DMA_release_DREQ (int nchan) {}
  81 void DMA_schedule(int nchan) {}
  82 void DMA_init (int high_page_enable) {}
  83 void DMA_register_channel (int nchan,
  84                            DMA_transfer_handler transfer_handler,
  85                            void *opaque)
  86 {
  87 }
  88
  89 static int nvram_boot_set(void *opaque, const char *boot_device)
  90 {
  91     unsigned int i;
  92     uint8_t image[sizeof(ohwcfg_v3_t)];
  93     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  94     m48t59_t *nvram = (m48t59_t *)opaque;
  95
  96     for (i = 0; i < sizeof(image); i++)
  97         image[i] = m48t59_read(nvram, i) & 0xff;
  98
  99     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 100             boot_device);
 101     header->nboot_devices = strlen(boot_device) & 0xff;
 102     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 103
 104     for (i = 0; i < sizeof(image); i++)
 105         m48t59_write(nvram, i, image[i]);
 106
 107     return 0;
 108 }
 109
 110 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 111                                    const char *arch,
 112                                    ram_addr_t RAM_size,
 113                                    const char *boot_devices,
 114                                    uint32_t kernel_image, uint32_t kernel_size,
 115                                    const char *cmdline,
 116                                    uint32_t initrd_image, uint32_t initrd_size,
 117                                    uint32_t NVRAM_image,
 118                                    int width, int height, int depth,
 119                                    const uint8_t *macaddr)
 120 {
 121     unsigned int i;
 122     uint32_t start, end;
 123     uint8_t image[0x1ff0];
 124     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
 125     struct sparc_arch_cfg *sparc_header;
 126     struct OpenBIOS_nvpart_v1 *part_header;
 127
 128     memset(image, '\0', sizeof(image));
 129
 130     // Try to match PPC NVRAM
 131     pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
 132             "QEMU_BIOS");
 133     header->struct_version = cpu_to_be32(3); /* structure v3 */
 134
 135     header->nvram_size = cpu_to_be16(NVRAM_size);
 136     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 137     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 138     pstrcpy((char *)header->arch, sizeof(header->arch), arch);
 139     header->nb_cpus = smp_cpus & 0xff;
 140     header->RAM0_base = 0;
 141     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 142     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 143             boot_devices);
 144     header->nboot_devices = strlen(boot_devices) & 0xff;
 145     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 146     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 147     if (cmdline) {
 148         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
 149         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 150         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 151     }
 152     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 153     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 154     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 155
 156     header->width = cpu_to_be16(width);
 157     header->height = cpu_to_be16(height);
 158     header->depth = cpu_to_be16(depth);
 159     if (nographic)
 160         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 161
 162     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 163
 164     // Architecture specific header
 165     start = sizeof(ohwcfg_v3_t);
 166     sparc_header = (struct sparc_arch_cfg *)&image[start];
 167     sparc_header->valid = 0;
 168     start += sizeof(struct sparc_arch_cfg);
 169
 170     // OpenBIOS nvram variables
 171     // Variable partition
 172     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 173     part_header->signature = OPENBIOS_PART_SYSTEM;
 174     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 175
 176     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 177     for (i = 0; i < nb_prom_envs; i++)
 178         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 179
 180     // End marker
 181     image[end++] = '\0';
 182
 183     end = start + ((end - start + 15) & ~15);
 184     OpenBIOS_finish_partition(part_header, end - start);
 185
 186     // free partition
 187     start = end;
 188     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 189     part_header->signature = OPENBIOS_PART_FREE;
 190     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 191
 192     end = 0x1fd0;
 193     OpenBIOS_finish_partition(part_header, end - start);
 194
 195     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 196
 197     for (i = 0; i < sizeof(image); i++)
 198         m48t59_write(nvram, i, image[i]);
 199
 200     qemu_register_boot_set(nvram_boot_set, nvram);
 201
 202     return 0;
 203 }
 204
 205 void pic_info(void)
 206 {
 207 }
 208
 209 void irq_info(void)
 210 {
 211 }
 212
 213 void cpu_check_irqs(CPUState *env)
 214 {
 215     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 216         ((env->softint & SOFTINT_TIMER) << 14);
 217
 218     if (pil && (env->interrupt_index == 0 ||
 219                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 220         unsigned int i;
 221
 222         for (i = 15; i > 0; i--) {
 223             if (pil & (1 << i)) {
 224                 int old_interrupt = env->interrupt_index;
 225
 226                 env->interrupt_index = TT_EXTINT | i;
 227                 if (old_interrupt != env->interrupt_index) {
 228                     DPRINTF("Set CPU IRQ %d\n", i);
 229                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 230                 }
 231                 break;
 232             }
 233         }
 234     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 235         DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 236         env->interrupt_index = 0;
 237         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 238     }
 239 }
 240
 241 static void cpu_set_irq(void *opaque, int irq, int level)
 242 {
 243     CPUState *env = opaque;
 244
 245     if (level) {
 246         DPRINTF("Raise CPU IRQ %d\n", irq);
 247         env->halted = 0;
 248         env->pil_in |= 1 << irq;
 249         cpu_check_irqs(env);
 250     } else {
 251         DPRINTF("Lower CPU IRQ %d\n", irq);
 252         env->pil_in &= ~(1 << irq);
 253         cpu_check_irqs(env);
 254     }
 255 }
 256
 257 void qemu_system_powerdown(void)
 258 {
 259 }
 260
 261 typedef struct ResetData {
 262     CPUState *env;
 263     uint64_t reset_addr;
 264 } ResetData;
 265
 266 static void main_cpu_reset(void *opaque)
 267 {
 268     ResetData *s = (ResetData *)opaque;
 269     CPUState *env = s->env;
 270
 271     cpu_reset(env);
 272     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 273     ptimer_run(env->tick, 0);
 274     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 275     ptimer_run(env->stick, 0);
 276     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 277     ptimer_run(env->hstick, 0);
 278     env->gregs[1] = 0; // Memory start
 279     env->gregs[2] = ram_size; // Memory size
 280     env->gregs[3] = 0; // Machine description XXX
 281     env->pc = s->reset_addr;
 282     env->npc = env->pc + 4;
 283 }
 284
 285 static void tick_irq(void *opaque)
 286 {
 287     CPUState *env = opaque;
 288
 289     env->softint |= SOFTINT_TIMER;
 290     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 291 }
 292
 293 static void stick_irq(void *opaque)
 294 {
 295     CPUState *env = opaque;
 296
 297     env->softint |= SOFTINT_TIMER;
 298     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 299 }
 300
 301 static void hstick_irq(void *opaque)
 302 {
 303     CPUState *env = opaque;
 304
 305     env->softint |= SOFTINT_TIMER;
 306     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 307 }
 308
 309 void cpu_tick_set_count(void *opaque, uint64_t count)
 310 {
 311     ptimer_set_count(opaque, -count);
 312 }
 313
 314 uint64_t cpu_tick_get_count(void *opaque)
 315 {
 316     return -ptimer_get_count(opaque);
 317 }
 318
 319 void cpu_tick_set_limit(void *opaque, uint64_t limit)
 320 {
 321     ptimer_set_limit(opaque, -limit, 0);
 322 }
 323
 324 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 325 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 326 static const int ide_irq[2] = { 14, 15 };
 327
 328 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 329 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 330
 331 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 332 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 333
 334 static fdctrl_t *floppy_controller;
 335
 336 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
 337                         const char *boot_devices, DisplayState *ds,
 338                         const char *kernel_filename, const char *kernel_cmdline,
 339                         const char *initrd_filename, const char *cpu_model,
 340                         const struct hwdef *hwdef)
 341 {
 342     CPUState *env;
 343     char buf[1024];
 344     m48t59_t *nvram;
 345     int ret, linux_boot;
 346     unsigned int i;
 347     ram_addr_t ram_offset, prom_offset, vga_ram_offset;
 348     long initrd_size, kernel_size;
 349     PCIBus *pci_bus;
 350     QEMUBH *bh;
 351     qemu_irq *irq;
 352     int drive_index;
 353     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 354     BlockDriverState *fd[MAX_FD];
 355     void *fw_cfg;
 356     ResetData *reset_info;
 357
 358     linux_boot = (kernel_filename != NULL);
 359
 360     /* init CPUs */
 361     if (!cpu_model)
 362         cpu_model = hwdef->default_cpu_model;
 363
 364     env = cpu_init(cpu_model);
 365     if (!env) {
 366         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 367         exit(1);
 368     }
 369     bh = qemu_bh_new(tick_irq, env);
 370     env->tick = ptimer_init(bh);
 371     ptimer_set_period(env->tick, 1ULL);
 372
 373     bh = qemu_bh_new(stick_irq, env);
 374     env->stick = ptimer_init(bh);
 375     ptimer_set_period(env->stick, 1ULL);
 376
 377     bh = qemu_bh_new(hstick_irq, env);
 378     env->hstick = ptimer_init(bh);
 379     ptimer_set_period(env->hstick, 1ULL);
 380
 381     reset_info = qemu_mallocz(sizeof(ResetData));
 382     reset_info->env = env;
 383     reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
 384     qemu_register_reset(main_cpu_reset, reset_info);
 385     main_cpu_reset(reset_info);
 386     // Override warm reset address with cold start address
 387     env->pc = hwdef->prom_addr + 0x20ULL;
 388     env->npc = env->pc + 4;
 389
 390     /* allocate RAM */
 391     ram_offset = qemu_ram_alloc(RAM_size);
 392     cpu_register_physical_memory(0, RAM_size, ram_offset);
 393
 394     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 395     cpu_register_physical_memory(hwdef->prom_addr,
 396                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 397                                  TARGET_PAGE_MASK,
 398                                  prom_offset | IO_MEM_ROM);
 399
 400     if (bios_name == NULL)
 401         bios_name = PROM_FILENAME;
 402     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 403     ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL);
 404     if (ret < 0) {
 405         ret = load_image_targphys(buf, hwdef->prom_addr,
 406                                   (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 407                                   TARGET_PAGE_MASK);
 408         if (ret < 0) {
 409             fprintf(stderr, "qemu: could not load prom '%s'\n",
 410                     buf);
 411             exit(1);
 412         }
 413     }
 414
 415     kernel_size = 0;
 416     initrd_size = 0;
 417     if (linux_boot) {
 418         /* XXX: put correct offset */
 419         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 420         if (kernel_size < 0)
 421             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 422                                     ram_size - KERNEL_LOAD_ADDR);
 423         if (kernel_size < 0)
 424             kernel_size = load_image_targphys(kernel_filename,
 425                                               KERNEL_LOAD_ADDR,
 426                                               ram_size - KERNEL_LOAD_ADDR);
 427         if (kernel_size < 0) {
 428             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 429                     kernel_filename);
 430             exit(1);
 431         }
 432
 433         /* load initrd */
 434         if (initrd_filename) {
 435             initrd_size = load_image_targphys(initrd_filename,
 436                                               INITRD_LOAD_ADDR,
 437                                               ram_size - INITRD_LOAD_ADDR);
 438             if (initrd_size < 0) {
 439                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 440                         initrd_filename);
 441                 exit(1);
 442             }
 443         }
 444         if (initrd_size > 0) {
 445             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 446                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 447                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 448                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 449                     break;
 450                 }
 451             }
 452         }
 453     }
 454     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 455     isa_mem_base = VGA_BASE;
 456     vga_ram_offset = qemu_ram_alloc(vga_ram_size);
 457     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
 458                         vga_ram_offset, vga_ram_size);
 459
 460     i = 0;
 461     if (hwdef->console_serial_base) {
 462         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 463                        serial_hds[i], 1);
 464         i++;
 465     }
 466     for(; i < MAX_SERIAL_PORTS; i++) {
 467         if (serial_hds[i]) {
 468             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 469                         serial_hds[i]);
 470         }
 471     }
 472
 473     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 474         if (parallel_hds[i]) {
 475             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 476                           parallel_hds[i]);
 477         }
 478     }
 479
 480     for(i = 0; i < nb_nics; i++) {
 481         if (!nd_table[i].model)
 482             nd_table[i].model = "ne2k_pci";
 483         pci_nic_init(pci_bus, &nd_table[i], -1);
 484     }
 485
 486     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 487     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 488         fprintf(stderr, "qemu: too many IDE bus\n");
 489         exit(1);
 490     }
 491     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 492         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 493                                       i % MAX_IDE_DEVS);
 494        if (drive_index != -1)
 495            hd[i] = drives_table[drive_index].bdrv;
 496        else
 497            hd[i] = NULL;
 498     }
 499
 500     // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
 501     pci_piix3_ide_init(pci_bus, hd, -1, irq);
 502     /* FIXME: wire up interrupts.  */
 503     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 504     for(i = 0; i < MAX_FD; i++) {
 505         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 506        if (drive_index != -1)
 507            fd[i] = drives_table[drive_index].bdrv;
 508        else
 509            fd[i] = NULL;
 510     }
 511     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 512     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 513     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 514                            KERNEL_LOAD_ADDR, kernel_size,
 515                            kernel_cmdline,
 516                            INITRD_LOAD_ADDR, initrd_size,
 517                            /* XXX: need an option to load a NVRAM image */
 518                            0,
 519                            graphic_width, graphic_height, graphic_depth,
 520                            (uint8_t *)&nd_table[0].macaddr);
 521
 522     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 523     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 524     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 525     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 526 }
 527
 528 enum {
 529     sun4u_id = 0,
 530     sun4v_id = 64,
 531     niagara_id,
 532 };
 533
 534 static const struct hwdef hwdefs[] = {
 535     /* Sun4u generic PC-like machine */
 536     {
 537         .default_cpu_model = "TI UltraSparc II",
 538         .machine_id = sun4u_id,
 539         .prom_addr = 0x1fff0000000ULL,
 540         .console_serial_base = 0,
 541     },
 542     /* Sun4v generic PC-like machine */
 543     {
 544         .default_cpu_model = "Sun UltraSparc T1",
 545         .machine_id = sun4v_id,
 546         .prom_addr = 0x1fff0000000ULL,
 547         .console_serial_base = 0,
 548     },
 549     /* Sun4v generic Niagara machine */
 550     {
 551         .default_cpu_model = "Sun UltraSparc T1",
 552         .machine_id = niagara_id,
 553         .prom_addr = 0xfff0000000ULL,
 554         .console_serial_base = 0xfff0c2c000ULL,
 555     },
 556 };
 557
 558 /* Sun4u hardware initialisation */
 559 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
 560                        const char *boot_devices, DisplayState *ds,
 561                        const char *kernel_filename, const char *kernel_cmdline,
 562                        const char *initrd_filename, const char *cpu_model)
 563 {
 564     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 565                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 566 }
 567
 568 /* Sun4v hardware initialisation */
 569 static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
 570                        const char *boot_devices, DisplayState *ds,
 571                        const char *kernel_filename, const char *kernel_cmdline,
 572                        const char *initrd_filename, const char *cpu_model)
 573 {
 574     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 575                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 576 }
 577
 578 /* Niagara hardware initialisation */
 579 static void niagara_init(ram_addr_t RAM_size, int vga_ram_size,
 580                          const char *boot_devices, DisplayState *ds,
 581                          const char *kernel_filename, const char *kernel_cmdline,
 582                          const char *initrd_filename, const char *cpu_model)
 583 {
 584     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 585                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 586 }
 587
 588 QEMUMachine sun4u_machine = {
 589     .name = "sun4u",
 590     .desc = "Sun4u platform",
 591     .init = sun4u_init,
 592     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 593     .nodisk_ok = 1,
 594     .max_cpus = 1, // XXX for now
 595 };
 596
 597 QEMUMachine sun4v_machine = {
 598     .name = "sun4v",
 599     .desc = "Sun4v platform",
 600     .init = sun4v_init,
 601     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 602     .nodisk_ok = 1,
 603     .max_cpus = 1, // XXX for now
 604 };
 605
 606 QEMUMachine niagara_machine = {
 607     .name = "Niagara",
 608     .desc = "Sun4v platform, Niagara",
 609     .init = niagara_init,
 610     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 611     .nodisk_ok = 1,
 612     .max_cpus = 1, // XXX for now
 613 };