target-ppc: fix TCGv type in fcmpu/fcmpo
[qemu/mini2440/sniper_sniper_test.git] / hw / pc.h
blob39b220ff85248b0f6ec2ae2c79fe57b27f316525
1 #ifndef HW_PC_H
2 #define HW_PC_H
3 /* PC-style peripherals (also used by other machines). */
5 /* serial.c */
7 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
8 CharDriverState *chr);
9 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
10 qemu_irq irq, int baudbase,
11 CharDriverState *chr, int ioregister);
12 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
13 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
14 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
15 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
16 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
17 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
19 /* parallel.c */
21 typedef struct ParallelState ParallelState;
22 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
23 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
25 /* i8259.c */
27 typedef struct PicState2 PicState2;
28 extern PicState2 *isa_pic;
29 void pic_set_irq(int irq, int level);
30 void pic_set_irq_new(void *opaque, int irq, int level);
31 qemu_irq *i8259_init(qemu_irq parent_irq);
32 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
33 void *alt_irq_opaque);
34 int pic_read_irq(PicState2 *s);
35 void pic_update_irq(PicState2 *s);
36 uint32_t pic_intack_read(PicState2 *s);
37 void pic_info(void);
38 void irq_info(void);
40 /* APIC */
41 typedef struct IOAPICState IOAPICState;
43 int apic_init(CPUState *env);
44 int apic_accept_pic_intr(CPUState *env);
45 void apic_deliver_pic_intr(CPUState *env, int level);
46 int apic_get_interrupt(CPUState *env);
47 IOAPICState *ioapic_init(void);
48 void ioapic_set_irq(void *opaque, int vector, int level);
50 /* i8254.c */
52 #define PIT_FREQ 1193182
54 typedef struct PITState PITState;
56 PITState *pit_init(int base, qemu_irq irq);
57 void pit_set_gate(PITState *pit, int channel, int val);
58 int pit_get_gate(PITState *pit, int channel);
59 int pit_get_initial_count(PITState *pit, int channel);
60 int pit_get_mode(PITState *pit, int channel);
61 int pit_get_out(PITState *pit, int channel, int64_t current_time);
63 /* vmport.c */
64 void vmport_init(void);
65 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
67 /* vmmouse.c */
68 void *vmmouse_init(void *m);
70 /* pckbd.c */
72 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
73 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
74 target_phys_addr_t base, ram_addr_t size,
75 target_phys_addr_t mask);
77 /* mc146818rtc.c */
79 typedef struct RTCState RTCState;
81 RTCState *rtc_init(int base, qemu_irq irq);
82 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
83 void rtc_set_memory(RTCState *s, int addr, int val);
84 void rtc_set_date(RTCState *s, const struct tm *tm);
86 /* pc.c */
87 extern int fd_bootchk;
89 void ioport_set_a20(int enable);
90 int ioport_get_a20(void);
92 /* acpi.c */
93 extern int acpi_enabled;
94 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
95 qemu_irq sci_irq);
96 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
97 void acpi_bios_init(void);
99 /* pcspk.c */
100 void pcspk_init(PITState *);
101 int pcspk_audio_init(AudioState *, qemu_irq *pic);
103 /* piix_pci.c */
104 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
105 void i440fx_set_smm(PCIDevice *d, int val);
106 int piix3_init(PCIBus *bus, int devfn);
107 void i440fx_init_memory_mappings(PCIDevice *d);
109 extern PCIDevice *piix4_dev;
110 int piix4_init(PCIBus *bus, int devfn);
112 /* vga.c */
113 enum vga_retrace_method {
114 VGA_RETRACE_DUMB,
115 VGA_RETRACE_PRECISE
118 extern enum vga_retrace_method vga_retrace_method;
120 #ifndef TARGET_SPARC
121 #define VGA_RAM_SIZE (8192 * 1024)
122 #else
123 #define VGA_RAM_SIZE (9 * 1024 * 1024)
124 #endif
126 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
127 unsigned long vga_ram_offset, int vga_ram_size);
128 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
129 unsigned long vga_ram_offset, int vga_ram_size,
130 unsigned long vga_bios_offset, int vga_bios_size);
131 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
132 unsigned long vga_ram_offset, int vga_ram_size,
133 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
134 int it_shift);
136 /* cirrus_vga.c */
137 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
138 ram_addr_t vga_ram_offset, int vga_ram_size);
139 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
140 ram_addr_t vga_ram_offset, int vga_ram_size);
142 /* ide.c */
143 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
144 BlockDriverState *hd0, BlockDriverState *hd1);
145 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
146 int secondary_ide_enabled);
147 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
148 qemu_irq *pic);
149 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
150 qemu_irq *pic);
152 /* ne2000.c */
154 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
156 #endif