2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 const char *tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
42 int tcg_target_reg_alloc_order
[] = {
60 const int tcg_target_call_iarg_regs
[4] = {
61 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
63 const int tcg_target_call_oarg_regs
[2] = {
64 TCG_REG_R0
, TCG_REG_R1
67 static void patch_reloc(uint8_t *code_ptr
, int type
,
68 tcg_target_long value
, tcg_target_long addend
)
72 *(uint32_t *) code_ptr
= value
;
81 *(uint32_t *) code_ptr
|=
82 ((value
- ((tcg_target_long
) code_ptr
+ 8)) >> 2) & 0xffffff;
87 /* maximum number of register used for input function arguments */
88 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
95 /* parse target specific constraints */
96 int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
103 #ifndef CONFIG_SOFTMMU
109 ct
->ct
|= TCG_CT_REG
;
110 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
113 #ifdef CONFIG_SOFTMMU
114 /* qemu_ld/st inputs (unless 'd', 'D' or 'X') */
116 ct
->ct
|= TCG_CT_REG
;
117 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
119 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
120 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
124 /* qemu_ld/st data_reg */
126 ct
->ct
|= TCG_CT_REG
;
127 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
128 /* r0 and optionally r1 will be overwritten by the address
129 * so don't use these. */
130 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
131 # if TARGET_LONG_BITS == 64 || defined(USE_TLB)
132 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
136 /* qemu_ld/st64 data_reg2 */
138 ct
->ct
|= TCG_CT_REG
;
139 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
140 /* r0, r1 and optionally r2 will be overwritten by the address
141 * and the low word of data, so don't use these. */
142 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
143 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
144 # if TARGET_LONG_BITS == 64
145 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
149 # if TARGET_LONG_BITS == 64
150 /* qemu_ld/st addr_reg2 */
152 ct
->ct
|= TCG_CT_REG
;
153 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
154 /* r0 will be overwritten by the low word of base, so don't use it. */
155 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
157 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
164 ct
->ct
|= TCG_CT_REG
;
165 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
166 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
170 ct
->ct
|= TCG_CT_REG
;
171 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
172 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
173 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
185 /* Test if a constant matches the constraint.
186 * TODO: define constraints for:
188 * ldr/str offset: between -0xfff and 0xfff
189 * ldrh/strh offset: between -0xff and 0xff
190 * mov operand2: values represented with x << (2 * y), x < 0x100
191 * add, sub, eor...: ditto
193 static inline int tcg_target_const_match(tcg_target_long val
,
194 const TCGArgConstraint
*arg_ct
)
198 if (ct
& TCG_CT_CONST
)
204 enum arm_data_opc_e
{
221 #define TO_CPSR(opc) ((opc == ARITH_CMP || opc == ARITH_CMN) << 20)
223 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
224 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
225 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
226 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
227 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
228 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
229 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
230 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
232 enum arm_cond_code_e
{
235 COND_CS
= 0x2, /* Unsigned greater or equal */
236 COND_CC
= 0x3, /* Unsigned less than */
237 COND_MI
= 0x4, /* Negative */
238 COND_PL
= 0x5, /* Zero or greater */
239 COND_VS
= 0x6, /* Overflow */
240 COND_VC
= 0x7, /* No overflow */
241 COND_HI
= 0x8, /* Unsigned greater than */
242 COND_LS
= 0x9, /* Unsigned less or equal */
250 static const uint8_t tcg_cond_to_arm_cond
[10] = {
251 [TCG_COND_EQ
] = COND_EQ
,
252 [TCG_COND_NE
] = COND_NE
,
253 [TCG_COND_LT
] = COND_LT
,
254 [TCG_COND_GE
] = COND_GE
,
255 [TCG_COND_LE
] = COND_LE
,
256 [TCG_COND_GT
] = COND_GT
,
258 [TCG_COND_LTU
] = COND_CC
,
259 [TCG_COND_GEU
] = COND_CS
,
260 [TCG_COND_LEU
] = COND_LS
,
261 [TCG_COND_GTU
] = COND_HI
,
264 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
266 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
269 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
271 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
272 (((offset
- 8) >> 2) & 0x00ffffff));
275 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
277 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
278 (((offset
- 8) >> 2) & 0x00ffffff));
281 static inline void tcg_out_dat_reg(TCGContext
*s
,
282 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
284 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
285 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
288 static inline void tcg_out_dat_reg2(TCGContext
*s
,
289 int cond
, int opc0
, int opc1
, int rd0
, int rd1
,
290 int rn0
, int rn1
, int rm0
, int rm1
, int shift
)
292 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
293 (rn0
<< 16) | (rd0
<< 12) | shift
| rm0
);
294 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
295 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
298 static inline void tcg_out_dat_imm(TCGContext
*s
,
299 int cond
, int opc
, int rd
, int rn
, int im
)
301 tcg_out32(s
, (cond
<< 28) | (1 << 25) | (opc
<< 21) |
302 (rn
<< 16) | (rd
<< 12) | im
);
305 static inline void tcg_out_movi32(TCGContext
*s
,
306 int cond
, int rd
, int32_t arg
)
308 int offset
= (uint32_t) arg
- ((uint32_t) s
->code_ptr
+ 8);
310 /* TODO: This is very suboptimal, we can easily have a constant
311 * pool somewhere after all the instructions. */
313 if (arg
< 0 && arg
> -0x100)
314 return tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0, (~arg
) & 0xff);
316 if (offset
< 0x100 && offset
> -0x100)
318 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, rd
, 15, offset
) :
319 tcg_out_dat_imm(s
, cond
, ARITH_SUB
, rd
, 15, -offset
);
321 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, rd
, 0, arg
& 0xff);
322 if (arg
& 0x0000ff00)
323 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
324 ((arg
>> 8) & 0xff) | 0xc00);
325 if (arg
& 0x00ff0000)
326 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
327 ((arg
>> 16) & 0xff) | 0x800);
328 if (arg
& 0xff000000)
329 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
330 ((arg
>> 24) & 0xff) | 0x400);
333 static inline void tcg_out_mul32(TCGContext
*s
,
334 int cond
, int rd
, int rs
, int rm
)
337 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
338 (rs
<< 8) | 0x90 | rm
);
340 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
341 (rm
<< 8) | 0x90 | rs
);
343 tcg_out32(s
, (cond
<< 28) | ( 8 << 16) | (0 << 12) |
344 (rs
<< 8) | 0x90 | rm
);
345 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
346 rd
, 0, 8, SHIFT_IMM_LSL(0));
350 static inline void tcg_out_umull32(TCGContext
*s
,
351 int cond
, int rd0
, int rd1
, int rs
, int rm
)
353 if (rd0
!= rm
&& rd1
!= rm
)
354 tcg_out32(s
, (cond
<< 28) | 0x800090 |
355 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
356 else if (rd0
!= rs
&& rd1
!= rs
)
357 tcg_out32(s
, (cond
<< 28) | 0x800090 |
358 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
360 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
361 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
362 tcg_out32(s
, (cond
<< 28) | 0x800098 |
363 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
367 static inline void tcg_out_smull32(TCGContext
*s
,
368 int cond
, int rd0
, int rd1
, int rs
, int rm
)
370 if (rd0
!= rm
&& rd1
!= rm
)
371 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
372 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
373 else if (rd0
!= rs
&& rd1
!= rs
)
374 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
375 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
377 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
378 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
379 tcg_out32(s
, (cond
<< 28) | 0xc00098 |
380 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
384 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
,
385 int rd
, int rn
, tcg_target_long im
)
388 tcg_out32(s
, (cond
<< 28) | 0x05900000 |
389 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
391 tcg_out32(s
, (cond
<< 28) | 0x05100000 |
392 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
395 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
,
396 int rd
, int rn
, tcg_target_long im
)
399 tcg_out32(s
, (cond
<< 28) | 0x05800000 |
400 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
402 tcg_out32(s
, (cond
<< 28) | 0x05000000 |
403 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
406 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
,
407 int rd
, int rn
, int rm
)
409 tcg_out32(s
, (cond
<< 28) | 0x07900000 |
410 (rn
<< 16) | (rd
<< 12) | rm
);
413 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
,
414 int rd
, int rn
, int rm
)
416 tcg_out32(s
, (cond
<< 28) | 0x07800000 |
417 (rn
<< 16) | (rd
<< 12) | rm
);
420 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
,
421 int rd
, int rn
, tcg_target_long im
)
424 tcg_out32(s
, (cond
<< 28) | 0x01d000b0 |
425 (rn
<< 16) | (rd
<< 12) |
426 ((im
& 0xf0) << 4) | (im
& 0xf));
428 tcg_out32(s
, (cond
<< 28) | 0x015000b0 |
429 (rn
<< 16) | (rd
<< 12) |
430 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
433 static inline void tcg_out_st16u_8(TCGContext
*s
, int cond
,
434 int rd
, int rn
, tcg_target_long im
)
437 tcg_out32(s
, (cond
<< 28) | 0x01c000b0 |
438 (rn
<< 16) | (rd
<< 12) |
439 ((im
& 0xf0) << 4) | (im
& 0xf));
441 tcg_out32(s
, (cond
<< 28) | 0x014000b0 |
442 (rn
<< 16) | (rd
<< 12) |
443 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
446 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
,
447 int rd
, int rn
, int rm
)
449 tcg_out32(s
, (cond
<< 28) | 0x019000b0 |
450 (rn
<< 16) | (rd
<< 12) | rm
);
453 static inline void tcg_out_st16u_r(TCGContext
*s
, int cond
,
454 int rd
, int rn
, int rm
)
456 tcg_out32(s
, (cond
<< 28) | 0x018000b0 |
457 (rn
<< 16) | (rd
<< 12) | rm
);
460 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
,
461 int rd
, int rn
, tcg_target_long im
)
464 tcg_out32(s
, (cond
<< 28) | 0x01d000f0 |
465 (rn
<< 16) | (rd
<< 12) |
466 ((im
& 0xf0) << 4) | (im
& 0xf));
468 tcg_out32(s
, (cond
<< 28) | 0x015000f0 |
469 (rn
<< 16) | (rd
<< 12) |
470 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
473 static inline void tcg_out_st16s_8(TCGContext
*s
, int cond
,
474 int rd
, int rn
, tcg_target_long im
)
477 tcg_out32(s
, (cond
<< 28) | 0x01c000f0 |
478 (rn
<< 16) | (rd
<< 12) |
479 ((im
& 0xf0) << 4) | (im
& 0xf));
481 tcg_out32(s
, (cond
<< 28) | 0x014000f0 |
482 (rn
<< 16) | (rd
<< 12) |
483 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
486 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
,
487 int rd
, int rn
, int rm
)
489 tcg_out32(s
, (cond
<< 28) | 0x019000f0 |
490 (rn
<< 16) | (rd
<< 12) | rm
);
493 static inline void tcg_out_st16s_r(TCGContext
*s
, int cond
,
494 int rd
, int rn
, int rm
)
496 tcg_out32(s
, (cond
<< 28) | 0x018000f0 |
497 (rn
<< 16) | (rd
<< 12) | rm
);
500 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
,
501 int rd
, int rn
, tcg_target_long im
)
504 tcg_out32(s
, (cond
<< 28) | 0x05d00000 |
505 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
507 tcg_out32(s
, (cond
<< 28) | 0x05500000 |
508 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
511 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
,
512 int rd
, int rn
, tcg_target_long im
)
515 tcg_out32(s
, (cond
<< 28) | 0x05c00000 |
516 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
518 tcg_out32(s
, (cond
<< 28) | 0x05400000 |
519 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
522 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
,
523 int rd
, int rn
, int rm
)
525 tcg_out32(s
, (cond
<< 28) | 0x07d00000 |
526 (rn
<< 16) | (rd
<< 12) | rm
);
529 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
,
530 int rd
, int rn
, int rm
)
532 tcg_out32(s
, (cond
<< 28) | 0x07c00000 |
533 (rn
<< 16) | (rd
<< 12) | rm
);
536 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
,
537 int rd
, int rn
, tcg_target_long im
)
540 tcg_out32(s
, (cond
<< 28) | 0x01d000d0 |
541 (rn
<< 16) | (rd
<< 12) |
542 ((im
& 0xf0) << 4) | (im
& 0xf));
544 tcg_out32(s
, (cond
<< 28) | 0x015000d0 |
545 (rn
<< 16) | (rd
<< 12) |
546 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
549 static inline void tcg_out_st8s_8(TCGContext
*s
, int cond
,
550 int rd
, int rn
, tcg_target_long im
)
553 tcg_out32(s
, (cond
<< 28) | 0x01c000d0 |
554 (rn
<< 16) | (rd
<< 12) |
555 ((im
& 0xf0) << 4) | (im
& 0xf));
557 tcg_out32(s
, (cond
<< 28) | 0x014000d0 |
558 (rn
<< 16) | (rd
<< 12) |
559 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
562 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
,
563 int rd
, int rn
, int rm
)
565 tcg_out32(s
, (cond
<< 28) | 0x019000d0 |
566 (rn
<< 16) | (rd
<< 12) | rm
);
569 static inline void tcg_out_st8s_r(TCGContext
*s
, int cond
,
570 int rd
, int rn
, int rm
)
572 tcg_out32(s
, (cond
<< 28) | 0x018000d0 |
573 (rn
<< 16) | (rd
<< 12) | rm
);
576 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
577 int rd
, int rn
, int32_t offset
)
579 if (offset
> 0xfff || offset
< -0xfff) {
580 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
581 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
583 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
586 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
587 int rd
, int rn
, int32_t offset
)
589 if (offset
> 0xfff || offset
< -0xfff) {
590 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
591 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
593 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
596 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
597 int rd
, int rn
, int32_t offset
)
599 if (offset
> 0xff || offset
< -0xff) {
600 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
601 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
603 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
606 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
607 int rd
, int rn
, int32_t offset
)
609 if (offset
> 0xff || offset
< -0xff) {
610 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
611 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
613 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
616 static inline void tcg_out_st16u(TCGContext
*s
, int cond
,
617 int rd
, int rn
, int32_t offset
)
619 if (offset
> 0xff || offset
< -0xff) {
620 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
621 tcg_out_st16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
623 tcg_out_st16u_8(s
, cond
, rd
, rn
, offset
);
626 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
627 int rd
, int rn
, int32_t offset
)
629 if (offset
> 0xfff || offset
< -0xfff) {
630 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
631 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
633 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
636 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
637 int rd
, int rn
, int32_t offset
)
639 if (offset
> 0xff || offset
< -0xff) {
640 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
641 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
643 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
646 static inline void tcg_out_st8u(TCGContext
*s
, int cond
,
647 int rd
, int rn
, int32_t offset
)
649 if (offset
> 0xfff || offset
< -0xfff) {
650 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
651 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
653 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
656 static inline void tcg_out_goto(TCGContext
*s
, int cond
, uint32_t addr
)
660 val
= addr
- (tcg_target_long
) s
->code_ptr
;
661 if (val
- 8 < 0x01fffffd && val
- 8 > -0x01fffffd)
662 tcg_out_b(s
, cond
, val
);
667 if (cond
== COND_AL
) {
668 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
669 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
671 tcg_out_movi32(s
, cond
, TCG_REG_R8
, val
- 8);
672 tcg_out_dat_reg(s
, cond
, ARITH_ADD
,
673 15, 15, TCG_REG_R8
, SHIFT_IMM_LSL(0));
679 static inline void tcg_out_call(TCGContext
*s
, int cond
, uint32_t addr
)
684 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R8
, 0, 14, SHIFT_IMM_LSL(0));
687 val
= addr
- (tcg_target_long
) s
->code_ptr
;
688 if (val
< 0x01fffffd && val
> -0x01fffffd)
689 tcg_out_bl(s
, cond
, val
);
694 if (cond
== COND_AL
) {
695 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, 14, 15, 4);
696 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
697 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
699 tcg_out_movi32(s
, cond
, TCG_REG_R9
, addr
);
700 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 14, 0, 15);
701 tcg_out_bx(s
, cond
, TCG_REG_R9
);
707 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 14, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
711 static inline void tcg_out_callr(TCGContext
*s
, int cond
, int arg
)
714 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R8
, 0, 14, SHIFT_IMM_LSL(0));
716 /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */
717 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 14, 0, 15, SHIFT_IMM_LSL(0));
718 tcg_out_bx(s
, cond
, arg
);
720 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 14, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
724 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, int label_index
)
726 TCGLabel
*l
= &s
->labels
[label_index
];
729 tcg_out_goto(s
, cond
, l
->u
.value
);
730 else if (cond
== COND_AL
) {
731 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
732 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_ABS32
, label_index
, 31337);
735 /* Probably this should be preferred even for COND_AL... */
736 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, label_index
, 31337);
737 tcg_out_b(s
, cond
, 8);
741 static void tcg_out_div_helper(TCGContext
*s
, int cond
, const TCGArg
*args
,
742 void *helper_div
, void *helper_rem
, int shift
)
744 int div_reg
= args
[0];
745 int rem_reg
= args
[1];
747 /* stmdb sp!, { r0 - r3, ip, lr } */
748 /* (Note that we need an even number of registers as per EABI) */
749 tcg_out32(s
, (cond
<< 28) | 0x092d500f);
751 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 0, 0, args
[2], SHIFT_IMM_LSL(0));
752 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 1, 0, args
[3], SHIFT_IMM_LSL(0));
753 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 2, 0, args
[4], SHIFT_IMM_LSL(0));
754 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 3, 0, 2, shift
);
756 tcg_out_call(s
, cond
, (uint32_t) helper_div
);
757 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 8, 0, 0, SHIFT_IMM_LSL(0));
759 /* ldmia sp, { r0 - r3, fp, lr } */
760 tcg_out32(s
, (cond
<< 28) | 0x089d500f);
762 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 0, 0, args
[2], SHIFT_IMM_LSL(0));
763 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 1, 0, args
[3], SHIFT_IMM_LSL(0));
764 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 2, 0, args
[4], SHIFT_IMM_LSL(0));
765 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 3, 0, 2, shift
);
767 tcg_out_call(s
, cond
, (uint32_t) helper_rem
);
769 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, rem_reg
, 0, 0, SHIFT_IMM_LSL(0));
770 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, div_reg
, 0, 8, SHIFT_IMM_LSL(0));
772 /* ldr r0, [sp], #4 */
773 if (rem_reg
!= 0 && div_reg
!= 0)
774 tcg_out32(s
, (cond
<< 28) | 0x04bd0004);
775 /* ldr r1, [sp], #4 */
776 if (rem_reg
!= 1 && div_reg
!= 1)
777 tcg_out32(s
, (cond
<< 28) | 0x04bd1004);
778 /* ldr r2, [sp], #4 */
779 if (rem_reg
!= 2 && div_reg
!= 2)
780 tcg_out32(s
, (cond
<< 28) | 0x04bd2004);
781 /* ldr r3, [sp], #4 */
782 if (rem_reg
!= 3 && div_reg
!= 3)
783 tcg_out32(s
, (cond
<< 28) | 0x04bd3004);
784 /* ldr ip, [sp], #4 */
785 if (rem_reg
!= 12 && div_reg
!= 12)
786 tcg_out32(s
, (cond
<< 28) | 0x04bdc004);
787 /* ldr lr, [sp], #4 */
788 if (rem_reg
!= 14 && div_reg
!= 14)
789 tcg_out32(s
, (cond
<< 28) | 0x04bde004);
792 #ifdef CONFIG_SOFTMMU
793 extern void __ldb_mmu(void);
794 extern void __ldw_mmu(void);
795 extern void __ldl_mmu(void);
796 extern void __ldq_mmu(void);
798 extern void __stb_mmu(void);
799 extern void __stw_mmu(void);
800 extern void __stl_mmu(void);
801 extern void __stq_mmu(void);
803 static void *qemu_ld_helpers
[4] = {
810 static void *qemu_st_helpers
[4] = {
818 static inline void tcg_out_qemu_ld(TCGContext
*s
, int cond
,
819 const TCGArg
*args
, int opc
)
821 int addr_reg
, data_reg
, data_reg2
;
822 #ifdef CONFIG_SOFTMMU
823 int mem_index
, s_bits
;
824 # if TARGET_LONG_BITS == 64
836 data_reg2
= 0; /* surpress warning */
838 #if TARGET_LONG_BITS == 64
841 #ifdef CONFIG_SOFTMMU
846 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
847 8, 0, addr_reg
, SHIFT_IMM_ROR(TARGET_PAGE_BITS
));
848 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
849 0, 8, CPU_TLB_SIZE
- 1);
850 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
,
851 0, TCG_AREG0
, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
852 tcg_out_ld32_12(s
, COND_AL
, 1, 0,
853 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_read
));
854 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
,
855 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
856 /* TODO: alignment check?
858 * tcg_out_data_reg(s, COND_EQ, ARITH_EOR,
859 * 0, 1, 8, SHIFT_IMM_LSR(32 - s_bits));
861 # if TARGET_LONG_BITS == 64
862 /* XXX: possibly we could use a block data load or writeback in
863 * the first access. */
864 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
865 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_read
) + 4);
866 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
,
867 0, 1, addr_reg2
, SHIFT_IMM_LSL(0));
869 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
870 offsetof(CPUState
, tlb_table
[mem_index
][0].addend
));
874 tcg_out_ld8_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
877 tcg_out_ld8s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
880 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
883 tcg_out_ld16s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
887 tcg_out_ld32_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
890 /* TODO: must write back */
891 tcg_out_ld32_r(s
, COND_EQ
, data_reg
, 1, addr_reg
);
892 tcg_out_ld32_12(s
, COND_EQ
, data_reg2
, 1, 4);
896 label_ptr
= (void *) s
->code_ptr
;
897 tcg_out_b(s
, COND_EQ
, 8);
901 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 8, 0, 14, SHIFT_IMM_LSL(0));
904 /* TODO: move this code to where the constants pool will be */
906 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
907 0, 0, addr_reg
, SHIFT_IMM_LSL(0));
908 # if TARGET_LONG_BITS == 32
909 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 1, 0, mem_index
);
912 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
913 1, 0, addr_reg2
, SHIFT_IMM_LSL(0));
914 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
916 tcg_out_bl(s
, cond
, (tcg_target_long
) qemu_ld_helpers
[s_bits
] -
917 (tcg_target_long
) s
->code_ptr
);
921 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
922 0, 0, 0, SHIFT_IMM_LSL(24));
923 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
924 data_reg
, 0, 0, SHIFT_IMM_ASR(24));
927 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
928 0, 0, 0, SHIFT_IMM_LSL(16));
929 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
930 data_reg
, 0, 0, SHIFT_IMM_ASR(16));
937 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
938 data_reg
, 0, 0, SHIFT_IMM_LSL(0));
942 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
943 data_reg2
, 0, 1, SHIFT_IMM_LSL(0));
945 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
946 data_reg
, 0, 0, SHIFT_IMM_LSL(0));
951 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 14, 0, 8, SHIFT_IMM_LSL(0));
955 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
960 tcg_out_ld8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
963 tcg_out_ld8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
966 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
969 tcg_out_ld16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
973 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
976 /* TODO: use block load */
977 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
978 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
984 static inline void tcg_out_qemu_st(TCGContext
*s
, int cond
,
985 const TCGArg
*args
, int opc
)
987 int addr_reg
, data_reg
, data_reg2
;
988 #ifdef CONFIG_SOFTMMU
989 int mem_index
, s_bits
;
990 # if TARGET_LONG_BITS == 64
1000 data_reg2
= *args
++;
1002 data_reg2
= 0; /* surpress warning */
1004 #if TARGET_LONG_BITS == 64
1005 addr_reg2
= *args
++;
1007 #ifdef CONFIG_SOFTMMU
1012 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1013 8, 0, addr_reg
, SHIFT_IMM_ROR(TARGET_PAGE_BITS
));
1014 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1015 0, 8, CPU_TLB_SIZE
- 1);
1016 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
,
1017 0, TCG_AREG0
, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1018 tcg_out_ld32_12(s
, COND_AL
, 1, 0,
1019 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_write
));
1020 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
,
1021 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1022 /* TODO: alignment check?
1024 * tcg_out_data_reg(s, COND_EQ, ARITH_EOR,
1025 * 0, 1, 8, SHIFT_IMM_LSR(32 - s_bits));
1027 # if TARGET_LONG_BITS == 64
1028 /* XXX: possibly we could use a block data load or writeback in
1029 * the first access. */
1030 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
1031 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_write
)
1033 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
,
1034 0, 1, addr_reg2
, SHIFT_IMM_LSL(0));
1036 tcg_out_ld32_12(s
, COND_EQ
, 1, 0,
1037 offsetof(CPUState
, tlb_table
[mem_index
][0].addend
));
1041 tcg_out_st8_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1044 tcg_out_st8s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1047 tcg_out_st16u_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1050 tcg_out_st16s_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1054 tcg_out_st32_r(s
, COND_EQ
, data_reg
, addr_reg
, 1);
1057 /* TODO: must write back */
1058 tcg_out_st32_r(s
, COND_EQ
, data_reg
, 1, addr_reg
);
1059 tcg_out_st32_12(s
, COND_EQ
, data_reg2
, 1, 4);
1063 label_ptr
= (void *) s
->code_ptr
;
1064 tcg_out_b(s
, COND_EQ
, 8);
1068 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 8, 0, 14, SHIFT_IMM_LSL(0));
1071 /* TODO: move this code to where the constants pool will be */
1073 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1074 0, 0, addr_reg
, SHIFT_IMM_LSL(0));
1075 # if TARGET_LONG_BITS == 32
1078 tcg_out_dat_imm(s
, cond
, ARITH_AND
, 1, data_reg
, 0xff);
1079 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
1082 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1083 1, 0, data_reg
, SHIFT_IMM_LSL(16));
1084 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1085 1, 0, 1, SHIFT_IMM_LSR(16));
1086 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
1090 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1091 1, 0, data_reg
, SHIFT_IMM_LSL(0));
1092 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 2, 0, mem_index
);
1096 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1097 1, 0, data_reg
, SHIFT_IMM_LSL(0));
1099 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1100 2, 0, data_reg2
, SHIFT_IMM_LSL(0));
1101 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1106 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1107 1, 0, addr_reg2
, SHIFT_IMM_LSL(0));
1110 tcg_out_dat_imm(s
, cond
, ARITH_AND
, 2, data_reg
, 0xff);
1111 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1114 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1115 2, 0, data_reg
, SHIFT_IMM_LSL(16));
1116 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1117 2, 0, 2, SHIFT_IMM_LSR(16));
1118 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1122 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1123 2, 0, data_reg
, SHIFT_IMM_LSL(0));
1124 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1127 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, 3, 0, mem_index
);
1128 tcg_out32(s
, (cond
<< 28) | 0x052d3010); /* str r3, [sp, #-0x10]! */
1130 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1131 2, 0, data_reg
, SHIFT_IMM_LSL(0));
1133 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
1134 3, 0, data_reg2
, SHIFT_IMM_LSL(0));
1139 tcg_out_bl(s
, cond
, (tcg_target_long
) qemu_st_helpers
[s_bits
] -
1140 (tcg_target_long
) s
->code_ptr
);
1142 # if TARGET_LONG_BITS == 64
1144 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, 13, 13, 0x10);
1148 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, 14, 0, 8, SHIFT_IMM_LSL(0));
1152 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
1157 tcg_out_st8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1160 tcg_out_st8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1163 tcg_out_st16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1166 tcg_out_st16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1170 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1173 /* TODO: use block store */
1174 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1175 tcg_out_st32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1181 static uint8_t *tb_ret_addr
;
1183 static inline void tcg_out_op(TCGContext
*s
, int opc
,
1184 const TCGArg
*args
, const int *const_args
)
1189 case INDEX_op_exit_tb
:
1192 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, 15, 0);
1194 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R0
, 0, args
[0]);
1195 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, 15, 0, 14, SHIFT_IMM_LSL(0));
1197 tcg_out32(s
, args
[0]);
1200 tcg_out_ld32_12(s
, COND_AL
, 0, 15, 0);
1202 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, 0, 0, args
[0]);
1203 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1205 tcg_out32(s
, args
[0]);
1208 case INDEX_op_goto_tb
:
1209 if (s
->tb_jmp_offset
) {
1210 /* Direct jump method */
1212 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1213 tcg_out_b(s
, COND_AL
, 8);
1215 tcg_out_ld32_12(s
, COND_AL
, 15, 15, -4);
1216 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1220 /* Indirect jump method */
1222 c
= (int) (s
->tb_next
+ args
[0]) - ((int) s
->code_ptr
+ 8);
1223 if (c
> 0xfff || c
< -0xfff) {
1224 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
,
1225 (tcg_target_long
) (s
->tb_next
+ args
[0]));
1226 tcg_out_ld32_12(s
, COND_AL
, 15, TCG_REG_R0
, 0);
1228 tcg_out_ld32_12(s
, COND_AL
, 15, 15, c
);
1230 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, 15, 0);
1231 tcg_out_ld32_12(s
, COND_AL
, 15, TCG_REG_R0
, 0);
1232 tcg_out32(s
, (tcg_target_long
) (s
->tb_next
+ args
[0]));
1235 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1239 tcg_out_call(s
, COND_AL
, args
[0]);
1241 tcg_out_callr(s
, COND_AL
, args
[0]);
1245 tcg_out_goto(s
, COND_AL
, args
[0]);
1247 tcg_out_bx(s
, COND_AL
, args
[0]);
1250 tcg_out_goto_label(s
, COND_AL
, args
[0]);
1253 case INDEX_op_ld8u_i32
:
1254 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1256 case INDEX_op_ld8s_i32
:
1257 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1259 case INDEX_op_ld16u_i32
:
1260 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1262 case INDEX_op_ld16s_i32
:
1263 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1265 case INDEX_op_ld_i32
:
1266 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1268 case INDEX_op_st8_i32
:
1269 tcg_out_st8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1271 case INDEX_op_st16_i32
:
1272 tcg_out_st16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1274 case INDEX_op_st_i32
:
1275 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1278 case INDEX_op_mov_i32
:
1279 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1280 args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1282 case INDEX_op_movi_i32
:
1283 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1]);
1285 case INDEX_op_add_i32
:
1288 case INDEX_op_sub_i32
:
1291 case INDEX_op_and_i32
:
1294 case INDEX_op_or_i32
:
1297 case INDEX_op_xor_i32
:
1301 tcg_out_dat_reg(s
, COND_AL
, c
,
1302 args
[0], args
[1], args
[2], SHIFT_IMM_LSL(0));
1304 case INDEX_op_add2_i32
:
1305 tcg_out_dat_reg2(s
, COND_AL
, ARITH_ADD
, ARITH_ADC
,
1306 args
[0], args
[1], args
[2], args
[3],
1307 args
[4], args
[5], SHIFT_IMM_LSL(0));
1309 case INDEX_op_sub2_i32
:
1310 tcg_out_dat_reg2(s
, COND_AL
, ARITH_SUB
, ARITH_SBC
,
1311 args
[0], args
[1], args
[2], args
[3],
1312 args
[4], args
[5], SHIFT_IMM_LSL(0));
1314 case INDEX_op_neg_i32
:
1315 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1317 case INDEX_op_mul_i32
:
1318 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1320 case INDEX_op_mulu2_i32
:
1321 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1323 case INDEX_op_div2_i32
:
1324 tcg_out_div_helper(s
, COND_AL
, args
,
1325 tcg_helper_div_i64
, tcg_helper_rem_i64
,
1328 case INDEX_op_divu2_i32
:
1329 tcg_out_div_helper(s
, COND_AL
, args
,
1330 tcg_helper_divu_i64
, tcg_helper_remu_i64
,
1333 /* XXX: Perhaps args[2] & 0x1f is wrong */
1334 case INDEX_op_shl_i32
:
1336 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1338 case INDEX_op_shr_i32
:
1339 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1340 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1342 case INDEX_op_sar_i32
:
1343 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1344 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1347 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1350 case INDEX_op_brcond_i32
:
1351 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1352 args
[0], args
[1], SHIFT_IMM_LSL(0));
1353 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]], args
[3]);
1355 case INDEX_op_brcond2_i32
:
1356 /* The resulting conditions are:
1357 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1358 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1359 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1360 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1361 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1362 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1364 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1365 args
[1], args
[3], SHIFT_IMM_LSL(0));
1366 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1367 args
[0], args
[2], SHIFT_IMM_LSL(0));
1368 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]], args
[5]);
1371 case INDEX_op_qemu_ld8u
:
1372 tcg_out_qemu_ld(s
, COND_AL
, args
, 0);
1374 case INDEX_op_qemu_ld8s
:
1375 tcg_out_qemu_ld(s
, COND_AL
, args
, 0 | 4);
1377 case INDEX_op_qemu_ld16u
:
1378 tcg_out_qemu_ld(s
, COND_AL
, args
, 1);
1380 case INDEX_op_qemu_ld16s
:
1381 tcg_out_qemu_ld(s
, COND_AL
, args
, 1 | 4);
1383 case INDEX_op_qemu_ld32u
:
1384 tcg_out_qemu_ld(s
, COND_AL
, args
, 2);
1386 case INDEX_op_qemu_ld64
:
1387 tcg_out_qemu_ld(s
, COND_AL
, args
, 3);
1390 case INDEX_op_qemu_st8
:
1391 tcg_out_qemu_st(s
, COND_AL
, args
, 0);
1393 case INDEX_op_qemu_st16
:
1394 tcg_out_qemu_st(s
, COND_AL
, args
, 1);
1396 case INDEX_op_qemu_st32
:
1397 tcg_out_qemu_st(s
, COND_AL
, args
, 2);
1399 case INDEX_op_qemu_st64
:
1400 tcg_out_qemu_st(s
, COND_AL
, args
, 3);
1403 case INDEX_op_ext8s_i32
:
1404 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1405 args
[0], 0, args
[1], SHIFT_IMM_LSL(24));
1406 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1407 args
[0], 0, args
[0], SHIFT_IMM_ASR(24));
1409 case INDEX_op_ext16s_i32
:
1410 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1411 args
[0], 0, args
[1], SHIFT_IMM_LSL(16));
1412 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1413 args
[0], 0, args
[0], SHIFT_IMM_ASR(16));
1421 static const TCGTargetOpDef arm_op_defs
[] = {
1422 { INDEX_op_exit_tb
, { } },
1423 { INDEX_op_goto_tb
, { } },
1424 { INDEX_op_call
, { "ri" } },
1425 { INDEX_op_jmp
, { "ri" } },
1426 { INDEX_op_br
, { } },
1428 { INDEX_op_mov_i32
, { "r", "r" } },
1429 { INDEX_op_movi_i32
, { "r" } },
1431 { INDEX_op_ld8u_i32
, { "r", "r" } },
1432 { INDEX_op_ld8s_i32
, { "r", "r" } },
1433 { INDEX_op_ld16u_i32
, { "r", "r" } },
1434 { INDEX_op_ld16s_i32
, { "r", "r" } },
1435 { INDEX_op_ld_i32
, { "r", "r" } },
1436 { INDEX_op_st8_i32
, { "r", "r" } },
1437 { INDEX_op_st16_i32
, { "r", "r" } },
1438 { INDEX_op_st_i32
, { "r", "r" } },
1440 /* TODO: "r", "r", "ri" */
1441 { INDEX_op_add_i32
, { "r", "r", "r" } },
1442 { INDEX_op_sub_i32
, { "r", "r", "r" } },
1443 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1444 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1445 { INDEX_op_div2_i32
, { "r", "r", "r", "1", "2" } },
1446 { INDEX_op_divu2_i32
, { "r", "r", "r", "1", "2" } },
1447 { INDEX_op_and_i32
, { "r", "r", "r" } },
1448 { INDEX_op_or_i32
, { "r", "r", "r" } },
1449 { INDEX_op_xor_i32
, { "r", "r", "r" } },
1450 { INDEX_op_neg_i32
, { "r", "r" } },
1452 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1453 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1454 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1456 { INDEX_op_brcond_i32
, { "r", "r" } },
1458 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1459 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1460 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1461 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1463 { INDEX_op_qemu_ld8u
, { "r", "x", "X" } },
1464 { INDEX_op_qemu_ld8s
, { "r", "x", "X" } },
1465 { INDEX_op_qemu_ld16u
, { "r", "x", "X" } },
1466 { INDEX_op_qemu_ld16s
, { "r", "x", "X" } },
1467 { INDEX_op_qemu_ld32u
, { "r", "x", "X" } },
1468 { INDEX_op_qemu_ld64
, { "r", "d", "x", "X" } },
1470 { INDEX_op_qemu_st8
, { "d", "x", "X" } },
1471 { INDEX_op_qemu_st16
, { "d", "x", "X" } },
1472 { INDEX_op_qemu_st32
, { "d", "x", "X" } },
1473 { INDEX_op_qemu_st64
, { "d", "D", "x", "X" } },
1475 { INDEX_op_ext8s_i32
, { "r", "r" } },
1476 { INDEX_op_ext16s_i32
, { "r", "r" } },
1481 void tcg_target_init(TCGContext
*s
)
1484 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1487 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0,
1488 ((2 << TCG_REG_R14
) - 1) & ~(1 << TCG_REG_R8
));
1489 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1490 ((2 << TCG_REG_R3
) - 1) |
1491 (1 << TCG_REG_R12
) | (1 << TCG_REG_R14
));
1493 tcg_regset_clear(s
->reserved_regs
);
1495 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R14
);
1497 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
1498 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R8
);
1500 tcg_add_target_add_op_defs(arm_op_defs
);
1503 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int arg
,
1504 int arg1
, tcg_target_long arg2
)
1506 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
1509 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
1510 int arg1
, tcg_target_long arg2
)
1512 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
1515 void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
1519 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, reg
, reg
, val
);
1524 tcg_out_dat_imm(s
, COND_AL
, ARITH_SUB
, reg
, reg
, -val
);
1530 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
1532 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
1535 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
1536 int ret
, tcg_target_long arg
)
1538 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
1541 void tcg_target_qemu_prologue(TCGContext
*s
)
1543 /* stmdb sp!, { r9 - r11, lr } */
1544 tcg_out32(s
, (COND_AL
<< 28) | 0x092d4e00);
1546 tcg_out_bx(s
, COND_AL
, TCG_REG_R0
);
1547 tb_ret_addr
= s
->code_ptr
;
1549 /* ldmia sp!, { r9 - r11, pc } */
1550 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd8e00);