hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 /* PCI includes legacy ISA access.  */
   5 #include "isa.h"
   6
   7 /* PCI bus */
   8
   9 extern target_phys_addr_t pci_mem_base;
  10
  11 #define PCI_VENDOR_ID_LSI_LOGIC          0x1000
  12 #define PCI_DEVICE_ID_LSI_53C895A        0x0012
  13
  14 #define PCI_VENDOR_ID_DEC                0x1011
  15
  16 #define PCI_VENDOR_ID_CIRRUS             0x1013
  17
  18 #define PCI_VENDOR_ID_IBM                0x1014
  19
  20 #define PCI_VENDOR_ID_AMD                0x1022
  21 #define PCI_DEVICE_ID_AMD_LANCE          0x2000
  22
  23 #define PCI_VENDOR_ID_HITACHI            0x1054
  24
  25 #define PCI_VENDOR_ID_MOTOROLA           0x1057
  26 #define PCI_DEVICE_ID_MOTOROLA_MPC106    0x0002
  27 #define PCI_DEVICE_ID_MOTOROLA_RAVEN     0x4801
  28
  29 #define PCI_VENDOR_ID_APPLE              0x106b
  30 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP    0x0020
  31
  32 #define PCI_VENDOR_ID_SUN                0x108e
  33 #define PCI_DEVICE_ID_SUN_EBUS           0x1000
  34 #define PCI_DEVICE_ID_SUN_SABRE          0xa000
  35
  36 #define PCI_VENDOR_ID_CMD                0x1095
  37 #define PCI_DEVICE_ID_CMD_646            0x0646
  38
  39 #define PCI_VENDOR_ID_REALTEK            0x10ec
  40 #define PCI_DEVICE_ID_REALTEK_8139       0x8139
  41
  42 #define PCI_VENDOR_ID_XILINX             0x10ee
  43
  44 #define PCI_VENDOR_ID_MARVELL            0x11ab
  45
  46 #define PCI_VENDOR_ID_ENSONIQ            0x1274
  47 #define PCI_DEVICE_ID_ENSONIQ_ES1370     0x5000
  48
  49 #define PCI_VENDOR_ID_VMWARE             0x15ad
  50 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  51 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  52 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  53 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  54 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  55
  56 #define PCI_VENDOR_ID_INTEL              0x8086
  57 #define PCI_DEVICE_ID_INTEL_82441        0x1237
  58 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
  59 #define PCI_DEVICE_ID_INTEL_82371SB_0    0x7000
  60 #define PCI_DEVICE_ID_INTEL_82371SB_1    0x7010
  61 #define PCI_DEVICE_ID_INTEL_82371SB_2    0x7020
  62 #define PCI_DEVICE_ID_INTEL_82371AB_0    0x7110
  63 #define PCI_DEVICE_ID_INTEL_82371AB      0x7111
  64 #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
  65 #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
  66
  67 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  68 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  69 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  70 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  71
  72 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  73 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  74 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  75 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  76
  77 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  78                                 uint32_t address, uint32_t data, int len);
  79 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  80                                    uint32_t address, int len);
  81 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  82                                 uint32_t addr, uint32_t size, int type);
  83
  84 #define PCI_ADDRESS_SPACE_MEM           0x00
  85 #define PCI_ADDRESS_SPACE_IO            0x01
  86 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  87
  88 typedef struct PCIIORegion {
  89     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  90     uint32_t size;
  91     uint8_t type;
  92     PCIMapIORegionFunc *map_func;
  93 } PCIIORegion;
  94
  95 #define PCI_ROM_SLOT 6
  96 #define PCI_NUM_REGIONS 7
  97
  98 #define PCI_DEVICES_MAX 64
  99
 100 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 101 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 102 #define PCI_COMMAND             0x04    /* 16 bits */
 103 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 104 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 105 #define PCI_REVISION            0x08
 106 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 107 #define PCI_SUBVENDOR_ID        0x2c    /* 16 bits */
 108 #define PCI_SUBDEVICE_ID        0x2e    /* 16 bits */
 109 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 110 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 111 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 112 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 113
 114 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 115 #define PCI_STATUS_RESERVED1    0x007
 116 #define PCI_STATUS_INT_STATUS   0x008
 117 #define PCI_STATUS_CAPABILITIES 0x010
 118 #define PCI_STATUS_66MHZ        0x020
 119 #define PCI_STATUS_RESERVED2    0x040
 120 #define PCI_STATUS_FAST_BACK    0x080
 121 #define PCI_STATUS_DEVSEL       0x600
 122
 123 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 124                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 125                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 126
 127 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 128
 129 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 130 #define PCI_COMMAND_RESERVED    0xf800
 131
 132 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 133
 134 struct PCIDevice {
 135     /* PCI config space */
 136     uint8_t config[256];
 137
 138     /* the following fields are read only */
 139     PCIBus *bus;
 140     int devfn;
 141     char name[64];
 142     PCIIORegion io_regions[PCI_NUM_REGIONS];
 143
 144     /* do not access the following fields */
 145     PCIConfigReadFunc *config_read;
 146     PCIConfigWriteFunc *config_write;
 147     /* ??? This is a PC-specific hack, and should be removed.  */
 148     int irq_index;
 149
 150     /* IRQ objects for the INTA-INTD pins.  */
 151     qemu_irq *irq;
 152
 153     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 154     int irq_state[4];
 155 };
 156
 157 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 158                                int instance_size, int devfn,
 159                                PCIConfigReadFunc *config_read,
 160                                PCIConfigWriteFunc *config_write);
 161
 162 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 163                             uint32_t size, int type,
 164                             PCIMapIORegionFunc *map_func);
 165
 166 uint32_t pci_default_read_config(PCIDevice *d,
 167                                  uint32_t address, int len);
 168 void pci_default_write_config(PCIDevice *d,
 169                               uint32_t address, uint32_t val, int len);
 170 void pci_device_save(PCIDevice *s, QEMUFile *f);
 171 int pci_device_load(PCIDevice *s, QEMUFile *f);
 172
 173 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 174 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 175 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 176                          qemu_irq *pic, int devfn_min, int nirq);
 177
 178 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 179                   const char *default_model);
 180 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 181 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 182 int pci_bus_num(PCIBus *s);
 183 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 184
 185 void pci_info(void);
 186 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 187                         pci_map_irq_fn map_irq, const char *name);
 188
 189 static inline void
 190 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 191 {
 192     cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
 193 }
 194
 195 static inline void
 196 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 197 {
 198     cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
 199 }
 200
 201 /* lsi53c895a.c */
 202 #define LSI_MAX_DEVS 7
 203 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
 204 void *lsi_scsi_init(PCIBus *bus, int devfn);
 205
 206 /* vmware_vga.c */
 207 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
 208                      unsigned long vga_ram_offset, int vga_ram_size);
 209
 210 /* usb-uhci.c */
 211 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 212 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 213
 214 /* usb-ohci.c */
 215 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 216
 217 /* eepro100.c */
 218
 219 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 220 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 221 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 222
 223 /* ne2000.c */
 224
 225 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 226
 227 /* rtl8139.c */
 228
 229 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 230
 231 /* e1000.c */
 232 void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
 233
 234 /* pcnet.c */
 235 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 236
 237 /* prep_pci.c */
 238 PCIBus *pci_prep_init(qemu_irq *pic);
 239
 240 /* apb_pci.c */
 241 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 242                      target_phys_addr_t mem_base,
 243                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 244
 245 /* sh_pci.c */
 246 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 247                             qemu_irq *pic, int devfn_min, int nirq);
 248
 249 #endif